From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 28DF5A0C47; Tue, 12 Oct 2021 09:07:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ECEC44111F; Tue, 12 Oct 2021 09:06:38 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A348E4111B for ; Tue, 12 Oct 2021 09:06:37 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19C4UeIq024076; Tue, 12 Oct 2021 00:06:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=gcKIreUXyGGFjCiySid6rb4wpJLfTRaIhyN3+swur6o=; b=WT/PGYrgCoILDMrp+WCP2yS9JShqTrLhQ8ymhn5TFL97pyvyDwcOYO9neOCxVvqSJ8YO mMOzxPEIkSdKMPLVjJEKYBTpR1sTi8P7prrN/8e/+BmuW6uH46Ckgz9/XLTnKVZUDVrD UfjPxVswqH18OkW+AhlizFzIfYsjy+OFSf9N5mGsCIllWeSpQZkvOKpMxqDX2wLk16LF +ES1qSU+CF2OkZwS0LBWI86oV27NPgE2vX8JBFx36f3iZWbyU7uU5MdA54Ec1ixQzd5z BrvojCHEoMX1XS9Wmbh7TIoR47geTIFS5lt8XVkn7M4lRV8suY8pru5lkAvob1zT2v4p 4g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 3bn3d58jps-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 12 Oct 2021 00:06:34 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 12 Oct 2021 00:06:33 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 12 Oct 2021 00:06:33 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 839BB3F7087; Tue, 12 Oct 2021 00:06:31 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Tue, 12 Oct 2021 12:35:51 +0530 Message-ID: <20211012070612.352164-8-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211012070612.352164-1-skori@marvell.com> References: <20211011155057.302142-2-skori@marvell.com> <20211012070612.352164-1-skori@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: qm-McOAzGy5SQzdOBTC3XD6jI056wbY7 X-Proofpoint-GUID: qm-McOAzGy5SQzdOBTC3XD6jI056wbY7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-12_01,2021-10-11_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v5 07/28] common/cnxk: support RoC API to toggle profile state X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement RoC API to enable or disable HW bandwidth profiles on CN10K platform. Signed-off-by: Sunil Kumar Kori --- v5: - Fix checkpatch errors - Fix patch apply errors v4: - Rebase support on dpdk-next-net-mrvl branch - Handled meter action during flow destroy - Handled meter cleanup during port shutdown v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/roc_nix.h | 4 ++++ drivers/common/cnxk/roc_nix_bpf.c | 39 +++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 44 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index c2cc823516..5b3bf38a82 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -217,6 +217,7 @@ struct roc_nix_stats_queue { struct roc_nix_rq { /* Input parameters */ uint16_t qid; + uint16_t bpf_id; uint64_t aura_handle; bool ipsech_ena; uint16_t first_skip; @@ -602,6 +603,9 @@ int __roc_api roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id, enum roc_nix_bpf_level_flag lvl_flag, struct roc_nix_bpf_cfg *cfg); +int __roc_api roc_nix_bpf_ena_dis(struct roc_nix *roc_nix, uint16_t id, + struct roc_nix_rq *rq, bool enable); + uint8_t __roc_api roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag); diff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c index aa5829ee42..c61a697f1a 100644 --- a/drivers/common/cnxk/roc_nix_bpf.c +++ b/drivers/common/cnxk/roc_nix_bpf.c @@ -449,3 +449,42 @@ roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id, return mbox_process(mbox); } + +int +roc_nix_bpf_ena_dis(struct roc_nix *roc_nix, uint16_t id, struct roc_nix_rq *rq, + bool enable) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct mbox *mbox = get_mbox(roc_nix); + struct nix_cn10k_aq_enq_req *aq; + int rc; + + if (roc_model_is_cn9k()) + return NIX_ERR_HW_NOTSUP; + + if (rq->qid >= nix->nb_rx_queues) + return NIX_ERR_QUEUE_INVALID_RANGE; + + aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); + if (aq == NULL) + return -ENOSPC; + aq->qidx = rq->qid; + aq->ctype = NIX_AQ_CTYPE_RQ; + aq->op = NIX_AQ_INSTOP_WRITE; + + aq->rq.policer_ena = enable; + aq->rq_mask.policer_ena = ~(aq->rq_mask.policer_ena); + if (enable) { + aq->rq.band_prof_id = id; + aq->rq_mask.band_prof_id = ~(aq->rq_mask.band_prof_id); + } + + rc = mbox_process(mbox); + if (rc) + goto exit; + + rq->bpf_id = id; + +exit: + return rc; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index f34fd3b4a4..05b19beaa2 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -85,6 +85,7 @@ INTERNAL { roc_nix_bpf_alloc; roc_nix_bpf_config; roc_nix_bpf_count_get; + roc_nix_bpf_ena_dis; roc_nix_bpf_free; roc_nix_bpf_free_all; roc_nix_bpf_level_to_idx; -- 2.25.1