From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 835C0A0C55; Wed, 13 Oct 2021 18:32:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5F4E141194; Wed, 13 Oct 2021 18:31:16 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id A87204115D for ; Wed, 13 Oct 2021 18:31:11 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10136"; a="313670760" X-IronPort-AV: E=Sophos;i="5.85,371,1624345200"; d="scan'208";a="313670760" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2021 09:31:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,371,1624345200"; d="scan'208";a="491541284" Received: from silpixa00401122.ir.intel.com ([10.55.128.10]) by orsmga008.jf.intel.com with ESMTP; 13 Oct 2021 09:31:09 -0700 From: Kevin Laatz To: dev@dpdk.org Cc: bruce.richardson@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, conor.walsh@intel.com, Kevin Laatz Date: Wed, 13 Oct 2021 16:30:43 +0000 Message-Id: <20211013163053.1033998-7-kevin.laatz@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211013163053.1033998-1-kevin.laatz@intel.com> References: <20210827172048.558704-1-kevin.laatz@intel.com> <20211013163053.1033998-1-kevin.laatz@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v7 06/16] dma/idxd: add datapath structures X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add data structures required for the data path for IDXD devices. Signed-off-by: Bruce Richardson Signed-off-by: Kevin Laatz Reviewed-by: Conor Walsh --- drivers/dma/idxd/idxd_bus.c | 1 + drivers/dma/idxd/idxd_common.c | 33 ++++++++++++++++++ drivers/dma/idxd/idxd_hw_defs.h | 60 ++++++++++++++++++++++++++++++++ drivers/dma/idxd/idxd_internal.h | 3 ++ drivers/dma/idxd/idxd_pci.c | 1 + 5 files changed, 98 insertions(+) diff --git a/drivers/dma/idxd/idxd_bus.c b/drivers/dma/idxd/idxd_bus.c index b48fa954ed..3c0837ec52 100644 --- a/drivers/dma/idxd/idxd_bus.c +++ b/drivers/dma/idxd/idxd_bus.c @@ -95,6 +95,7 @@ idxd_dev_close(struct rte_dma_dev *dev) static const struct rte_dma_dev_ops idxd_bus_ops = { .dev_close = idxd_dev_close, + .dev_dump = idxd_dump, }; static void * diff --git a/drivers/dma/idxd/idxd_common.c b/drivers/dma/idxd/idxd_common.c index be8f684bd5..5480a29c7b 100644 --- a/drivers/dma/idxd/idxd_common.c +++ b/drivers/dma/idxd/idxd_common.c @@ -10,6 +10,35 @@ #define IDXD_PMD_NAME_STR "dmadev_idxd" +int +idxd_dump(const struct rte_dma_dev *dev, FILE *f) +{ + struct idxd_dmadev *idxd = dev->fp_obj->dev_private; + unsigned int i; + + fprintf(f, "== IDXD Private Data ==\n"); + fprintf(f, " Portal: %p\n", idxd->portal); + fprintf(f, " Config: { ring_size: %u }\n", + idxd->qcfg.nb_desc); + fprintf(f, " Batch ring (sz = %u, max_batches = %u):\n\t", + idxd->max_batches + 1, idxd->max_batches); + for (i = 0; i <= idxd->max_batches; i++) { + fprintf(f, " %u ", idxd->batch_idx_ring[i]); + if (i == idxd->batch_idx_read && i == idxd->batch_idx_write) + fprintf(f, "[rd ptr, wr ptr] "); + else if (i == idxd->batch_idx_read) + fprintf(f, "[rd ptr] "); + else if (i == idxd->batch_idx_write) + fprintf(f, "[wr ptr] "); + if (i == idxd->max_batches) + fprintf(f, "\n"); + } + + fprintf(f, " Curr batch: start = %u, size = %u\n", idxd->batch_start, idxd->batch_size); + fprintf(f, " IDS: avail = %u, returned: %u\n", idxd->ids_avail, idxd->ids_returned); + return 0; +} + int idxd_dmadev_create(const char *name, struct rte_device *dev, const struct idxd_dmadev *base_idxd, @@ -19,6 +48,10 @@ idxd_dmadev_create(const char *name, struct rte_device *dev, struct rte_dma_dev *dmadev = NULL; int ret = 0; + RTE_BUILD_BUG_ON(sizeof(struct idxd_hw_desc) != 64); + RTE_BUILD_BUG_ON(offsetof(struct idxd_hw_desc, size) != 32); + RTE_BUILD_BUG_ON(sizeof(struct idxd_completion) != 32); + if (!name) { IDXD_PMD_ERR("Invalid name of the device!"); ret = -EINVAL; diff --git a/drivers/dma/idxd/idxd_hw_defs.h b/drivers/dma/idxd/idxd_hw_defs.h index ea627cba6d..55ca9f7f52 100644 --- a/drivers/dma/idxd/idxd_hw_defs.h +++ b/drivers/dma/idxd/idxd_hw_defs.h @@ -5,6 +5,66 @@ #ifndef _IDXD_HW_DEFS_H_ #define _IDXD_HW_DEFS_H_ +/* + * Defines used in the data path for interacting with IDXD hardware. + */ +#define IDXD_CMD_OP_SHIFT 24 +enum rte_idxd_ops { + idxd_op_nop = 0, + idxd_op_batch, + idxd_op_drain, + idxd_op_memmove, + idxd_op_fill +}; + +#define IDXD_FLAG_FENCE (1 << 0) +#define IDXD_FLAG_COMPLETION_ADDR_VALID (1 << 2) +#define IDXD_FLAG_REQUEST_COMPLETION (1 << 3) +#define IDXD_FLAG_CACHE_CONTROL (1 << 8) + +/** + * Hardware descriptor used by DSA hardware, for both bursts and + * for individual operations. + */ +struct idxd_hw_desc { + uint32_t pasid; + uint32_t op_flags; + rte_iova_t completion; + + RTE_STD_C11 + union { + rte_iova_t src; /* source address for copy ops etc. */ + rte_iova_t desc_addr; /* descriptor pointer for batch */ + }; + rte_iova_t dst; + + uint32_t size; /* length of data for op, or batch size */ + + uint16_t intr_handle; /* completion interrupt handle */ + + /* remaining 26 bytes are reserved */ + uint16_t __reserved[13]; +} __rte_aligned(64); + +#define IDXD_COMP_STATUS_INCOMPLETE 0 +#define IDXD_COMP_STATUS_SUCCESS 1 +#define IDXD_COMP_STATUS_INVALID_OPCODE 0x10 +#define IDXD_COMP_STATUS_INVALID_SIZE 0x13 +#define IDXD_COMP_STATUS_SKIPPED 0xFF /* not official IDXD error, needed as placeholder */ + +/** + * Completion record structure written back by DSA + */ +struct idxd_completion { + uint8_t status; + uint8_t result; + /* 16-bits pad here */ + uint32_t completed_size; /* data length, or descriptors for batch */ + + rte_iova_t fault_address; + uint32_t invalid_flags; +} __rte_aligned(32); + /*** Definitions for Intel(R) Data Streaming Accelerator ***/ #define IDXD_CMD_SHIFT 20 diff --git a/drivers/dma/idxd/idxd_internal.h b/drivers/dma/idxd/idxd_internal.h index cb3a68c69b..99c8e04302 100644 --- a/drivers/dma/idxd/idxd_internal.h +++ b/drivers/dma/idxd/idxd_internal.h @@ -39,6 +39,8 @@ struct idxd_pci_common { }; struct idxd_dmadev { + struct idxd_hw_desc *desc_ring; + /* counters to track the batches */ unsigned short max_batches; unsigned short batch_idx_read; @@ -79,5 +81,6 @@ struct idxd_dmadev { int idxd_dmadev_create(const char *name, struct rte_device *dev, const struct idxd_dmadev *base_idxd, const struct rte_dma_dev_ops *ops); +int idxd_dump(const struct rte_dma_dev *dev, FILE *f); #endif /* _IDXD_INTERNAL_H_ */ diff --git a/drivers/dma/idxd/idxd_pci.c b/drivers/dma/idxd/idxd_pci.c index 2589d59a7d..72d9723fe7 100644 --- a/drivers/dma/idxd/idxd_pci.c +++ b/drivers/dma/idxd/idxd_pci.c @@ -83,6 +83,7 @@ idxd_pci_dev_close(struct rte_dma_dev *dev) static const struct rte_dma_dev_ops idxd_pci_ops = { .dev_close = idxd_pci_dev_close, + .dev_dump = idxd_dump, }; /* each portal uses 4 x 4k pages */ -- 2.30.2