From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A10E8A0C4B; Thu, 14 Oct 2021 16:52:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DDDB14129C; Thu, 14 Oct 2021 16:52:11 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 50FF741294 for ; Thu, 14 Oct 2021 16:52:08 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10136"; a="214855048" X-IronPort-AV: E=Sophos;i="5.85,372,1624345200"; d="scan'208";a="214855048" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 07:52:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,372,1624345200"; d="scan'208";a="563853383" Received: from silpixa00401089.ir.intel.com ([10.55.128.47]) by FMSMGA003.fm.intel.com with ESMTP; 14 Oct 2021 07:52:06 -0700 From: Harry van Haaren To: dev@dpdk.org Cc: jerinj@marvell.com, pravin.pathak@intel.com, rashmi.shetty@intel.com, Pathak@dpdk.org Date: Thu, 14 Oct 2021 14:51:41 +0000 Message-Id: <20211014145141.679372-4-harry.van.haaren@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211014145141.679372-1-harry.van.haaren@intel.com> References: <20210909125422.31144-2-harry.van.haaren@intel.com> <20211014145141.679372-1-harry.van.haaren@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v2 4/4] event/dlb2: optimize credit allocations using port hint flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: "Pathak, Pravin" This commit implements the changes required for using suggested port type hint feature. Each port uses different credit quanta based on port type specified using port configuration flags. Each port has separate quanta defined in dlb2_priv.h Producer and consumer ports will need larger quanta value to reduce number of credit calls they make. Workers can use small quanta as they mostly work out of locally cached credits and don't request/return credits often. Signed-off-by: Pathak, Pravin --- drivers/event/dlb2/dlb2.c | 61 ++++++++++++++++++++++++++++++--- drivers/event/dlb2/dlb2_priv.h | 12 +++++-- drivers/event/dlb2/pf/dlb2_pf.c | 1 + 3 files changed, 67 insertions(+), 7 deletions(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index 252bbd8d5e..f77f00c0bc 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -355,6 +355,26 @@ set_sw_credit_quanta(const char *key __rte_unused, return 0; } +static int +set_hw_credit_quanta(const char *key __rte_unused, + const char *value, + void *opaque) +{ + int *hw_credit_quanta = opaque; + int ret; + + if (value == NULL || opaque == NULL) { + DLB2_LOG_ERR("NULL pointer\n"); + return -EINVAL; + } + + ret = dlb2_string_to_int(hw_credit_quanta, value); + if (ret < 0) + return ret; + + return 0; +} + static int set_default_depth_thresh(const char *key __rte_unused, const char *value, @@ -769,7 +789,7 @@ dlb2_eventdev_configure(const struct rte_eventdev *dev) if (rsrcs->num_ldb_queues) rsrcs->num_ldb_credits = config->nb_events_limit; if (rsrcs->num_dir_ports) - rsrcs->num_dir_credits = config->nb_events_limit / 4; + rsrcs->num_dir_credits = config->nb_events_limit / 2; if (dlb2->num_dir_credits_override != -1) rsrcs->num_dir_credits = dlb2->num_dir_credits_override; } @@ -1693,6 +1713,7 @@ dlb2_eventdev_port_setup(struct rte_eventdev *dev, struct dlb2_eventdev *dlb2; struct dlb2_eventdev_port *ev_port; int ret; + uint32_t hw_credit_quanta, sw_credit_quanta; if (dev == NULL || port_conf == NULL) { DLB2_LOG_ERR("Null parameter\n"); @@ -1753,9 +1774,25 @@ dlb2_eventdev_port_setup(struct rte_eventdev *dev, RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL); ev_port->outstanding_releases = 0; ev_port->inflight_credits = 0; - ev_port->credit_update_quanta = dlb2->sw_credit_quanta; ev_port->dlb2 = dlb2; /* reverse link */ + /* Default for worker ports */ + sw_credit_quanta = dlb2->sw_credit_quanta; + hw_credit_quanta = dlb2->hw_credit_quanta; + + if (port_conf->event_port_cfg & RTE_EVENT_PORT_CFG_HINT_PRODUCER) { + /* Producer type ports. Mostly enqueue */ + sw_credit_quanta = DLB2_SW_CREDIT_P_QUANTA_DEFAULT; + hw_credit_quanta = DLB2_SW_CREDIT_P_BATCH_SZ; + } + if (port_conf->event_port_cfg & RTE_EVENT_PORT_CFG_HINT_CONSUMER) { + /* Consumer type ports. Mostly dequeue */ + sw_credit_quanta = DLB2_SW_CREDIT_C_QUANTA_DEFAULT; + hw_credit_quanta = DLB2_SW_CREDIT_C_BATCH_SZ; + } + ev_port->credit_update_quanta = sw_credit_quanta; + ev_port->qm_port.hw_credit_quanta = hw_credit_quanta; + /* Tear down pre-existing port->queue links */ if (dlb2->run_state == DLB2_RUN_STATE_STOPPED) dlb2_port_link_teardown(dlb2, &dlb2->ev_ports[ev_port_id]); @@ -2378,7 +2415,8 @@ dlb2_port_credits_get(struct dlb2_port *qm_port, enum dlb2_hw_queue_types type) { uint32_t credits = *qm_port->credit_pool[type]; - uint32_t batch_size = DLB2_SW_CREDIT_BATCH_SZ; + /* By default hw_credit_quanta is DLB2_SW_CREDIT_BATCH_SZ */ + uint32_t batch_size = qm_port->hw_credit_quanta; if (unlikely(credits < batch_size)) batch_size = credits; @@ -3112,7 +3150,7 @@ dlb2_event_release(struct dlb2_eventdev *dlb2, static inline void dlb2_port_credits_inc(struct dlb2_port *qm_port, int num) { - uint32_t batch_size = DLB2_SW_CREDIT_BATCH_SZ; + uint32_t batch_size = qm_port->hw_credit_quanta; /* increment port credits, and return to pool if exceeds threshold */ if (!qm_port->is_directed) { @@ -4446,6 +4484,7 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev, dlb2->qm_instance.cos_id = dlb2_args->cos_id; dlb2->poll_interval = dlb2_args->poll_interval; dlb2->sw_credit_quanta = dlb2_args->sw_credit_quanta; + dlb2->hw_credit_quanta = dlb2_args->hw_credit_quanta; dlb2->default_depth_thresh = dlb2_args->default_depth_thresh; dlb2->vector_opts_enabled = dlb2_args->vector_opts_enabled; @@ -4550,6 +4589,7 @@ dlb2_parse_params(const char *params, DLB2_COS_ARG, DLB2_POLL_INTERVAL_ARG, DLB2_SW_CREDIT_QUANTA_ARG, + DLB2_HW_CREDIT_QUANTA_ARG, DLB2_DEPTH_THRESH_ARG, DLB2_VECTOR_OPTS_ENAB_ARG, NULL }; @@ -4649,7 +4689,18 @@ dlb2_parse_params(const char *params, set_sw_credit_quanta, &dlb2_args->sw_credit_quanta); if (ret != 0) { - DLB2_LOG_ERR("%s: Error parsing sw xredit quanta parameter", + DLB2_LOG_ERR("%s: Error parsing sw credit quanta parameter", + name); + rte_kvargs_free(kvlist); + return ret; + } + + ret = rte_kvargs_process(kvlist, + DLB2_HW_CREDIT_QUANTA_ARG, + set_hw_credit_quanta, + &dlb2_args->hw_credit_quanta); + if (ret != 0) { + DLB2_LOG_ERR("%s: Error parsing hw credit quanta parameter", name); rte_kvargs_free(kvlist); return ret; diff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h index bb87072da0..5132c52115 100644 --- a/drivers/event/dlb2/dlb2_priv.h +++ b/drivers/event/dlb2/dlb2_priv.h @@ -24,7 +24,9 @@ /* Default values for command line devargs */ #define DLB2_POLL_INTERVAL_DEFAULT 1000 -#define DLB2_SW_CREDIT_QUANTA_DEFAULT 32 +#define DLB2_SW_CREDIT_QUANTA_DEFAULT 32 /* Defaut = Worker */ +#define DLB2_SW_CREDIT_P_QUANTA_DEFAULT 256 /* Producer */ +#define DLB2_SW_CREDIT_C_QUANTA_DEFAULT 256 /* Consumer */ #define DLB2_DEPTH_THRESH_DEFAULT 256 /* command line arg strings */ @@ -36,6 +38,7 @@ #define DLB2_COS_ARG "cos" #define DLB2_POLL_INTERVAL_ARG "poll_interval" #define DLB2_SW_CREDIT_QUANTA_ARG "sw_credit_quanta" +#define DLB2_HW_CREDIT_QUANTA_ARG "hw_credit_quanta" #define DLB2_DEPTH_THRESH_ARG "default_depth_thresh" #define DLB2_VECTOR_OPTS_ENAB_ARG "vector_opts_enable" @@ -72,7 +75,9 @@ #define DLB2_MIN_DEQUEUE_TIMEOUT_NS 1 /* Note: "- 1" here to support the timeout range check in eventdev_autotest */ #define DLB2_MAX_DEQUEUE_TIMEOUT_NS (UINT32_MAX - 1) -#define DLB2_SW_CREDIT_BATCH_SZ 32 +#define DLB2_SW_CREDIT_BATCH_SZ 32 /* Default - Worker */ +#define DLB2_SW_CREDIT_P_BATCH_SZ 256 /* Producer */ +#define DLB2_SW_CREDIT_C_BATCH_SZ 256 /* Consumer */ #define DLB2_NUM_SN_GROUPS 2 #define DLB2_MAX_LDB_SN_ALLOC 1024 #define DLB2_MAX_QUEUE_DEPTH_THRESHOLD 8191 @@ -367,6 +372,7 @@ struct dlb2_port { struct dlb2_eventdev *dlb2; /* back ptr */ struct dlb2_eventdev_port *ev_port; /* back ptr */ bool use_scalar; /* force usage of scalar code */ + uint16_t hw_credit_quanta; }; /* Per-process per-port mmio and memory pointers */ @@ -587,6 +593,7 @@ struct dlb2_eventdev { enum dlb2_cq_poll_modes poll_mode; int poll_interval; int sw_credit_quanta; + int hw_credit_quanta; int default_depth_thresh; uint8_t revision; uint8_t version; @@ -622,6 +629,7 @@ struct dlb2_devargs { enum dlb2_cos cos_id; int poll_interval; int sw_credit_quanta; + int hw_credit_quanta; int default_depth_thresh; bool vector_opts_enabled; }; diff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c index e9da89d650..dba6f3d5f7 100644 --- a/drivers/event/dlb2/pf/dlb2_pf.c +++ b/drivers/event/dlb2/pf/dlb2_pf.c @@ -618,6 +618,7 @@ dlb2_eventdev_pci_init(struct rte_eventdev *eventdev) .cos_id = DLB2_COS_DEFAULT, .poll_interval = DLB2_POLL_INTERVAL_DEFAULT, .sw_credit_quanta = DLB2_SW_CREDIT_QUANTA_DEFAULT, + .hw_credit_quanta = DLB2_SW_CREDIT_BATCH_SZ, .default_depth_thresh = DLB2_DEPTH_THRESH_DEFAULT }; struct dlb2_eventdev *dlb2; -- 2.30.2