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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(8936002)(2906002)(26005)(47076005)(7636003)(6666004)(16526019)(4326008)(6286002)(107886003)(356005)(186003)(86362001)(55016002)(8676002)(36756003)(426003)(2616005)(508600001)(36860700001)(82310400003)(7696005)(70586007)(70206006)(36906005)(54906003)(316002)(83380400001)(336012)(5660300002)(6916009)(1076003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2021 09:12:37.4572 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8b3c2fc-74d7-4c9b-5915-08d990851921 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1708 Subject: [dpdk-dev] [PATCH v2 01/13] common/mlx5: support receive queue user index X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" RQ user index is saved in CQE when packet received by RQ. Signed-off-by: Xueming Li --- drivers/common/mlx5/mlx5_prm.h | 8 +++++++- drivers/net/mlx5/mlx5_rxtx_vec_altivec.h | 8 ++++---- drivers/regex/mlx5/mlx5_regex_fastpath.c | 2 +- 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 54e62aa1531..5fd93958ac3 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -393,7 +393,13 @@ struct mlx5_cqe { uint16_t hdr_type_etc; uint16_t vlan_info; uint8_t lro_num_seg; - uint8_t rsvd3[3]; + union { + uint8_t user_index_bytes[3]; + struct { + uint8_t user_index_hi; + uint16_t user_index_low; + } __rte_packed; + }; uint32_t flow_table_metadata; uint8_t rsvd4[4]; uint32_t byte_cnt; diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h index 68cef1a83ed..82586f012cb 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h +++ b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h @@ -974,10 +974,10 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, (vector unsigned short)cqe_tmp1, cqe_sel_mask1); cqe_tmp2 = (vector unsigned char)(vector unsigned long){ *(__rte_aligned(8) unsigned long *) - &cq[pos + p3].rsvd3[9], 0LL}; + &cq[pos + p3].user_index_bytes[9], 0LL}; cqe_tmp1 = (vector unsigned char)(vector unsigned long){ *(__rte_aligned(8) unsigned long *) - &cq[pos + p2].rsvd3[9], 0LL}; + &cq[pos + p2].user_index_bytes[9], 0LL}; cqes[3] = (vector unsigned char) vec_sel((vector unsigned short)cqes[3], (vector unsigned short)cqe_tmp2, @@ -1037,10 +1037,10 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, (vector unsigned short)cqe_tmp1, cqe_sel_mask1); cqe_tmp2 = (vector unsigned char)(vector unsigned long){ *(__rte_aligned(8) unsigned long *) - &cq[pos + p1].rsvd3[9], 0LL}; + &cq[pos + p1].user_index_bytes[9], 0LL}; cqe_tmp1 = (vector unsigned char)(vector unsigned long){ *(__rte_aligned(8) unsigned long *) - &cq[pos].rsvd3[9], 0LL}; + &cq[pos].user_index_bytes[9], 0LL}; cqes[1] = (vector unsigned char) vec_sel((vector unsigned short)cqes[1], (vector unsigned short)cqe_tmp2, cqe_sel_mask2); diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c index 0833b2817e2..e51e632c1f8 100644 --- a/drivers/regex/mlx5/mlx5_regex_fastpath.c +++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c @@ -571,7 +571,7 @@ mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, uint16_t wq_counter = (rte_be_to_cpu_16(cqe->wqe_counter) + 1) & MLX5_REGEX_MAX_WQE_INDEX; - size_t hw_qpid = cqe->rsvd3[2]; + size_t hw_qpid = cqe->user_index_bytes[2]; struct mlx5_regex_hw_qp *qp_obj = &queue->qps[hw_qpid]; /* UMR mode WQE counter move as WQE set(4 WQEBBS).*/ -- 2.33.0