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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT057.mail.protection.outlook.com (10.13.172.252) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4628.16 via Frontend Transport; Fri, 22 Oct 2021 15:47:38 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 22 Oct 2021 15:47:36 +0000 From: Francis Kelly To: , Ori Kam CC: , , Date: Fri, 22 Oct 2021 15:45:52 +0000 Message-ID: <20211022154600.2180938-2-fkelly@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022154600.2180938-1-fkelly@nvidia.com> References: <20211022154600.2180938-1-fkelly@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 42fd75e3-9ddc-458f-ac1f-08d99573466a X-MS-TrafficTypeDiagnostic: BN9PR12MB5114: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:19; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(1076003)(16526019)(186003)(6636002)(508600001)(70206006)(47076005)(4326008)(26005)(2616005)(2906002)(36756003)(356005)(6666004)(426003)(5660300002)(8936002)(7636003)(70586007)(336012)(82310400003)(316002)(55016002)(7696005)(110136005)(36906005)(6286002)(36860700001)(83380400001)(8676002)(54906003)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2021 15:47:38.3610 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42fd75e3-9ddc-458f-ac1f-08d99573466a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT057.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5114 Subject: [dpdk-dev] [PATCH 02/10] regex/mlx5: add cleanup code X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ori Kam When stopping the device we should release all data allocated. This commit add this cleanup logic. Signed-off-by: Ori Kam --- drivers/regex/mlx5/mlx5_regex.c | 14 ++++++++++++++ drivers/regex/mlx5/mlx5_regex.h | 1 + drivers/regex/mlx5/mlx5_regex_control.c | 20 ++++++++++++++++++++ drivers/regex/mlx5/mlx5_rxp.c | 4 ++-- 4 files changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c index 2124fd15f0..b7175ff8e9 100644 --- a/drivers/regex/mlx5/mlx5_regex.c +++ b/drivers/regex/mlx5/mlx5_regex.c @@ -48,6 +48,20 @@ mlx5_regex_start(struct rte_regexdev *dev __rte_unused) int mlx5_regex_stop(struct rte_regexdev *dev __rte_unused) { + struct mlx5_regex_priv *priv = dev->data->dev_private; + uint32_t i; + + mlx5_regex_clean_ctrl(dev); + rte_free(priv->qps); + priv->qps = NULL; + + for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) { + if (priv->db[i].umem.umem) + mlx5_glue->devx_umem_dereg(priv->db[i].umem.umem); + rte_free(priv->db[i].ptr); + priv->db[i].ptr = NULL; + } + return 0; } diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h index 2242d250a3..329768980d 100644 --- a/drivers/regex/mlx5/mlx5_regex.h +++ b/drivers/regex/mlx5/mlx5_regex.h @@ -125,6 +125,7 @@ int mlx5_devx_regex_database_program(void *ctx, uint8_t engine, /* mlx5_regex_control.c */ int mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind, const struct rte_regexdev_qp_conf *cfg); +void mlx5_regex_clean_ctrl(struct rte_regexdev *dev); /* mlx5_regex_fastpath.c */ int mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id); diff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c index 572ecc6d86..1783df923c 100644 --- a/drivers/regex/mlx5/mlx5_regex_control.c +++ b/drivers/regex/mlx5/mlx5_regex_control.c @@ -271,3 +271,23 @@ mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind, rte_free(qp->qps); return ret; } + +void +mlx5_regex_clean_ctrl(struct rte_regexdev *dev) +{ + struct mlx5_regex_priv *priv = dev->data->dev_private; + struct mlx5_regex_qp *qp; + int qp_ind; + int i; + + if (!priv->qps) + return; + for (qp_ind = 0; qp_ind < priv->nb_queues; qp_ind++) { + qp = &priv->qps[qp_ind]; + mlx5_regexdev_teardown_fastpath(priv, qp_ind); + mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh); + for (i = 0; i < qp->nb_obj; i++) + regex_ctrl_destroy_hw_qp(qp, i); + regex_ctrl_destroy_cq(&qp->cq); + } +} diff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c index 380037e24c..5afdcb35cc 100644 --- a/drivers/regex/mlx5/mlx5_rxp.c +++ b/drivers/regex/mlx5/mlx5_rxp.c @@ -776,10 +776,10 @@ rxp_db_setup(struct mlx5_regex_priv *priv) return 0; tidyup_error: for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) { - if (priv->db[i].ptr) - rte_free(priv->db[i].ptr); if (priv->db[i].umem.umem) mlx5_glue->devx_umem_dereg(priv->db[i].umem.umem); + rte_free(priv->db[i].ptr); + priv->db[i].ptr = NULL; } return -ret; } -- 2.25.1