From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6D848A0C45; Mon, 25 Oct 2021 10:47:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7D1F94113F; Mon, 25 Oct 2021 10:47:13 +0200 (CEST) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2044.outbound.protection.outlook.com [40.107.92.44]) by mails.dpdk.org (Postfix) with ESMTP id BF4EF41123; Mon, 25 Oct 2021 10:47:09 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=csoM4ibgbs2MbkP+zp6fsLvRFgCtgDyATnpynXssRf/ETYS4MZ4Rxw+Hs9FjAfI/NqyHCwwEIysTXa3ON0dVQ66g2DJFiZS41iceXpJjqzmIeegblBdzQTgNnugi5FfOmMfTPZkPp0xyeHOyxlWNmeABmXvG6tIaIJbvJ1cDDNWYScrDuBGjOlBN8XEqTKTbV7QBpoABBYvGJ2FkBJuCd9sP3wSdnl+1y3/G80bdG16twg82OKSFle4Bm2er6PpcQldy802d3Qwk0TB2B8IFOweyrEn/qBdOj0UIh9lloHZBn4W+5n2tEVXgdf8BR14ZqTAO630fVt8rgBgEW5dXpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dVbFDznNiO6Iw1FWfOTlyq1jPT9+P0otYwaNWDB+yK8=; b=aRZfl4XRxHWRCG/lkKcowdPCy9/AyFaxESHWLfywRqs1jB35e+9vVNClQ8cicbr6oMvQ8t0fs8vd/G1jUNnzpuWPTN9v7bWoqrB5oXYbh8LFh7uqOpk202KXGlndKmLYunVGu3VFnRNsYdcQ0Q33+Ba9pqMPS3U3o/mlR2aZN1HAv7SCK1tsZ5/WFE7N8e32pU8cq/1+k1SwZxWzjfNEqvht7nTckuJbtdTj29oVWSZ2EoF+OFkVeTkE3K9F00nnNWRkJfztNbzFn/Msl2DfqZY00fRpg5UsSC5tz19CE29Zax391hsKCwfrp5EUSikei1zr0PV7yIbAlqO1nW9SVg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dVbFDznNiO6Iw1FWfOTlyq1jPT9+P0otYwaNWDB+yK8=; b=GmYFmhpODZsOegdsQuGOmWkArLCWuhgaue671QAdOPS3B1ge+jsy4e4R+k9DDBn7pRx3l86oI5/cBeOfA9C5zn3vEgxJ67kCgexW8ssYO73S3hDa6kunhrB2TbqLdlsvPG5N/gPoUvEmgxvsx4gSdM0dA/6dhJ5KupnrHL3mGnp8bn4c2YdYpZxZM3gpmjWJ9lPQLcdc2AgLokRjG3Kt7z775G/lt07RYfoBKlDEZRFpWU+W78h2vRyH07rLz4KXXilYzmRsFZ/c991NlO2+Q8afrxQ27j5zON7v6lqWrGYo45NhclQ7jbJY2omippjKJUFFdY9LhnjL6vf4KdfWFg== Received: from MW4PR03CA0133.namprd03.prod.outlook.com (2603:10b6:303:8c::18) by CH2PR12MB4921.namprd12.prod.outlook.com (2603:10b6:610:62::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.16; Mon, 25 Oct 2021 08:47:08 +0000 Received: from CO1NAM11FT030.eop-nam11.prod.protection.outlook.com (2603:10b6:303:8c:cafe::42) by MW4PR03CA0133.outlook.office365.com (2603:10b6:303:8c::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18 via Frontend Transport; Mon, 25 Oct 2021 08:47:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT030.mail.protection.outlook.com (10.13.174.125) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4628.16 via Frontend Transport; Mon, 25 Oct 2021 08:47:07 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 25 Oct 2021 08:47:05 +0000 From: Tal Shnaiderman To: CC: , , , , , , , , Date: Mon, 25 Oct 2021 11:46:15 +0300 Message-ID: <20211025084617.4952-4-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20211025084617.4952-1-talshn@nvidia.com> References: <20211017094133.18988-2-talshn@nvidia.com> <20211025084617.4952-1-talshn@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: dfb4e281-8724-4bc1-e481-08d99794072b X-MS-TrafficTypeDiagnostic: CH2PR12MB4921: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zq9x2cchQWHji+F4CrHjamzfpqzu/MVARUC4QCtaY8Su5GcsVa2YCP7SclECWvPuUk+EVpSi+sVaRgrUNMHvJ7rpREwwIa3ynut42F9NfMMsNRj/rXdcwuQ5c4GSXQzssBj0nRrPvhpzb7sbS/b8tUgAkpj+9OklVgbPBcTaBzyFIqrgRYz+FY3fvfmm4WdfwWCEYlAlqe5r1GuNyGafjTOPUcamD3B8FS/edqBoXutjP3M0kuBV5mpHoM2Cjezb970YOD0hgsrsd+RulKmlOLFLniH2/t0FatejzmIyKXmSaOR6eIRzPu4xmjYjATIBJAFK0QFXaMyWZHLJZ+iXyIcxcoujIkArbL3ftYZvIYVHZDbI5IcsmB/4lM5YRbExOMhIdShJ2qxW40w21a0Mf3qyik67E1npxlsuLvvgg2CEaDmjrDAj+a0JtPJx0iXfKOvARbNSuRwNYD6bY6qZiM04MlxRXyHgwQp8aTNXh7tz6YvGAjl5cxPcvpz+kE2LXsHS0q64UfYv76RZdPpVJgzP0W7cWGCiodqg2VDX4Fq/24Vd+YNLdkDm4Yr5bEUy+97L3OwVCyPDnn6dU017u0RmgmTQDhO8mSGMosYnT2QE7YkUXksSTFfQDyGzy2blg1hXSyB2+tYpfGrowu4b6BsSwK3gLNiKL8jqu0l3p52eD4uVF8KpUemcQ3FjhQeGsaD/SrU9mIwrrbJvUhqwew== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(2906002)(7636003)(36906005)(1076003)(54906003)(47076005)(5660300002)(70586007)(70206006)(8936002)(336012)(82310400003)(36860700001)(316002)(6666004)(16526019)(6286002)(186003)(86362001)(36756003)(55016002)(7696005)(2616005)(508600001)(8676002)(83380400001)(356005)(26005)(426003)(4326008)(6916009); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2021 08:47:07.9907 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dfb4e281-8724-4bc1-e481-08d99794072b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4921 Subject: [dpdk-dev] [PATCH v3 3/5] crypto/mlx5: fix size of UMR WQE X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The size of the UMR WQE allocated object is decided by a sizof operation on the struct, however since the struct contains a union of flexible array members this sizeof results can differ between compilers. GCC for example treats the union as 0 sized, MSVC adds a padding of 16Bits. To resolve the ambiguity the allocation size will be calculated by the sizes of the members excluding the flexible union. Fixes: a1978aa23bf4 ("crypto/mlx5: add maximum segments configuration") Cc: stable@dpdk.org Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/crypto/mlx5/mlx5_crypto.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 6bebc83c39..07c2a9c68b 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -909,7 +909,9 @@ mlx5_crypto_dev_probe(struct mlx5_common_device *cdev) priv->keytag = rte_cpu_to_be_64(devarg_prms.keytag); priv->max_segs_num = devarg_prms.max_segs_num; priv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) + - sizeof(struct mlx5_umr_wqe) + + sizeof(struct mlx5_wqe_cseg) + + sizeof(struct mlx5_wqe_umr_cseg) + + sizeof(struct mlx5_wqe_mkey_cseg) + RTE_ALIGN(priv->max_segs_num, 4) * sizeof(struct mlx5_wqe_dseg); rdmw_wqe_size = sizeof(struct mlx5_rdma_write_wqe) + -- 2.16.1.windows.4