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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(26005)(7696005)(1076003)(186003)(8676002)(47076005)(16526019)(8936002)(316002)(450100002)(6916009)(6666004)(55016002)(86362001)(82310400003)(5660300002)(70586007)(6286002)(36756003)(70206006)(2616005)(7636003)(508600001)(426003)(36860700001)(4326008)(336012)(83380400001)(356005)(2906002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Oct 2021 01:53:05.9856 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c56478b1-6352-42a4-16e5-08d998235aa2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3480 Subject: [dpdk-dev] [PATCH 1/2] compress/mlx5: fix level configuration in compress X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The mlx5 compress PMD uses HW acceleration for the compress operations. The mlx5 HW device has no level style mode, which does a tradeoff between throughput and compression ratio, unlike SW drivers where the CPU is doing the compress, and more CPU effort can cause a better compression ratio. The mlx5 driver wrongly defined the Huffman block size configuration according to the level that doesn't fill the level API requirement for the tradeoff. Remove the effect of the level configuration in compress operation. Fixes: 237aad88245b ("compress/mlx5: fix compression level translation") Fixes: 39a2c8715f8f ("compress/mlx5: add transformation operations") Cc: stable@dpdk.org Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- drivers/compress/mlx5/mlx5_compress.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index c4081c5f7d..9adc0e41e0 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -343,21 +343,9 @@ mlx5_compress_xform_create(struct rte_compressdev *dev, xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size), MLX5_COMP_MAX_WIN_SIZE_CONF) << WQE_GGA_COMP_WIN_SIZE_OFFSET; - switch (xform->compress.level) { - case RTE_COMP_LEVEL_PMD_DEFAULT: - size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; - break; - case RTE_COMP_LEVEL_MAX: - size = priv->min_block_size; - break; - default: - size = RTE_MAX(MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX - + 1 - xform->compress.level, - priv->min_block_size); - } - xfrm->gga_ctrl1 += RTE_MIN(size, - MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) << - WQE_GGA_COMP_BLOCK_SIZE_OFFSET; + size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; + xfrm->gga_ctrl1 += size << + WQE_GGA_COMP_BLOCK_SIZE_OFFSET; xfrm->opcode += MLX5_OPC_MOD_MMO_COMP << WQE_CSEG_OPC_MOD_OFFSET; size = xform->compress.deflate.huffman == -- 2.17.1