From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 16456A0C47; Wed, 27 Oct 2021 17:08:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E28BA40DDA; Wed, 27 Oct 2021 17:08:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 06AEA410DD; Tue, 26 Oct 2021 14:02:19 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19QAMn7N014732; Tue, 26 Oct 2021 05:02:19 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=f+WHHJd53Pq1/YnL/wruOvy6DyCi8HAOZevh0BKAE+k=; b=SPfbYstxP1dTK8vYZlLXE/qKLNoDBoBSXzik+HxfZmN10QkD/Rs0t6I+A6L0Hu8zhwCZ Im8sT0xoJnxj+HpeoXBZO+bkB8r2WalJrwTz0ODtOYcZYWNGHe8O506xaHF9uqY9f3Mv xJchqfYml8Xgs8Ew4AufU+kFDmmS5dOayP0IrOLdqY9+c0OsA31Vu81z+bGVKVPKHgMQ 7RvK1WgzMgghPm7hlEydK3b70Yv6ihMFWPdzfZlssu2He9pCihVzC1U6v5/KqW8So90+ XzCoUxxSzcrwUkxT5jDAxyaW3NqFuw08HnDo13gH16s4p8N5tJfLOx5qNbaERyNGOaDf iw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 3bxfv8gd2b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 26 Oct 2021 05:02:18 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 26 Oct 2021 05:02:17 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 26 Oct 2021 05:02:17 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 381113F7082; Tue, 26 Oct 2021 05:02:14 -0700 (PDT) From: Volodymyr Fialko To: , Ashwin Sekhar T K , Pavan Nikhilesh CC: , Volodymyr Fialko , Date: Tue, 26 Oct 2021 14:01:22 +0200 Message-ID: <20211026120122.2420536-1-vfialko@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: mDcUI5DTW8nO_9ab6eLDfa0vRzz3ta_f X-Proofpoint-ORIG-GUID: mDcUI5DTW8nO_9ab6eLDfa0vRzz3ta_f X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-26_02,2021-10-26_01,2020-04-07_01 X-Mailman-Approved-At: Wed, 27 Oct 2021 17:08:05 +0200 Subject: [dpdk-dev] [PATCH] mempool/cnxk: fix max pools argument parsing X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" roc_idev_npa_maxpools_set expects max_pools original value, not the aura Fixes: 0a50a5aad299 ("mempool/cnxk: add device probe/remove") Cc: stable@dpdk.org Signed-off-by: Volodymyr Fialko Reviewed-by: Jerin Jacob --- drivers/mempool/cnxk/cnxk_mempool.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/mempool/cnxk/cnxk_mempool.c b/drivers/mempool/cnxk/cnxk_mempool.c index dc36be54f6..828bf3fc36 100644 --- a/drivers/mempool/cnxk/cnxk_mempool.c +++ b/drivers/mempool/cnxk/cnxk_mempool.c @@ -31,25 +31,25 @@ npa_aura_size_to_u32(uint8_t val) } static int -parse_max_pools(const char *key, const char *value, void *extra_args) +parse_max_pools_handler(const char *key, const char *value, void *extra_args) { RTE_SET_USED(key); uint32_t val; - val = atoi(value); + val = rte_align32pow2(atoi(value)); if (val < npa_aura_size_to_u32(NPA_AURA_SZ_128)) val = 128; if (val > npa_aura_size_to_u32(NPA_AURA_SZ_1M)) val = BIT_ULL(20); - *(uint8_t *)extra_args = rte_log2_u32(val) - 6; + *(uint32_t *)extra_args = val; return 0; } -static inline uint8_t -parse_aura_size(struct rte_devargs *devargs) +static inline uint32_t +parse_max_pools(struct rte_devargs *devargs) { - uint8_t aura_sz = NPA_AURA_SZ_128; + uint32_t max_pools = npa_aura_size_to_u32(NPA_AURA_SZ_128); struct rte_kvargs *kvlist; if (devargs == NULL) @@ -58,11 +58,11 @@ parse_aura_size(struct rte_devargs *devargs) if (kvlist == NULL) goto exit; - rte_kvargs_process(kvlist, CNXK_NPA_MAX_POOLS_PARAM, &parse_max_pools, - &aura_sz); + rte_kvargs_process(kvlist, CNXK_NPA_MAX_POOLS_PARAM, + &parse_max_pools_handler, &max_pools); rte_kvargs_free(kvlist); exit: - return aura_sz; + return max_pools; } static inline char * @@ -92,7 +92,7 @@ npa_init(struct rte_pci_device *pci_dev) dev = mz->addr; dev->pci_dev = pci_dev; - roc_idev_npa_maxpools_set(parse_aura_size(pci_dev->device.devargs)); + roc_idev_npa_maxpools_set(parse_max_pools(pci_dev->device.devargs)); rc = roc_npa_dev_init(dev); if (rc) goto mz_free; -- 2.25.1