From: Pradeep Nalla <pnalla@marvell.com>
To: Nalla Pradeep <pnalla@marvell.com>,
Radha Mohan Chintakuntla <radhac@marvell.com>,
Veerasenareddy Burru <vburru@marvell.com>
Cc: <jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>
Subject: [dpdk-dev] [PATCH] net/octeontx_ep: Remove otx2 common dependency
Date: Tue, 26 Oct 2021 08:39:33 -0700 [thread overview]
Message-ID: <20211026153933.15467-1-pnalla@marvell.com> (raw)
octeontx_ep driver's dependency on octeontx2 common code is
removed as going forward ep driver will include files from
its own path.
Signed-off-by: Pradeep Nalla <pnalla@marvell.com>
---
drivers/net/octeontx_ep/meson.build | 2 -
drivers/net/octeontx_ep/otx2_ep_vf.c | 13 +--
drivers/net/octeontx_ep/otx2_ep_vf.h | 112 ++++++++++++++++++++++++
drivers/net/octeontx_ep/otx_ep_common.h | 3 +
drivers/net/octeontx_ep/otx_ep_ethdev.c | 1 -
5 files changed, 122 insertions(+), 9 deletions(-)
diff --git a/drivers/net/octeontx_ep/meson.build b/drivers/net/octeontx_ep/meson.build
index 89f88caff0..b15646b82a 100644
--- a/drivers/net/octeontx_ep/meson.build
+++ b/drivers/net/octeontx_ep/meson.build
@@ -2,7 +2,6 @@
# Copyright(C) 2021 Marvell.
#
-deps += ['common_octeontx2']
sources = files(
'otx_ep_ethdev.c',
'otx_ep_rxtx.c',
@@ -10,4 +9,3 @@ sources = files(
'otx2_ep_vf.c',
)
-includes += include_directories('../../common/octeontx2')
diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.c b/drivers/net/octeontx_ep/otx2_ep_vf.c
index 64cd8731d3..0716beb9b1 100644
--- a/drivers/net/octeontx_ep/otx2_ep_vf.c
+++ b/drivers/net/octeontx_ep/otx2_ep_vf.c
@@ -2,7 +2,8 @@
* Copyright(C) 2021 Marvell.
*/
-#include "otx2_common.h"
+#include <rte_common.h>
+#include <rte_cycles.h>
#include "otx_ep_common.h"
#include "otx2_ep_vf.h"
@@ -215,7 +216,7 @@ otx2_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
- otx2_info("IQ[%d] enable done", q_no);
+ otx_ep_info("IQ[%d] enable done", q_no);
return 0;
}
@@ -229,7 +230,7 @@ otx2_vf_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
reg_val |= 0x1ull;
otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
- otx2_info("OQ[%d] enable done", q_no);
+ otx_ep_info("OQ[%d] enable done", q_no);
return 0;
}
@@ -326,10 +327,10 @@ otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)
if (otx_ep->conf == NULL) {
otx_ep->conf = otx2_ep_get_defconf(otx_ep);
if (otx_ep->conf == NULL) {
- otx2_err("SDP VF default config not found");
+ otx_ep_err("SDP VF default config not found");
return -ENOENT;
}
- otx2_info("Default config is used");
+ otx_ep_info("Default config is used");
}
/* Get IOQs (RPVF] count */
@@ -338,7 +339,7 @@ otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)
otx_ep->sriov_info.rings_per_vf = ((reg_val >> SDP_VF_R_IN_CTL_RPVF_POS)
& SDP_VF_R_IN_CTL_RPVF_MASK);
- otx2_info("SDP RPVF: %d", otx_ep->sriov_info.rings_per_vf);
+ otx_ep_info("SDP RPVF: %d", otx_ep->sriov_info.rings_per_vf);
otx_ep->fn_list.setup_iq_regs = otx2_vf_setup_iq_regs;
otx_ep->fn_list.setup_oq_regs = otx2_vf_setup_oq_regs;
diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.h b/drivers/net/octeontx_ep/otx2_ep_vf.h
index 5e5aefbc1c..9326925025 100644
--- a/drivers/net/octeontx_ep/otx2_ep_vf.h
+++ b/drivers/net/octeontx_ep/otx2_ep_vf.h
@@ -4,6 +4,118 @@
#ifndef _OTX2_EP_VF_H_
#define _OTX2_EP_VF_H_
+#include <rte_io.h>
+
+#define SDP_VF_R_IN_CTL_IDLE (0x1ull << 28)
+#define SDP_VF_R_IN_CTL_RDSIZE (0x3ull << 25) /* Setting to max(4) */
+#define SDP_VF_R_IN_CTL_IS_64B (0x1ull << 24)
+#define SDP_VF_R_IN_CTL_ESR (0x1ull << 1)
+
+#define SDP_VF_BUSY_LOOP_COUNT (10000)
+
+/* SDP VF OQ Masks */
+#define SDP_VF_R_OUT_CTL_IDLE (1ull << 40)
+#define SDP_VF_R_OUT_CTL_ES_I (1ull << 34)
+#define SDP_VF_R_OUT_CTL_NSR_I (1ull << 33)
+#define SDP_VF_R_OUT_CTL_ROR_I (1ull << 32)
+#define SDP_VF_R_OUT_CTL_ES_D (1ull << 30)
+#define SDP_VF_R_OUT_CTL_NSR_D (1ull << 29)
+#define SDP_VF_R_OUT_CTL_ROR_D (1ull << 28)
+#define SDP_VF_R_OUT_CTL_ES_P (1ull << 26)
+#define SDP_VF_R_OUT_CTL_NSR_P (1ull << 25)
+#define SDP_VF_R_OUT_CTL_ROR_P (1ull << 24)
+#define SDP_VF_R_OUT_CTL_IMODE (1ull << 23)
+
+/* SDP VF Register definitions */
+#define SDP_VF_RING_OFFSET (0x1ull << 17)
+
+/* SDP VF IQ Registers */
+#define SDP_VF_R_IN_CONTROL_START (0x10000)
+#define SDP_VF_R_IN_ENABLE_START (0x10010)
+#define SDP_VF_R_IN_INSTR_BADDR_START (0x10020)
+#define SDP_VF_R_IN_INSTR_RSIZE_START (0x10030)
+#define SDP_VF_R_IN_INSTR_DBELL_START (0x10040)
+#define SDP_VF_R_IN_CNTS_START (0x10050)
+#define SDP_VF_R_IN_INT_LEVELS_START (0x10060)
+#define SDP_VF_R_IN_PKT_CNT_START (0x10080)
+#define SDP_VF_R_IN_BYTE_CNT_START (0x10090)
+
+#define SDP_VF_R_IN_CONTROL(ring) \
+ (SDP_VF_R_IN_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_IN_ENABLE(ring) \
+ (SDP_VF_R_IN_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_IN_INSTR_BADDR(ring) \
+ (SDP_VF_R_IN_INSTR_BADDR_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_IN_INSTR_RSIZE(ring) \
+ (SDP_VF_R_IN_INSTR_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_IN_INSTR_DBELL(ring) \
+ (SDP_VF_R_IN_INSTR_DBELL_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_IN_CNTS(ring) \
+ (SDP_VF_R_IN_CNTS_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_IN_INT_LEVELS(ring) \
+ (SDP_VF_R_IN_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_IN_PKT_CNT(ring) \
+ (SDP_VF_R_IN_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_IN_BYTE_CNT(ring) \
+ (SDP_VF_R_IN_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
+
+/* SDP VF OQ Registers */
+#define SDP_VF_R_OUT_CNTS_START (0x10100)
+#define SDP_VF_R_OUT_INT_LEVELS_START (0x10110)
+#define SDP_VF_R_OUT_SLIST_BADDR_START (0x10120)
+#define SDP_VF_R_OUT_SLIST_RSIZE_START (0x10130)
+#define SDP_VF_R_OUT_SLIST_DBELL_START (0x10140)
+#define SDP_VF_R_OUT_CONTROL_START (0x10150)
+#define SDP_VF_R_OUT_ENABLE_START (0x10160)
+#define SDP_VF_R_OUT_PKT_CNT_START (0x10180)
+#define SDP_VF_R_OUT_BYTE_CNT_START (0x10190)
+
+#define SDP_VF_R_OUT_CONTROL(ring) \
+ (SDP_VF_R_OUT_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_OUT_ENABLE(ring) \
+ (SDP_VF_R_OUT_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_OUT_SLIST_BADDR(ring) \
+ (SDP_VF_R_OUT_SLIST_BADDR_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_OUT_SLIST_RSIZE(ring) \
+ (SDP_VF_R_OUT_SLIST_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_OUT_SLIST_DBELL(ring) \
+ (SDP_VF_R_OUT_SLIST_DBELL_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_OUT_CNTS(ring) \
+ (SDP_VF_R_OUT_CNTS_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_OUT_INT_LEVELS(ring) \
+ (SDP_VF_R_OUT_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_OUT_PKT_CNT(ring) \
+ (SDP_VF_R_OUT_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
+
+#define SDP_VF_R_OUT_BYTE_CNT(ring) \
+ (SDP_VF_R_OUT_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
+
+/* SDP VF IQ Masks */
+#define SDP_VF_R_IN_CTL_RPVF_MASK (0xF)
+#define SDP_VF_R_IN_CTL_RPVF_POS (48)
+
+/* IO Access */
+#define otx2_read64(addr) rte_read64_relaxed((void *)(addr))
+#define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))
+
+#define PCI_DEVID_OCTEONTX2_EP_NET_VF 0xB203 /* OCTEON TX2 EP mode */
+#define PCI_DEVID_CN98XX_EP_NET_VF 0xB103
+
int
otx2_ep_vf_setup_device(struct otx_ep_device *sdpvf);
diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h
index 5d0b30a1f0..fd5e8ed263 100644
--- a/drivers/net/octeontx_ep/otx_ep_common.h
+++ b/drivers/net/octeontx_ep/otx_ep_common.h
@@ -504,5 +504,8 @@ struct otx_ep_buf_free_info {
#define OTX_EP_CLEAR_SLIST_DBELL 0xFFFFFFFF
#define OTX_EP_CLEAR_SDP_OUT_PKT_CNT 0xFFFFFFFFF
+/* PCI IDs */
+#define PCI_VENDOR_ID_CAVIUM 0x177D
+
extern int otx_net_ep_logtype;
#endif /* _OTX_EP_COMMON_H_ */
diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c
index 698d22e226..5e371595a5 100644
--- a/drivers/net/octeontx_ep/otx_ep_ethdev.c
+++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c
@@ -4,7 +4,6 @@
#include <ethdev_pci.h>
-#include "otx2_common.h"
#include "otx_ep_common.h"
#include "otx_ep_vf.h"
#include "otx2_ep_vf.h"
--
2.17.1
next reply other threads:[~2021-10-26 15:40 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-26 15:39 Pradeep Nalla [this message]
2021-10-29 14:16 ` Jerin Jacob
2021-10-28 4:11 Pradeep Nalla
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