From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 25DF9A0547; Tue, 26 Oct 2021 17:57:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7B63D4114F; Tue, 26 Oct 2021 17:57:22 +0200 (CEST) Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) by mails.dpdk.org (Postfix) with ESMTP id 2469741134 for ; Tue, 26 Oct 2021 17:57:21 +0200 (CEST) Received: by mail-pj1-f46.google.com with SMTP id u6-20020a17090a3fc600b001a00250584aso2659886pjm.4 for ; Tue, 26 Oct 2021 08:57:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vvdntech-in.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bgeuoJKYE6GkkRtXEfkWXyO7lLTLWDDHFw43FyCdnlE=; b=kByRlWgTzgFB1MBkzjounenYFrM4daDtCC6xEhKbGrFMK6tv6NnFoBOpwf3xIlpkbu M8yfP0n+EnpMmimqBADUrpbk4o6WktD6U+JCDApm9bybAR4XoKKBb/92zyk9oJhz4n0H +dXa91IJeZO9zBac9Qv/QTFgsIz7+H+bSL2WZc4ZUt3DF+4ZE1leJZIkFVu6KTqTH3gG ofKqsWkHRw2OHtSWx1v/62GSz4y0O6qTmWobGMRhECllPYXSJbV8QHnTW9MF6YwFTMPr smd8HsGcdGLr7peNOQh7VE2T9Umo4PLVl/PWfKGDhYvzqD/FyU6hOULqAElwK9fM642c kTZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bgeuoJKYE6GkkRtXEfkWXyO7lLTLWDDHFw43FyCdnlE=; b=sgVWRxHsmisJlaJgnkE3osVQgpvtEmNFztR7wjyidS5bmjBIzzFqOmQWmeeJhveGSX R7Cw8/grQaukzXQ4EiR84FwwQhH3ANhMyBFEYSqAidOGZwxbCzR9TKOm5TPWzLGxTBJ6 xFPvUBdKVaawlIq75XF+QRyN0cBT3PNHCAtVzQhoZy36UgMrsXjly+B2FTKbYr9CzaEJ gf9NJLfDdIWq+oQ6CJpkD2bVCMvVSJFPcMIMtl7YFGCgV7z8Vjwf2dwE2J9HxYiyny/i m5Bu441T6tOr+tIyneinFEWOZEUULVuJNHEbZVwWqzAzc9FAhbA1CnR3Z/wKIJswe9m2 KzCw== X-Gm-Message-State: AOAM531tot0RAMegl1rNxwZGXomPv4UZuiTPuzbS/f+3qWRRzZ5YcHq/ lq4W9QRoZZkYshU8zvfC0goNWTa8ZwUaBlvl X-Google-Smtp-Source: ABdhPJzyUewkx3zaYjTn8ws5TGtMXTZg/lfB+Gkg8PTSP8UdWZ7X/N5A2ouOimc/U1HXG2xFquv53Q== X-Received: by 2002:a17:902:b593:b0:12d:7aa5:de2d with SMTP id a19-20020a170902b59300b0012d7aa5de2dmr23609491pls.31.1635263840000; Tue, 26 Oct 2021 08:57:20 -0700 (PDT) Received: from 470--5GDC--BLR.blore.vvdntech.com ([106.51.39.131]) by smtp.gmail.com with ESMTPSA id b8sm24649824pfv.56.2021.10.26.08.57.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Oct 2021 08:57:19 -0700 (PDT) From: Aman Kumar To: dev@dpdk.org Cc: thomas@monjalon.net, viacheslavo@nvidia.com, anatoly.burakov@intel.com, keesang.song@amd.com, aman.kumar@vvdntech.in, jerinjacobk@gmail.com, konstantin.ananyev@intel.com, bruce.richardson@intel.com Date: Tue, 26 Oct 2021 21:26:44 +0530 Message-Id: <20211026155645.246783-2-aman.kumar@vvdntech.in> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211026155645.246783-1-aman.kumar@vvdntech.in> References: <20211019104724.19416-1-aman.kumar@vvdntech.in> <20211026155645.246783-1-aman.kumar@vvdntech.in> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v3 2/3] doc/guides: add dpdk build instruction for AMD platforms X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" linux guide updated with AMD platform related build instructions. Signed-off-by: Aman Kumar --- doc/guides/linux_gsg/build_dpdk.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/doc/guides/linux_gsg/build_dpdk.rst b/doc/guides/linux_gsg/build_dpdk.rst index 0b08492ca2..3110448467 100644 --- a/doc/guides/linux_gsg/build_dpdk.rst +++ b/doc/guides/linux_gsg/build_dpdk.rst @@ -113,6 +113,10 @@ The instruction set will be set automatically by default according to these rule To override what instruction set will be used, set the ``cpu_instruction_set`` parameter to the instruction set of your choice (such as ``corei7``, ``power8``, etc.). +To build dpdk for AMD Zen CPU based platforms, pass ``-Dcpu_instruction_set=`` +to meson when configuring the build folder initially. Supported options are znver1, +znver2 and znver3. + ``cpu_instruction_set`` is not used in Arm builds, as setting the instruction set without other parameters leads to inferior builds. The way to tailor Arm builds is to build for a SoC using ``-Dplatform=`` mentioned above. -- 2.25.1