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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(36756003)(47076005)(356005)(316002)(426003)(2616005)(508600001)(4744005)(7696005)(6666004)(1076003)(55016002)(4326008)(70206006)(70586007)(8936002)(36860700001)(6286002)(82310400003)(83380400001)(6916009)(107886003)(26005)(2906002)(336012)(86362001)(5660300002)(186003)(8676002)(7636003)(16526019); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 13:59:15.5572 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e17f8096-b79f-42b4-c6e0-08d99a1b20e9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT016.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1871 Subject: [dpdk-dev] [PATCH 1/2] common/mlx5: fix HCA cap PRM alignment X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 0x20 reserved bytes were missed in the HCA cap PRM structure before the newly added fields for MMO QP capabilities. That caused reading MMO QP caps incorrectly. Add the reserved fields in the HCA cap structure. Fixes: cbc4c13a255e ("common/mlx5: update MMO HCA capabilities") Signed-off-by: Raja Zidane --- drivers/common/mlx5/mlx5_prm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index eab80eaead..f14727877c 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1636,7 +1636,7 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 num_vhca_ports[0x8]; u8 reserved_at_618[0x6]; u8 sw_owner_id[0x1]; - u8 reserved_at_61f[0x109]; + u8 reserved_at_61f[0x129]; u8 dma_mmo_qp[0x1]; u8 regexp_mmo_qp[0x1]; u8 compress_mmo_qp[0x1]; -- 2.17.1