From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 49C70A0C57; Mon, 1 Nov 2021 09:52:39 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DFF0841125; Mon, 1 Nov 2021 09:52:17 +0100 (CET) Received: from EUR02-VE1-obe.outbound.protection.outlook.com (mail-eopbgr20087.outbound.protection.outlook.com [40.107.2.87]) by mails.dpdk.org (Postfix) with ESMTP id 1023F41125 for ; Mon, 1 Nov 2021 09:52:16 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=n0j1SwFBGGYYPJbc+7iOsirlJ957qWaZKe6T50QMOWo2m//P8PkMRKy9Fx5fpI6Kesrk9nybvP7TGAsB0BjeNG9PN5cSqGUS8mtucRcori5a8HtopEUjh5YRnRmHRpEfE5yvu30M45VQeLPGVSaP3l2gHL1nZLYyVrG1Kh8cDeuym9zcZgv998XIOM/e2NRK+6Q6sP5xXDB7nxk6TPqzGkjrpbJSpOE02K4dALvnlZqH2WNqFHEt/ot7if/xm7eJFTGl5Ft983iNtQAsQXzVPgpQq5Vk6Ie1PzAwRlBEH7qsAv3hQt4+/TlEg74HYkiXiuej1AIdj8Jj2hnCPOKH/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2jRMICiofap2sspGpRCRNciAwUyzBmPtd5uyV2tWtkU=; b=oV9WN1in2u0oBTzii6O9ifnkBEFhwhmqtDEBYPjMpBArfndFM/eJ3qkhdcX1dNAVH6CM8H5gkisVRNEihGI3vm4JduujzCIr4ZdlJ/9pCNbMQU6PG0ricuS0/UIo2mVvx3XxWvH04QcwlMEuqLhWmq5pPJwltxDXurJsd8eASAd1SgivXNvwvbWvmFMb7kkkOaSYzrzL/wWmlLdFZ82bBIBVrK0w6B/TTlHFMoKtx+pjDY5h5PXl7+Hmf9R7ZCvZuqjn3LBZZN8YFCOloJOiDG8riiAiejE+sWiGCidxDBJTcSxK2Uqb4p4R4/HmRYlq5eM82Vx8ZvPw8zKsBgoRzg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2jRMICiofap2sspGpRCRNciAwUyzBmPtd5uyV2tWtkU=; b=meIkmfER+vF7Hq1suxhHUiXrTDiL/hMHUP2lAJFwGsGtPiLvl2RFU3H7ZhhCJcbXe99qldGNLOzigk8KMg7JmkLoMIolUd9tgDIhvmKtqdA8o/v8rY3Hn/I+QI1ox3ngsTs8qzSANNzWYkMHQtVqqV38gpmZFW4OySsmQxL+zcI= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB6960.eurprd04.prod.outlook.com (2603:10a6:803:12d::10) by VI1PR04MB5086.eurprd04.prod.outlook.com (2603:10a6:803:62::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.15; Mon, 1 Nov 2021 08:52:15 +0000 Received: from VI1PR04MB6960.eurprd04.prod.outlook.com ([fe80::11d9:6f32:90e:80c1]) by VI1PR04MB6960.eurprd04.prod.outlook.com ([fe80::11d9:6f32:90e:80c1%7]) with mapi id 15.20.4649.019; Mon, 1 Nov 2021 08:52:15 +0000 From: Gagandeep Singh To: thomas@monjalon.net, dev@dpdk.org Cc: nipun.gupta@nxp.com, Gagandeep Singh Date: Mon, 1 Nov 2021 14:21:41 +0530 Message-Id: <20211101085143.2472241-5-g.singh@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211101085143.2472241-1-g.singh@nxp.com> References: <20210909111500.3901706-1-g.singh@nxp.com> <20211101085143.2472241-1-g.singh@nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SG2PR02CA0092.apcprd02.prod.outlook.com (2603:1096:4:90::32) To VI1PR04MB6960.eurprd04.prod.outlook.com (2603:10a6:803:12d::10) MIME-Version: 1.0 Received: from lsv03457.swis.in-blr01.nxp.com (14.142.151.118) by SG2PR02CA0092.apcprd02.prod.outlook.com (2603:1096:4:90::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.15 via Frontend Transport; Mon, 1 Nov 2021 08:52:13 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8aa53b17-93a4-4c07-11c1-08d99d14e6cd X-MS-TrafficTypeDiagnostic: VI1PR04MB5086: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2958; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ETKdFCA4uWJ9O+Y4Xt9OU+E+NWZDPJpo9Ce7HKhZVeLDEMVykEClH7CwwaadKE1LSqljyZlRSjdAR1SzU+4bvGklyFyeoKOsnPZy9p/hJ4eRl/0olXipEF4hAhzQUnX+QSNWlOIZ4q7qsU/yvA4PhktGhNCPpnVsPZzefFZvwYpZf9vSiyBkBRRHqsch7UNfxTtE/VXfsvTl+7EC5kTEeYOSls71pX+8md1rtMgedA46jeumzSyFuXl1vqf2doN6A9YDG63nzVdOCBOOfBPclHSmNcL7lHDsVrJzPj+c5s+5TTXDHuRFcu+VZAFDf4TnKsq+SYpdFhGX+dNJimxvObQeQp+kqlrY4sFnAPfL2peOQglxJLnPbslEoeESLeS7Bx4cERp2T4fef1yJ6XQIsu0i8KznoP356I63ZKo0n9YJ1KEKKKOxSv6L8S5nCVNqtMIYwJGYjnTOId8fwLQqtiY97603PMAw2cMXj4bnedoMCYq2S6nHPT2fj9tMisFuzSnFOyDAJhh0l3V/bc56GPIow+aE9U/OeSa4bw6srvMdLBehdapoKHLfLTglcsa9zGxZAYrMYD+7PI6nUDyiEejzb2Ep3Vqnu3kjUAnUAYM0lQs496GIek+1TiNhFMVwTkSlnGwy/M4R2nuEVoHq8EfMQgALpRM5c1tpLMmKdf3myzk3Ro+KOKXl6cdHsCuv9lLSYD14QRGwGxzrVniosDjcz2nWzkdeHX/HUR7CSxA= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VI1PR04MB6960.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(38350700002)(38100700002)(55236004)(6486002)(6666004)(186003)(1006002)(4326008)(5660300002)(316002)(956004)(2616005)(86362001)(66556008)(7696005)(66476007)(26005)(36756003)(52116002)(8936002)(2906002)(66946007)(8676002)(83380400001)(508600001)(1076003)(110426009); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?PPtDWtSYCg+7Md4rQwwaOxSOX3QhYQKjBL+MwQ5ATwZuS44Gx2Sy9YPFFHW2?= =?us-ascii?Q?kIbhS7qNe6cbYHCIk3klgqurJbT6W1e7mF693A6lPykhE2L6rO6uxj/1f0ci?= =?us-ascii?Q?pNiNK3ilvcY7+8AekVIRk3CQPV2KmJu2t2xzH6LIHhiYX9FMcbJvdH0SrQAP?= =?us-ascii?Q?sGdjSEEKjxwVnoxZ0ObWAWIlZAi8ty0gZcToOzvDqKn4BtvCoW8Ju8Qr0Syw?= =?us-ascii?Q?MdsAd0IU6gfu2CICVnR0hhB8caWiRo6X3jUoSeDjEsfRVW0pWlxAuKqEfhyA?= =?us-ascii?Q?IPEJ8EEAIzGODiqTk1Mj5J1JxlfKqAx2JwcqhlM8s7vErjtICnOl5ATLIrXt?= =?us-ascii?Q?hMhVUjOZCfpZn8plM2xVfePvWSIBxKilcvLEnivJcRpvBVEgJi932TFj+smm?= =?us-ascii?Q?FnKmFhrUqmvD5//0yhtXcqS0CneqkQ4xCVzw2/1TcCYJtEgotXbbJZ7/r1qe?= =?us-ascii?Q?GbLY4sv27dKnY9hHxweT+cke3gE0OhAdrUZtVc/WUbi6KgzR56Ax7qWtNj1A?= =?us-ascii?Q?f0QAyzZ4rDhjkzq6m8/KTbRikJJpXUrN1KX5HsfsoxBvQTEQpsZcjItgORum?= =?us-ascii?Q?JbwMFRvHi1GMSZARU3k5nT92j5C8VdoK4BwHLZqWBkY193YF3fE54GOo9fau?= =?us-ascii?Q?wXGe5thRqhSJNRTQ3y0ptJYmgFdcAaM2PmdrxULXiL0xdUoUDGLa6tfZkWN7?= =?us-ascii?Q?2n66yfGNWL9lhN0z0NQbQ6ePPSNl5jyWYGP7FD1bN3+yDt6aJo3aJaSjHu8z?= =?us-ascii?Q?C0QddqLbZG/D7PJpcXDU445itzituKSQZiMSD4jul/4X8v1d+eYjKDeoupdh?= =?us-ascii?Q?S+DnFnXrMXSGSNOgI/UcSJPpZKXgc2sUBcrEFpIlDK5nwM2EKMhWxBknZJ/P?= =?us-ascii?Q?iEZTESI4bSGGvQg3P2P6e3awVBo7wsiZKWjBt+vilA19zzPTh5UWr8keM/t7?= =?us-ascii?Q?Gq7fKasrImW+8O4CqOsaRk2ziv9B78xr5yC8hJV+rqOtQmQmd7LQR6h5JRl3?= =?us-ascii?Q?t+b6Kn/N+qxMx3O8fOs4GVTPLfi+ElJDqMceJV0tX9u7x2ClVHTLkRO9zCTN?= =?us-ascii?Q?5NsTlihPYdChtfzv5ymGbTztOqtTNXs1gVgvKHcYymDDFyezPDXEtXxSIKEK?= =?us-ascii?Q?BdZHJFUwX4ex53DfLl5Rfc/Z1WcYez6YfDfnS7Mp7DpxkNx1eRWEnoyiX/rq?= =?us-ascii?Q?8ltmDIUgDQklX/fy1P70ODZDn5BehPF8Zey+Wb7wKlKx5fawzvQTDsFAw0AJ?= =?us-ascii?Q?ZUU/GcX4bFFBV3qfwtdRDcD9maFnUboVcYxN3dFrbstFkyx6YhcjG4/Msyaw?= =?us-ascii?Q?JIehztRxW4ssbLObjx9U5igRmsOCzEX/IHuURs3tINn3wNA+yBhbw+kqTXFd?= =?us-ascii?Q?lQhUdphQt3Wbz8JC00OsuanYI/ym29BuskY5vr9ni77wwpaJUpAmZtntI1MZ?= =?us-ascii?Q?gS5e3Mg1/+foqKSamjNKL42f9nDrRsR6m2Gg6wI6DulVVRyZVbDmeEh7W1+S?= =?us-ascii?Q?d8enJAsAm11CR71SRrdr7DYNvGhoaFb5RWSgGCdtutpZiy9tXTk8FxzibmEA?= =?us-ascii?Q?+lDdKIdzN4wi5SV80N8=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8aa53b17-93a4-4c07-11c1-08d99d14e6cd X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB6960.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Nov 2021 08:52:15.1391 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: uVNxAlOG9GbDjXOWAEQnZxdY3quCouXIo9WNxQu5TECDTHrICl5zjzhU75+sYKLc X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5086 Subject: [dpdk-dev] [PATCH v2 4/6] dma/dpaa: support basic operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch support basic DMA operations which includes device capability and channel setup. Signed-off-by: Gagandeep Singh --- drivers/dma/dpaa/dpaa_qdma.c | 185 +++++++++++++++++++++++++++++++++++ drivers/dma/dpaa/dpaa_qdma.h | 6 ++ 2 files changed, 191 insertions(+) diff --git a/drivers/dma/dpaa/dpaa_qdma.c b/drivers/dma/dpaa/dpaa_qdma.c index 7808b3de7f..0240f40907 100644 --- a/drivers/dma/dpaa/dpaa_qdma.c +++ b/drivers/dma/dpaa/dpaa_qdma.c @@ -8,6 +8,18 @@ #include "dpaa_qdma.h" #include "dpaa_qdma_logs.h" +static inline void +qdma_desc_addr_set64(struct fsl_qdma_format *ccdf, u64 addr) +{ + ccdf->addr_hi = upper_32_bits(addr); + ccdf->addr_lo = rte_cpu_to_le_32(lower_32_bits(addr)); +} + +static inline void qdma_csgf_set_len(struct fsl_qdma_format *csgf, int len) +{ + csgf->cfg = rte_cpu_to_le_32(len & QDMA_SG_LEN_MASK); +} + static inline int ilog2(int x) { int log = 0; @@ -84,6 +96,64 @@ static void fsl_qdma_free_chan_resources(struct fsl_qdma_chan *fsl_chan) finally: fsl_qdma->desc_allocated--; } + +/* + * Pre-request command descriptor and compound S/G for enqueue. + */ +static int fsl_qdma_pre_request_enqueue_comp_sd_desc( + struct fsl_qdma_queue *queue, + int size, int aligned) +{ + struct fsl_qdma_comp *comp_temp; + struct fsl_qdma_sdf *sdf; + struct fsl_qdma_ddf *ddf; + struct fsl_qdma_format *csgf_desc; + int i; + + for (i = 0; i < (int)(queue->n_cq + COMMAND_QUEUE_OVERFLLOW); i++) { + comp_temp = rte_zmalloc("qdma: comp temp", + sizeof(*comp_temp), 0); + if (!comp_temp) + return -ENOMEM; + + comp_temp->virt_addr = + dma_pool_alloc(size, aligned, &comp_temp->bus_addr); + if (!comp_temp->virt_addr) { + rte_free(comp_temp); + return -ENOMEM; + } + + comp_temp->desc_virt_addr = + dma_pool_alloc(size, aligned, &comp_temp->desc_bus_addr); + if (!comp_temp->desc_virt_addr) + return -ENOMEM; + + memset(comp_temp->virt_addr, 0, FSL_QDMA_COMMAND_BUFFER_SIZE); + memset(comp_temp->desc_virt_addr, 0, + FSL_QDMA_DESCRIPTOR_BUFFER_SIZE); + + csgf_desc = (struct fsl_qdma_format *)comp_temp->virt_addr + 1; + sdf = (struct fsl_qdma_sdf *)comp_temp->desc_virt_addr; + ddf = (struct fsl_qdma_ddf *)comp_temp->desc_virt_addr + 1; + /* Compound Command Descriptor(Frame List Table) */ + qdma_desc_addr_set64(csgf_desc, comp_temp->desc_bus_addr); + /* It must be 32 as Compound S/G Descriptor */ + qdma_csgf_set_len(csgf_desc, 32); + /* Descriptor Buffer */ + sdf->cmd = rte_cpu_to_le_32(FSL_QDMA_CMD_RWTTYPE << + FSL_QDMA_CMD_RWTTYPE_OFFSET); + ddf->cmd = rte_cpu_to_le_32(FSL_QDMA_CMD_RWTTYPE << + FSL_QDMA_CMD_RWTTYPE_OFFSET); + ddf->cmd |= rte_cpu_to_le_32(FSL_QDMA_CMD_LWC << + FSL_QDMA_CMD_LWC_OFFSET); + + list_add_tail(&comp_temp->list, &queue->comp_free); + } + + return 0; +} + + static struct fsl_qdma_queue *fsl_qdma_alloc_queue_resources(struct fsl_qdma_engine *fsl_qdma) { @@ -311,6 +381,79 @@ static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma) return 0; } +static int fsl_qdma_alloc_chan_resources(struct fsl_qdma_chan *fsl_chan) +{ + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue; + struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma; + int ret; + + if (fsl_queue->count++) + goto finally; + + INIT_LIST_HEAD(&fsl_queue->comp_free); + INIT_LIST_HEAD(&fsl_queue->comp_used); + + ret = fsl_qdma_pre_request_enqueue_comp_sd_desc(fsl_queue, + FSL_QDMA_COMMAND_BUFFER_SIZE, 64); + if (ret) { + DPAA_QDMA_ERR( + "failed to alloc dma buffer for comp descriptor\n"); + goto exit; + } + +finally: + return fsl_qdma->desc_allocated++; + +exit: + return -ENOMEM; +} + +static int +dpaa_info_get(const struct rte_dma_dev *dev, struct rte_dma_info *dev_info, + uint32_t info_sz) +{ +#define DPAADMA_MAX_DESC 64 +#define DPAADMA_MIN_DESC 64 + + RTE_SET_USED(dev); + RTE_SET_USED(info_sz); + + dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM | + RTE_DMA_CAPA_MEM_TO_DEV | + RTE_DMA_CAPA_DEV_TO_DEV | + RTE_DMA_CAPA_DEV_TO_MEM | + RTE_DMA_CAPA_SILENT | + RTE_DMA_CAPA_OPS_COPY; + dev_info->max_vchans = 1; + dev_info->max_desc = DPAADMA_MAX_DESC; + dev_info->min_desc = DPAADMA_MIN_DESC; + + return 0; +} + +static int +dpaa_get_channel(struct fsl_qdma_engine *fsl_qdma, uint16_t vchan) +{ + u32 i, start, end; + + start = fsl_qdma->free_block_id * QDMA_QUEUES; + fsl_qdma->free_block_id++; + + end = start + 1; + for (i = start; i < end; i++) { + struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i]; + + if (fsl_chan->free) { + fsl_chan->free = false; + fsl_qdma_alloc_chan_resources(fsl_chan); + fsl_qdma->vchan_map[vchan] = i; + return 0; + } + } + + return -1; +} + static void dma_release(void *fsl_chan) { @@ -318,6 +461,45 @@ dma_release(void *fsl_chan) fsl_qdma_free_chan_resources((struct fsl_qdma_chan *)fsl_chan); } +static int +dpaa_qdma_configure(__rte_unused struct rte_dma_dev *dmadev, + __rte_unused const struct rte_dma_conf *dev_conf, + __rte_unused uint32_t conf_sz) +{ + return 0; +} + +static int +dpaa_qdma_start(__rte_unused struct rte_dma_dev *dev) +{ + return 0; +} + +static int +dpaa_qdma_close(__rte_unused struct rte_dma_dev *dev) +{ + return 0; +} + +static int +dpaa_qdma_queue_setup(struct rte_dma_dev *dmadev, + uint16_t vchan, + __rte_unused const struct rte_dma_vchan_conf *conf, + __rte_unused uint32_t conf_sz) +{ + struct fsl_qdma_engine *fsl_qdma = dmadev->data->dev_private; + + return dpaa_get_channel(fsl_qdma, vchan); +} + +static struct rte_dma_dev_ops dpaa_qdma_ops = { + .dev_info_get = dpaa_info_get, + .dev_configure = dpaa_qdma_configure, + .dev_start = dpaa_qdma_start, + .dev_close = dpaa_qdma_close, + .vchan_setup = dpaa_qdma_queue_setup, +}; + static int dpaa_qdma_init(struct rte_dma_dev *dmadev) { @@ -424,6 +606,9 @@ dpaa_qdma_probe(__rte_unused struct rte_dpaa_driver *dpaa_drv, } dpaa_dev->dmadev = dmadev; + dmadev->dev_ops = &dpaa_qdma_ops; + dmadev->device = &dpaa_dev->device; + dmadev->fp_obj->dev_private = dmadev->data->dev_private; /* Invoke PMD device initialization function */ ret = dpaa_qdma_init(dmadev); diff --git a/drivers/dma/dpaa/dpaa_qdma.h b/drivers/dma/dpaa/dpaa_qdma.h index cc0d1f114e..f482b16334 100644 --- a/drivers/dma/dpaa/dpaa_qdma.h +++ b/drivers/dma/dpaa/dpaa_qdma.h @@ -8,6 +8,12 @@ #define CORE_NUMBER 4 #define RETRIES 5 +#ifndef GENMASK +#define BITS_PER_LONG (__SIZEOF_LONG__ * 8) +#define GENMASK(h, l) \ + (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) +#endif + #define FSL_QDMA_DMR 0x0 #define FSL_QDMA_DSR 0x4 #define FSL_QDMA_DEIER 0xe00 -- 2.25.1