From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 88B6AA0548; Mon, 1 Nov 2021 18:54:06 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 751B7410FB; Mon, 1 Nov 2021 18:54:06 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 3446940DF6 for ; Mon, 1 Nov 2021 18:54:05 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A1CKSAF001065; Mon, 1 Nov 2021 10:54:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=VVhLpch5kLSZ8s0NIh7LJxi570fNNlHulqy5UAtBrck=; b=Isnz7EmATGgLRpdakNVd+goqn+lmnsjPri6UpTWYhDGS+ed0sE0EMNlyA00zUwDRs8bw xZnn48TLNa8cQ9Qx4EfV54mNiwaF7478o8ekmC7xzwQYKakE0qKi4GWICewyajaQJXum D2JUO7dwn/dzw4oCkURbAZDKiEbS0IFRPr0xxMwDP/xQ8OfH0P3446Ap4q/ovmaFMK4s cMF6Nw7RfDp+suZymjHTVzbbFYPMC5ZgEtj6LR6S3BvDQY2j7P0PShtxLk2VtXoS2N8B jmaZjCGJKjY52tkfH+MOtbk9GTyShz0xOvV/dZEEUgm7Ob8zVvfPTbU4qFR9xqNP4Cax cQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3c25c4bscm-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 01 Nov 2021 10:54:04 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 1 Nov 2021 10:54:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 1 Nov 2021 10:54:02 -0700 Received: from localhost.marvell.com (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id 296BF3F70B3; Mon, 1 Nov 2021 10:54:00 -0700 (PDT) From: Harman Kalra To: , Haiyue Wang CC: , , Harman Kalra Date: Mon, 1 Nov 2021 23:23:34 +0530 Message-ID: <20211101175337.83358-3-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211101175337.83358-1-hkalra@marvell.com> References: <20211101175337.83358-1-hkalra@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: h9ag4avFpGL_76qnl4Bs0mAo_5SLp5UG X-Proofpoint-GUID: h9ag4avFpGL_76qnl4Bs0mAo_5SLp5UG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-01_06,2021-11-01_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 3/6] drivers: fix bad bit shift operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch fixes coverity issue by adding a check for negative value to avoid bad bit shift operation. Coverity issue: 373717,373697,373685 Fixes: d61138d4f0e2 ("drivers: remove direct access to interrupt handle") Signed-off-by: Harman Kalra --- drivers/net/e1000/igb_ethdev.c | 17 +++++++++++------ drivers/net/igc/igc_ethdev.c | 18 +++++++++++++----- 2 files changed, 24 insertions(+), 11 deletions(-) diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c index ff06575f03..031a880b6a 100644 --- a/drivers/net/e1000/igb_ethdev.c +++ b/drivers/net/e1000/igb_ethdev.c @@ -5194,7 +5194,7 @@ eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction, static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev) { - int queue_id; + int queue_id, nb_efd; uint32_t tmpval, regval, intr_mask; struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); @@ -5243,9 +5243,11 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev) E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE | E1000_GPIE_PBA | E1000_GPIE_EIAME | E1000_GPIE_NSICR); - intr_mask = - RTE_LEN2MASK(rte_intr_nb_efd_get(intr_handle), - uint32_t) << misc_shift; + nb_efd = rte_intr_nb_efd_get(intr_handle); + if (nb_efd < 0) + return; + + intr_mask = RTE_LEN2MASK(nb_efd, uint32_t) << misc_shift; if (dev->data->dev_conf.intr_conf.lsc != 0) intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC); @@ -5263,8 +5265,11 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev) /* use EIAM to auto-mask when MSI-X interrupt * is asserted, this saves a register write for every interrupt */ - intr_mask = RTE_LEN2MASK(rte_intr_nb_efd_get(intr_handle), - uint32_t) << misc_shift; + nb_efd = rte_intr_nb_efd_get(intr_handle); + if (nb_efd < 0) + return; + + intr_mask = RTE_LEN2MASK(nb_efd, uint32_t) << misc_shift; if (dev->data->dev_conf.intr_conf.lsc != 0) intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC); diff --git a/drivers/net/igc/igc_ethdev.c b/drivers/net/igc/igc_ethdev.c index 8189ad412a..6652c3c806 100644 --- a/drivers/net/igc/igc_ethdev.c +++ b/drivers/net/igc/igc_ethdev.c @@ -727,7 +727,7 @@ igc_configure_msix_intr(struct rte_eth_dev *dev) uint32_t vec = IGC_MISC_VEC_ID; uint32_t base = IGC_MISC_VEC_ID; uint32_t misc_shift = 0; - int i; + int i, nb_efd; /* won't configure msix register if no mapping is done * between intr vector and event fd @@ -745,8 +745,12 @@ igc_configure_msix_intr(struct rte_eth_dev *dev) IGC_WRITE_REG(hw, IGC_GPIE, IGC_GPIE_MSIX_MODE | IGC_GPIE_PBA | IGC_GPIE_EIAME | IGC_GPIE_NSICR); - intr_mask = RTE_LEN2MASK(rte_intr_nb_efd_get(intr_handle), - uint32_t) << misc_shift; + + nb_efd = rte_intr_nb_efd_get(intr_handle); + if (nb_efd < 0) + return; + + intr_mask = RTE_LEN2MASK(nb_efd, uint32_t) << misc_shift; if (dev->data->dev_conf.intr_conf.lsc) intr_mask |= (1u << IGC_MSIX_OTHER_INTR_VEC); @@ -802,6 +806,7 @@ igc_rxq_interrupt_setup(struct rte_eth_dev *dev) struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct rte_intr_handle *intr_handle = pci_dev->intr_handle; int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0; + int nb_efd; /* won't configure msix register if no mapping is done * between intr vector and event fd @@ -809,8 +814,11 @@ igc_rxq_interrupt_setup(struct rte_eth_dev *dev) if (!rte_intr_dp_is_en(intr_handle)) return; - mask = RTE_LEN2MASK(rte_intr_nb_efd_get(intr_handle), uint32_t) - << misc_shift; + nb_efd = rte_intr_nb_efd_get(intr_handle); + if (nb_efd < 0) + return; + + mask = RTE_LEN2MASK(nb_efd, uint32_t) << misc_shift; IGC_WRITE_REG(hw, IGC_EIMS, mask); } -- 2.18.0