* [dpdk-dev] [PATCH 0/9] fixes and enhancements to Truflow
@ 2021-10-01 5:59 Venkat Duvvuru
2021-10-01 5:59 ` [dpdk-dev] [PATCH 1/9] net/bnxt: add nat support for dest IP and port combination Venkat Duvvuru
` (10 more replies)
0 siblings, 11 replies; 118+ messages in thread
From: Venkat Duvvuru @ 2021-10-01 5:59 UTC (permalink / raw)
To: dev; +Cc: Venkat Duvvuru
This patch set adds enhancements and fixes to Truflow feature.
Enhancements include:
* Scaling numbers on Thor
* Inner IP header support for GRE tunnel flows
* Enable wildcard match for ingress flows
* Add clear on read for flow stats on Thor
* Add nat support for dest IP and port combination
Farah Smith (1):
net/bnxt: add clear on read stats support for Thor
Jay Ding (1):
net/bnxt: get Truflow version
Kishore Padmanabha (6):
net/bnxt: add nat support for dest IP and port combination
net/bnxt: support multi root capability flag
net/bnxt: fix the out of boundary issue in hash list
net/bnxt: add feature capability option for socket direct
net/bnxt: enable wildcard match for ingress flows
net/bnxt: support inner IP header for GRE tunnel flows
Shahaji Bhosle (1):
net/bnxt: increase scaling numbers on Thor
drivers/net/bnxt/bnxt.h | 27 +-
drivers/net/bnxt/bnxt_cpr.c | 2 +-
drivers/net/bnxt/bnxt_ethdev.c | 221 +-
drivers/net/bnxt/bnxt_hwrm.c | 8 +
drivers/net/bnxt/bnxt_reps.c | 3 +-
drivers/net/bnxt/hsi_struct_def_dpdk.h | 2979 ++++++++++++++---
drivers/net/bnxt/tf_core/tf_core.c | 30 +
drivers/net/bnxt/tf_core/tf_core.h | 75 +
drivers/net/bnxt/tf_core/tf_device.h | 50 +
drivers/net/bnxt/tf_core/tf_device_p4.c | 65 +-
drivers/net/bnxt/tf_core/tf_device_p4.h | 79 +
drivers/net/bnxt/tf_core/tf_device_p58.c | 65 +-
drivers/net/bnxt/tf_core/tf_device_p58.h | 87 +
drivers/net/bnxt/tf_core/tf_msg.c | 59 +-
drivers/net/bnxt/tf_core/tf_msg.h | 25 +-
drivers/net/bnxt/tf_core/tf_tbl.c | 6 +-
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 13 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 24 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 8 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 10 +-
.../generic_templates/ulp_template_db_act.c | 376 ++-
.../generic_templates/ulp_template_db_enum.h | 26 +-
.../generic_templates/ulp_template_db_tbl.c | 23 +-
.../ulp_template_db_thor_class.c | 251 +-
.../ulp_template_db_wh_plus_act.c | 96 +-
drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 6 +-
drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 20 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 7 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +-
29 files changed, 3627 insertions(+), 1016 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 118+ messages in thread* [dpdk-dev] [PATCH 1/9] net/bnxt: add nat support for dest IP and port combination 2021-10-01 5:59 [dpdk-dev] [PATCH 0/9] fixes and enhancements to Truflow Venkat Duvvuru @ 2021-10-01 5:59 ` Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 2/9] net/bnxt: support multi root capability flag Venkat Duvvuru ` (9 subsequent siblings) 10 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-01 5:59 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> * Added support for nat action for the destination ip and port combination for the thor platform. This is not supported for whitney platform. * Consolidated the encapsulation and nat entries for scaling flows with nat actions. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- .../generic_templates/ulp_template_db_act.c | 376 +++++++++++------- .../generic_templates/ulp_template_db_enum.h | 18 +- .../generic_templates/ulp_template_db_tbl.c | 14 +- .../ulp_template_db_thor_class.c | 2 +- .../ulp_template_db_wh_plus_act.c | 96 +++-- 5 files changed, 317 insertions(+), 189 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c index 0da6070d7d..ce878d8e02 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon May 17 15:30:41 2021 */ +/* date: Wed Aug 25 14:37:06 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -47,59 +47,67 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { [BNXT_ULP_ACT_HID_04bc] = 30, [BNXT_ULP_ACT_HID_00a9] = 31, [BNXT_ULP_ACT_HID_020f] = 32, - [BNXT_ULP_ACT_HID_04a9] = 33, - [BNXT_ULP_ACT_HID_01fc] = 34, - [BNXT_ULP_ACT_HID_04be] = 35, - [BNXT_ULP_ACT_HID_00ab] = 36, - [BNXT_ULP_ACT_HID_0211] = 37, - [BNXT_ULP_ACT_HID_04ab] = 38, - [BNXT_ULP_ACT_HID_01fe] = 39, - [BNXT_ULP_ACT_HID_0667] = 40, - [BNXT_ULP_ACT_HID_0254] = 41, - [BNXT_ULP_ACT_HID_03ba] = 42, - [BNXT_ULP_ACT_HID_0654] = 43, - [BNXT_ULP_ACT_HID_03a7] = 44, - [BNXT_ULP_ACT_HID_0669] = 45, - [BNXT_ULP_ACT_HID_0256] = 46, - [BNXT_ULP_ACT_HID_03bc] = 47, - [BNXT_ULP_ACT_HID_0656] = 48, - [BNXT_ULP_ACT_HID_03a9] = 49, - [BNXT_ULP_ACT_HID_021b] = 50, - [BNXT_ULP_ACT_HID_021c] = 51, - [BNXT_ULP_ACT_HID_021e] = 52, - [BNXT_ULP_ACT_HID_063f] = 53, - [BNXT_ULP_ACT_HID_0510] = 54, - [BNXT_ULP_ACT_HID_03c6] = 55, - [BNXT_ULP_ACT_HID_0082] = 56, - [BNXT_ULP_ACT_HID_06bb] = 57, - [BNXT_ULP_ACT_HID_021d] = 58, - [BNXT_ULP_ACT_HID_0641] = 59, - [BNXT_ULP_ACT_HID_0512] = 60, - [BNXT_ULP_ACT_HID_03c8] = 61, - [BNXT_ULP_ACT_HID_0084] = 62, - [BNXT_ULP_ACT_HID_06bd] = 63, - [BNXT_ULP_ACT_HID_06d7] = 64, - [BNXT_ULP_ACT_HID_02c4] = 65, - [BNXT_ULP_ACT_HID_042a] = 66, - [BNXT_ULP_ACT_HID_06c4] = 67, - [BNXT_ULP_ACT_HID_0417] = 68, - [BNXT_ULP_ACT_HID_06d9] = 69, - [BNXT_ULP_ACT_HID_02c6] = 70, - [BNXT_ULP_ACT_HID_042c] = 71, - [BNXT_ULP_ACT_HID_06c6] = 72, - [BNXT_ULP_ACT_HID_0419] = 73, - [BNXT_ULP_ACT_HID_0119] = 74, - [BNXT_ULP_ACT_HID_046f] = 75, - [BNXT_ULP_ACT_HID_05d5] = 76, - [BNXT_ULP_ACT_HID_0106] = 77, - [BNXT_ULP_ACT_HID_05c2] = 78, - [BNXT_ULP_ACT_HID_011b] = 79, - [BNXT_ULP_ACT_HID_0471] = 80, - [BNXT_ULP_ACT_HID_05d7] = 81, - [BNXT_ULP_ACT_HID_0108] = 82, - [BNXT_ULP_ACT_HID_05c4] = 83, - [BNXT_ULP_ACT_HID_00a2] = 84, - [BNXT_ULP_ACT_HID_00a4] = 85 + [BNXT_ULP_ACT_HID_0153] = 33, + [BNXT_ULP_ACT_HID_04a9] = 34, + [BNXT_ULP_ACT_HID_01fc] = 35, + [BNXT_ULP_ACT_HID_04be] = 36, + [BNXT_ULP_ACT_HID_00ab] = 37, + [BNXT_ULP_ACT_HID_0211] = 38, + [BNXT_ULP_ACT_HID_0155] = 39, + [BNXT_ULP_ACT_HID_04ab] = 40, + [BNXT_ULP_ACT_HID_01fe] = 41, + [BNXT_ULP_ACT_HID_0667] = 42, + [BNXT_ULP_ACT_HID_0254] = 43, + [BNXT_ULP_ACT_HID_03ba] = 44, + [BNXT_ULP_ACT_HID_02fe] = 45, + [BNXT_ULP_ACT_HID_0654] = 46, + [BNXT_ULP_ACT_HID_03a7] = 47, + [BNXT_ULP_ACT_HID_0669] = 48, + [BNXT_ULP_ACT_HID_0256] = 49, + [BNXT_ULP_ACT_HID_03bc] = 50, + [BNXT_ULP_ACT_HID_0300] = 51, + [BNXT_ULP_ACT_HID_0656] = 52, + [BNXT_ULP_ACT_HID_03a9] = 53, + [BNXT_ULP_ACT_HID_021b] = 54, + [BNXT_ULP_ACT_HID_021c] = 55, + [BNXT_ULP_ACT_HID_021e] = 56, + [BNXT_ULP_ACT_HID_063f] = 57, + [BNXT_ULP_ACT_HID_0510] = 58, + [BNXT_ULP_ACT_HID_03c6] = 59, + [BNXT_ULP_ACT_HID_0082] = 60, + [BNXT_ULP_ACT_HID_06bb] = 61, + [BNXT_ULP_ACT_HID_021d] = 62, + [BNXT_ULP_ACT_HID_0641] = 63, + [BNXT_ULP_ACT_HID_0512] = 64, + [BNXT_ULP_ACT_HID_03c8] = 65, + [BNXT_ULP_ACT_HID_0084] = 66, + [BNXT_ULP_ACT_HID_06bd] = 67, + [BNXT_ULP_ACT_HID_06d7] = 68, + [BNXT_ULP_ACT_HID_02c4] = 69, + [BNXT_ULP_ACT_HID_042a] = 70, + [BNXT_ULP_ACT_HID_036e] = 71, + [BNXT_ULP_ACT_HID_06c4] = 72, + [BNXT_ULP_ACT_HID_0417] = 73, + [BNXT_ULP_ACT_HID_06d9] = 74, + [BNXT_ULP_ACT_HID_02c6] = 75, + [BNXT_ULP_ACT_HID_042c] = 76, + [BNXT_ULP_ACT_HID_0370] = 77, + [BNXT_ULP_ACT_HID_06c6] = 78, + [BNXT_ULP_ACT_HID_0419] = 79, + [BNXT_ULP_ACT_HID_0119] = 80, + [BNXT_ULP_ACT_HID_046f] = 81, + [BNXT_ULP_ACT_HID_05d5] = 82, + [BNXT_ULP_ACT_HID_0519] = 83, + [BNXT_ULP_ACT_HID_0106] = 84, + [BNXT_ULP_ACT_HID_05c2] = 85, + [BNXT_ULP_ACT_HID_011b] = 86, + [BNXT_ULP_ACT_HID_0471] = 87, + [BNXT_ULP_ACT_HID_05d7] = 88, + [BNXT_ULP_ACT_HID_051b] = 89, + [BNXT_ULP_ACT_HID_0108] = 90, + [BNXT_ULP_ACT_HID_05c4] = 91, + [BNXT_ULP_ACT_HID_00a2] = 92, + [BNXT_ULP_ACT_HID_00a4] = 93 }; /* Array for the act matcher list */ @@ -429,22 +437,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 3 }, [33] = { - .act_hid = BNXT_ULP_ACT_HID_04a9, + .act_hid = BNXT_ULP_ACT_HID_0153, .act_pattern_id = 3, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [34] = { - .act_hid = BNXT_ULP_ACT_HID_01fc, + .act_hid = BNXT_ULP_ACT_HID_04a9, .act_pattern_id = 4, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | @@ -452,40 +458,63 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 3 }, [35] = { - .act_hid = BNXT_ULP_ACT_HID_04be, + .act_hid = BNXT_ULP_ACT_HID_01fc, .act_pattern_id = 5, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [36] = { - .act_hid = BNXT_ULP_ACT_HID_00ab, + .act_hid = BNXT_ULP_ACT_HID_04be, .act_pattern_id = 6, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [37] = { - .act_hid = BNXT_ULP_ACT_HID_0211, + .act_hid = BNXT_ULP_ACT_HID_00ab, .act_pattern_id = 7, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [38] = { - .act_hid = BNXT_ULP_ACT_HID_04ab, + .act_hid = BNXT_ULP_ACT_HID_0211, .act_pattern_id = 8, .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [39] = { + .act_hid = BNXT_ULP_ACT_HID_0155, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [40] = { + .act_hid = BNXT_ULP_ACT_HID_04ab, + .act_pattern_id = 10, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -494,9 +523,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [39] = { + [41] = { .act_hid = BNXT_ULP_ACT_HID_01fe, - .act_pattern_id = 9, + .act_pattern_id = 11, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -507,9 +536,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [40] = { + [42] = { .act_hid = BNXT_ULP_ACT_HID_0667, - .act_pattern_id = 10, + .act_pattern_id = 12, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -517,9 +546,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [41] = { + [43] = { .act_hid = BNXT_ULP_ACT_HID_0254, - .act_pattern_id = 11, + .act_pattern_id = 13, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -528,9 +557,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [42] = { + [44] = { .act_hid = BNXT_ULP_ACT_HID_03ba, - .act_pattern_id = 12, + .act_pattern_id = 14, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -538,9 +567,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [43] = { + [45] = { + .act_hid = BNXT_ULP_ACT_HID_02fe, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [46] = { .act_hid = BNXT_ULP_ACT_HID_0654, - .act_pattern_id = 13, + .act_pattern_id = 16, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -550,9 +590,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [44] = { + [47] = { .act_hid = BNXT_ULP_ACT_HID_03a7, - .act_pattern_id = 14, + .act_pattern_id = 17, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -563,9 +603,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [45] = { + [48] = { .act_hid = BNXT_ULP_ACT_HID_0669, - .act_pattern_id = 15, + .act_pattern_id = 18, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -574,9 +614,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [46] = { + [49] = { .act_hid = BNXT_ULP_ACT_HID_0256, - .act_pattern_id = 16, + .act_pattern_id = 19, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -586,9 +626,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [47] = { + [50] = { .act_hid = BNXT_ULP_ACT_HID_03bc, - .act_pattern_id = 17, + .act_pattern_id = 20, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -597,9 +637,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [48] = { + [51] = { + .act_hid = BNXT_ULP_ACT_HID_0300, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [52] = { .act_hid = BNXT_ULP_ACT_HID_0656, - .act_pattern_id = 18, + .act_pattern_id = 22, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -610,9 +662,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [49] = { + [53] = { .act_hid = BNXT_ULP_ACT_HID_03a9, - .act_pattern_id = 19, + .act_pattern_id = 23, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -624,7 +676,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [50] = { + [54] = { .act_hid = BNXT_ULP_ACT_HID_021b, .act_pattern_id = 0, .app_sig = 0, @@ -632,7 +684,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [51] = { + [55] = { .act_hid = BNXT_ULP_ACT_HID_021c, .act_pattern_id = 1, .app_sig = 0, @@ -641,7 +693,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [52] = { + [56] = { .act_hid = BNXT_ULP_ACT_HID_021e, .act_pattern_id = 2, .app_sig = 0, @@ -651,7 +703,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [53] = { + [57] = { .act_hid = BNXT_ULP_ACT_HID_063f, .act_pattern_id = 3, .app_sig = 0, @@ -662,7 +714,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [54] = { + [58] = { .act_hid = BNXT_ULP_ACT_HID_0510, .act_pattern_id = 4, .app_sig = 0, @@ -672,7 +724,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [55] = { + [59] = { .act_hid = BNXT_ULP_ACT_HID_03c6, .act_pattern_id = 5, .app_sig = 0, @@ -681,7 +733,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [56] = { + [60] = { .act_hid = BNXT_ULP_ACT_HID_0082, .act_pattern_id = 6, .app_sig = 0, @@ -693,7 +745,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [57] = { + [61] = { .act_hid = BNXT_ULP_ACT_HID_06bb, .act_pattern_id = 7, .app_sig = 0, @@ -704,7 +756,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [58] = { + [62] = { .act_hid = BNXT_ULP_ACT_HID_021d, .act_pattern_id = 8, .app_sig = 0, @@ -713,7 +765,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [59] = { + [63] = { .act_hid = BNXT_ULP_ACT_HID_0641, .act_pattern_id = 9, .app_sig = 0, @@ -725,7 +777,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [60] = { + [64] = { .act_hid = BNXT_ULP_ACT_HID_0512, .act_pattern_id = 10, .app_sig = 0, @@ -736,7 +788,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [61] = { + [65] = { .act_hid = BNXT_ULP_ACT_HID_03c8, .act_pattern_id = 11, .app_sig = 0, @@ -746,7 +798,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [62] = { + [66] = { .act_hid = BNXT_ULP_ACT_HID_0084, .act_pattern_id = 12, .app_sig = 0, @@ -759,7 +811,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [63] = { + [67] = { .act_hid = BNXT_ULP_ACT_HID_06bd, .act_pattern_id = 13, .app_sig = 0, @@ -771,7 +823,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [64] = { + [68] = { .act_hid = BNXT_ULP_ACT_HID_06d7, .act_pattern_id = 0, .app_sig = 0, @@ -780,7 +832,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [65] = { + [69] = { .act_hid = BNXT_ULP_ACT_HID_02c4, .act_pattern_id = 1, .app_sig = 0, @@ -790,7 +842,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [66] = { + [70] = { .act_hid = BNXT_ULP_ACT_HID_042a, .act_pattern_id = 2, .app_sig = 0, @@ -799,10 +851,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [67] = { - .act_hid = BNXT_ULP_ACT_HID_06c4, + [71] = { + .act_hid = BNXT_ULP_ACT_HID_036e, .act_pattern_id = 3, .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [72] = { + .act_hid = BNXT_ULP_ACT_HID_06c4, + .act_pattern_id = 4, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | @@ -810,9 +872,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [68] = { + [73] = { .act_hid = BNXT_ULP_ACT_HID_0417, - .act_pattern_id = 4, + .act_pattern_id = 5, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -822,9 +884,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [69] = { + [74] = { .act_hid = BNXT_ULP_ACT_HID_06d9, - .act_pattern_id = 5, + .act_pattern_id = 6, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -832,9 +894,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [70] = { + [75] = { .act_hid = BNXT_ULP_ACT_HID_02c6, - .act_pattern_id = 6, + .act_pattern_id = 7, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -843,9 +905,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [71] = { + [76] = { .act_hid = BNXT_ULP_ACT_HID_042c, - .act_pattern_id = 7, + .act_pattern_id = 8, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -853,9 +915,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [72] = { + [77] = { + .act_hid = BNXT_ULP_ACT_HID_0370, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [78] = { .act_hid = BNXT_ULP_ACT_HID_06c6, - .act_pattern_id = 8, + .act_pattern_id = 10, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -865,9 +938,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [73] = { + [79] = { .act_hid = BNXT_ULP_ACT_HID_0419, - .act_pattern_id = 9, + .act_pattern_id = 11, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -878,9 +951,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [74] = { + [80] = { .act_hid = BNXT_ULP_ACT_HID_0119, - .act_pattern_id = 10, + .act_pattern_id = 12, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -888,9 +961,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [75] = { + [81] = { .act_hid = BNXT_ULP_ACT_HID_046f, - .act_pattern_id = 11, + .act_pattern_id = 13, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -899,9 +972,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [76] = { + [82] = { .act_hid = BNXT_ULP_ACT_HID_05d5, - .act_pattern_id = 12, + .act_pattern_id = 14, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -909,9 +982,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [77] = { + [83] = { + .act_hid = BNXT_ULP_ACT_HID_0519, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [84] = { .act_hid = BNXT_ULP_ACT_HID_0106, - .act_pattern_id = 13, + .act_pattern_id = 16, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -921,9 +1005,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [78] = { + [85] = { .act_hid = BNXT_ULP_ACT_HID_05c2, - .act_pattern_id = 14, + .act_pattern_id = 17, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -934,9 +1018,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [79] = { + [86] = { .act_hid = BNXT_ULP_ACT_HID_011b, - .act_pattern_id = 15, + .act_pattern_id = 18, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -945,9 +1029,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [80] = { + [87] = { .act_hid = BNXT_ULP_ACT_HID_0471, - .act_pattern_id = 16, + .act_pattern_id = 19, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -957,9 +1041,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [81] = { + [88] = { .act_hid = BNXT_ULP_ACT_HID_05d7, - .act_pattern_id = 17, + .act_pattern_id = 20, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -968,9 +1052,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [82] = { + [89] = { + .act_hid = BNXT_ULP_ACT_HID_051b, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [90] = { .act_hid = BNXT_ULP_ACT_HID_0108, - .act_pattern_id = 18, + .act_pattern_id = 22, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -981,9 +1077,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [83] = { + [91] = { .act_hid = BNXT_ULP_ACT_HID_05c4, - .act_pattern_id = 19, + .act_pattern_id = 23, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -995,7 +1091,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [84] = { + [92] = { .act_hid = BNXT_ULP_ACT_HID_00a2, .act_pattern_id = 0, .app_sig = 0, @@ -1004,7 +1100,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [85] = { + [93] = { .act_hid = BNXT_ULP_ACT_HID_00a4, .act_pattern_id = 1, .app_sig = 0, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index c016e1940a..fcd460e707 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 20 17:59:14 2021 */ +/* date: Thu Aug 26 17:43:36 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -20,7 +20,7 @@ #define BNXT_ULP_CLASS_HID_SHFTL 28 #define BNXT_ULP_CLASS_HID_MASK 65535 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 -#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86 +#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 94 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 #define BNXT_ULP_ACT_HID_HIGH_PRIME 3793 #define BNXT_ULP_ACT_HID_SHFTR 27 @@ -29,7 +29,7 @@ #define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110 #define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50 -#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278 +#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 277 #define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 @@ -50,11 +50,11 @@ #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313 #define ULP_THOR_CLASS_COND_LIST_SIZE 55 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 -#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35 +#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1 #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536 -#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39 +#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 41 #define ULP_THOR_ACT_TMPL_LIST_SIZE 7 #define ULP_THOR_ACT_TBL_LIST_SIZE 36 #define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16 @@ -2224,21 +2224,25 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_04bc = 0x04bc, BNXT_ULP_ACT_HID_00a9 = 0x00a9, BNXT_ULP_ACT_HID_020f = 0x020f, + BNXT_ULP_ACT_HID_0153 = 0x0153, BNXT_ULP_ACT_HID_04a9 = 0x04a9, BNXT_ULP_ACT_HID_01fc = 0x01fc, BNXT_ULP_ACT_HID_04be = 0x04be, BNXT_ULP_ACT_HID_00ab = 0x00ab, BNXT_ULP_ACT_HID_0211 = 0x0211, + BNXT_ULP_ACT_HID_0155 = 0x0155, BNXT_ULP_ACT_HID_04ab = 0x04ab, BNXT_ULP_ACT_HID_01fe = 0x01fe, BNXT_ULP_ACT_HID_0667 = 0x0667, BNXT_ULP_ACT_HID_0254 = 0x0254, BNXT_ULP_ACT_HID_03ba = 0x03ba, + BNXT_ULP_ACT_HID_02fe = 0x02fe, BNXT_ULP_ACT_HID_0654 = 0x0654, BNXT_ULP_ACT_HID_03a7 = 0x03a7, BNXT_ULP_ACT_HID_0669 = 0x0669, BNXT_ULP_ACT_HID_0256 = 0x0256, BNXT_ULP_ACT_HID_03bc = 0x03bc, + BNXT_ULP_ACT_HID_0300 = 0x0300, BNXT_ULP_ACT_HID_0656 = 0x0656, BNXT_ULP_ACT_HID_03a9 = 0x03a9, BNXT_ULP_ACT_HID_021b = 0x021b, @@ -2258,21 +2262,25 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_06d7 = 0x06d7, BNXT_ULP_ACT_HID_02c4 = 0x02c4, BNXT_ULP_ACT_HID_042a = 0x042a, + BNXT_ULP_ACT_HID_036e = 0x036e, BNXT_ULP_ACT_HID_06c4 = 0x06c4, BNXT_ULP_ACT_HID_0417 = 0x0417, BNXT_ULP_ACT_HID_06d9 = 0x06d9, BNXT_ULP_ACT_HID_02c6 = 0x02c6, BNXT_ULP_ACT_HID_042c = 0x042c, + BNXT_ULP_ACT_HID_0370 = 0x0370, BNXT_ULP_ACT_HID_06c6 = 0x06c6, BNXT_ULP_ACT_HID_0419 = 0x0419, BNXT_ULP_ACT_HID_0119 = 0x0119, BNXT_ULP_ACT_HID_046f = 0x046f, BNXT_ULP_ACT_HID_05d5 = 0x05d5, + BNXT_ULP_ACT_HID_0519 = 0x0519, BNXT_ULP_ACT_HID_0106 = 0x0106, BNXT_ULP_ACT_HID_05c2 = 0x05c2, BNXT_ULP_ACT_HID_011b = 0x011b, BNXT_ULP_ACT_HID_0471 = 0x0471, BNXT_ULP_ACT_HID_05d7 = 0x05d7, + BNXT_ULP_ACT_HID_051b = 0x051b, BNXT_ULP_ACT_HID_0108 = 0x0108, BNXT_ULP_ACT_HID_05c4 = 0x05c4, BNXT_ULP_ACT_HID_00a2 = 0x00a2, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 684fa66f48..84be09b368 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Aug 17 12:16:42 2021 */ +/* date: Thu Aug 26 17:43:36 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -2121,7 +2121,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 2048 }, { .app_id = 0, @@ -2249,7 +2249,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 2048 }, { .app_id = 0, @@ -2263,14 +2263,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, - .count = 32 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 272 diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 68c1e292b2..95205a2421 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 20 18:05:25 2021 */ +/* date: Wed Aug 25 16:41:37 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c index 578ede8bba..4a2d201c2d 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Jun 1 16:05:30 2021 */ +/* date: Wed Aug 25 14:37:06 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -35,7 +35,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { /* act_tid: 3, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, + .num_tbls = 7, .start_tbl_idx = 12, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, @@ -46,30 +46,30 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, - .start_tbl_idx = 18, + .start_tbl_idx = 19, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 20, + .cond_start_idx = 21, .cond_nums = 0 } }, /* act_tid: 5, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 23, + .num_tbls = 7, + .start_tbl_idx = 24, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 28, + .cond_start_idx = 29, .cond_nums = 0 } }, /* act_tid: 6, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, - .start_tbl_idx = 29, + .start_tbl_idx = 31, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 0 } } }; @@ -322,6 +322,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 34, .result_num_fields = 2 }, + { /* act_tid: 3, , table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 15, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, { /* act_tid: 3, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, @@ -332,7 +343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 15, + .cond_start_idx = 16, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -351,7 +362,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 16, + .cond_start_idx = 17, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, @@ -370,7 +381,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, + .cond_start_idx = 18, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, @@ -389,7 +400,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, @@ -410,7 +421,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 18, + .cond_start_idx = 19, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -429,7 +440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 19, + .cond_start_idx = 20, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -449,7 +460,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 21, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -468,7 +479,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 21, + .cond_start_idx = 22, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -489,7 +500,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 23, + .cond_start_idx = 24, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -508,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 25, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -528,7 +539,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 26, + .cond_start_idx = 27, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -538,6 +549,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 11 }, + { /* act_tid: 5, , table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 29, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, { /* act_tid: 5, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, @@ -548,7 +570,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 28, + .cond_start_idx = 30, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -567,7 +589,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, + .cond_start_idx = 31, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, @@ -586,7 +608,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 32, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, @@ -605,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 33, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, @@ -626,7 +648,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, + .cond_start_idx = 33, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -645,7 +667,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, + .cond_start_idx = 34, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -665,7 +687,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -684,7 +706,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 36, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, @@ -705,7 +727,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 37, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, @@ -726,7 +748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 38, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -747,7 +769,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 39, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -766,7 +788,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, + .cond_start_idx = 40, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -844,6 +866,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, + /* cond_execute: act_tid: 3, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, @@ -900,6 +927,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN }, + /* cond_execute: act_tid: 5, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH 2/9] net/bnxt: support multi root capability flag 2021-10-01 5:59 [dpdk-dev] [PATCH 0/9] fixes and enhancements to Truflow Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 1/9] net/bnxt: add nat support for dest IP and port combination Venkat Duvvuru @ 2021-10-01 5:59 ` Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 3/9] net/bnxt: fix the out of boundary issue in hash list Venkat Duvvuru ` (8 subsequent siblings) 10 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-01 5:59 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Update driver to read the multi root capability and ignore pci address check while creating ulp session when multi root capability is enabled in the hardware. DPDK HSI version updated from 1.10.1.70 to 1.10.2.54. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/bnxt.h | 8 + drivers/net/bnxt/bnxt_hwrm.c | 8 + drivers/net/bnxt/hsi_struct_def_dpdk.h | 2698 +++++++++++++++++++++--- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 10 +- 4 files changed, 2420 insertions(+), 304 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 5121d05da6..b9e120d94b 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -724,6 +724,14 @@ struct bnxt { uint16_t chip_num; #define CHIP_NUM_58818 0xd818 #define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818) +#define BNXT_FLAGS2_TESTPMD_EN BIT(3) +#define BNXT_TESTPMD_EN(bp) \ + ((bp)->flags2 & BNXT_FLAGS2_TESTPMD_EN) +#define BNXT_THOR_PTP_TIMESYNC_ENABLED(bp) \ + ((bp)->flags & BNXT_FLAGS_PTP_TIMESYNC_ENABLED) +#define BNXT_FLAGS2_MULTIROOT_EN BIT(4) +#define BNXT_MULTIROOT_EN(bp) \ + ((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN) uint32_t fw_cap; #define BNXT_FW_CAP_HOT_RESET BIT(0) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 503add42fd..8ccee79f0a 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -3385,6 +3385,7 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp) { struct hwrm_func_qcfg_input req = {0}; struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; + uint16_t flags; int rc; if (!BNXT_VF_IS_TRUSTED(bp)) @@ -3408,6 +3409,13 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp) bp->parent->fid = rte_le_to_cpu_16(resp->fid); bp->parent->port_id = rte_le_to_cpu_16(resp->port_id); + flags = rte_le_to_cpu_16(resp->flags); + /* check for the multi-root support */ + if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) { + bp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN; + PMD_DRV_LOG(DEBUG, "PF enabled with multi root capability\n"); + } + HWRM_UNLOCK(); return 0; diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 4d7efb19f4..9ed66525b7 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -657,6 +657,8 @@ struct cmd_nums { #define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0) /* PTP - Query extended PTP configuration. */ #define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1) + /* The command is used to allocate KTLS crypto key contexts. */ + #define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -1056,8 +1058,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 44 -#define HWRM_VERSION_STR "1.10.2.44" +#define HWRM_VERSION_RSVD 54 +#define HWRM_VERSION_STR "1.10.2.54" /**************** * hwrm_ver_get * @@ -1357,6 +1359,12 @@ struct hwrm_ver_get_output { */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \ UINT32_C(0x4000) + /* + * If set to 1, then firmware supports secure boot. + * If set to 0, then firmware doesn't support secure boot. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE \ + UINT32_C(0x8000) /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. @@ -8283,8 +8291,14 @@ struct hwrm_async_event_cmpl_reset_notify { /* Fast reset */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \ (UINT32_C(0x4) << 8) + /* + * Reset was a result of a firmware activation. That is, the + * fw_activation flag was set in a FW_RESET operation. + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION \ + (UINT32_C(0x5) << 8) #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION /* * Minimum time before driver should attempt access - units 100ms ticks. * Range 0-65535 @@ -10244,8 +10258,21 @@ struct hwrm_async_event_cmpl_error_report_base { */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \ UINT32_C(0x2) + /* + * There was a low level error with an NVM write or erase. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM \ + UINT32_C(0x3) + /* + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD } __rte_packed; /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ @@ -10386,6 +10413,162 @@ struct hwrm_async_event_cmpl_error_report_invalid_signal { HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL } __rte_packed; +/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_nvm { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Indicates the address where error was detected */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK \ + UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT \ + 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * There was a low level error with an NVM operation. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR + /* The specific type of NVM error */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT \ + 8 + /* + * There was a low level error with an NVM write operation. + * Verification of written data did not match. + * event_data2 will be the failing address. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE \ + (UINT32_C(0x1) << 8) + /* + * There was a low level error with an NVM erase operation. + * All the bits were not erased. + * event_data2 will be the failing address. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE \ + (UINT32_C(0x2) << 8) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT \ + 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD +} __rte_packed; + /* metadata_base_msg (size:64b/8B) */ struct metadata_base_msg { uint16_t md_type_link; @@ -11204,6 +11387,18 @@ struct hwrm_func_vf_cfg_input { */ #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ UINT32_C(0x800) + /* + * This bit must be '1' for the num_tx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the num_rx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS \ + UINT32_C(0x2000) /* * The maximum transmission unit requested on the function. * The HWRM should make sure that the mtu of @@ -11353,7 +11548,10 @@ struct hwrm_func_vf_cfg_input { uint16_t num_stat_ctxs; /* The number of HW ring groups requested for the VF. */ uint16_t num_hw_ring_grps; - uint8_t unused_0[4]; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; } __rte_packed; /* hwrm_func_vf_cfg_output (size:128b/16B) */ @@ -11423,7 +11621,7 @@ struct hwrm_func_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcaps_output (size:704b/88B) */ +/* hwrm_func_qcaps_output (size:768b/96B) */ struct hwrm_func_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -11787,7 +11985,13 @@ struct hwrm_func_qcaps_output { * (max_tx_rings) to the function. */ uint16_t max_sp_tx_rings; - uint8_t unused_0[2]; + /* + * The maximum number of MSI-X vectors that may be allocated across + * all VFs for the function. This is valid only on the PF with SR-IOV + * enabled. Returns zero if this command is called on a PF with + * SR-IOV disabled or on a VF. + */ + uint16_t max_msix_vfs; uint32_t flags_ext; /* * If 1, the device can be configured to set the ECN bits in the @@ -11965,7 +12169,12 @@ struct hwrm_func_qcaps_output { * to the primate processor block. */ #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10) - uint8_t unused_1; + /* + * Maximum number of Key Contexts supported per HWRM + * function call for allocating Key Contexts. + */ + uint16_t max_key_ctxs_alloc; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12023,7 +12232,7 @@ struct hwrm_func_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcfg_output (size:832b/104B) */ +/* hwrm_func_qcfg_output (size:896b/112B) */ struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -12614,7 +12823,11 @@ struct hwrm_func_qcfg_output { * value is used if ring MTU is not specified. */ uint16_t host_mtu; - uint8_t unused_3; + /* Number of Tx Key Contexts allocated. */ + uint16_t alloc_tx_key_ctxs; + /* Number of Rx Key Contexts allocated. */ + uint16_t alloc_rx_key_ctxs; + uint8_t unused_3[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12630,7 +12843,7 @@ struct hwrm_func_qcfg_output { *****************/ -/* hwrm_func_cfg_input (size:832b/104B) */ +/* hwrm_func_cfg_input (size:896b/112B) */ struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -12663,7 +12876,7 @@ struct hwrm_func_cfg_input { /* * Function ID of the function that is being * configured. - * If set to 0xFF... (All Fs), then the configuration is + * If set to 0xFF... (All Fs), then the the configuration is * for the requesting function. */ uint16_t fid; @@ -13076,6 +13289,18 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \ UINT32_C(0x20000000) + /* + * This bit must be '1' for the number of Tx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS \ + UINT32_C(0x40000000) + /* + * This bit must be '1' for the number of Rx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS \ + UINT32_C(0x80000000) /* * This field can be used by the admin PF to configure * mtu of foster PFs. @@ -13390,7 +13615,7 @@ struct hwrm_func_cfg_input { /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the TX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block block. When this bit is ‘0’, this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \ UINT32_C(0x20) @@ -13404,7 +13629,7 @@ struct hwrm_func_cfg_input { /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the RX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block block. When this bit is ‘0’, this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \ UINT32_C(0x80) @@ -13527,6 +13752,11 @@ struct hwrm_func_cfg_input { * ring that is assigned to a function has a valid mtu. */ uint16_t host_mtu; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; + uint8_t unused_0[4]; } __rte_packed; /* hwrm_func_cfg_output (size:128b/16B) */ @@ -14103,6 +14333,13 @@ struct hwrm_func_drv_rgtr_input { */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \ UINT32_C(0x100) + /* + * When this bit is 1, the function's driver is indicating the + * support of handling the NPAR 1.2 feature where the s-tag may be + * a value other than 0x8100 or 0x88a8. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \ + UINT32_C(0x200) uint32_t enables; /* * This bit must be '1' for the os_type field to be @@ -14664,7 +14901,7 @@ struct hwrm_func_resource_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_resource_qcaps_output (size:448b/56B) */ +/* hwrm_func_resource_qcaps_output (size:512b/64B) */ struct hwrm_func_resource_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -14739,6 +14976,14 @@ struct hwrm_func_resource_qcaps_output { */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output @@ -14755,7 +15000,7 @@ struct hwrm_func_resource_qcaps_output { *****************************/ -/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ +/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ struct hwrm_func_vf_resource_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -14829,6 +15074,14 @@ struct hwrm_func_vf_resource_cfg_input { */ #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; uint8_t unused_0[2]; } __rte_packed; @@ -14858,7 +15111,11 @@ struct hwrm_func_vf_resource_cfg_output { uint16_t reserved_stat_ctx; /* Reserved number of ring groups */ uint16_t reserved_hw_ring_grps; - uint8_t unused_0[7]; + /* Actual number of Tx Key Contexts reserved */ + uint16_t reserved_tx_key_ctxs; + /* Actual number of Rx Key Contexts reserved */ + uint16_t reserved_rx_key_ctxs; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18132,7 +18389,7 @@ struct hwrm_error_recovery_qcfg_output { /*************************** * hwrm_func_echo_response * - ****************************/ + ***************************/ /* hwrm_func_echo_response_input (size:192b/24B) */ @@ -18190,13 +18447,13 @@ struct hwrm_func_echo_response_output { uint8_t valid; } __rte_packed; -/*********************** - * hwrm_func_vlan_qcfg * - ***********************/ +/************************** + * hwrm_func_ptp_pin_qcfg * + **************************/ -/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ -struct hwrm_func_vlan_qcfg_input { +/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_pin_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18225,18 +18482,11 @@ struct hwrm_func_vlan_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[6]; + uint8_t unused_0[8]; } __rte_packed; -/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ -struct hwrm_func_vlan_qcfg_output { +/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18245,32 +18495,94 @@ struct hwrm_func_vlan_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint64_t unused_0; - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * The number of TSIO pins that are configured on this board + * Up to 4 pins can be returned in the response. */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; + uint8_t num_pins; + /* Pin state */ + uint8_t state; /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * When this bit is '1', TSIO pin 0 is enabled. + * When this bit is '0', TSIO pin 0 is disabled. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd2; - /* Future use. */ - uint32_t rsvd3; - uint8_t unused_3[3]; + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED \ + UINT32_C(0x1) + /* + * When this bit is '1', TSIO pin 1 is enabled. + * When this bit is '0', TSIO pin 1 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED \ + UINT32_C(0x2) + /* + * When this bit is '1', TSIO pin 2 is enabled. + * When this bit is '0', TSIO pin 2 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED \ + UINT32_C(0x4) + /* + * When this bit is '1', TSIO pin 3 is enabled. + * When this bit is '0', TSIO pin 3 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED \ + UINT32_C(0x8) + /* Type of function for Pin #0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT + /* Type of function for Pin #1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT + /* Type of function for Pin #2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT + /* Type of function for Pin #3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18281,13 +18593,13 @@ struct hwrm_func_vlan_qcfg_output { uint8_t valid; } __rte_packed; -/********************** - * hwrm_func_vlan_cfg * - **********************/ +/************************* + * hwrm_func_ptp_pin_cfg * + *************************/ -/* hwrm_func_vlan_cfg_input (size:384b/48B) */ -struct hwrm_func_vlan_cfg_input { +/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_pin_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18316,74 +18628,148 @@ struct hwrm_func_vlan_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[2]; uint32_t enables; /* - * This bit must be '1' for the stag_vid field to be + * This bit must be '1' for the pin0_state field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE \ + UINT32_C(0x1) /* - * This bit must be '1' for the ctag_vid field to be + * This bit must be '1' for the pin0_usage field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE \ + UINT32_C(0x2) /* - * This bit must be '1' for the stag_pcp field to be + * This bit must be '1' for the pin1_state field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE \ + UINT32_C(0x4) /* - * This bit must be '1' for the ctag_pcp field to be + * This bit must be '1' for the pin1_usage field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE \ + UINT32_C(0x8) /* - * This bit must be '1' for the stag_tpid field to be + * This bit must be '1' for the pin2_state field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE \ + UINT32_C(0x10) /* - * This bit must be '1' for the ctag_tpid field to be + * This bit must be '1' for the pin2_usage field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE \ + UINT32_C(0x20) /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * This bit must be '1' for the pin3_state field to be + * configured. */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE \ + UINT32_C(0x40) /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * This bit must be '1' for the pin3_usage field to be + * configured. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd1; - /* Future use. */ - uint32_t rsvd2; - uint8_t unused_3[4]; + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE \ + UINT32_C(0x80) + /* Enable or disable functionality of Pin #0. */ + uint8_t pin0_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED + /* Configure function for TSIO pin#0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #1. */ + uint8_t pin1_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED + /* Configure function for TSIO pin#1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #2. */ + uint8_t pin2_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED + /* Configure function for TSIO pin#2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #3. */ + uint8_t pin3_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED + /* Configure function for TSIO pin#3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0[4]; } __rte_packed; -/* hwrm_func_vlan_cfg_output (size:128b/16B) */ -struct hwrm_func_vlan_cfg_output { +/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18403,13 +18789,812 @@ struct hwrm_func_vlan_cfg_output { uint8_t valid; } __rte_packed; -/******************************* - * hwrm_func_vf_vnic_ids_query * - *******************************/ +/********************* + * hwrm_func_ptp_cfg * + *********************/ -/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ -struct hwrm_func_vf_vnic_ids_query_input { +/* hwrm_func_ptp_cfg_input (size:320b/40B) */ +struct hwrm_func_ptp_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the ptp_pps_event field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT \ + UINT32_C(0x1) + /* + * This bit must be '1' for the ptp_freq_adj_dll_source field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the ptp_freq_adj_dll_phase field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the ptp_freq_adj_ext_period field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD \ + UINT32_C(0x8) + /* + * This bit must be '1' for the ptp_freq_adj_ext_up field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP \ + UINT32_C(0x10) + /* + * This bit must be '1' for the ptp_freq_adj_ext_phase field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE \ + UINT32_C(0x20) + /* This field is used to enable interrupt for a specific PPS event. */ + uint8_t ptp_pps_event; + /* + * When this bit is set to '1', interrupt is enabled for internal + * PPS event. Latches timestamp on PPS_OUT TSIO Pin. If user does + * not configure PPS_OUT on a TSIO pin, then firmware will allocate + * PPS_OUT to an unallocated pin. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL \ + UINT32_C(0x1) + /* + * When this bit is set to '1', interrupt is enabled for external + * PPS event. Latches timestamp on PPS_IN TSIO pin. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL \ + UINT32_C(0x2) + /* + * This field is used to set the source signal used to discipline + * PHC (PTP Hardware Clock) + */ + uint8_t ptp_freq_adj_dll_source; + /* No source is selected. Use servo to discipline PHC */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE \ + UINT32_C(0x0) + /* TSIO Pin #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 \ + UINT32_C(0x1) + /* TSIO Pin #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 \ + UINT32_C(0x2) + /* TSIO Pin #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 \ + UINT32_C(0x3) + /* TSIO Pin #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 \ + UINT32_C(0x4) + /* Port #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 \ + UINT32_C(0x5) + /* Port #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 \ + UINT32_C(0x6) + /* Port #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 \ + UINT32_C(0x7) + /* Port #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 \ + UINT32_C(0x8) + /* Invalid signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID \ + UINT32_C(0xff) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID + /* + * This field is used to provide phase adjustment for DLL + * used to discipline PHC (PTP Hardware clock) + */ + uint8_t ptp_freq_adj_dll_phase; + /* No Phase adjustment. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE \ + UINT32_C(0x0) + /* 4Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K \ + UINT32_C(0x1) + /* 8Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K \ + UINT32_C(0x2) + /* 10Mhz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M \ + UINT32_C(0x3) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M + uint8_t unused_0[3]; + /* + * Period in nanoseconds (ns) for external signal + * input. + */ + uint32_t ptp_freq_adj_ext_period; + /* + * Up time in nanoseconds (ns) of the duty cycle + * of the external signal. This value should be + * less than ptp_freq_adj_ext_period. + */ + uint32_t ptp_freq_adj_ext_up; + /* + * Phase value is provided. This field provides the + * least significant 32 bits of the phase input. The + * most significant 16 bits come from + * ptp_freq_adj_ext_phase_upper field. Setting this + * field requires setting ptp_freq_adj_ext_period + * field as well to identify the external signal + * pin. + */ + uint32_t ptp_freq_adj_ext_phase_lower; + /* + * Phase value is provided. The lower 16 bits of this field is used + * with the 32 bit value from ptp_freq_adj_ext_phase_lower + * to provide a 48 bit value input for Phase. + */ + uint32_t ptp_freq_adj_ext_phase_upper; +} __rte_packed; + +/* hwrm_func_ptp_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ts_query * + **************************/ + + +/* hwrm_func_ptp_ts_query_input (size:192b/24B) */ +struct hwrm_func_ptp_ts_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* If set, the response includes PPS event timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1) + /* If set, the response includes PTM timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_ptp_ts_query_output (size:320b/40B) */ +struct hwrm_func_ptp_ts_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Timestamp value of last PPS event latched. */ + uint64_t pps_event_ts; + /* PTM local timestamp value. */ + uint64_t ptm_res_local_ts; + /* PTM Master timestamp value. */ + uint64_t ptm_pmstr_ts; + /* PTM Master propagation delay */ + uint32_t ptm_mstr_prop_dly; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_func_ptp_ext_cfg * + *************************/ + + +/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_ext_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the phc_master_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the phc_sec_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the phc_sec_mode field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the failover_timer field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER \ + UINT32_C(0x8) + /* + * This field is used to configure the Master function. Only this + * function can modify or condition the PHC. Only driver calls from + * this function are allowed to adjust frequency of PHC or configure + * PPS functionality. + * If driver does not specify this FID, then firmware will auto select + * the first function that makes the call to modify PHC as the Master. + */ + uint16_t phc_master_fid; + /* + * This field is used to configure the secondary function. This + * function becomes the Master function in case of failover from + * Master function. + * If driver does not specify this FID, firmware will auto select + * the last non-master function to make a call to condition PHC as + * secondary. + */ + uint16_t phc_sec_fid; + /* + * This field is used to configure conditions under which a function + * can become a secondary function. + */ + uint8_t phc_sec_mode; + /* + * Immediately failover to the current secondary function. If there + * is no secondary function available, failover does not happen. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0) + /* + * All functions (PF and VF) can be used during auto selection + * of a secondary function. This is not used in case of admin + * configured secondary function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1) + /* + * Only PF's can be selected as a secondary function during auto + * selection. This is not used in case of admin configured secondary + * function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2) + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_LAST \ + HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY + uint8_t unused_0; + /* + * This field indicates the failover time is milliseconds. If the + * timeout expires, firmware will failover PTP configurability from + * current master to secondary fid. + * 0 - Failover timer is automatically selected based on the last + * adjFreq() call. If adjFreq() is not called for 3 * (last interval) + * the failover kicks in. For example, if last interval between + * adjFreq() calls was 2 seconds and the next adjFreq() is not made for + * at least 6 seconds, then secondary takes over as master to condition + * PHC. Firmware rounds up the failover timer to be a multiple of 250 + * ms. Firmware checks every 250 ms to see if timer expired. + * 0xFFFFFFFF - If driver specifies this value, then failover never + * happens. Admin or auto selected Master will always be used for + * conditioning PHC. + * X - If driver specifies any other value, this is admin indicated + * failover timeout. If no adjFreq() call is made within this timeout + * value, then failover happens. This value should be a multiple of + * 250 ms. Firmware checks every 250 ms to see if timer expired. + */ + uint32_t failover_timer; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_ext_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ext_qcfg * + **************************/ + + +/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_ext_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ +struct hwrm_func_ptp_ext_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Firmware returns the current PHC master function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_master_fid; + /* + * Firmware returns the current PHC secondary function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_sec_fid; + /* + * Firmware returns the last non-master/non-secondary function to + * make a call to condition PHC. + */ + uint16_t phc_active_fid0; + /* + * Firmware returns the second last non-master/non-secondary function + * to make a call to condition PHC. + */ + uint16_t phc_active_fid1; + /* + * Timestamp indicating the last time a failover happened. The master + * and secondary functions in the failover event is indicated in the + * next two fields. + */ + uint32_t last_failover_event; + /* + * Last failover happened from this function. This was the master + * function at the time of failover. + */ + uint16_t from_fid; + /* + * Last failover happened to this function. This was the secondary + * function at the time of failover. + */ + uint16_t to_fid; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_func_key_ctx_alloc * + ***************************/ + + +/* hwrm_func_key_ctx_alloc_input (size:320b/40B) */ +struct hwrm_func_key_ctx_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Function ID. */ + uint16_t fid; + /* Number of Key Contexts to be allocated. */ + uint16_t num_key_ctxs; + /* DMA buffer size in bytes. */ + uint32_t dma_bufr_size_bytes; + /* Key Context type. */ + uint8_t key_ctx_type; + /* Tx Key Context. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0) + /* Rx KTLS Context. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1) + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST \ + HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX + uint8_t unused_0[7]; + /* Host DMA address to send back KTLS context IDs. */ + uint64_t host_dma_addr; +} __rte_packed; + +/* hwrm_func_key_ctx_alloc_output (size:128b/16B) */ +struct hwrm_func_key_ctx_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Actual number of Key Contexts allocated. */ + uint16_t num_key_ctxs_allocated; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_func_vlan_qcfg * + ***********************/ + + +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ +struct hwrm_func_vlan_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ +struct hwrm_func_vlan_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint64_t unused_0; + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd2; + /* Future use. */ + uint32_t rsvd3; + uint8_t unused_3[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_vlan_cfg * + **********************/ + + +/* hwrm_func_vlan_cfg_input (size:384b/48B) */ +struct hwrm_func_vlan_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[2]; + uint32_t enables; + /* + * This bit must be '1' for the stag_vid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) + /* + * This bit must be '1' for the ctag_vid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) + /* + * This bit must be '1' for the stag_pcp field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) + /* + * This bit must be '1' for the ctag_pcp field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) + /* + * This bit must be '1' for the stag_tpid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) + /* + * This bit must be '1' for the ctag_tpid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd1; + /* Future use. */ + uint32_t rsvd2; + uint8_t unused_3[4]; +} __rte_packed; + +/* hwrm_func_vlan_cfg_output (size:128b/16B) */ +struct hwrm_func_vlan_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_func_vf_vnic_ids_query * + *******************************/ + + +/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ +struct hwrm_func_vf_vnic_ids_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -19128,7 +20313,7 @@ struct hwrm_func_spd_cfg_input { UINT32_C(0x10) /* * Ethertype value used in the encapsulated SPD packet header. - * The user must choose a value that is not conflicting with + * The user must chooose a value that is not conflicting with * publicly defined ethertype values. By default, the ethertype * value of 0xffff is used if there is no user specified value. */ @@ -19387,7 +20572,7 @@ struct hwrm_func_spd_qcfg_output { uint8_t unused_1; /* * Ethertype value used in the encapsulated SPD packet header. - * The user must choose a value that is not conflicting with + * The user must chooose a value that is not conflicting with * publicly defined ethertype values. By default, the ethertype * value of 0xffff is used if there is no user specified value. */ @@ -21398,6 +22583,12 @@ struct hwrm_port_mac_cfg_input { */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \ UINT32_C(0x200) + /* + * This bit must be '1' for the ptp_adj_phase field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE \ + UINT32_C(0x400) /* Port ID of port that is to be configured. */ uint16_t port_id; /* @@ -21590,7 +22781,12 @@ struct hwrm_port_mac_cfg_input { * of sync timer updates (measured in parts per billion). */ int32_t ptp_freq_adj_ppb; - uint8_t unused_1[4]; + /* + * This unsigned field specifies the phase offset to be applied + * to the PHC (PTP Hardware Clock). This field is specified in + * nanoseconds. + */ + uint32_t ptp_adj_phase; } __rte_packed; /* hwrm_port_mac_cfg_output (size:128b/16B) */ @@ -21991,7 +23187,7 @@ struct hwrm_port_mac_ptp_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ +/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ struct hwrm_port_mac_ptp_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -22024,10 +23220,23 @@ struct hwrm_port_mac_ptp_qcfg_output { */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ UINT32_C(0x8) + /* + * When this bit is set to '1', two specific registers for current + * time (ts_ref_clock_reg_lower and ts_ref_clock_reg_upper) are + * directly accessible by the host. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK \ + UINT32_C(0x10) uint8_t unused_0[3]; - /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for RX. */ uint32_t rx_ts_reg_off_seq_id; @@ -22045,9 +23254,15 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t rx_ts_reg_off_fifo_adv; /* PTP timestamp granularity for RX. */ uint32_t rx_ts_reg_off_granularity; - /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for TX. */ uint32_t tx_ts_reg_off_seq_id; @@ -22055,6 +23270,10 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t tx_ts_reg_off_fifo; /* PTP timestamp granularity for TX. */ uint32_t tx_ts_reg_off_granularity; + /* Offset of register to get lower 32 bits of current time. */ + uint32_t ts_ref_clock_reg_lower; + /* Offset of register to get upper 32 bits of current time. */ + uint32_t ts_ref_clock_reg_upper; uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output @@ -22578,7 +23797,7 @@ struct tx_port_stats_ext { } __rte_packed; /* Port Rx Statistics extended Format */ -/* rx_port_stats_ext (size:3648b/456B) */ +/* rx_port_stats_ext (size:3776b/472B) */ struct rx_port_stats_ext { /* Number of times link state changed to down */ uint64_t link_down_events; @@ -22697,6 +23916,13 @@ struct rx_port_stats_ext { uint64_t rx_discard_packets_cos6; /* Total number of rx discard packets count on cos queue 7 */ uint64_t rx_discard_packets_cos7; + /* Total number of FEC blocks corrected by the FEC function in the PHY */ + uint64_t rx_fec_corrected_blocks; + /* + * Total number of FEC blocks determined to be uncorrectable by the + * FEC function in the PHY + */ + uint64_t rx_fec_uncorrectable_blocks; } __rte_packed; /* @@ -25981,6 +27207,309 @@ struct hwrm_port_tx_fir_qcfg_output { uint8_t valid; } __rte_packed; +/*********************** + * hwrm_port_ep_tx_cfg * + ***********************/ + + +/* hwrm_port_ep_tx_cfg_input (size:256b/32B) */ +struct hwrm_port_ep_tx_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* When this bit is '1', the value in the ep0_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1) + /* When this bit is '1', the value in the ep0_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2) + /* When this bit is '1', the value in the ep1_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4) + /* When this bit is '1', the value in the ep1_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8) + /* When this bit is '1', the value in the ep2_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10) + /* When this bit is '1', the value in the ep2_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20) + /* When this bit is '1', the value in the ep3_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40) + /* When this bit is '1', the value in the ep3_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80) + /* A port index, from 0 to the number of front panel ports, minus 1. */ + uint8_t port_id; + uint8_t unused; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set of + * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of + * the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_output (size:128b/16B) */ +struct hwrm_port_ep_tx_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_cmd_err (size:64b/8B) */ +struct hwrm_port_ep_tx_cfg_cmd_err { + /* + * command specific error codes for the cmd_err field in + * hwrm_err_output + */ + uint8_t code; + /* Unknown error. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* The port ID is invalid */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID \ + UINT32_C(0x1) + /* One of the PCIe endpoints configured is not active. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE \ + UINT32_C(0x2) + /* A minimum bandwidth is out of range. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE \ + UINT32_C(0x3) + /* + * One endpoint's minimum bandwidth is more than its maximum + * bandwidth. + */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX \ + UINT32_C(0x4) + /* The sum of the minimum bandwidths on the port is more than 100%. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM \ + UINT32_C(0x5) + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_LAST \ + HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM + uint8_t unused_0[7]; +} __rte_packed; + +/************************ + * hwrm_port_ep_tx_qcfg * + ************************/ + + +/* hwrm_port_ep_tx_qcfg_input (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The port whose endpoint rate limits are queried. */ + uint8_t port_id; + uint8_t unused[7]; +} __rte_packed; + +/* hwrm_port_ep_tx_qcfg_output (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /*********************** * hwrm_queue_qportcfg * ***********************/ @@ -26097,6 +27626,13 @@ struct hwrm_queue_qportcfg_output { */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ UINT32_C(0x1) + /* + * If this flag is set to '1', then service_profile will carry + * either lossy/lossless type and the new service_profile_type + * field will be used to determine if the queue is for L2/ROCE/CNP. + */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE \ + UINT32_C(0x2) /* * Bitmask indicating which queues can be configured by the * hwrm_queue_pfcenable_cfg command. @@ -30204,67 +31740,221 @@ struct hwrm_queue_vlanpri2pri_qcfg_input { * to configure VLAN priority to user priority mapping on this port. */ uint8_t port_id; - uint8_t unused_0[7]; -} __rte_packed; - -/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ -struct hwrm_queue_vlanpri2pri_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ +struct hwrm_queue_vlanpri2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * User priority assigned to VLAN priority 0. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri0_user_pri_id; + /* + * User priority assigned to VLAN priority 1. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri1_user_pri_id; + /* + * User priority assigned to VLAN priority 2. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri2_user_pri_id; + /* + * User priority assigned to VLAN priority 3. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri3_user_pri_id; + /* + * User priority assigned to VLAN priority 4. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri4_user_pri_id; + /* + * User priority assigned to VLAN priority 5. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri5_user_pri_id; + /* + * User priority assigned to VLAN priority 6. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri6_user_pri_id; + /* + * User priority assigned to VLAN priority 7. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri7_user_pri_id; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_queue_vlanpri2pri_cfg * + ******************************/ + + +/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ +struct hwrm_queue_vlanpri2pri_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vlanpri0_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the vlanpri1_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the vlanpri2_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vlanpri3_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the vlanpri4_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the vlanpri5_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the vlanpri6_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the vlanpri7_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ + UINT32_C(0x80) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure VLAN priority to user priority mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[3]; /* - * User priority assigned to VLAN priority 0. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 0. This value can only + * be changed before traffic has started. */ uint8_t vlanpri0_user_pri_id; /* - * User priority assigned to VLAN priority 1. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 1. This value can only + * be changed before traffic has started. */ uint8_t vlanpri1_user_pri_id; /* - * User priority assigned to VLAN priority 2. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 2. This value can only + * be changed before traffic has started. */ uint8_t vlanpri2_user_pri_id; /* - * User priority assigned to VLAN priority 3. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 3. This value can only + * be changed before traffic has started. */ uint8_t vlanpri3_user_pri_id; /* - * User priority assigned to VLAN priority 4. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 4. This value can only + * be changed before traffic has started. */ uint8_t vlanpri4_user_pri_id; /* - * User priority assigned to VLAN priority 5. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 5. This value can only + * be changed before traffic has started. */ uint8_t vlanpri5_user_pri_id; /* - * User priority assigned to VLAN priority 6. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 6. This value can only + * be changed before traffic has started. */ uint8_t vlanpri6_user_pri_id; /* - * User priority assigned to VLAN priority 7. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 7. This value can only + * be changed before traffic has started. */ uint8_t vlanpri7_user_pri_id; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_vlanpri2pri_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -30276,13 +31966,13 @@ struct hwrm_queue_vlanpri2pri_qcfg_output { uint8_t valid; } __rte_packed; -/****************************** - * hwrm_queue_vlanpri2pri_cfg * - ******************************/ +/************************* + * hwrm_queue_global_cfg * + *************************/ -/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ -struct hwrm_queue_vlanpri2pri_cfg_input { +/* hwrm_queue_global_cfg_input (size:192b/24B) */ +struct hwrm_queue_global_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30311,106 +32001,142 @@ struct hwrm_queue_vlanpri2pri_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the vlanpri0_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ - UINT32_C(0x1) - /* - * This bit must be '1' for the vlanpri1_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ - UINT32_C(0x2) /* - * This bit must be '1' for the vlanpri2_user_pri_id field to be - * configured. + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ - UINT32_C(0x4) + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0) /* - * This bit must be '1' for the vlanpri3_user_pri_id field to be - * configured. + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ - UINT32_C(0x8) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT + uint8_t unused_0; + uint16_t enables; + /* This bit must be '1' when the mode field is configured. */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1) /* - * This bit must be '1' for the vlanpri4_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 0 + * (g0_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ - UINT32_C(0x10) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2) /* - * This bit must be '1' for the vlanpri5_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 1 + * (g1_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ - UINT32_C(0x20) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4) /* - * This bit must be '1' for the vlanpri6_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 2 + * (g2_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ - UINT32_C(0x40) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8) /* - * This bit must be '1' for the vlanpri7_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 3 + * (g3_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ - UINT32_C(0x80) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW \ + UINT32_C(0x10) /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure VLAN priority to user priority mapping on this port. + * Specifies the maximum receive rate, as a percentage of total link + * bandwidth, of the receive traffic through queue group 0. A value + * of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. */ - uint8_t port_id; - uint8_t unused_0[3]; + uint8_t g0_max_bw; /* - * User priority assigned to VLAN priority 0. This value can only - * be changed before traffic has started. + * Specifies the maximum rate of the traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. */ - uint8_t vlanpri0_user_pri_id; + uint8_t g1_max_bw; /* - * User priority assigned to VLAN priority 1. This value can only - * be changed before traffic has started. + * Specifies the maximum rate of the traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. */ - uint8_t vlanpri1_user_pri_id; + uint8_t g2_max_bw; /* - * User priority assigned to VLAN priority 2. This value can only - * be changed before traffic has started. + * Specifies the maximum receive rate, in Mbps, of the receive traffic + * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0 + * indicates no rate limit. */ - uint8_t vlanpri2_user_pri_id; + uint8_t g3_max_bw; +} __rte_packed; + +/* hwrm_queue_global_cfg_output (size:128b/16B) */ +struct hwrm_queue_global_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * User priority assigned to VLAN priority 3. This value can only - * be changed before traffic has started. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint8_t vlanpri3_user_pri_id; + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_queue_global_qcfg * + **************************/ + + +/* hwrm_queue_global_qcfg_input (size:128b/16B) */ +struct hwrm_queue_global_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * User priority assigned to VLAN priority 4. This value can only - * be changed before traffic has started. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint8_t vlanpri4_user_pri_id; + uint16_t cmpl_ring; /* - * User priority assigned to VLAN priority 5. This value can only - * be changed before traffic has started. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t vlanpri5_user_pri_id; + uint16_t seq_id; /* - * User priority assigned to VLAN priority 6. This value can only - * be changed before traffic has started. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint8_t vlanpri6_user_pri_id; + uint16_t target_id; /* - * User priority assigned to VLAN priority 7. This value can only - * be changed before traffic has started. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint8_t vlanpri7_user_pri_id; + uint64_t resp_addr; } __rte_packed; -/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_vlanpri2pri_cfg_output { +/* hwrm_queue_global_qcfg_output (size:320b/40B) */ +struct hwrm_queue_global_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30419,7 +32145,95 @@ struct hwrm_queue_vlanpri2pri_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Port or PCIe endpoint id to be mapped for buffer pool 0. */ + uint8_t buffer_pool_id0_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 1. */ + uint8_t buffer_pool_id1_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 2. */ + uint8_t buffer_pool_id2_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 3. */ + uint8_t buffer_pool_id3_map; + /* Size of buffer pool 0 (KBytes). */ + uint32_t buffer_pool_id0_size; + /* Size of buffer pool 1 (KBytes). */ + uint32_t buffer_pool_id1_size; + /* Size of buffer pool 2 (KBytes). */ + uint32_t buffer_pool_id2_size; + /* Size of buffer pool 3 (KBytes). */ + uint32_t buffer_pool_id3_size; + uint16_t flags; + /* + * Enumeration denoting whether the rx buffer pool mapping is + * per port or per PCIe endpoint + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING \ + UINT32_C(0x1) + /* + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a port. + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT \ + UINT32_C(0x0) + /* + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a PCIe endpoint. + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT \ + UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT + /* + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. + */ + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0) + /* + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT + uint8_t unused_0; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 0. The rate limit is a percentage of total link bandwidth. A + * value of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. + */ + uint8_t g0_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g1_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g2_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 3 (for port 3 or PCIe endpoint 3). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g3_max_bw; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -30902,7 +32716,7 @@ struct hwrm_vnic_cfg_input { * queue ID will be arriving on this VNIC. Packet priority to CoS mapping * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode, * ntuple filters with VNIC destination specified are invalid since they - * conflict with the CoS to VNIC steering rules in this mode. + * conflict with the the CoS to VNIC steering rules in this mode. * * If this field is not specified, packet to VNIC steering will be * subject to the standard L2 filter rules and any additional ntuple @@ -31324,6 +33138,13 @@ struct hwrm_vnic_qcaps_output { */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \ UINT32_C(0x1000) + /* + * When this bit is set '1', it indicates that firmware returns + * INVALID_PARAM error, if host drivers choose invalid hash type + * bit combinations in vnic_rss_cfg. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP \ + UINT32_C(0x2000) /* * This field advertises the maximum concurrent TPA aggregations * supported by the VNIC on new devices that support TPA v2. @@ -31674,7 +33495,34 @@ struct hwrm_vnic_rss_cfg_input { uint64_t hash_key_tbl_addr; /* Index to the rss indirection table. */ uint16_t rss_ctx_idx; - uint8_t unused_1[6]; + uint8_t flags; + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to add to the current + * hash. Zeroes designate the hash_type state bits that should remain + * unchanged, if possible. If this constraint on the existing state + * cannot be satisfied, then the implementation should preference + * adding other headers so as to honor the request to add the + * specified headers. It is an error to set this flag concurrently + * with hash_type_exclude. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to remove from the + * current hash. Zeroes designate the hash_type state bits that + * should remain unchanged, if possible. If this constraint on the + * existing state cannot be satisfied, then the implementation should + * preference removing other headers so as to honor the request to + * remove the specified headers. It is an error to set this flag + * concurrently with hash_type_include. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE \ + UINT32_C(0x2) + uint8_t unused_1[5]; } __rte_packed; /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ @@ -42426,14 +44274,14 @@ struct hwrm_cfa_eem_qcaps_output { #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \ UINT32_C(0x2) /* - * When set to 1, indicates the FW supports the Centralized + * When set to 1, indicates the the FW supports the Centralized * Memory Model. The concept designates one entity for the * memory allocation while all others ‘subscribe’ to it. */ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ UINT32_C(0x4) /* - * When set to 1, indicates the FW supports the Detached + * When set to 1, indicates the the FW supports the Detached * Centralized Memory Model. The memory is allocated and managed * as a separate entity. All PFs and VFs will be granted direct * or semi-direct access to the allocated memory while none of @@ -43062,6 +44910,161 @@ struct hwrm_cfa_tflib_output { uint8_t valid; } __rte_packed; +/********************************** + * hwrm_cfa_lag_group_member_rgtr * + **********************************/ + + +/* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t mode; + /* + * Transmit only on the active port. Automatically failover + * to backup port. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP \ + UINT32_C(0x1) + /* + * Transmit based on packet header ntuple hash. Packet with only + * layer 2 headers will hash using the destination MAC, source MAC + * and Ethertype fields. Packets with layer 3 (IP) headers will + * hash using the destination MAC, source MAC, IP protocol/next + * header, source IP address and destination IP address. Packets + * with layer 4 (TCP/UDP) headers will hash using the destination + * MAC, source MAC, IP protocol/next header, source IP address, + * destination IP address, source port and destination port fields. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR \ + UINT32_C(0x2) + /* Transmit packets on all specified ports. */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST \ + UINT32_C(0x3) + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST \ + HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST + /* + * Supports up to 5 ports. bit0 = port 0, bit1 = port 1, + * bit2 = port 2, bit3 = port 4, bit4 = loopback port + */ + uint8_t port_bitmap; + /* Specify the active port when active-backup mode is specified */ + uint8_t active_port; + uint8_t unused_0[5]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************************ + * hwrm_cfa_lag_group_member_unrgtr * + ************************************/ + + +/* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /*********** * hwrm_tf * ***********/ @@ -43263,8 +45266,13 @@ struct hwrm_tf_session_open_output { * the newly created session. */ uint32_t fw_session_client_id; + /* This field is used to return the status of fw session to host. */ uint32_t flags; - /* Indicates if the shared session has been created. */ + /* + * Indicates if the shared session has been created. Shared seesion + * should be the first session created ever. Its fw_rm_client_id + * should be 1. The AFM session's fw_rm_client_id is 0. + */ #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \ UINT32_C(0x1) /* @@ -43745,7 +45753,7 @@ struct hwrm_tf_session_resc_qcaps_input { #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX @@ -43860,7 +45868,7 @@ struct hwrm_tf_session_resc_alloc_input { #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX @@ -43959,7 +45967,7 @@ struct hwrm_tf_session_resc_free_input { #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX @@ -44043,7 +46051,7 @@ struct hwrm_tf_session_resc_flush_input { #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX @@ -44248,7 +46256,7 @@ struct hwrm_tf_tbl_type_get_input { #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX @@ -44337,7 +46345,7 @@ struct hwrm_tf_tbl_type_set_input { #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX @@ -44819,7 +46827,7 @@ struct hwrm_tf_ext_em_qcaps_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \ @@ -44843,14 +46851,14 @@ struct hwrm_tf_ext_em_qcaps_output { uint16_t resp_len; uint32_t flags; /* - * When set to 1, indicates the FW supports the Centralized + * When set to 1, indicates the the FW supports the Centralized * Memory Model. The concept designates one entity for the * memory allocation while all others ‘subscribe’ to it. */ #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ UINT32_C(0x1) /* - * When set to 1, indicates the FW supports the Detached + * When set to 1, indicates the the FW supports the Detached * Centralized Memory Model. The memory is allocated and managed * as a separate entity. All PFs and VFs will be granted direct * or semi-direct access to the allocated memory while none of @@ -44997,7 +47005,7 @@ struct hwrm_tf_ext_em_op_input { #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX @@ -45104,7 +47112,7 @@ struct hwrm_tf_ext_em_cfg_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \ @@ -45309,7 +47317,7 @@ struct hwrm_tf_ext_em_qcfg_input { #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX @@ -45335,7 +47343,7 @@ struct hwrm_tf_ext_em_qcfg_output { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ @@ -45475,7 +47483,7 @@ struct hwrm_tf_em_insert_input { #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX @@ -45556,7 +47564,7 @@ struct hwrm_tf_em_hash_insert_input { #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX @@ -45637,13 +47645,13 @@ struct hwrm_tf_em_delete_input { #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX /* Unused0 */ uint16_t unused0; - /* EM internal flow hanndle. */ + /* EM internal flow handle. */ uint64_t flow_handle; /* EM Key value */ uint64_t em_key[8]; @@ -45785,7 +47793,7 @@ struct hwrm_tf_tcam_set_input { #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX @@ -45887,7 +47895,7 @@ struct hwrm_tf_tcam_get_input { #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX @@ -45983,7 +47991,7 @@ struct hwrm_tf_tcam_move_input { #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX @@ -46066,7 +48074,7 @@ struct hwrm_tf_tcam_free_input { #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX @@ -46149,7 +48157,7 @@ struct hwrm_tf_global_cfg_set_input { #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX @@ -46233,7 +48241,7 @@ struct hwrm_tf_global_cfg_get_input { #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX @@ -46308,7 +48316,7 @@ struct hwrm_tf_if_tbl_get_input { #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX @@ -46397,7 +48405,7 @@ struct hwrm_tf_if_tbl_set_input { #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX @@ -46484,7 +48492,7 @@ struct hwrm_tf_tbl_type_bulk_get_input { #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX @@ -48261,7 +50269,7 @@ struct hwrm_nvm_get_dir_info_output { ******************/ -/* hwrm_nvm_write_input (size:384b/48B) */ +/* hwrm_nvm_write_input (size:448b/56B) */ struct hwrm_nvm_write_input { /* The HWRM command request type. */ uint16_t req_type; @@ -48296,10 +50304,7 @@ struct hwrm_nvm_write_input { * This is where the source data is. */ uint64_t host_src_addr; - /* - * The Directory Entry Type (valid values are defined in the - * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). - */ + /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */ uint16_t dir_type; /* * Directory ordinal. @@ -48311,10 +50316,8 @@ struct hwrm_nvm_write_input { /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ uint16_t dir_attr; /* - * Length of data to write, in bytes.May be - * less than or equal to the allocated size for the directory entry. - * The data length stored in the directory entry will be updated to - * reflect this value once the write is complete. + * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry. + * The data length stored in the directory entry will be updated to reflect this value once the write is complete. */ uint32_t dir_data_length; /* Option. */ @@ -48327,17 +50330,41 @@ struct hwrm_nvm_write_input { #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ UINT32_C(0x1) /* - * The requested length of the allocated NVM for the item, in bytes. - * This value may be greater than or equal to the specified data length (dir_data_length). + * This flag indicates the sender wants to modify a continuous + * NVRAM area using a batch of this HWRM requests. The + * offset of a request must be continuous to the end of previous + * request's. Firmware does not update the directory entry until + * receiving the last request, which is indicated by the batch_last + * flag. This flag is set usually when a sender does not have a + * block of memory that is big enough to hold the entire NVRAM + * data for send at one time. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE \ + UINT32_C(0x2) + /* + * This flag can be used only when the batch_mode flag is set. It + * indicates this request is the last of batch requests. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST \ + UINT32_C(0x4) + /* + * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length). * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, which may - * be greater than the requested item length. - * The purpose for allocating more than the required number of bytes for - * an item's data is to pre-allocate extra storage (padding) to accommodate - * the potential future growth of an item (e.g. upgraded firmware with - * a size increase, log growth, expanded configuration data). + * The response will contain the actual allocated item length, which may be greater than the requested item length. + * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate + * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data). */ uint32_t dir_item_length; + /* + * 32-bit offset of data blob from where data is being written. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t offset; + /* + * Length of data to be written.Should be non-zero. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t len; uint32_t unused_0; } __rte_packed; @@ -48352,10 +50379,8 @@ struct hwrm_nvm_write_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Length of the allocated NVM for the item, in bytes. The value may be - * greater than or equal to the specified data length or the requested item length. - * The actual item length used when creating a new directory entry will - * be a multiple of an NVM block size. + * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length. + * The actual item length used when creating a new directory entry will be a multiple of an NVM block size. */ uint32_t dir_item_length; /* The directory index of the created or modified item. */ @@ -48699,10 +50724,7 @@ struct hwrm_nvm_get_dev_info_output { /* Total size, in bytes of the NVRAM device. */ uint32_t nvram_size; uint32_t reserved_size; - /* - * Available size that can be used, in bytes. Available size is the - * NVRAM size take away the used size and reserved size. - */ + /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */ uint32_t available_size; /* This field represents the major version of NVM cfg */ uint8_t nvm_cfg_ver_maj; @@ -48844,10 +50866,7 @@ struct hwrm_nvm_mod_dir_entry_input { * The (0-based) instance of this Directory Type. */ uint16_t dir_ordinal; - /* - * The Directory Entry Extension flags (see BNX_DIR_EXT_* for - * extension flag definitions). - */ + /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */ uint16_t dir_ext; /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */ uint16_t dir_attr; @@ -49016,10 +51035,8 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \ UINT32_C(0x1) /* - * If set to 1, then unspecified images, images not in the package file, - * will be safely deleted. - * When combined with erase_unused_space then unspecified images will be - * securely erased. + * If set to 1, then unspecified images, images not in the package file, will be safely deleted. + * When combined with erase_unused_space then unspecified images will be securely erased. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ UINT32_C(0x2) @@ -49116,13 +51133,19 @@ struct hwrm_nvm_install_update_cmd_err { */ uint8_t code; /* Unknown error */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) /* Unable to complete operation due to fragmentation */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR \ + UINT32_C(0x1) /* nvm is completely full. */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE \ + UINT32_C(0x2) + /* Firmware update failed due to Anti-rollback. */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \ + UINT32_C(0x3) #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \ - HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE + HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK uint8_t unused_0[7]; } __rte_packed; @@ -49404,10 +51427,7 @@ struct hwrm_nvm_set_variable_input { /* index for the 4th dimensions */ uint16_t index_3; uint8_t flags; - /* - * When this bit is 1, flush internal cache after this write operation - * (see hwrm_nvm_flush command.) - */ + /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */ #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \ UINT32_C(0x1) /* encryption method */ @@ -49589,6 +51609,84 @@ struct hwrm_nvm_validate_option_cmd_err { uint8_t unused_0[7]; } __rte_packed; +/******************* + * hwrm_nvm_defrag * + *******************/ + + +/* hwrm_nvm_defrag_input (size:192b/24B) */ +struct hwrm_nvm_defrag_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* This bit must be '1' to perform NVM defragmentation. */ + #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_nvm_defrag_output (size:128b/16B) */ +struct hwrm_nvm_defrag_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_nvm_defrag_cmd_err (size:64b/8B) */ +struct hwrm_nvm_defrag_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* NVM defragmentation could not be performed */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1) + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST \ + HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL + uint8_t unused_0[7]; +} __rte_packed; + /**************** * hwrm_oem_cmd * ****************/ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 3b86410fb1..092c22e505 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1015,13 +1015,15 @@ ulp_context_initialized(struct bnxt_ulp_session_state *session, bool *init) * pointer, otherwise allocate a new session. */ static struct bnxt_ulp_session_state * -ulp_get_session(struct rte_pci_addr *pci_addr) +ulp_get_session(struct bnxt *bp, struct rte_pci_addr *pci_addr) { struct bnxt_ulp_session_state *session; + /* if multi root capability is enabled, then ignore the pci bus id */ STAILQ_FOREACH(session, &bnxt_ulp_session_list, next) { if (session->pci_info.domain == pci_addr->domain && - session->pci_info.bus == pci_addr->bus) { + (BNXT_MULTIROOT_EN(bp) || + session->pci_info.bus == pci_addr->bus)) { return session; } } @@ -1049,7 +1051,7 @@ ulp_session_init(struct bnxt *bp, pthread_mutex_lock(&bnxt_ulp_global_mutex); - session = ulp_get_session(pci_addr); + session = ulp_get_session(bp, pci_addr); if (!session) { /* Not Found the session Allocate a new one */ session = rte_zmalloc("bnxt_ulp_session", @@ -1552,7 +1554,7 @@ bnxt_ulp_port_deinit(struct bnxt *bp) pci_dev = RTE_DEV_TO_PCI(bp->eth_dev->device); pci_addr = &pci_dev->addr; pthread_mutex_lock(&bnxt_ulp_global_mutex); - session = ulp_get_session(pci_addr); + session = ulp_get_session(bp, pci_addr); pthread_mutex_unlock(&bnxt_ulp_global_mutex); /* session not found then just exit */ -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH 3/9] net/bnxt: fix the out of boundary issue in hash list 2021-10-01 5:59 [dpdk-dev] [PATCH 0/9] fixes and enhancements to Truflow Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 1/9] net/bnxt: add nat support for dest IP and port combination Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 2/9] net/bnxt: support multi root capability flag Venkat Duvvuru @ 2021-10-01 5:59 ` Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 4/9] net/bnxt: add clear on read stats support for Thor Venkat Duvvuru ` (7 subsequent siblings) 10 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-01 5:59 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, stable, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> The number of hash bucket list calculation is fixed and added check to limit the out of boundary condition Fixes: 0001cc58d362 ("net/bnxt: support generic hash table") Cc: stable@dpdk.org Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c index 3c6e7fe924..84c83de35c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c @@ -16,20 +16,21 @@ int32_t ulp_bit_alloc_list_alloc(struct bit_alloc_list *blist, { uint64_t bentry; uint32_t idx = 0, jdx = 0; + uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES; /* Iterate all numbers that have all 1's */ do { bentry = blist->bdata[idx++]; - } while (bentry == -1UL && idx < blist->bsize); + } while (bentry == -1UL && idx <= bsize_64); - if (idx < blist->bsize) { + if (idx <= bsize_64) { if (bentry) jdx = __builtin_clzl(~bentry); *index = ((idx - 1) * ULP_INDEX_BITMAP_SIZE) + jdx; ULP_INDEX_BITMAP_SET(blist->bdata[(idx - 1)], jdx); return 0; } - jdx = (uint32_t)(blist->bsize * ULP_INDEX_BITMAP_SIZE); + jdx = (uint32_t)(bsize_64 * ULP_INDEX_BITMAP_SIZE); BNXT_TF_DBG(ERR, "bit allocator is full reached max:%x\n", jdx); return -1; } @@ -39,9 +40,10 @@ int32_t ulp_bit_alloc_list_dealloc(struct bit_alloc_list *blist, uint32_t index) { uint32_t idx = 0, jdx; + uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES; idx = index / ULP_INDEX_BITMAP_SIZE; - if (idx >= blist->bsize) { + if (idx >= bsize_64) { BNXT_TF_DBG(ERR, "invalid bit index %x:%x\n", idx, blist->bsize); return -EINVAL; @@ -127,7 +129,8 @@ ulp_gen_hash_tbl_list_init(struct ulp_hash_create_params *cparams, hash_tbl->hash_mask = size - 1; /* allocate the memory for the bit allocator */ - size = (cparams->num_key_entries / sizeof(uint64_t)) + 1; + size = (cparams->num_key_entries / sizeof(uint64_t)); + size = ULP_BYTE_ROUND_OFF_8(size); hash_tbl->bit_list.bsize = size; hash_tbl->bit_list.bdata = rte_zmalloc("Generic hash bit alloc", size, ULP_BUFFER_ALIGN_64_BYTE); @@ -311,7 +314,12 @@ ulp_gen_hash_tbl_list_add(struct ulp_gen_hash_tbl *hash_tbl, BNXT_TF_DBG(ERR, "Error in bit list alloc\n"); return -ENOMEM; } - + if (key_index > hash_tbl->num_key_entries) { + BNXT_TF_DBG(ERR, "reached max size %u:%u\n", key_index, + hash_tbl->num_key_entries); + ulp_bit_alloc_list_dealloc(&hash_tbl->bit_list, key_index); + return -ENOMEM; + } /* Update the hash entry */ ULP_HASH_BUCKET_MARK_INUSE(bucket, (uint16_t)key_index); -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH 4/9] net/bnxt: add clear on read stats support for Thor 2021-10-01 5:59 [dpdk-dev] [PATCH 0/9] fixes and enhancements to Truflow Venkat Duvvuru ` (2 preceding siblings ...) 2021-10-01 5:59 ` [dpdk-dev] [PATCH 3/9] net/bnxt: fix the out of boundary issue in hash list Venkat Duvvuru @ 2021-10-01 5:59 ` Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 5/9] net/bnxt: add feature capability option for socket direct Venkat Duvvuru ` (6 subsequent siblings) 10 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-01 5:59 UTC (permalink / raw) To: dev; +Cc: Farah Smith, Kishore Padmanabha, Venkat Duvvuru From: Farah Smith <farah.smith@broadcom.com> Currently, the flow stats are not cleared after they are read from the fw. This patch adds support for clear on read. Since clear on read support is added for flow stats in Thor, the flow accumulation is enabled on Thor as well. Signed-off-by: Farah Smith <farah.smith@broadcom.com> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com> --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 34 ++++++++++++++++++++------ drivers/net/bnxt/tf_core/tf_msg.c | 24 +++++++++++++++--- drivers/net/bnxt/tf_core/tf_msg.h | 6 +++-- drivers/net/bnxt/tf_core/tf_tbl.c | 6 +++-- drivers/net/bnxt/tf_core/tf_tbl_sram.c | 13 ++++++++-- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 3 ++- 6 files changed, 67 insertions(+), 19 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 9ed66525b7..c2146bd53c 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1058,8 +1058,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 54 -#define HWRM_VERSION_STR "1.10.2.54" +#define HWRM_VERSION_RSVD 55 +#define HWRM_VERSION_STR "1.10.2.55" /**************** * hwrm_ver_get * @@ -46253,13 +46253,22 @@ struct hwrm_tf_tbl_type_get_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entry on read. + */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* @@ -48489,13 +48498,22 @@ struct hwrm_tf_tbl_type_bulk_get_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entries on read. + */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 0fbb2fe837..ea6e2af7ce 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -1851,7 +1851,8 @@ tf_msg_get_tbl_entry(struct tf *tfp, uint16_t hcapi_type, uint16_t size, uint8_t *data, - uint32_t index) + uint32_t index, + bool clear_on_read) { int rc; struct hwrm_tf_tbl_type_get_input req = { 0 }; @@ -1860,6 +1861,7 @@ tf_msg_get_tbl_entry(struct tf *tfp, uint8_t fw_session_id; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t flags = 0; /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); @@ -1889,10 +1891,16 @@ tf_msg_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } + flags = (dir == TF_DIR_TX ? + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX : + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX); + + if (clear_on_read) + flags |= HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ; /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); - req.flags = tfp_cpu_to_le_16(dir); + req.flags = tfp_cpu_to_le_16(flags); req.type = tfp_cpu_to_le_32(hcapi_type); req.index = tfp_cpu_to_le_32(index); @@ -2105,7 +2113,8 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint32_t starting_idx, uint16_t num_entries, uint16_t entry_sz_in_bytes, - uint64_t physical_mem_addr) + uint64_t physical_mem_addr, + bool clear_on_read) { int rc; struct tfp_send_msg_parms parms = { 0 }; @@ -2115,6 +2124,7 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint8_t fw_session_id; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t flags = 0; /* Retrieve the session information */ rc = tf_session_get_session(tfp, &tfs); @@ -2144,10 +2154,16 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } + flags = (dir == TF_DIR_TX ? + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX : + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX); + + if (clear_on_read) + flags |= HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ; /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); - req.flags = tfp_cpu_to_le_16(dir); + req.flags = tfp_cpu_to_le_16(flags); req.type = tfp_cpu_to_le_32(hcapi_type); req.start_index = tfp_cpu_to_le_32(starting_idx); req.num_entries = tfp_cpu_to_le_32(num_entries); diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index b26b15bfa3..718bc2f3b2 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -652,7 +652,8 @@ int tf_msg_get_tbl_entry(struct tf *tfp, uint16_t hcapi_type, uint16_t size, uint8_t *data, - uint32_t index); + uint32_t index, + bool clear_on_read); /* HWRM Tunneled messages */ @@ -704,7 +705,8 @@ int tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint32_t starting_idx, uint16_t num_entries, uint16_t entry_sz_in_bytes, - uint64_t physical_mem_addr); + uint64_t physical_mem_addr, + bool clear_on_read); /** * Sends Set message of a IF Table Type element to the firmware. diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 0a8720e7b6..12eca36491 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -441,7 +441,8 @@ tf_tbl_get(struct tf *tfp, hcapi_type, parms->data_sz_in_bytes, parms->data, - parms->idx); + parms->idx, + false); if (rc) { TFP_DRV_LOG(ERR, "%s, Get failed, type:%s, rc:%s\n", @@ -526,7 +527,8 @@ tf_tbl_bulk_get(struct tf *tfp, parms->starting_idx, parms->num_entries, parms->entry_sz_in_bytes, - parms->physical_mem_addr); + parms->physical_mem_addr, + false); if (rc) { TFP_DRV_LOG(ERR, "%s, Bulk get failed, type:%s, rc:%s\n", diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c index 636811bc2d..567f912dfa 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c +++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c @@ -539,6 +539,7 @@ tf_tbl_sram_get(struct tf *tfp, struct tf_tbl_sram_get_info_parms iparms = { 0 }; struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; void *sram_handle = NULL; + bool clear_on_read = false; TF_CHECK_PARMS3(tfp, parms, parms->data); @@ -608,6 +609,8 @@ tf_tbl_sram_get(struct tf *tfp, strerror(-rc)); return rc; } + if (parms->type == TF_TBL_TYPE_ACT_STATS_64) + clear_on_read = true; /* Get the entry */ rc = tf_msg_get_tbl_entry(tfp, @@ -615,7 +618,8 @@ tf_tbl_sram_get(struct tf *tfp, hcapi_type, parms->data_sz_in_bytes, parms->data, - parms->idx); + parms->idx, + clear_on_read); if (rc) { TFP_DRV_LOG(ERR, "%s, Get failed, type:%s, rc:%s\n", @@ -643,6 +647,7 @@ tf_tbl_sram_bulk_get(struct tf *tfp, struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; bool allocated = false; void *sram_handle = NULL; + bool clear_on_read = false; TF_CHECK_PARMS2(tfp, parms); @@ -728,6 +733,9 @@ tf_tbl_sram_bulk_get(struct tf *tfp, return rc; } + if (parms->type == TF_TBL_TYPE_ACT_STATS_64) + clear_on_read = true; + /* Get the entries */ rc = tf_msg_bulk_get_tbl_entry(tfp, parms->dir, @@ -735,7 +743,8 @@ tf_tbl_sram_bulk_get(struct tf *tfp, parms->starting_idx, parms->num_entries, parms->entry_sz_in_bytes, - parms->physical_mem_addr); + parms->physical_mem_addr, + clear_on_read); if (rc) { TFP_DRV_LOG(ERR, "%s, Bulk get failed, type:%s, rc:%s\n", diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 092c22e505..3083c40113 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1488,7 +1488,8 @@ bnxt_ulp_port_init(struct bnxt *bp) goto jump_to_error; } - if (devid != BNXT_ULP_DEVICE_ID_THOR && BNXT_ACCUM_STATS_EN(bp)) + /* set the accumulation of the stats */ + if (BNXT_ACCUM_STATS_EN(bp)) bp->ulp_ctx->cfg_data->accum_stats = true; BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init, accum_stats:%d\n", -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH 5/9] net/bnxt: add feature capability option for socket direct 2021-10-01 5:59 [dpdk-dev] [PATCH 0/9] fixes and enhancements to Truflow Venkat Duvvuru ` (3 preceding siblings ...) 2021-10-01 5:59 ` [dpdk-dev] [PATCH 4/9] net/bnxt: add clear on read stats support for Thor Venkat Duvvuru @ 2021-10-01 5:59 ` Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 6/9] net/bnxt: enable wildcard match for ingress flows Venkat Duvvuru ` (5 subsequent siblings) 10 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-01 5:59 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Added support for socket direct feature capability so applications can enable or disable this feature. This patch contains the template changes. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/bnxt.h | 13 -- drivers/net/bnxt/bnxt_ethdev.c | 203 ------------------ drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 11 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 6 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 10 +- .../generic_templates/ulp_template_db_enum.h | 8 +- .../generic_templates/ulp_template_db_tbl.c | 5 +- 7 files changed, 30 insertions(+), 226 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index b9e120d94b..9bf6697006 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -1060,19 +1060,6 @@ int32_t bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); int32_t bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); -void bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, - uint8_t *mac, uint8_t *parent_mac); -uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); -struct bnxt *bnxt_get_bp(uint16_t port); -uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, - enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_phy_port_id(uint16_t port); -uint16_t bnxt_get_vport(uint16_t port); -enum bnxt_ulp_intf_type -bnxt_get_interface_type(uint16_t port); int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev); void bnxt_cancel_fc_thread(struct bnxt *bp); diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index aa7e7fdc85..63d764f968 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -5068,209 +5068,6 @@ static void bnxt_config_vf_req_fwd(struct bnxt *bp) BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); } -struct bnxt * -bnxt_get_bp(uint16_t port) -{ - struct bnxt *bp; - struct rte_eth_dev *dev; - - if (!rte_eth_dev_is_valid_port(port)) { - PMD_DRV_LOG(ERR, "Invalid port %d\n", port); - return NULL; - } - - dev = &rte_eth_devices[port]; - if (!is_bnxt_supported(dev)) { - PMD_DRV_LOG(ERR, "Device %d not supported\n", port); - return NULL; - } - - bp = (struct bnxt *)dev->data->dev_private; - if (!BNXT_TRUFLOW_EN(bp)) { - PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); - return NULL; - } - - return bp; -} - -uint16_t -bnxt_get_svif(uint16_t port_id, bool func_svif, - enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->svif; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return func_svif ? bp->func_svif : bp->port_svif; -} - -void -bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, - uint8_t *mac, uint8_t *parent_mac) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF && - type != BNXT_ULP_INTF_TYPE_PF) - return; - - eth_dev = &rte_eth_devices[port]; - bp = eth_dev->data->dev_private; - memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN); - - if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF) - memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN); -} - -uint16_t -bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF) - return 0; - - eth_dev = &rte_eth_devices[port]; - bp = eth_dev->data->dev_private; - - return bp->parent->vnic; -} -uint16_t -bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt_vnic_info *vnic; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->dflt_vnic_id; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - vnic = BNXT_GET_DEFAULT_VNIC(bp); - - return vnic->fw_vnic_id; -} - -uint16_t -bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->fw_fid; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return bp->fw_fid; -} - -enum bnxt_ulp_intf_type -bnxt_get_interface_type(uint16_t port) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) - return BNXT_ULP_INTF_TYPE_VF_REP; - - bp = eth_dev->data->dev_private; - if (BNXT_PF(bp)) - return BNXT_ULP_INTF_TYPE_PF; - else if (BNXT_VF_IS_TRUSTED(bp)) - return BNXT_ULP_INTF_TYPE_TRUSTED_VF; - else if (BNXT_VF(bp)) - return BNXT_ULP_INTF_TYPE_VF; - - return BNXT_ULP_INTF_TYPE_INVALID; -} - -uint16_t -bnxt_get_phy_port_id(uint16_t port_id) -{ - struct bnxt_representor *vfr; - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; -} - -uint16_t -bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->fw_fid - 1; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; -} - -uint16_t -bnxt_get_vport(uint16_t port_id) -{ - return (1 << bnxt_get_phy_port_id(port_id)); -} - static void bnxt_alloc_error_recovery_info(struct bnxt *bp) { struct bnxt_error_recovery_info *info = bp->recovery_info; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 3083c40113..58a58a431d 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -301,13 +301,14 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, } int32_t -bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, uint8_t app_id, uint32_t dev_id) { struct bnxt_ulp_app_capabilities_info *info; uint32_t num = 0; uint16_t i; bool found = false; + struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx; if (ULP_APP_DEV_UNSUPPORTED_ENABLED(ulp_ctx->cfg_data->ulp_flags)) { BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", @@ -334,6 +335,12 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, if (info[i].flags & BNXT_ULP_APP_CAP_UNICAST_ONLY) ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_APP_UNICAST_ONLY; + if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) { + /* Enable socket direction only if MR is enabled in fw*/ + if (BNXT_MULTIROOT_EN(bp)) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_SOCKET_DIRECT; + } } if (!found) { BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", @@ -837,7 +844,7 @@ ulp_ctx_init(struct bnxt *bp, } BNXT_TF_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id); - rc = bnxt_ulp_cntxt_app_caps_init(bp->ulp_ctx, bp->app_id, devid); + rc = bnxt_ulp_cntxt_app_caps_init(bp, bp->app_id, devid); if (rc) { BNXT_TF_DBG(ERR, "Unable to set caps for app(%x)/dev(%x)\n", bp->app_id, devid); diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 006df9cbc5..68f1470c61 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -13,6 +13,7 @@ #include "rte_version.h" #include "rte_ethdev.h" +#include "bnxt.h" #include "ulp_template_db_enum.h" #include "ulp_tun.h" #include "bnxt_tf_common.h" @@ -33,12 +34,15 @@ #define BNXT_ULP_APP_DEV_UNSUPPORTED 0x4 #define BNXT_ULP_HIGH_AVAIL_ENABLED 0x8 #define BNXT_ULP_APP_UNICAST_ONLY 0x10 +#define BNXT_ULP_APP_SOCKET_DIRECT 0x20 + #define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED) #define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\ BNXT_ULP_SHARED_SESSION_ENABLED) #define ULP_APP_DEV_UNSUPPORTED_ENABLED(flag) ((flag) &\ BNXT_ULP_APP_DEV_UNSUPPORTED) #define ULP_HIGH_AVAIL_IS_ENABLED(flag) ((flag) & BNXT_ULP_HIGH_AVAIL_ENABLED) +#define ULP_SOCKET_DIRECT_IS_ENABLED(flag) ((flag) & BNXT_ULP_APP_SOCKET_DIRECT) enum bnxt_ulp_flow_mem_type { BNXT_ULP_FLOW_MEM_TYPE_INT = 0, @@ -287,7 +291,7 @@ struct bnxt_ulp_app_capabilities_info * bnxt_ulp_app_cap_list_get(uint32_t *num_entries); int32_t -bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, uint8_t app_id, uint32_t dev_id); struct bnxt_ulp_resource_resv_info * diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 413e4c3b26..6413afdaf2 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -118,9 +118,11 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FLOW_SIG_ID, params->flow_sig_id); + if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags)) + return; + /* update the WC Priority flag */ - if (!bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags) && - ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) { + if (ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) { enum ulp_ha_mgr_region region = ULP_HA_REGION_LOW; int32_t rc; @@ -132,6 +134,10 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG, 1); } + + /* Update the socket direct flag */ + if (ULP_SOCKET_DIRECT_IS_ENABLED(ulp_flags)) + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT, 1); } /* Function to create the rte flow. */ diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index fcd460e707..31a94c14dc 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Aug 26 17:43:36 2021 */ +/* date: Thu Sep 9 11:11:05 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -211,7 +211,8 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 71, BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72, BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73, - BNXT_ULP_CF_IDX_LAST = 74 + BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74, + BNXT_ULP_CF_IDX_LAST = 75 }; enum bnxt_ulp_cond_list_opc { @@ -582,7 +583,8 @@ enum bnxt_ulp_template_type { enum bnxt_ulp_app_cap { BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001, BNXT_ULP_APP_CAP_HOT_UPGRADE_EN = 0x00000002, - BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004 + BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004, + BNXT_ULP_APP_CAP_SOCKET_DIRECT = 0x00000008 }; enum bnxt_ulp_fdb_resource_flags { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 84be09b368..5383e2cd70 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Aug 26 17:43:36 2021 */ +/* date: Thu Sep 9 11:11:05 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -347,7 +347,8 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { .device_id = BNXT_ULP_DEVICE_ID_THOR, .flags = BNXT_ULP_APP_CAP_SHARED_EN | BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | - BNXT_ULP_APP_CAP_UNICAST_ONLY + BNXT_ULP_APP_CAP_UNICAST_ONLY | + BNXT_ULP_APP_CAP_SOCKET_DIRECT }, { .app_id = 2, -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH 6/9] net/bnxt: enable wildcard match for ingress flows 2021-10-01 5:59 [dpdk-dev] [PATCH 0/9] fixes and enhancements to Truflow Venkat Duvvuru ` (4 preceding siblings ...) 2021-10-01 5:59 ` [dpdk-dev] [PATCH 5/9] net/bnxt: add feature capability option for socket direct Venkat Duvvuru @ 2021-10-01 5:59 ` Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 7/9] net/bnxt: support inner IP header for GRE tunnel flows Venkat Duvvuru ` (4 subsequent siblings) 10 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-01 5:59 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Enabled wildcard match support for ipv4 ingress flows. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- .../generic_templates/ulp_template_db_enum.h | 4 +- .../ulp_template_db_thor_class.c | 251 +++++++++--------- 2 files changed, 125 insertions(+), 130 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index 31a94c14dc..8706e45f28 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 11:11:05 2021 */ +/* date: Thu Sep 9 12:11:08 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -48,7 +48,7 @@ #define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2323 #define ULP_THOR_CLASS_IDENT_LIST_SIZE 38 #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313 -#define ULP_THOR_CLASS_COND_LIST_SIZE 55 +#define ULP_THOR_CLASS_COND_LIST_SIZE 54 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 95205a2421..54bc032b0c 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Aug 25 16:41:37 2021 */ +/* date: Thu Sep 9 12:11:08 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -18,9 +18,9 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .num_tbls = 28, .start_tbl_idx = 0, .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 0, - .cond_nums = 1 } + .cond_nums = 0 } }, /* class_tid: 2, ingress */ [2] = { @@ -29,7 +29,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 28, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 } }, /* class_tid: 3, egress */ @@ -39,7 +39,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 52, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 0 } }, /* class_tid: 4, ingress */ @@ -49,7 +49,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 70, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 } }, /* class_tid: 5, egress */ @@ -59,7 +59,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 91, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 } } }; @@ -74,7 +74,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -96,7 +96,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 5, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -117,7 +117,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -136,7 +136,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -149,7 +149,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -176,7 +176,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -196,7 +196,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -209,7 +209,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 4, + .cond_start_idx = 3, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -228,7 +228,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 5, + .cond_start_idx = 4, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -240,7 +240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 6, + .cond_start_idx = 5, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -259,7 +259,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 7, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -277,7 +277,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 7, + .cond_start_idx = 6, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -307,7 +307,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -328,7 +328,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -349,7 +349,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -368,7 +368,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 6, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -381,7 +381,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 9, + .cond_start_idx = 8, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, @@ -398,7 +398,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 10, + .cond_start_idx = 9, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, @@ -415,7 +415,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 11, + .cond_start_idx = 10, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -443,7 +443,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 13, + .cond_start_idx = 12, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -473,7 +473,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -494,7 +494,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 14, + .cond_start_idx = 13, .cond_nums = 3 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -519,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, + .cond_start_idx = 16, .cond_nums = 3 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -544,7 +544,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 19, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -569,7 +569,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 22, + .cond_start_idx = 21, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -594,7 +594,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 23, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -619,7 +619,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 25, + .cond_start_idx = 24, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -644,7 +644,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 27, + .cond_start_idx = 26, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -670,7 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -691,7 +691,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -710,7 +710,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -723,7 +723,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -750,7 +750,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -770,7 +770,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -783,7 +783,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 30, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -802,7 +802,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, + .cond_start_idx = 30, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -815,7 +815,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -842,7 +842,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -862,7 +862,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -875,7 +875,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, + .cond_start_idx = 32, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -894,7 +894,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 33, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -906,7 +906,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 34, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -925,7 +925,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -943,7 +943,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -973,7 +973,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -994,7 +994,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -1016,7 +1016,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1035,7 +1035,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1048,7 +1048,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 36, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, @@ -1065,7 +1065,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1093,7 +1093,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1114,7 +1114,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1140,7 +1140,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1159,7 +1159,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -1172,7 +1172,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 40, + .cond_start_idx = 39, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1191,7 +1191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 41, + .cond_start_idx = 40, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1203,7 +1203,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 42, + .cond_start_idx = 41, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -1222,7 +1222,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -1240,7 +1240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1270,7 +1270,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1291,7 +1291,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -1312,7 +1312,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1331,7 +1331,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1344,7 +1344,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 44, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, @@ -1361,7 +1361,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 44, + .cond_start_idx = 43, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1389,7 +1389,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1419,7 +1419,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1440,7 +1440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1465,7 +1465,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 47, + .cond_start_idx = 46, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1490,7 +1490,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1517,7 +1517,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, @@ -1536,7 +1536,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1558,7 +1558,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1577,7 +1577,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1590,7 +1590,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1619,7 +1619,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1640,7 +1640,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -1657,7 +1657,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -1676,7 +1676,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -1696,7 +1696,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1716,7 +1716,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -1729,7 +1729,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 50, + .cond_start_idx = 49, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1748,7 +1748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 50, + .cond_start_idx = 49, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1761,7 +1761,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, @@ -1780,7 +1780,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1802,7 +1802,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1821,7 +1821,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1834,7 +1834,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1861,7 +1861,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1882,7 +1882,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1899,7 +1899,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1918,7 +1918,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, @@ -1938,7 +1938,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1960,7 +1960,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1979,7 +1979,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1992,7 +1992,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -2019,7 +2019,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2040,7 +2040,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, @@ -2057,7 +2057,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, @@ -2076,7 +2076,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2095,7 +2095,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF, @@ -2114,7 +2114,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2133,7 +2133,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -2146,7 +2146,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, @@ -2165,7 +2165,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2188,7 +2188,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0, @@ -2207,7 +2207,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, @@ -2227,7 +2227,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2246,7 +2246,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2265,7 +2265,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -2278,7 +2278,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -2306,7 +2306,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, @@ -2323,7 +2323,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -2350,7 +2350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2373,7 +2373,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2391,7 +2391,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -2406,11 +2406,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { }; struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { - /* cond_reject: thor, class_tid: 1 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH - }, /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */ { .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH 7/9] net/bnxt: support inner IP header for GRE tunnel flows 2021-10-01 5:59 [dpdk-dev] [PATCH 0/9] fixes and enhancements to Truflow Venkat Duvvuru ` (5 preceding siblings ...) 2021-10-01 5:59 ` [dpdk-dev] [PATCH 6/9] net/bnxt: enable wildcard match for ingress flows Venkat Duvvuru @ 2021-10-01 5:59 ` Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 8/9] net/bnxt: get Truflow version Venkat Duvvuru ` (3 subsequent siblings) 10 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-01 5:59 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> This change allows adding ip header matches for GRE flows that does not specify outer ip header in the flow match pattern. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 7 ++++--- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 3a9c9bba27..09ebfeb785 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -1079,7 +1079,8 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, /* Set the ipv4 header bitmap and computed l3 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) { + ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6) || + ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV4); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1); inner_flag = 1; @@ -1205,7 +1206,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, /* Set the ipv6 header bitmap and computed l3 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) { + ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6) || + ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV6); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1); inner_flag = 1; @@ -2087,7 +2089,6 @@ ulp_rte_vxlan_decap_act_handler(const struct rte_flow_action *action_item BNXT_ULP_ACT_BIT_VXLAN_DECAP); /* Update computational field with tunnel decap info */ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN_DECAP, 1); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1); return BNXT_TF_RC_SUCCESS; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index d3bfb8c12d..7d1bc06a3e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -27,7 +27,7 @@ #define BNXT_ULP_PROTO_HDR_UDP_NUM 4 #define BNXT_ULP_PROTO_HDR_TCP_NUM 9 #define BNXT_ULP_PROTO_HDR_VXLAN_NUM 4 -#define BNXT_ULP_PROTO_HDR_GRE_NUM 6 +#define BNXT_ULP_PROTO_HDR_GRE_NUM 2 #define BNXT_ULP_PROTO_HDR_ICMP_NUM 5 #define BNXT_ULP_PROTO_HDR_MAX 128 #define BNXT_ULP_PROTO_HDR_ENCAP_MAX 64 -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH 8/9] net/bnxt: get Truflow version 2021-10-01 5:59 [dpdk-dev] [PATCH 0/9] fixes and enhancements to Truflow Venkat Duvvuru ` (6 preceding siblings ...) 2021-10-01 5:59 ` [dpdk-dev] [PATCH 7/9] net/bnxt: support inner IP header for GRE tunnel flows Venkat Duvvuru @ 2021-10-01 5:59 ` Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 9/9] net/bnxt: increase scaling numbers on Thor Venkat Duvvuru ` (2 subsequent siblings) 10 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-01 5:59 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru From: Jay Ding <jay.ding@broadcom.com> Implement TF_GET_VERSION that returns Truflow version numbers and CFA resources capabilities. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com> --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 15 ++-- drivers/net/bnxt/tf_core/tf_core.c | 30 ++++++++ drivers/net/bnxt/tf_core/tf_core.h | 75 ++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device.h | 50 ++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p4.c | 65 +++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p4.h | 79 +++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p58.c | 65 +++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p58.h | 87 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_msg.c | 35 ++++++++++ drivers/net/bnxt/tf_core/tf_msg.h | 19 ++++++ 10 files changed, 514 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index c2146bd53c..114e9fcc88 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1058,8 +1058,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 55 -#define HWRM_VERSION_STR "1.10.2.55" +#define HWRM_VERSION_RSVD 58 +#define HWRM_VERSION_STR "1.10.2.58" /**************** * hwrm_ver_get * @@ -45178,7 +45178,7 @@ struct hwrm_tf_version_get_input { uint64_t resp_addr; } __rte_packed; -/* hwrm_tf_version_get_output (size:128b/16B) */ +/* hwrm_tf_version_get_output (size:256b/32B) */ struct hwrm_tf_version_get_output { /* The specific error status for the command. */ uint16_t error_code; @@ -45195,7 +45195,14 @@ struct hwrm_tf_version_get_output { /* Version Update number. */ uint8_t update; /* unused. */ - uint8_t unused0[4]; + uint8_t unused0[5]; + /* + * This field is used to indicate device's capabilities and + * configurations. + */ + uint64_t dev_caps_cfg; + /* unused. */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 936102c804..7873bfc02c 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1802,3 +1802,33 @@ int tf_get_session_info(struct tf *tfp, return 0; } + +int tf_get_version(struct tf *tfp, + struct tf_get_version_parms *parms) +{ + int rc; + struct tf_dev_info dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_WH && + parms->device_type != TF_DEVICE_TYPE_THOR && + parms->device_type != TF_DEVICE_TYPE_SR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + rc = tf_msg_get_version(parms->bp, &dev, parms); + if (rc) + return rc; + + return 0; +} + diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index fb02c2b161..ba9881c69d 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2363,4 +2363,79 @@ struct tf_get_if_tbl_entry_parms { int tf_get_if_tbl_entry(struct tf *tfp, struct tf_get_if_tbl_entry_parms *parms); +/** + * tf_get_version parameters definition. + */ +struct tf_get_version_parms { + /** + * [in] device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] bp + * The pointer to the parent bp struct. This is only used for HWRM + * message passing within the portability layer. The type is struct + * bnxt. + */ + void *bp; + + /* [out] major + * + * Version Major number. + */ + uint8_t major; + + /* [out] minor + * + * Version Minor number. + */ + uint8_t minor; + + /* [out] update + * + * Version Update number. + */ + uint8_t update; + + /** + * [out] dev_ident_caps + * + * fw available identifier resource list + */ + uint32_t dev_ident_caps; + + /** + * [out] dev_tbl_caps + * + * fw available table resource list + */ + uint32_t dev_tbl_caps; + + /** + * [out] dev_tcam_caps + * + * fw available tcam resource list + */ + uint32_t dev_tcam_caps; + + /** + * [out] dev_em_caps + * + * fw available em resource list + */ + uint32_t dev_em_caps; +}; + +/** + * Get tf fw version + * + * Used to retrieve Truflow fw version information. + * + * Returns success or failure code. + */ +int tf_get_version(struct tf *tfp, + struct tf_get_version_parms *parms); #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 9b0c037db0..88bd4515ff 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -6,6 +6,7 @@ #ifndef _TF_DEVICE_H_ #define _TF_DEVICE_H_ +#include "cfa_resource_types.h" #include "tf_core.h" #include "tf_identifier.h" #include "tf_tbl.h" @@ -36,6 +37,21 @@ struct tf_dev_info { const struct tf_dev_ops *ops; }; +/** + * This structure can be used to translate the CFA resource type to TF type. + */ +struct tf_hcapi_resource_map { + /** + * Truflow module type associated with this resource type. + */ + enum tf_module_type module_type; + + /** + * Bitmap of TF sub-type for the element. + */ + uint32_t type_caps; +}; + /** * @page device Device * @@ -1037,6 +1053,34 @@ struct tf_dev_ops { */ uint64_t (*tf_dev_cfa_key_hash)(uint64_t *key_data, uint16_t bitlen); + + /** + * Translate the CFA resource type to Truflow type + * + * [in] hcapi_types + * CFA resource type bitmap + * + * [out] ident_types + * Pointer to identifier type bitmap + * + * [out] tcam_types + * Pointer to tcam type bitmap + * + * [out] tbl_types + * Pointer to table type bitmap + * + * [out] em_types + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_map_hcapi_caps)(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps); }; /** @@ -1047,4 +1091,10 @@ extern const struct tf_dev_ops tf_dev_ops_p4; extern const struct tf_dev_ops tf_dev_ops_p58_init; extern const struct tf_dev_ops tf_dev_ops_p58; +/** + * Supported device resource type mapping structures + */ +extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1]; +extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1]; + #endif /* _TF_DEVICE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 826cd0cdbc..8089785b82 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -271,6 +271,67 @@ static bool tf_dev_p4_is_sram_managed(struct tf *tfp __rte_unused, { return false; } + +/** + * Device specific function that maps the hcapi resource types + * to Truflow type. + * + * [in] hcapi_caps + * CFA resource type bitmap + * + * [out] ident_caps + * Pointer to identifier type bitmap + * + * [out] tcam_caps + * Pointer to tcam type bitmap + * + * [out] tbl_caps + * Pointer to table type bitmap + * + * [out] em_caps + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p4_map_hcapi_caps(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps) +{ + uint32_t i; + + *ident_caps = 0; + *tcam_caps = 0; + *tbl_caps = 0; + *em_caps = 0; + + for (i = 0; i <= CFA_RESOURCE_TYPE_P4_LAST; i++) { + if (hcapi_caps & 1ULL << i) { + switch (tf_hcapi_res_map_p4[i].module_type) { + case TF_MODULE_TYPE_IDENTIFIER: + *ident_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_TABLE: + *tbl_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_TCAM: + *tcam_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_EM: + *em_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + default: + return -EINVAL; + } + } + } + + return 0; +} + /** * Truflow P4 device specific functions */ @@ -321,6 +382,7 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = NULL, + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps }; /** @@ -382,5 +444,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = tf_dev_p4_word_align, - .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash + .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index c1357913f1..e84c0f9e83 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -157,4 +157,83 @@ struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = { TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK }, }; + +const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { + [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW + }, + [CFA_RESOURCE_TYPE_P4_PROF_FUNC] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC + }, + [CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF + }, + [CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW + }, + [CFA_RESOURCE_TYPE_P4_PROF_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM + }, + [CFA_RESOURCE_TYPE_P4_WC_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM + }, + [CFA_RESOURCE_TYPE_P4_SP_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_SP_TCAM + }, + [CFA_RESOURCE_TYPE_P4_NAT_IPV4] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_MODIFY_IPV4 + }, + [CFA_RESOURCE_TYPE_P4_METER_PROF] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF + }, + [CFA_RESOURCE_TYPE_P4_METER] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST + }, + [CFA_RESOURCE_TYPE_P4_MIRROR] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG + }, + [CFA_RESOURCE_TYPE_P4_FULL_ACTION] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_FULL_ACT_RECORD + }, + [CFA_RESOURCE_TYPE_P4_MCG] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MCAST_GROUPS + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_8B + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_16B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_16B + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_64B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_64B + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4 + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6 + }, + [CFA_RESOURCE_TYPE_P4_COUNTER_64B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64 + }, + [CFA_RESOURCE_TYPE_P4_EM_REC] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD + }, + [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_TBL_SCOPE + }, +}; + #endif /* _TF_DEVICE_P4_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 47d7836a58..03e72b90f5 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -45,6 +45,7 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { [CFA_RESOURCE_TYPE_P58_WC_FKB] = "wc_fkb ", [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = "veb ", [CFA_RESOURCE_TYPE_P58_METADATA] = "metadata", + [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = "meter_dc", }; /** @@ -336,6 +337,66 @@ static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused, return 0; } +/** + * Device specific function that maps the hcapi resource types + * to Truflow type. + * + * [in] hcapi_caps + * CFA resource type bitmap + * + * [out] ident_caps + * Pointer to identifier type bitmap + * + * [out] tcam_caps + * Pointer to tcam type bitmap + * + * [out] tbl_caps + * Pointer to table type bitmap + * + * [out] em_caps + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_map_hcapi_caps(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps) +{ + uint32_t i; + + *ident_caps = 0; + *tcam_caps = 0; + *tbl_caps = 0; + *em_caps = 0; + + for (i = 0; i <= CFA_RESOURCE_TYPE_P58_LAST; i++) { + if (hcapi_caps & 1ULL << i) { + switch (tf_hcapi_res_map_p58[i].module_type) { + case TF_MODULE_TYPE_IDENTIFIER: + *ident_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_TABLE: + *tbl_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_TCAM: + *tcam_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_EM: + *em_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + default: + return -EINVAL; + } + } + } + + return 0; +} + /** * Truflow P58 device specific functions */ @@ -386,6 +447,7 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = NULL, + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps }; /** @@ -448,5 +510,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = tf_dev_p58_word_align, - .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash + .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index 3e8759f2df..f6e66936f3 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -209,4 +209,91 @@ struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = { TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_INTERVAL_CFG }, }; + +const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { + [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW + }, + [CFA_RESOURCE_TYPE_P58_PROF_FUNC] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC + }, + [CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF + }, + [CFA_RESOURCE_TYPE_P58_EM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW + }, + [CFA_RESOURCE_TYPE_P58_PROF_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM + }, + [CFA_RESOURCE_TYPE_P58_WC_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM + }, + [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_VEB_TCAM + }, + [CFA_RESOURCE_TYPE_P58_EM_FKB] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_EM_FKB + }, + [CFA_RESOURCE_TYPE_P58_WC_FKB] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_WC_FKB + }, + [CFA_RESOURCE_TYPE_P58_METER_PROF] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF + }, + [CFA_RESOURCE_TYPE_P58_METER] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST + }, + [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_DROP_CNT + }, + [CFA_RESOURCE_TYPE_P58_MIRROR] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG + }, + [CFA_RESOURCE_TYPE_P58_METADATA] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METADATA + }, + /* Resources in bank 1 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_FULL_ACT_RECORD + | 1 << TF_TBL_TYPE_COMPACT_ACT_RECORD + }, + /* Resources in bank 2 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_ACT_ENCAP_8B | + 1 << TF_TBL_TYPE_ACT_ENCAP_16B | + 1 << TF_TBL_TYPE_ACT_ENCAP_32B | + 1 << TF_TBL_TYPE_ACT_ENCAP_64B | + 1 << TF_TBL_TYPE_ACT_MODIFY_8B | + 1 << TF_TBL_TYPE_ACT_MODIFY_16B | + 1 << TF_TBL_TYPE_ACT_MODIFY_32B | + 1 << TF_TBL_TYPE_ACT_MODIFY_64B + + }, + /* Resources in bank 0 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_ACT_SP_SMAC | + 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4 | + 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6 + }, + /* Resources in bank 3 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64 + }, + [CFA_RESOURCE_TYPE_P58_EM_REC] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD + }, +}; #endif /* _TF_DEVICE_P58_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index ea6e2af7ce..25bf026658 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -2306,3 +2306,38 @@ tf_msg_set_if_tbl_entry(struct tf *tfp, return 0; } + +int +tf_msg_get_version(struct bnxt *bp, + struct tf_dev_info *dev, + struct tf_get_version_parms *params) + +{ + int rc; + struct hwrm_tf_version_get_input req = { 0 }; + struct hwrm_tf_version_get_output resp = { 0 }; + struct tfp_send_msg_parms parms = { 0 }; + + /* Populate the request */ + parms.tf_type = HWRM_TF_VERSION_GET, + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(bp, + &parms); + + params->major = resp.major; + params->minor = resp.minor; + params->update = resp.update; + + dev->ops->tf_dev_map_hcapi_caps(resp.dev_caps_cfg, + ¶ms->dev_ident_caps, + ¶ms->dev_tcam_caps, + ¶ms->dev_tbl_caps, + ¶ms->dev_em_caps); + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 718bc2f3b2..08d20cdd7a 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -738,4 +738,23 @@ int tf_msg_set_if_tbl_entry(struct tf *tfp, int tf_msg_get_if_tbl_entry(struct tf *tfp, struct tf_if_tbl_get_parms *params); +/** + * Send get version request to the firmware. + * + * [in] bp + * Pointer to bnxt handle + * + * [in] dev + * Pointer to the associated device + * + * [in/out] parms + * Pointer to the version info parameter + * + * Returns: + * 0 on Success else internal Truflow error + */ +int +tf_msg_get_version(struct bnxt *bp, + struct tf_dev_info *dev, + struct tf_get_version_parms *parms); #endif /* _TF_MSG_H_ */ -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH 9/9] net/bnxt: increase scaling numbers on Thor 2021-10-01 5:59 [dpdk-dev] [PATCH 0/9] fixes and enhancements to Truflow Venkat Duvvuru ` (7 preceding siblings ...) 2021-10-01 5:59 ` [dpdk-dev] [PATCH 8/9] net/bnxt: get Truflow version Venkat Duvvuru @ 2021-10-01 5:59 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru 10 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-01 5:59 UTC (permalink / raw) To: dev; +Cc: Shahaji Bhosle, Kishore Padmanabha, Venkat Duvvuru From: Shahaji Bhosle <sbhosle@broadcom.com> * Updated defines and data types to allow 256 VFRs. * Increased the encap record cache to support 256 to 4K entries. So vxlan connections can be scaled to 4k entries. Signed-off-by: Shahaji Bhosle <sbhosle@broadcom.com> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/bnxt.h | 6 +++++- drivers/net/bnxt/bnxt_cpr.c | 2 +- drivers/net/bnxt/bnxt_ethdev.c | 18 +++++++++--------- drivers/net/bnxt/bnxt_reps.c | 3 +-- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 2 +- .../generic_templates/ulp_template_db_tbl.c | 8 ++++---- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 6 +++--- 7 files changed, 24 insertions(+), 21 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 9bf6697006..0209bb5c39 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -240,7 +240,11 @@ struct bnxt_parent_info { struct bnxt_pf_info { #define BNXT_FIRST_PF_FID 1 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) -#define BNXT_MAX_VF_REPS 64 +#define BNXT_MAX_VF_REPS_WH 64 +#define BNXT_MAX_VF_REPS_TH 256 +#define BNXT_MAX_VF_REPS(bp) \ + (BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_TH : \ + BNXT_MAX_VF_REPS_WH) #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) #define BNXT_FIRST_VF_FID 128 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) diff --git a/drivers/net/bnxt/bnxt_cpr.c b/drivers/net/bnxt/bnxt_cpr.c index 63ff02a198..6bb70d516e 100644 --- a/drivers/net/bnxt/bnxt_cpr.c +++ b/drivers/net/bnxt/bnxt_cpr.c @@ -74,7 +74,7 @@ bnxt_process_default_vnic_change(struct bnxt *bp, BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT; PMD_DRV_LOG(INFO, "async event received vf_id 0x%x\n", vf_fid); - for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) { + for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS(bp); vf_id++) { eth_dev = bp->rep_info[vf_id].vfr_eth_dev; if (!eth_dev) continue; diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 63d764f968..034f4cdcaa 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1185,7 +1185,7 @@ void bnxt_print_link_info(struct rte_eth_dev *eth_dev) struct rte_eth_link *link = ð_dev->data->dev_link; if (link->link_status) - PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", + PMD_DRV_LOG(DEBUG, "Port %d Link Up - speed %u Mbps - %s\n", eth_dev->data->port_id, (uint32_t)link->link_speed, (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? @@ -6046,7 +6046,7 @@ static int bnxt_init_rep_info(struct bnxt *bp) return 0; bp->rep_info = rte_zmalloc("bnxt_rep_info", - sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, + sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS(bp), 0); if (!bp->rep_info) { PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); @@ -6088,7 +6088,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, { struct rte_eth_dev *vf_rep_eth_dev; char name[RTE_ETH_NAME_MAX_LEN]; - struct bnxt *backing_bp; + struct bnxt *backing_bp = backing_eth_dev->data->dev_private; + uint16_t max_vf_reps = BNXT_MAX_VF_REPS(backing_bp); + uint16_t num_rep; int i, ret = 0; struct rte_kvargs *kvlist = NULL; @@ -6101,9 +6103,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, return -ENOTSUP; } num_rep = eth_da->nb_representor_ports; - if (num_rep > BNXT_MAX_VF_REPS) { + if (num_rep > max_vf_reps) { PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", - num_rep, BNXT_MAX_VF_REPS); + num_rep, max_vf_reps); return -EINVAL; } @@ -6114,8 +6116,6 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, return -EINVAL; } - backing_bp = backing_eth_dev->data->dev_private; - if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { PMD_DRV_LOG(ERR, "Not a PF or trusted VF. No Representor support\n"); @@ -6135,9 +6135,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, .parent_dev = backing_eth_dev }; - if (representor.vf_id >= BNXT_MAX_VF_REPS) { + if (representor.vf_id >= max_vf_reps) { PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", - representor.vf_id, BNXT_MAX_VF_REPS); + representor.vf_id, max_vf_reps); continue; } diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c index bdbad53b7d..0feefe156c 100644 --- a/drivers/net/bnxt/bnxt_reps.c +++ b/drivers/net/bnxt/bnxt_reps.c @@ -209,7 +209,6 @@ int bnxt_representor_init(struct rte_eth_dev *eth_dev, void *params) eth_dev->data->dev_link.link_status = link->link_status; eth_dev->data->dev_link.link_autoneg = link->link_autoneg; - PMD_DRV_LOG(INFO, "calling bnxt_print_link_info\n"); bnxt_print_link_info(eth_dev); PMD_DRV_LOG(INFO, @@ -818,7 +817,7 @@ int bnxt_rep_stop_all(struct bnxt *bp) if (!bp->rep_info) return 0; - for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) { + for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS(bp); vf_id++) { rep_eth_dev = bp->rep_info[vf_id].vfr_eth_dev; if (!rep_eth_dev) continue; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 68f1470c61..960a5a0c93 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -262,7 +262,7 @@ bnxt_ulp_cntxt_ptr2_ulp_flags_get(struct bnxt_ulp_context *ulp_ctx, uint32_t *flags); int32_t -bnxt_ulp_get_df_rule_info(uint8_t port_id, struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_get_df_rule_info(uint16_t port_id, struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_df_rule_info *info); struct bnxt_ulp_vfr_rule_info* diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 5383e2cd70..e43e341927 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 11:11:05 2021 */ +/* date: Thu Sep 16 11:49:55 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -164,12 +164,12 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE", - .result_num_entries = 256, + .name = "EGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE", + .result_num_entries = 4096, .result_num_bytes = 6, .key_num_bytes = 17, .num_buckets = 8, - .hash_tbl_entries = 1024, + .hash_tbl_entries = 16384, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index d8336d164e..01233c0f5e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -441,7 +441,7 @@ void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global) { struct bnxt_ulp_df_rule_info *info; - uint8_t port_id; + uint16_t port_id; if (!BNXT_TRUFLOW_EN(bp) || BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev)) @@ -505,7 +505,7 @@ int32_t bnxt_ulp_create_df_rules(struct bnxt *bp) { struct bnxt_ulp_df_rule_info *info; - uint8_t port_id; + uint16_t port_id; int rc = 0; if (!BNXT_TRUFLOW_EN(bp) || @@ -562,7 +562,7 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev) struct rte_eth_dev *parent_dev = vfr->parent_dev; struct bnxt *bp = parent_dev->data->dev_private; uint16_t vfr_port_id = vfr_ethdev->data->port_id; - uint8_t port_id; + uint16_t port_id; int rc; if (!bp || !BNXT_TRUFLOW_EN(bp)) -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow 2021-10-01 5:59 [dpdk-dev] [PATCH 0/9] fixes and enhancements to Truflow Venkat Duvvuru ` (8 preceding siblings ...) 2021-10-01 5:59 ` [dpdk-dev] [PATCH 9/9] net/bnxt: increase scaling numbers on Thor Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 01/19] net/bnxt: add NAT support for dest IP and port combination Venkat Duvvuru ` (18 more replies) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru 10 siblings, 19 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Venkat Duvvuru This patch set adds enhancements and fixes to Truflow feature. Enhancements include: * Scaling numbers on Thor * Inner IP header support for GRE tunnel flows * Enable wildcard match for ingress flows * Add clear on read for flow stats on Thor * Add nat support for dest IP and port combination * Remove 2-slice WC support * Add support for socket redirect feature * Add new API TruFlow get SRAM resources * Remove accumulation of stats devargs argument * Add TruFlow and AFM SRAM partitioning support V2: * Compilation fixes * Remove 2-slice WC support * Add support for socket redirect feature * Add new API TruFlow get SRAM resources * Remove accumulation of stats devargs argument * Add TruFlow and AFM SRAM partitioning support Farah Smith (1): net/bnxt: add clear on read support Jay Ding (4): net/bnxt: get TruFlow version net/bnxt: add new API TruFlow get SRAM resources net/bnxt: add TruFlow and AFM SRAM partitioning support net/bnxt: add Tx TruFlow table config for p4 Kishore Padmanabha (11): net/bnxt: add NAT support for dest IP and port combination net/bnxt: add support for multi root capability net/bnxt: fix the out of boundary issue in hash list net/bnxt: add capability option for socket redirect net/bnxt: enable wildcard match for ingress flows net/bnxt: support inner IP header for GRE tunnel flows net/bnxt: remove accumulation of stats devargs argument net/bnxt: updated the log messages net/bnxt: add support for socket redirect feature net/bnxt: delete the VF pair before VF representor alloc net/bnxt: check for mismatch of control and physical port Mike Baucom (1): net/bnxt: remove 2-slice WC entries for scale Shahaji Bhosle (2): net/bnxt: increase flow scale for Thor net/bnxt: fix clang compiler warnings drivers/net/bnxt/bnxt.h | 25 +- drivers/net/bnxt/bnxt_cpr.c | 2 +- drivers/net/bnxt/bnxt_ethdev.c | 274 +- drivers/net/bnxt/bnxt_hwrm.c | 36 + drivers/net/bnxt/bnxt_hwrm.h | 1 + drivers/net/bnxt/bnxt_reps.c | 9 +- drivers/net/bnxt/hsi_struct_def_dpdk.h | 2970 +++++++++++-- drivers/net/bnxt/tf_core/tf_core.c | 197 + drivers/net/bnxt/tf_core/tf_core.h | 202 + drivers/net/bnxt/tf_core/tf_device.c | 11 +- drivers/net/bnxt/tf_core/tf_device.h | 102 + drivers/net/bnxt/tf_core/tf_device_p4.c | 178 +- drivers/net/bnxt/tf_core/tf_device_p4.h | 137 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 421 +- drivers/net/bnxt/tf_core/tf_device_p58.h | 205 +- drivers/net/bnxt/tf_core/tf_msg.c | 87 +- drivers/net/bnxt/tf_core/tf_msg.h | 31 +- drivers/net/bnxt/tf_core/tf_rm.c | 3 +- drivers/net/bnxt/tf_core/tf_sram_mgr.h | 10 - drivers/net/bnxt/tf_core/tf_tbl.c | 8 +- drivers/net/bnxt/tf_core/tf_tbl_sram.c | 13 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 58 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 9 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 29 +- .../generic_templates/ulp_template_db_act.c | 376 +- .../generic_templates/ulp_template_db_class.c | 1986 ++++----- .../generic_templates/ulp_template_db_enum.h | 91 +- .../generic_templates/ulp_template_db_tbl.c | 3946 +++++++++++++---- .../ulp_template_db_thor_act.c | 150 +- .../ulp_template_db_thor_class.c | 909 ++-- .../ulp_template_db_wh_plus_act.c | 336 +- .../ulp_template_db_wh_plus_class.c | 222 +- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 8 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 12 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 20 +- drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_port_db.c | 23 + drivers/net/bnxt/tf_ulp/ulp_port_db.h | 13 + drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 32 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +- 41 files changed, 9254 insertions(+), 3894 deletions(-) -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 01/19] net/bnxt: add NAT support for dest IP and port combination 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 02/19] net/bnxt: add support for multi root capability Venkat Duvvuru ` (17 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> * Added support for NAT action for the destination IP and port combination for the Thor platform. This is not supported for Whitney platform. * Consolidated the encapsulation and NAT entries for scaling flows with NAT actions. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- .../generic_templates/ulp_template_db_act.c | 376 +++++++++++------- .../generic_templates/ulp_template_db_enum.h | 18 +- .../generic_templates/ulp_template_db_tbl.c | 14 +- .../ulp_template_db_thor_class.c | 2 +- .../ulp_template_db_wh_plus_act.c | 96 +++-- 5 files changed, 317 insertions(+), 189 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c index 0da6070d7d..ce878d8e02 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon May 17 15:30:41 2021 */ +/* date: Wed Aug 25 14:37:06 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -47,59 +47,67 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { [BNXT_ULP_ACT_HID_04bc] = 30, [BNXT_ULP_ACT_HID_00a9] = 31, [BNXT_ULP_ACT_HID_020f] = 32, - [BNXT_ULP_ACT_HID_04a9] = 33, - [BNXT_ULP_ACT_HID_01fc] = 34, - [BNXT_ULP_ACT_HID_04be] = 35, - [BNXT_ULP_ACT_HID_00ab] = 36, - [BNXT_ULP_ACT_HID_0211] = 37, - [BNXT_ULP_ACT_HID_04ab] = 38, - [BNXT_ULP_ACT_HID_01fe] = 39, - [BNXT_ULP_ACT_HID_0667] = 40, - [BNXT_ULP_ACT_HID_0254] = 41, - [BNXT_ULP_ACT_HID_03ba] = 42, - [BNXT_ULP_ACT_HID_0654] = 43, - [BNXT_ULP_ACT_HID_03a7] = 44, - [BNXT_ULP_ACT_HID_0669] = 45, - [BNXT_ULP_ACT_HID_0256] = 46, - [BNXT_ULP_ACT_HID_03bc] = 47, - [BNXT_ULP_ACT_HID_0656] = 48, - [BNXT_ULP_ACT_HID_03a9] = 49, - [BNXT_ULP_ACT_HID_021b] = 50, - [BNXT_ULP_ACT_HID_021c] = 51, - [BNXT_ULP_ACT_HID_021e] = 52, - [BNXT_ULP_ACT_HID_063f] = 53, - [BNXT_ULP_ACT_HID_0510] = 54, - [BNXT_ULP_ACT_HID_03c6] = 55, - [BNXT_ULP_ACT_HID_0082] = 56, - [BNXT_ULP_ACT_HID_06bb] = 57, - [BNXT_ULP_ACT_HID_021d] = 58, - [BNXT_ULP_ACT_HID_0641] = 59, - [BNXT_ULP_ACT_HID_0512] = 60, - [BNXT_ULP_ACT_HID_03c8] = 61, - [BNXT_ULP_ACT_HID_0084] = 62, - [BNXT_ULP_ACT_HID_06bd] = 63, - [BNXT_ULP_ACT_HID_06d7] = 64, - [BNXT_ULP_ACT_HID_02c4] = 65, - [BNXT_ULP_ACT_HID_042a] = 66, - [BNXT_ULP_ACT_HID_06c4] = 67, - [BNXT_ULP_ACT_HID_0417] = 68, - [BNXT_ULP_ACT_HID_06d9] = 69, - [BNXT_ULP_ACT_HID_02c6] = 70, - [BNXT_ULP_ACT_HID_042c] = 71, - [BNXT_ULP_ACT_HID_06c6] = 72, - [BNXT_ULP_ACT_HID_0419] = 73, - [BNXT_ULP_ACT_HID_0119] = 74, - [BNXT_ULP_ACT_HID_046f] = 75, - [BNXT_ULP_ACT_HID_05d5] = 76, - [BNXT_ULP_ACT_HID_0106] = 77, - [BNXT_ULP_ACT_HID_05c2] = 78, - [BNXT_ULP_ACT_HID_011b] = 79, - [BNXT_ULP_ACT_HID_0471] = 80, - [BNXT_ULP_ACT_HID_05d7] = 81, - [BNXT_ULP_ACT_HID_0108] = 82, - [BNXT_ULP_ACT_HID_05c4] = 83, - [BNXT_ULP_ACT_HID_00a2] = 84, - [BNXT_ULP_ACT_HID_00a4] = 85 + [BNXT_ULP_ACT_HID_0153] = 33, + [BNXT_ULP_ACT_HID_04a9] = 34, + [BNXT_ULP_ACT_HID_01fc] = 35, + [BNXT_ULP_ACT_HID_04be] = 36, + [BNXT_ULP_ACT_HID_00ab] = 37, + [BNXT_ULP_ACT_HID_0211] = 38, + [BNXT_ULP_ACT_HID_0155] = 39, + [BNXT_ULP_ACT_HID_04ab] = 40, + [BNXT_ULP_ACT_HID_01fe] = 41, + [BNXT_ULP_ACT_HID_0667] = 42, + [BNXT_ULP_ACT_HID_0254] = 43, + [BNXT_ULP_ACT_HID_03ba] = 44, + [BNXT_ULP_ACT_HID_02fe] = 45, + [BNXT_ULP_ACT_HID_0654] = 46, + [BNXT_ULP_ACT_HID_03a7] = 47, + [BNXT_ULP_ACT_HID_0669] = 48, + [BNXT_ULP_ACT_HID_0256] = 49, + [BNXT_ULP_ACT_HID_03bc] = 50, + [BNXT_ULP_ACT_HID_0300] = 51, + [BNXT_ULP_ACT_HID_0656] = 52, + [BNXT_ULP_ACT_HID_03a9] = 53, + [BNXT_ULP_ACT_HID_021b] = 54, + [BNXT_ULP_ACT_HID_021c] = 55, + [BNXT_ULP_ACT_HID_021e] = 56, + [BNXT_ULP_ACT_HID_063f] = 57, + [BNXT_ULP_ACT_HID_0510] = 58, + [BNXT_ULP_ACT_HID_03c6] = 59, + [BNXT_ULP_ACT_HID_0082] = 60, + [BNXT_ULP_ACT_HID_06bb] = 61, + [BNXT_ULP_ACT_HID_021d] = 62, + [BNXT_ULP_ACT_HID_0641] = 63, + [BNXT_ULP_ACT_HID_0512] = 64, + [BNXT_ULP_ACT_HID_03c8] = 65, + [BNXT_ULP_ACT_HID_0084] = 66, + [BNXT_ULP_ACT_HID_06bd] = 67, + [BNXT_ULP_ACT_HID_06d7] = 68, + [BNXT_ULP_ACT_HID_02c4] = 69, + [BNXT_ULP_ACT_HID_042a] = 70, + [BNXT_ULP_ACT_HID_036e] = 71, + [BNXT_ULP_ACT_HID_06c4] = 72, + [BNXT_ULP_ACT_HID_0417] = 73, + [BNXT_ULP_ACT_HID_06d9] = 74, + [BNXT_ULP_ACT_HID_02c6] = 75, + [BNXT_ULP_ACT_HID_042c] = 76, + [BNXT_ULP_ACT_HID_0370] = 77, + [BNXT_ULP_ACT_HID_06c6] = 78, + [BNXT_ULP_ACT_HID_0419] = 79, + [BNXT_ULP_ACT_HID_0119] = 80, + [BNXT_ULP_ACT_HID_046f] = 81, + [BNXT_ULP_ACT_HID_05d5] = 82, + [BNXT_ULP_ACT_HID_0519] = 83, + [BNXT_ULP_ACT_HID_0106] = 84, + [BNXT_ULP_ACT_HID_05c2] = 85, + [BNXT_ULP_ACT_HID_011b] = 86, + [BNXT_ULP_ACT_HID_0471] = 87, + [BNXT_ULP_ACT_HID_05d7] = 88, + [BNXT_ULP_ACT_HID_051b] = 89, + [BNXT_ULP_ACT_HID_0108] = 90, + [BNXT_ULP_ACT_HID_05c4] = 91, + [BNXT_ULP_ACT_HID_00a2] = 92, + [BNXT_ULP_ACT_HID_00a4] = 93 }; /* Array for the act matcher list */ @@ -429,22 +437,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 3 }, [33] = { - .act_hid = BNXT_ULP_ACT_HID_04a9, + .act_hid = BNXT_ULP_ACT_HID_0153, .act_pattern_id = 3, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [34] = { - .act_hid = BNXT_ULP_ACT_HID_01fc, + .act_hid = BNXT_ULP_ACT_HID_04a9, .act_pattern_id = 4, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | @@ -452,40 +458,63 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 3 }, [35] = { - .act_hid = BNXT_ULP_ACT_HID_04be, + .act_hid = BNXT_ULP_ACT_HID_01fc, .act_pattern_id = 5, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [36] = { - .act_hid = BNXT_ULP_ACT_HID_00ab, + .act_hid = BNXT_ULP_ACT_HID_04be, .act_pattern_id = 6, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [37] = { - .act_hid = BNXT_ULP_ACT_HID_0211, + .act_hid = BNXT_ULP_ACT_HID_00ab, .act_pattern_id = 7, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [38] = { - .act_hid = BNXT_ULP_ACT_HID_04ab, + .act_hid = BNXT_ULP_ACT_HID_0211, .act_pattern_id = 8, .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [39] = { + .act_hid = BNXT_ULP_ACT_HID_0155, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [40] = { + .act_hid = BNXT_ULP_ACT_HID_04ab, + .act_pattern_id = 10, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -494,9 +523,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [39] = { + [41] = { .act_hid = BNXT_ULP_ACT_HID_01fe, - .act_pattern_id = 9, + .act_pattern_id = 11, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -507,9 +536,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [40] = { + [42] = { .act_hid = BNXT_ULP_ACT_HID_0667, - .act_pattern_id = 10, + .act_pattern_id = 12, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -517,9 +546,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [41] = { + [43] = { .act_hid = BNXT_ULP_ACT_HID_0254, - .act_pattern_id = 11, + .act_pattern_id = 13, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -528,9 +557,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [42] = { + [44] = { .act_hid = BNXT_ULP_ACT_HID_03ba, - .act_pattern_id = 12, + .act_pattern_id = 14, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -538,9 +567,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [43] = { + [45] = { + .act_hid = BNXT_ULP_ACT_HID_02fe, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [46] = { .act_hid = BNXT_ULP_ACT_HID_0654, - .act_pattern_id = 13, + .act_pattern_id = 16, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -550,9 +590,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [44] = { + [47] = { .act_hid = BNXT_ULP_ACT_HID_03a7, - .act_pattern_id = 14, + .act_pattern_id = 17, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -563,9 +603,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [45] = { + [48] = { .act_hid = BNXT_ULP_ACT_HID_0669, - .act_pattern_id = 15, + .act_pattern_id = 18, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -574,9 +614,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [46] = { + [49] = { .act_hid = BNXT_ULP_ACT_HID_0256, - .act_pattern_id = 16, + .act_pattern_id = 19, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -586,9 +626,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [47] = { + [50] = { .act_hid = BNXT_ULP_ACT_HID_03bc, - .act_pattern_id = 17, + .act_pattern_id = 20, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -597,9 +637,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [48] = { + [51] = { + .act_hid = BNXT_ULP_ACT_HID_0300, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [52] = { .act_hid = BNXT_ULP_ACT_HID_0656, - .act_pattern_id = 18, + .act_pattern_id = 22, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -610,9 +662,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [49] = { + [53] = { .act_hid = BNXT_ULP_ACT_HID_03a9, - .act_pattern_id = 19, + .act_pattern_id = 23, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -624,7 +676,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [50] = { + [54] = { .act_hid = BNXT_ULP_ACT_HID_021b, .act_pattern_id = 0, .app_sig = 0, @@ -632,7 +684,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [51] = { + [55] = { .act_hid = BNXT_ULP_ACT_HID_021c, .act_pattern_id = 1, .app_sig = 0, @@ -641,7 +693,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [52] = { + [56] = { .act_hid = BNXT_ULP_ACT_HID_021e, .act_pattern_id = 2, .app_sig = 0, @@ -651,7 +703,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [53] = { + [57] = { .act_hid = BNXT_ULP_ACT_HID_063f, .act_pattern_id = 3, .app_sig = 0, @@ -662,7 +714,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [54] = { + [58] = { .act_hid = BNXT_ULP_ACT_HID_0510, .act_pattern_id = 4, .app_sig = 0, @@ -672,7 +724,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [55] = { + [59] = { .act_hid = BNXT_ULP_ACT_HID_03c6, .act_pattern_id = 5, .app_sig = 0, @@ -681,7 +733,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [56] = { + [60] = { .act_hid = BNXT_ULP_ACT_HID_0082, .act_pattern_id = 6, .app_sig = 0, @@ -693,7 +745,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [57] = { + [61] = { .act_hid = BNXT_ULP_ACT_HID_06bb, .act_pattern_id = 7, .app_sig = 0, @@ -704,7 +756,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [58] = { + [62] = { .act_hid = BNXT_ULP_ACT_HID_021d, .act_pattern_id = 8, .app_sig = 0, @@ -713,7 +765,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [59] = { + [63] = { .act_hid = BNXT_ULP_ACT_HID_0641, .act_pattern_id = 9, .app_sig = 0, @@ -725,7 +777,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [60] = { + [64] = { .act_hid = BNXT_ULP_ACT_HID_0512, .act_pattern_id = 10, .app_sig = 0, @@ -736,7 +788,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [61] = { + [65] = { .act_hid = BNXT_ULP_ACT_HID_03c8, .act_pattern_id = 11, .app_sig = 0, @@ -746,7 +798,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [62] = { + [66] = { .act_hid = BNXT_ULP_ACT_HID_0084, .act_pattern_id = 12, .app_sig = 0, @@ -759,7 +811,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [63] = { + [67] = { .act_hid = BNXT_ULP_ACT_HID_06bd, .act_pattern_id = 13, .app_sig = 0, @@ -771,7 +823,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [64] = { + [68] = { .act_hid = BNXT_ULP_ACT_HID_06d7, .act_pattern_id = 0, .app_sig = 0, @@ -780,7 +832,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [65] = { + [69] = { .act_hid = BNXT_ULP_ACT_HID_02c4, .act_pattern_id = 1, .app_sig = 0, @@ -790,7 +842,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [66] = { + [70] = { .act_hid = BNXT_ULP_ACT_HID_042a, .act_pattern_id = 2, .app_sig = 0, @@ -799,10 +851,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [67] = { - .act_hid = BNXT_ULP_ACT_HID_06c4, + [71] = { + .act_hid = BNXT_ULP_ACT_HID_036e, .act_pattern_id = 3, .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [72] = { + .act_hid = BNXT_ULP_ACT_HID_06c4, + .act_pattern_id = 4, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | @@ -810,9 +872,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [68] = { + [73] = { .act_hid = BNXT_ULP_ACT_HID_0417, - .act_pattern_id = 4, + .act_pattern_id = 5, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -822,9 +884,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [69] = { + [74] = { .act_hid = BNXT_ULP_ACT_HID_06d9, - .act_pattern_id = 5, + .act_pattern_id = 6, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -832,9 +894,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [70] = { + [75] = { .act_hid = BNXT_ULP_ACT_HID_02c6, - .act_pattern_id = 6, + .act_pattern_id = 7, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -843,9 +905,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [71] = { + [76] = { .act_hid = BNXT_ULP_ACT_HID_042c, - .act_pattern_id = 7, + .act_pattern_id = 8, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -853,9 +915,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [72] = { + [77] = { + .act_hid = BNXT_ULP_ACT_HID_0370, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [78] = { .act_hid = BNXT_ULP_ACT_HID_06c6, - .act_pattern_id = 8, + .act_pattern_id = 10, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -865,9 +938,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [73] = { + [79] = { .act_hid = BNXT_ULP_ACT_HID_0419, - .act_pattern_id = 9, + .act_pattern_id = 11, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -878,9 +951,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [74] = { + [80] = { .act_hid = BNXT_ULP_ACT_HID_0119, - .act_pattern_id = 10, + .act_pattern_id = 12, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -888,9 +961,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [75] = { + [81] = { .act_hid = BNXT_ULP_ACT_HID_046f, - .act_pattern_id = 11, + .act_pattern_id = 13, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -899,9 +972,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [76] = { + [82] = { .act_hid = BNXT_ULP_ACT_HID_05d5, - .act_pattern_id = 12, + .act_pattern_id = 14, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -909,9 +982,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [77] = { + [83] = { + .act_hid = BNXT_ULP_ACT_HID_0519, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [84] = { .act_hid = BNXT_ULP_ACT_HID_0106, - .act_pattern_id = 13, + .act_pattern_id = 16, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -921,9 +1005,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [78] = { + [85] = { .act_hid = BNXT_ULP_ACT_HID_05c2, - .act_pattern_id = 14, + .act_pattern_id = 17, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -934,9 +1018,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [79] = { + [86] = { .act_hid = BNXT_ULP_ACT_HID_011b, - .act_pattern_id = 15, + .act_pattern_id = 18, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -945,9 +1029,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [80] = { + [87] = { .act_hid = BNXT_ULP_ACT_HID_0471, - .act_pattern_id = 16, + .act_pattern_id = 19, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -957,9 +1041,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [81] = { + [88] = { .act_hid = BNXT_ULP_ACT_HID_05d7, - .act_pattern_id = 17, + .act_pattern_id = 20, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -968,9 +1052,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [82] = { + [89] = { + .act_hid = BNXT_ULP_ACT_HID_051b, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [90] = { .act_hid = BNXT_ULP_ACT_HID_0108, - .act_pattern_id = 18, + .act_pattern_id = 22, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -981,9 +1077,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [83] = { + [91] = { .act_hid = BNXT_ULP_ACT_HID_05c4, - .act_pattern_id = 19, + .act_pattern_id = 23, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -995,7 +1091,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [84] = { + [92] = { .act_hid = BNXT_ULP_ACT_HID_00a2, .act_pattern_id = 0, .app_sig = 0, @@ -1004,7 +1100,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [85] = { + [93] = { .act_hid = BNXT_ULP_ACT_HID_00a4, .act_pattern_id = 1, .app_sig = 0, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index c016e1940a..fcd460e707 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 20 17:59:14 2021 */ +/* date: Thu Aug 26 17:43:36 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -20,7 +20,7 @@ #define BNXT_ULP_CLASS_HID_SHFTL 28 #define BNXT_ULP_CLASS_HID_MASK 65535 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 -#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86 +#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 94 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 #define BNXT_ULP_ACT_HID_HIGH_PRIME 3793 #define BNXT_ULP_ACT_HID_SHFTR 27 @@ -29,7 +29,7 @@ #define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110 #define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50 -#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278 +#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 277 #define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 @@ -50,11 +50,11 @@ #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313 #define ULP_THOR_CLASS_COND_LIST_SIZE 55 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 -#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35 +#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1 #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536 -#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39 +#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 41 #define ULP_THOR_ACT_TMPL_LIST_SIZE 7 #define ULP_THOR_ACT_TBL_LIST_SIZE 36 #define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16 @@ -2224,21 +2224,25 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_04bc = 0x04bc, BNXT_ULP_ACT_HID_00a9 = 0x00a9, BNXT_ULP_ACT_HID_020f = 0x020f, + BNXT_ULP_ACT_HID_0153 = 0x0153, BNXT_ULP_ACT_HID_04a9 = 0x04a9, BNXT_ULP_ACT_HID_01fc = 0x01fc, BNXT_ULP_ACT_HID_04be = 0x04be, BNXT_ULP_ACT_HID_00ab = 0x00ab, BNXT_ULP_ACT_HID_0211 = 0x0211, + BNXT_ULP_ACT_HID_0155 = 0x0155, BNXT_ULP_ACT_HID_04ab = 0x04ab, BNXT_ULP_ACT_HID_01fe = 0x01fe, BNXT_ULP_ACT_HID_0667 = 0x0667, BNXT_ULP_ACT_HID_0254 = 0x0254, BNXT_ULP_ACT_HID_03ba = 0x03ba, + BNXT_ULP_ACT_HID_02fe = 0x02fe, BNXT_ULP_ACT_HID_0654 = 0x0654, BNXT_ULP_ACT_HID_03a7 = 0x03a7, BNXT_ULP_ACT_HID_0669 = 0x0669, BNXT_ULP_ACT_HID_0256 = 0x0256, BNXT_ULP_ACT_HID_03bc = 0x03bc, + BNXT_ULP_ACT_HID_0300 = 0x0300, BNXT_ULP_ACT_HID_0656 = 0x0656, BNXT_ULP_ACT_HID_03a9 = 0x03a9, BNXT_ULP_ACT_HID_021b = 0x021b, @@ -2258,21 +2262,25 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_06d7 = 0x06d7, BNXT_ULP_ACT_HID_02c4 = 0x02c4, BNXT_ULP_ACT_HID_042a = 0x042a, + BNXT_ULP_ACT_HID_036e = 0x036e, BNXT_ULP_ACT_HID_06c4 = 0x06c4, BNXT_ULP_ACT_HID_0417 = 0x0417, BNXT_ULP_ACT_HID_06d9 = 0x06d9, BNXT_ULP_ACT_HID_02c6 = 0x02c6, BNXT_ULP_ACT_HID_042c = 0x042c, + BNXT_ULP_ACT_HID_0370 = 0x0370, BNXT_ULP_ACT_HID_06c6 = 0x06c6, BNXT_ULP_ACT_HID_0419 = 0x0419, BNXT_ULP_ACT_HID_0119 = 0x0119, BNXT_ULP_ACT_HID_046f = 0x046f, BNXT_ULP_ACT_HID_05d5 = 0x05d5, + BNXT_ULP_ACT_HID_0519 = 0x0519, BNXT_ULP_ACT_HID_0106 = 0x0106, BNXT_ULP_ACT_HID_05c2 = 0x05c2, BNXT_ULP_ACT_HID_011b = 0x011b, BNXT_ULP_ACT_HID_0471 = 0x0471, BNXT_ULP_ACT_HID_05d7 = 0x05d7, + BNXT_ULP_ACT_HID_051b = 0x051b, BNXT_ULP_ACT_HID_0108 = 0x0108, BNXT_ULP_ACT_HID_05c4 = 0x05c4, BNXT_ULP_ACT_HID_00a2 = 0x00a2, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 684fa66f48..84be09b368 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Aug 17 12:16:42 2021 */ +/* date: Thu Aug 26 17:43:36 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -2121,7 +2121,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 2048 }, { .app_id = 0, @@ -2249,7 +2249,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 2048 }, { .app_id = 0, @@ -2263,14 +2263,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, - .count = 32 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 272 diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 68c1e292b2..95205a2421 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 20 18:05:25 2021 */ +/* date: Wed Aug 25 16:41:37 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c index 578ede8bba..4a2d201c2d 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Jun 1 16:05:30 2021 */ +/* date: Wed Aug 25 14:37:06 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -35,7 +35,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { /* act_tid: 3, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, + .num_tbls = 7, .start_tbl_idx = 12, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, @@ -46,30 +46,30 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, - .start_tbl_idx = 18, + .start_tbl_idx = 19, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 20, + .cond_start_idx = 21, .cond_nums = 0 } }, /* act_tid: 5, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 23, + .num_tbls = 7, + .start_tbl_idx = 24, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 28, + .cond_start_idx = 29, .cond_nums = 0 } }, /* act_tid: 6, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, - .start_tbl_idx = 29, + .start_tbl_idx = 31, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 0 } } }; @@ -322,6 +322,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 34, .result_num_fields = 2 }, + { /* act_tid: 3, , table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 15, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, { /* act_tid: 3, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, @@ -332,7 +343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 15, + .cond_start_idx = 16, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -351,7 +362,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 16, + .cond_start_idx = 17, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, @@ -370,7 +381,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, + .cond_start_idx = 18, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, @@ -389,7 +400,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, @@ -410,7 +421,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 18, + .cond_start_idx = 19, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -429,7 +440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 19, + .cond_start_idx = 20, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -449,7 +460,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 21, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -468,7 +479,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 21, + .cond_start_idx = 22, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -489,7 +500,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 23, + .cond_start_idx = 24, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -508,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 25, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -528,7 +539,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 26, + .cond_start_idx = 27, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -538,6 +549,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 11 }, + { /* act_tid: 5, , table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 29, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, { /* act_tid: 5, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, @@ -548,7 +570,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 28, + .cond_start_idx = 30, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -567,7 +589,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, + .cond_start_idx = 31, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, @@ -586,7 +608,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 32, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, @@ -605,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 33, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, @@ -626,7 +648,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, + .cond_start_idx = 33, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -645,7 +667,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, + .cond_start_idx = 34, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -665,7 +687,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -684,7 +706,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 36, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, @@ -705,7 +727,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 37, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, @@ -726,7 +748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 38, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -747,7 +769,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 39, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -766,7 +788,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, + .cond_start_idx = 40, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -844,6 +866,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, + /* cond_execute: act_tid: 3, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, @@ -900,6 +927,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN }, + /* cond_execute: act_tid: 5, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 02/19] net/bnxt: add support for multi root capability 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 01/19] net/bnxt: add NAT support for dest IP and port combination Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 03/19] net/bnxt: fix the out of boundary issue in hash list Venkat Duvvuru ` (16 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Update driver to read the multi root capability and ignore pci address check while creating ulp session when multi root capability is enabled in the hardware. DPDK HSI version updated from 1.10.1.70 to 1.10.2.54. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/bnxt.h | 3 + drivers/net/bnxt/bnxt_hwrm.c | 8 + drivers/net/bnxt/hsi_struct_def_dpdk.h | 2682 +++++++++++++++++++++--- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 10 +- 4 files changed, 2407 insertions(+), 296 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 6743cf92b0..e3e38ffa19 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -723,6 +723,9 @@ struct bnxt { uint16_t chip_num; #define CHIP_NUM_58818 0xd818 #define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818) +#define BNXT_FLAGS2_MULTIROOT_EN BIT(4) +#define BNXT_MULTIROOT_EN(bp) \ + ((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN) uint32_t fw_cap; #define BNXT_FW_CAP_HOT_RESET BIT(0) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 181e607d7b..c7041143a3 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -3394,6 +3394,7 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp) { struct hwrm_func_qcfg_input req = {0}; struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; + uint16_t flags; int rc; if (!BNXT_VF_IS_TRUSTED(bp)) @@ -3417,6 +3418,13 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp) bp->parent->fid = rte_le_to_cpu_16(resp->fid); bp->parent->port_id = rte_le_to_cpu_16(resp->port_id); + flags = rte_le_to_cpu_16(resp->flags); + /* check for the multi-root support */ + if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) { + bp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN; + PMD_DRV_LOG(DEBUG, "PF enabled with multi root capability\n"); + } + HWRM_UNLOCK(); return 0; diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 4d7efb19f4..2a1e6ab97e 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -657,6 +657,8 @@ struct cmd_nums { #define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0) /* PTP - Query extended PTP configuration. */ #define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1) + /* The command is used to allocate KTLS crypto key contexts. */ + #define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -1056,8 +1058,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 44 -#define HWRM_VERSION_STR "1.10.2.44" +#define HWRM_VERSION_RSVD 54 +#define HWRM_VERSION_STR "1.10.2.54" /**************** * hwrm_ver_get * @@ -1357,6 +1359,12 @@ struct hwrm_ver_get_output { */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \ UINT32_C(0x4000) + /* + * If set to 1, then firmware supports secure boot. + * If set to 0, then firmware doesn't support secure boot. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE \ + UINT32_C(0x8000) /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. @@ -8283,8 +8291,14 @@ struct hwrm_async_event_cmpl_reset_notify { /* Fast reset */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \ (UINT32_C(0x4) << 8) + /* + * Reset was a result of a firmware activation. That is, the + * fw_activation flag was set in a FW_RESET operation. + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION \ + (UINT32_C(0x5) << 8) #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION /* * Minimum time before driver should attempt access - units 100ms ticks. * Range 0-65535 @@ -10244,8 +10258,21 @@ struct hwrm_async_event_cmpl_error_report_base { */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \ UINT32_C(0x2) + /* + * There was a low level error with an NVM write or erase. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM \ + UINT32_C(0x3) + /* + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD } __rte_packed; /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ @@ -10386,6 +10413,162 @@ struct hwrm_async_event_cmpl_error_report_invalid_signal { HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL } __rte_packed; +/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_nvm { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Indicates the address where error was detected */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK \ + UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT \ + 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * There was a low level error with an NVM operation. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR + /* The specific type of NVM error */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT \ + 8 + /* + * There was a low level error with an NVM write operation. + * Verification of written data did not match. + * event_data2 will be the failing address. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE \ + (UINT32_C(0x1) << 8) + /* + * There was a low level error with an NVM erase operation. + * All the bits were not erased. + * event_data2 will be the failing address. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE \ + (UINT32_C(0x2) << 8) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT \ + 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD +} __rte_packed; + /* metadata_base_msg (size:64b/8B) */ struct metadata_base_msg { uint16_t md_type_link; @@ -11204,6 +11387,18 @@ struct hwrm_func_vf_cfg_input { */ #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ UINT32_C(0x800) + /* + * This bit must be '1' for the num_tx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the num_rx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS \ + UINT32_C(0x2000) /* * The maximum transmission unit requested on the function. * The HWRM should make sure that the mtu of @@ -11353,7 +11548,10 @@ struct hwrm_func_vf_cfg_input { uint16_t num_stat_ctxs; /* The number of HW ring groups requested for the VF. */ uint16_t num_hw_ring_grps; - uint8_t unused_0[4]; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; } __rte_packed; /* hwrm_func_vf_cfg_output (size:128b/16B) */ @@ -11423,7 +11621,7 @@ struct hwrm_func_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcaps_output (size:704b/88B) */ +/* hwrm_func_qcaps_output (size:768b/96B) */ struct hwrm_func_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -11787,7 +11985,13 @@ struct hwrm_func_qcaps_output { * (max_tx_rings) to the function. */ uint16_t max_sp_tx_rings; - uint8_t unused_0[2]; + /* + * The maximum number of MSI-X vectors that may be allocated across + * all VFs for the function. This is valid only on the PF with SR-IOV + * enabled. Returns zero if this command is called on a PF with + * SR-IOV disabled or on a VF. + */ + uint16_t max_msix_vfs; uint32_t flags_ext; /* * If 1, the device can be configured to set the ECN bits in the @@ -11965,7 +12169,12 @@ struct hwrm_func_qcaps_output { * to the primate processor block. */ #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10) - uint8_t unused_1; + /* + * Maximum number of Key Contexts supported per HWRM + * function call for allocating Key Contexts. + */ + uint16_t max_key_ctxs_alloc; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12023,7 +12232,7 @@ struct hwrm_func_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcfg_output (size:832b/104B) */ +/* hwrm_func_qcfg_output (size:896b/112B) */ struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -12614,7 +12823,11 @@ struct hwrm_func_qcfg_output { * value is used if ring MTU is not specified. */ uint16_t host_mtu; - uint8_t unused_3; + /* Number of Tx Key Contexts allocated. */ + uint16_t alloc_tx_key_ctxs; + /* Number of Rx Key Contexts allocated. */ + uint16_t alloc_rx_key_ctxs; + uint8_t unused_3[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12630,7 +12843,7 @@ struct hwrm_func_qcfg_output { *****************/ -/* hwrm_func_cfg_input (size:832b/104B) */ +/* hwrm_func_cfg_input (size:896b/112B) */ struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -13076,6 +13289,18 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \ UINT32_C(0x20000000) + /* + * This bit must be '1' for the number of Tx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS \ + UINT32_C(0x40000000) + /* + * This bit must be '1' for the number of Rx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS \ + UINT32_C(0x80000000) /* * This field can be used by the admin PF to configure * mtu of foster PFs. @@ -13527,6 +13752,11 @@ struct hwrm_func_cfg_input { * ring that is assigned to a function has a valid mtu. */ uint16_t host_mtu; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; + uint8_t unused_0[4]; } __rte_packed; /* hwrm_func_cfg_output (size:128b/16B) */ @@ -14103,6 +14333,13 @@ struct hwrm_func_drv_rgtr_input { */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \ UINT32_C(0x100) + /* + * When this bit is 1, the function's driver is indicating the + * support of handling the NPAR 1.2 feature where the s-tag may be + * a value other than 0x8100 or 0x88a8. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \ + UINT32_C(0x200) uint32_t enables; /* * This bit must be '1' for the os_type field to be @@ -14664,7 +14901,7 @@ struct hwrm_func_resource_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_resource_qcaps_output (size:448b/56B) */ +/* hwrm_func_resource_qcaps_output (size:512b/64B) */ struct hwrm_func_resource_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -14739,6 +14976,14 @@ struct hwrm_func_resource_qcaps_output { */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output @@ -14755,7 +15000,7 @@ struct hwrm_func_resource_qcaps_output { *****************************/ -/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ +/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ struct hwrm_func_vf_resource_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -14829,6 +15074,14 @@ struct hwrm_func_vf_resource_cfg_input { */ #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; uint8_t unused_0[2]; } __rte_packed; @@ -14858,7 +15111,11 @@ struct hwrm_func_vf_resource_cfg_output { uint16_t reserved_stat_ctx; /* Reserved number of ring groups */ uint16_t reserved_hw_ring_grps; - uint8_t unused_0[7]; + /* Actual number of Tx Key Contexts reserved */ + uint16_t reserved_tx_key_ctxs; + /* Actual number of Rx Key Contexts reserved */ + uint16_t reserved_rx_key_ctxs; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18132,7 +18389,7 @@ struct hwrm_error_recovery_qcfg_output { /*************************** * hwrm_func_echo_response * - ****************************/ + ***************************/ /* hwrm_func_echo_response_input (size:192b/24B) */ @@ -18190,13 +18447,13 @@ struct hwrm_func_echo_response_output { uint8_t valid; } __rte_packed; -/*********************** - * hwrm_func_vlan_qcfg * - ***********************/ +/************************** + * hwrm_func_ptp_pin_qcfg * + **************************/ -/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ -struct hwrm_func_vlan_qcfg_input { +/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_pin_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18225,18 +18482,11 @@ struct hwrm_func_vlan_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[6]; + uint8_t unused_0[8]; } __rte_packed; -/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ -struct hwrm_func_vlan_qcfg_output { +/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18245,32 +18495,94 @@ struct hwrm_func_vlan_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint64_t unused_0; - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * The number of TSIO pins that are configured on this board + * Up to 4 pins can be returned in the response. */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; + uint8_t num_pins; + /* Pin state */ + uint8_t state; /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * When this bit is '1', TSIO pin 0 is enabled. + * When this bit is '0', TSIO pin 0 is disabled. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd2; - /* Future use. */ - uint32_t rsvd3; - uint8_t unused_3[3]; + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED \ + UINT32_C(0x1) + /* + * When this bit is '1', TSIO pin 1 is enabled. + * When this bit is '0', TSIO pin 1 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED \ + UINT32_C(0x2) + /* + * When this bit is '1', TSIO pin 2 is enabled. + * When this bit is '0', TSIO pin 2 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED \ + UINT32_C(0x4) + /* + * When this bit is '1', TSIO pin 3 is enabled. + * When this bit is '0', TSIO pin 3 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED \ + UINT32_C(0x8) + /* Type of function for Pin #0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT + /* Type of function for Pin #1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT + /* Type of function for Pin #2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT + /* Type of function for Pin #3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18281,13 +18593,13 @@ struct hwrm_func_vlan_qcfg_output { uint8_t valid; } __rte_packed; -/********************** - * hwrm_func_vlan_cfg * - **********************/ +/************************* + * hwrm_func_ptp_pin_cfg * + *************************/ -/* hwrm_func_vlan_cfg_input (size:384b/48B) */ -struct hwrm_func_vlan_cfg_input { +/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_pin_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18316,74 +18628,148 @@ struct hwrm_func_vlan_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[2]; uint32_t enables; /* - * This bit must be '1' for the stag_vid field to be + * This bit must be '1' for the pin0_state field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE \ + UINT32_C(0x1) /* - * This bit must be '1' for the ctag_vid field to be + * This bit must be '1' for the pin0_usage field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE \ + UINT32_C(0x2) /* - * This bit must be '1' for the stag_pcp field to be + * This bit must be '1' for the pin1_state field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE \ + UINT32_C(0x4) /* - * This bit must be '1' for the ctag_pcp field to be + * This bit must be '1' for the pin1_usage field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE \ + UINT32_C(0x8) /* - * This bit must be '1' for the stag_tpid field to be + * This bit must be '1' for the pin2_state field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE \ + UINT32_C(0x10) /* - * This bit must be '1' for the ctag_tpid field to be + * This bit must be '1' for the pin2_usage field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE \ + UINT32_C(0x20) /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * This bit must be '1' for the pin3_state field to be + * configured. */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE \ + UINT32_C(0x40) /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * This bit must be '1' for the pin3_usage field to be + * configured. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd1; - /* Future use. */ - uint32_t rsvd2; - uint8_t unused_3[4]; + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE \ + UINT32_C(0x80) + /* Enable or disable functionality of Pin #0. */ + uint8_t pin0_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED + /* Configure function for TSIO pin#0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #1. */ + uint8_t pin1_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED + /* Configure function for TSIO pin#1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #2. */ + uint8_t pin2_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED + /* Configure function for TSIO pin#2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #3. */ + uint8_t pin3_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED + /* Configure function for TSIO pin#3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0[4]; } __rte_packed; -/* hwrm_func_vlan_cfg_output (size:128b/16B) */ -struct hwrm_func_vlan_cfg_output { +/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18403,13 +18789,812 @@ struct hwrm_func_vlan_cfg_output { uint8_t valid; } __rte_packed; -/******************************* - * hwrm_func_vf_vnic_ids_query * - *******************************/ +/********************* + * hwrm_func_ptp_cfg * + *********************/ -/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ -struct hwrm_func_vf_vnic_ids_query_input { +/* hwrm_func_ptp_cfg_input (size:320b/40B) */ +struct hwrm_func_ptp_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the ptp_pps_event field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT \ + UINT32_C(0x1) + /* + * This bit must be '1' for the ptp_freq_adj_dll_source field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the ptp_freq_adj_dll_phase field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the ptp_freq_adj_ext_period field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD \ + UINT32_C(0x8) + /* + * This bit must be '1' for the ptp_freq_adj_ext_up field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP \ + UINT32_C(0x10) + /* + * This bit must be '1' for the ptp_freq_adj_ext_phase field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE \ + UINT32_C(0x20) + /* This field is used to enable interrupt for a specific PPS event. */ + uint8_t ptp_pps_event; + /* + * When this bit is set to '1', interrupt is enabled for internal + * PPS event. Latches timestamp on PPS_OUT TSIO Pin. If user does + * not configure PPS_OUT on a TSIO pin, then firmware will allocate + * PPS_OUT to an unallocated pin. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL \ + UINT32_C(0x1) + /* + * When this bit is set to '1', interrupt is enabled for external + * PPS event. Latches timestamp on PPS_IN TSIO pin. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL \ + UINT32_C(0x2) + /* + * This field is used to set the source signal used to discipline + * PHC (PTP Hardware Clock) + */ + uint8_t ptp_freq_adj_dll_source; + /* No source is selected. Use servo to discipline PHC */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE \ + UINT32_C(0x0) + /* TSIO Pin #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 \ + UINT32_C(0x1) + /* TSIO Pin #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 \ + UINT32_C(0x2) + /* TSIO Pin #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 \ + UINT32_C(0x3) + /* TSIO Pin #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 \ + UINT32_C(0x4) + /* Port #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 \ + UINT32_C(0x5) + /* Port #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 \ + UINT32_C(0x6) + /* Port #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 \ + UINT32_C(0x7) + /* Port #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 \ + UINT32_C(0x8) + /* Invalid signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID \ + UINT32_C(0xff) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID + /* + * This field is used to provide phase adjustment for DLL + * used to discipline PHC (PTP Hardware clock) + */ + uint8_t ptp_freq_adj_dll_phase; + /* No Phase adjustment. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE \ + UINT32_C(0x0) + /* 4Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K \ + UINT32_C(0x1) + /* 8Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K \ + UINT32_C(0x2) + /* 10Mhz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M \ + UINT32_C(0x3) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M + uint8_t unused_0[3]; + /* + * Period in nanoseconds (ns) for external signal + * input. + */ + uint32_t ptp_freq_adj_ext_period; + /* + * Up time in nanoseconds (ns) of the duty cycle + * of the external signal. This value should be + * less than ptp_freq_adj_ext_period. + */ + uint32_t ptp_freq_adj_ext_up; + /* + * Phase value is provided. This field provides the + * least significant 32 bits of the phase input. The + * most significant 16 bits come from + * ptp_freq_adj_ext_phase_upper field. Setting this + * field requires setting ptp_freq_adj_ext_period + * field as well to identify the external signal + * pin. + */ + uint32_t ptp_freq_adj_ext_phase_lower; + /* + * Phase value is provided. The lower 16 bits of this field is used + * with the 32 bit value from ptp_freq_adj_ext_phase_lower + * to provide a 48 bit value input for Phase. + */ + uint32_t ptp_freq_adj_ext_phase_upper; +} __rte_packed; + +/* hwrm_func_ptp_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ts_query * + **************************/ + + +/* hwrm_func_ptp_ts_query_input (size:192b/24B) */ +struct hwrm_func_ptp_ts_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* If set, the response includes PPS event timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1) + /* If set, the response includes PTM timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_ptp_ts_query_output (size:320b/40B) */ +struct hwrm_func_ptp_ts_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Timestamp value of last PPS event latched. */ + uint64_t pps_event_ts; + /* PTM local timestamp value. */ + uint64_t ptm_res_local_ts; + /* PTM Master timestamp value. */ + uint64_t ptm_pmstr_ts; + /* PTM Master propagation delay */ + uint32_t ptm_mstr_prop_dly; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_func_ptp_ext_cfg * + *************************/ + + +/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_ext_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the phc_master_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the phc_sec_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the phc_sec_mode field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the failover_timer field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER \ + UINT32_C(0x8) + /* + * This field is used to configure the Master function. Only this + * function can modify or condition the PHC. Only driver calls from + * this function are allowed to adjust frequency of PHC or configure + * PPS functionality. + * If driver does not specify this FID, then firmware will auto select + * the first function that makes the call to modify PHC as the Master. + */ + uint16_t phc_master_fid; + /* + * This field is used to configure the secondary function. This + * function becomes the Master function in case of failover from + * Master function. + * If driver does not specify this FID, firmware will auto select + * the last non-master function to make a call to condition PHC as + * secondary. + */ + uint16_t phc_sec_fid; + /* + * This field is used to configure conditions under which a function + * can become a secondary function. + */ + uint8_t phc_sec_mode; + /* + * Immediately failover to the current secondary function. If there + * is no secondary function available, failover does not happen. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0) + /* + * All functions (PF and VF) can be used during auto selection + * of a secondary function. This is not used in case of admin + * configured secondary function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1) + /* + * Only PF's can be selected as a secondary function during auto + * selection. This is not used in case of admin configured secondary + * function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2) + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_LAST \ + HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY + uint8_t unused_0; + /* + * This field indicates the failover time is milliseconds. If the + * timeout expires, firmware will failover PTP configurability from + * current master to secondary fid. + * 0 - Failover timer is automatically selected based on the last + * adjFreq() call. If adjFreq() is not called for 3 * (last interval) + * the failover kicks in. For example, if last interval between + * adjFreq() calls was 2 seconds and the next adjFreq() is not made for + * at least 6 seconds, then secondary takes over as master to condition + * PHC. Firmware rounds up the failover timer to be a multiple of 250 + * ms. Firmware checks every 250 ms to see if timer expired. + * 0xFFFFFFFF - If driver specifies this value, then failover never + * happens. Admin or auto selected Master will always be used for + * conditioning PHC. + * X - If driver specifies any other value, this is admin indicated + * failover timeout. If no adjFreq() call is made within this timeout + * value, then failover happens. This value should be a multiple of + * 250 ms. Firmware checks every 250 ms to see if timer expired. + */ + uint32_t failover_timer; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_ext_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ext_qcfg * + **************************/ + + +/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_ext_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ +struct hwrm_func_ptp_ext_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Firmware returns the current PHC master function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_master_fid; + /* + * Firmware returns the current PHC secondary function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_sec_fid; + /* + * Firmware returns the last non-master/non-secondary function to + * make a call to condition PHC. + */ + uint16_t phc_active_fid0; + /* + * Firmware returns the second last non-master/non-secondary function + * to make a call to condition PHC. + */ + uint16_t phc_active_fid1; + /* + * Timestamp indicating the last time a failover happened. The master + * and secondary functions in the failover event is indicated in the + * next two fields. + */ + uint32_t last_failover_event; + /* + * Last failover happened from this function. This was the master + * function at the time of failover. + */ + uint16_t from_fid; + /* + * Last failover happened to this function. This was the secondary + * function at the time of failover. + */ + uint16_t to_fid; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_func_key_ctx_alloc * + ***************************/ + + +/* hwrm_func_key_ctx_alloc_input (size:320b/40B) */ +struct hwrm_func_key_ctx_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Function ID. */ + uint16_t fid; + /* Number of Key Contexts to be allocated. */ + uint16_t num_key_ctxs; + /* DMA buffer size in bytes. */ + uint32_t dma_bufr_size_bytes; + /* Key Context type. */ + uint8_t key_ctx_type; + /* Tx Key Context. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0) + /* Rx KTLS Context. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1) + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST \ + HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX + uint8_t unused_0[7]; + /* Host DMA address to send back KTLS context IDs. */ + uint64_t host_dma_addr; +} __rte_packed; + +/* hwrm_func_key_ctx_alloc_output (size:128b/16B) */ +struct hwrm_func_key_ctx_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Actual number of Key Contexts allocated. */ + uint16_t num_key_ctxs_allocated; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_func_vlan_qcfg * + ***********************/ + + +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ +struct hwrm_func_vlan_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ +struct hwrm_func_vlan_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint64_t unused_0; + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd2; + /* Future use. */ + uint32_t rsvd3; + uint8_t unused_3[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_vlan_cfg * + **********************/ + + +/* hwrm_func_vlan_cfg_input (size:384b/48B) */ +struct hwrm_func_vlan_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[2]; + uint32_t enables; + /* + * This bit must be '1' for the stag_vid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) + /* + * This bit must be '1' for the ctag_vid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) + /* + * This bit must be '1' for the stag_pcp field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) + /* + * This bit must be '1' for the ctag_pcp field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) + /* + * This bit must be '1' for the stag_tpid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) + /* + * This bit must be '1' for the ctag_tpid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd1; + /* Future use. */ + uint32_t rsvd2; + uint8_t unused_3[4]; +} __rte_packed; + +/* hwrm_func_vlan_cfg_output (size:128b/16B) */ +struct hwrm_func_vlan_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_func_vf_vnic_ids_query * + *******************************/ + + +/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ +struct hwrm_func_vf_vnic_ids_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -19128,7 +20313,7 @@ struct hwrm_func_spd_cfg_input { UINT32_C(0x10) /* * Ethertype value used in the encapsulated SPD packet header. - * The user must choose a value that is not conflicting with + * The user must chooose a value that is not conflicting with * publicly defined ethertype values. By default, the ethertype * value of 0xffff is used if there is no user specified value. */ @@ -19387,7 +20572,7 @@ struct hwrm_func_spd_qcfg_output { uint8_t unused_1; /* * Ethertype value used in the encapsulated SPD packet header. - * The user must choose a value that is not conflicting with + * The user must chooose a value that is not conflicting with * publicly defined ethertype values. By default, the ethertype * value of 0xffff is used if there is no user specified value. */ @@ -21398,6 +22583,12 @@ struct hwrm_port_mac_cfg_input { */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \ UINT32_C(0x200) + /* + * This bit must be '1' for the ptp_adj_phase field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE \ + UINT32_C(0x400) /* Port ID of port that is to be configured. */ uint16_t port_id; /* @@ -21590,7 +22781,12 @@ struct hwrm_port_mac_cfg_input { * of sync timer updates (measured in parts per billion). */ int32_t ptp_freq_adj_ppb; - uint8_t unused_1[4]; + /* + * This unsigned field specifies the phase offset to be applied + * to the PHC (PTP Hardware Clock). This field is specified in + * nanoseconds. + */ + uint32_t ptp_adj_phase; } __rte_packed; /* hwrm_port_mac_cfg_output (size:128b/16B) */ @@ -21991,7 +23187,7 @@ struct hwrm_port_mac_ptp_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ +/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ struct hwrm_port_mac_ptp_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -22024,10 +23220,23 @@ struct hwrm_port_mac_ptp_qcfg_output { */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ UINT32_C(0x8) + /* + * When this bit is set to '1', two specific registers for current + * time (ts_ref_clock_reg_lower and ts_ref_clock_reg_upper) are + * directly accessible by the host. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK \ + UINT32_C(0x10) uint8_t unused_0[3]; - /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for RX. */ uint32_t rx_ts_reg_off_seq_id; @@ -22045,9 +23254,15 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t rx_ts_reg_off_fifo_adv; /* PTP timestamp granularity for RX. */ uint32_t rx_ts_reg_off_granularity; - /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for TX. */ uint32_t tx_ts_reg_off_seq_id; @@ -22055,6 +23270,10 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t tx_ts_reg_off_fifo; /* PTP timestamp granularity for TX. */ uint32_t tx_ts_reg_off_granularity; + /* Offset of register to get lower 32 bits of current time. */ + uint32_t ts_ref_clock_reg_lower; + /* Offset of register to get upper 32 bits of current time. */ + uint32_t ts_ref_clock_reg_upper; uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output @@ -22578,7 +23797,7 @@ struct tx_port_stats_ext { } __rte_packed; /* Port Rx Statistics extended Format */ -/* rx_port_stats_ext (size:3648b/456B) */ +/* rx_port_stats_ext (size:3776b/472B) */ struct rx_port_stats_ext { /* Number of times link state changed to down */ uint64_t link_down_events; @@ -22697,6 +23916,13 @@ struct rx_port_stats_ext { uint64_t rx_discard_packets_cos6; /* Total number of rx discard packets count on cos queue 7 */ uint64_t rx_discard_packets_cos7; + /* Total number of FEC blocks corrected by the FEC function in the PHY */ + uint64_t rx_fec_corrected_blocks; + /* + * Total number of FEC blocks determined to be uncorrectable by the + * FEC function in the PHY + */ + uint64_t rx_fec_uncorrectable_blocks; } __rte_packed; /* @@ -25981,6 +27207,309 @@ struct hwrm_port_tx_fir_qcfg_output { uint8_t valid; } __rte_packed; +/*********************** + * hwrm_port_ep_tx_cfg * + ***********************/ + + +/* hwrm_port_ep_tx_cfg_input (size:256b/32B) */ +struct hwrm_port_ep_tx_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* When this bit is '1', the value in the ep0_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1) + /* When this bit is '1', the value in the ep0_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2) + /* When this bit is '1', the value in the ep1_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4) + /* When this bit is '1', the value in the ep1_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8) + /* When this bit is '1', the value in the ep2_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10) + /* When this bit is '1', the value in the ep2_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20) + /* When this bit is '1', the value in the ep3_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40) + /* When this bit is '1', the value in the ep3_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80) + /* A port index, from 0 to the number of front panel ports, minus 1. */ + uint8_t port_id; + uint8_t unused; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set of + * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of + * the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_output (size:128b/16B) */ +struct hwrm_port_ep_tx_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_cmd_err (size:64b/8B) */ +struct hwrm_port_ep_tx_cfg_cmd_err { + /* + * command specific error codes for the cmd_err field in + * hwrm_err_output + */ + uint8_t code; + /* Unknown error. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* The port ID is invalid */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID \ + UINT32_C(0x1) + /* One of the PCIe endpoints configured is not active. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE \ + UINT32_C(0x2) + /* A minimum bandwidth is out of range. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE \ + UINT32_C(0x3) + /* + * One endpoint's minimum bandwidth is more than its maximum + * bandwidth. + */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX \ + UINT32_C(0x4) + /* The sum of the minimum bandwidths on the port is more than 100%. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM \ + UINT32_C(0x5) + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_LAST \ + HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM + uint8_t unused_0[7]; +} __rte_packed; + +/************************ + * hwrm_port_ep_tx_qcfg * + ************************/ + + +/* hwrm_port_ep_tx_qcfg_input (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The port whose endpoint rate limits are queried. */ + uint8_t port_id; + uint8_t unused[7]; +} __rte_packed; + +/* hwrm_port_ep_tx_qcfg_output (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /*********************** * hwrm_queue_qportcfg * ***********************/ @@ -26097,6 +27626,13 @@ struct hwrm_queue_qportcfg_output { */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ UINT32_C(0x1) + /* + * If this flag is set to '1', then service_profile will carry + * either lossy/lossless type and the new service_profile_type + * field will be used to determine if the queue is for L2/ROCE/CNP. + */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE \ + UINT32_C(0x2) /* * Bitmask indicating which queues can be configured by the * hwrm_queue_pfcenable_cfg command. @@ -30204,67 +31740,221 @@ struct hwrm_queue_vlanpri2pri_qcfg_input { * to configure VLAN priority to user priority mapping on this port. */ uint8_t port_id; - uint8_t unused_0[7]; -} __rte_packed; - -/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ -struct hwrm_queue_vlanpri2pri_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ +struct hwrm_queue_vlanpri2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * User priority assigned to VLAN priority 0. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri0_user_pri_id; + /* + * User priority assigned to VLAN priority 1. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri1_user_pri_id; + /* + * User priority assigned to VLAN priority 2. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri2_user_pri_id; + /* + * User priority assigned to VLAN priority 3. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri3_user_pri_id; + /* + * User priority assigned to VLAN priority 4. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri4_user_pri_id; + /* + * User priority assigned to VLAN priority 5. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri5_user_pri_id; + /* + * User priority assigned to VLAN priority 6. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri6_user_pri_id; + /* + * User priority assigned to VLAN priority 7. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri7_user_pri_id; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_queue_vlanpri2pri_cfg * + ******************************/ + + +/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ +struct hwrm_queue_vlanpri2pri_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vlanpri0_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the vlanpri1_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the vlanpri2_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vlanpri3_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the vlanpri4_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the vlanpri5_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the vlanpri6_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the vlanpri7_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ + UINT32_C(0x80) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure VLAN priority to user priority mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[3]; /* - * User priority assigned to VLAN priority 0. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 0. This value can only + * be changed before traffic has started. */ uint8_t vlanpri0_user_pri_id; /* - * User priority assigned to VLAN priority 1. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 1. This value can only + * be changed before traffic has started. */ uint8_t vlanpri1_user_pri_id; /* - * User priority assigned to VLAN priority 2. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 2. This value can only + * be changed before traffic has started. */ uint8_t vlanpri2_user_pri_id; /* - * User priority assigned to VLAN priority 3. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 3. This value can only + * be changed before traffic has started. */ uint8_t vlanpri3_user_pri_id; /* - * User priority assigned to VLAN priority 4. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 4. This value can only + * be changed before traffic has started. */ uint8_t vlanpri4_user_pri_id; /* - * User priority assigned to VLAN priority 5. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 5. This value can only + * be changed before traffic has started. */ uint8_t vlanpri5_user_pri_id; /* - * User priority assigned to VLAN priority 6. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 6. This value can only + * be changed before traffic has started. */ uint8_t vlanpri6_user_pri_id; /* - * User priority assigned to VLAN priority 7. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 7. This value can only + * be changed before traffic has started. */ uint8_t vlanpri7_user_pri_id; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_vlanpri2pri_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -30276,13 +31966,13 @@ struct hwrm_queue_vlanpri2pri_qcfg_output { uint8_t valid; } __rte_packed; -/****************************** - * hwrm_queue_vlanpri2pri_cfg * - ******************************/ +/************************* + * hwrm_queue_global_cfg * + *************************/ -/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ -struct hwrm_queue_vlanpri2pri_cfg_input { +/* hwrm_queue_global_cfg_input (size:192b/24B) */ +struct hwrm_queue_global_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30311,106 +32001,142 @@ struct hwrm_queue_vlanpri2pri_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the vlanpri0_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ - UINT32_C(0x1) - /* - * This bit must be '1' for the vlanpri1_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ - UINT32_C(0x2) /* - * This bit must be '1' for the vlanpri2_user_pri_id field to be - * configured. + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ - UINT32_C(0x4) + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0) /* - * This bit must be '1' for the vlanpri3_user_pri_id field to be - * configured. + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ - UINT32_C(0x8) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT + uint8_t unused_0; + uint16_t enables; + /* This bit must be '1' when the mode field is configured. */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1) /* - * This bit must be '1' for the vlanpri4_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 0 + * (g0_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ - UINT32_C(0x10) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2) /* - * This bit must be '1' for the vlanpri5_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 1 + * (g1_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ - UINT32_C(0x20) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4) /* - * This bit must be '1' for the vlanpri6_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 2 + * (g2_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ - UINT32_C(0x40) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8) /* - * This bit must be '1' for the vlanpri7_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 3 + * (g3_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ - UINT32_C(0x80) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW \ + UINT32_C(0x10) /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure VLAN priority to user priority mapping on this port. + * Specifies the maximum receive rate, as a percentage of total link + * bandwidth, of the receive traffic through queue group 0. A value + * of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. */ - uint8_t port_id; - uint8_t unused_0[3]; + uint8_t g0_max_bw; /* - * User priority assigned to VLAN priority 0. This value can only - * be changed before traffic has started. + * Specifies the maximum rate of the traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. */ - uint8_t vlanpri0_user_pri_id; + uint8_t g1_max_bw; /* - * User priority assigned to VLAN priority 1. This value can only - * be changed before traffic has started. + * Specifies the maximum rate of the traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. */ - uint8_t vlanpri1_user_pri_id; + uint8_t g2_max_bw; /* - * User priority assigned to VLAN priority 2. This value can only - * be changed before traffic has started. + * Specifies the maximum receive rate, in Mbps, of the receive traffic + * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0 + * indicates no rate limit. */ - uint8_t vlanpri2_user_pri_id; + uint8_t g3_max_bw; +} __rte_packed; + +/* hwrm_queue_global_cfg_output (size:128b/16B) */ +struct hwrm_queue_global_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * User priority assigned to VLAN priority 3. This value can only - * be changed before traffic has started. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint8_t vlanpri3_user_pri_id; + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_queue_global_qcfg * + **************************/ + + +/* hwrm_queue_global_qcfg_input (size:128b/16B) */ +struct hwrm_queue_global_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * User priority assigned to VLAN priority 4. This value can only - * be changed before traffic has started. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint8_t vlanpri4_user_pri_id; + uint16_t cmpl_ring; /* - * User priority assigned to VLAN priority 5. This value can only - * be changed before traffic has started. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t vlanpri5_user_pri_id; + uint16_t seq_id; /* - * User priority assigned to VLAN priority 6. This value can only - * be changed before traffic has started. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint8_t vlanpri6_user_pri_id; + uint16_t target_id; /* - * User priority assigned to VLAN priority 7. This value can only - * be changed before traffic has started. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint8_t vlanpri7_user_pri_id; + uint64_t resp_addr; } __rte_packed; -/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_vlanpri2pri_cfg_output { +/* hwrm_queue_global_qcfg_output (size:320b/40B) */ +struct hwrm_queue_global_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30419,7 +32145,95 @@ struct hwrm_queue_vlanpri2pri_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Port or PCIe endpoint id to be mapped for buffer pool 0. */ + uint8_t buffer_pool_id0_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 1. */ + uint8_t buffer_pool_id1_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 2. */ + uint8_t buffer_pool_id2_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 3. */ + uint8_t buffer_pool_id3_map; + /* Size of buffer pool 0 (KBytes). */ + uint32_t buffer_pool_id0_size; + /* Size of buffer pool 1 (KBytes). */ + uint32_t buffer_pool_id1_size; + /* Size of buffer pool 2 (KBytes). */ + uint32_t buffer_pool_id2_size; + /* Size of buffer pool 3 (KBytes). */ + uint32_t buffer_pool_id3_size; + uint16_t flags; + /* + * Enumeration denoting whether the rx buffer pool mapping is + * per port or per PCIe endpoint + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING \ + UINT32_C(0x1) + /* + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a port. + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT \ + UINT32_C(0x0) + /* + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a PCIe endpoint. + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT \ + UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT + /* + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. + */ + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0) + /* + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT + uint8_t unused_0; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 0. The rate limit is a percentage of total link bandwidth. A + * value of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. + */ + uint8_t g0_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g1_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g2_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 3 (for port 3 or PCIe endpoint 3). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g3_max_bw; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -31324,6 +33138,13 @@ struct hwrm_vnic_qcaps_output { */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \ UINT32_C(0x1000) + /* + * When this bit is set '1', it indicates that firmware returns + * INVALID_PARAM error, if host drivers choose invalid hash type + * bit combinations in vnic_rss_cfg. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP \ + UINT32_C(0x2000) /* * This field advertises the maximum concurrent TPA aggregations * supported by the VNIC on new devices that support TPA v2. @@ -31674,7 +33495,34 @@ struct hwrm_vnic_rss_cfg_input { uint64_t hash_key_tbl_addr; /* Index to the rss indirection table. */ uint16_t rss_ctx_idx; - uint8_t unused_1[6]; + uint8_t flags; + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to add to the current + * hash. Zeroes designate the hash_type state bits that should remain + * unchanged, if possible. If this constraint on the existing state + * cannot be satisfied, then the implementation should preference + * adding other headers so as to honor the request to add the + * specified headers. It is an error to set this flag concurrently + * with hash_type_exclude. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to remove from the + * current hash. Zeroes designate the hash_type state bits that + * should remain unchanged, if possible. If this constraint on the + * existing state cannot be satisfied, then the implementation should + * preference removing other headers so as to honor the request to + * remove the specified headers. It is an error to set this flag + * concurrently with hash_type_include. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE \ + UINT32_C(0x2) + uint8_t unused_1[5]; } __rte_packed; /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ @@ -43062,6 +44910,161 @@ struct hwrm_cfa_tflib_output { uint8_t valid; } __rte_packed; +/********************************** + * hwrm_cfa_lag_group_member_rgtr * + **********************************/ + + +/* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t mode; + /* + * Transmit only on the active port. Automatically failover + * to backup port. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP \ + UINT32_C(0x1) + /* + * Transmit based on packet header ntuple hash. Packet with only + * layer 2 headers will hash using the destination MAC, source MAC + * and Ethertype fields. Packets with layer 3 (IP) headers will + * hash using the destination MAC, source MAC, IP protocol/next + * header, source IP address and destination IP address. Packets + * with layer 4 (TCP/UDP) headers will hash using the destination + * MAC, source MAC, IP protocol/next header, source IP address, + * destination IP address, source port and destination port fields. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR \ + UINT32_C(0x2) + /* Transmit packets on all specified ports. */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST \ + UINT32_C(0x3) + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST \ + HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST + /* + * Supports up to 5 ports. bit0 = port 0, bit1 = port 1, + * bit2 = port 2, bit3 = port 4, bit4 = loopback port + */ + uint8_t port_bitmap; + /* Specify the active port when active-backup mode is specified */ + uint8_t active_port; + uint8_t unused_0[5]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************************ + * hwrm_cfa_lag_group_member_unrgtr * + ************************************/ + + +/* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /*********** * hwrm_tf * ***********/ @@ -43263,8 +45266,13 @@ struct hwrm_tf_session_open_output { * the newly created session. */ uint32_t fw_session_client_id; + /* This field is used to return the status of fw session to host. */ uint32_t flags; - /* Indicates if the shared session has been created. */ + /* + * Indicates if the shared session has been created. Shared seesion + * should be the first session created ever. Its fw_rm_client_id + * should be 1. The AFM session's fw_rm_client_id is 0. + */ #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \ UINT32_C(0x1) /* @@ -43745,7 +45753,7 @@ struct hwrm_tf_session_resc_qcaps_input { #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX @@ -43860,7 +45868,7 @@ struct hwrm_tf_session_resc_alloc_input { #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX @@ -43959,7 +45967,7 @@ struct hwrm_tf_session_resc_free_input { #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX @@ -44043,7 +46051,7 @@ struct hwrm_tf_session_resc_flush_input { #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX @@ -44248,7 +46256,7 @@ struct hwrm_tf_tbl_type_get_input { #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX @@ -44337,7 +46345,7 @@ struct hwrm_tf_tbl_type_set_input { #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX @@ -44819,7 +46827,7 @@ struct hwrm_tf_ext_em_qcaps_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \ @@ -44997,7 +47005,7 @@ struct hwrm_tf_ext_em_op_input { #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX @@ -45104,7 +47112,7 @@ struct hwrm_tf_ext_em_cfg_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \ @@ -45309,7 +47317,7 @@ struct hwrm_tf_ext_em_qcfg_input { #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX @@ -45335,7 +47343,7 @@ struct hwrm_tf_ext_em_qcfg_output { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ @@ -45475,7 +47483,7 @@ struct hwrm_tf_em_insert_input { #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX @@ -45556,7 +47564,7 @@ struct hwrm_tf_em_hash_insert_input { #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX @@ -45637,13 +47645,13 @@ struct hwrm_tf_em_delete_input { #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX /* Unused0 */ uint16_t unused0; - /* EM internal flow hanndle. */ + /* EM internal flow handle. */ uint64_t flow_handle; /* EM Key value */ uint64_t em_key[8]; @@ -45785,7 +47793,7 @@ struct hwrm_tf_tcam_set_input { #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX @@ -45887,7 +47895,7 @@ struct hwrm_tf_tcam_get_input { #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX @@ -45983,7 +47991,7 @@ struct hwrm_tf_tcam_move_input { #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX @@ -46066,7 +48074,7 @@ struct hwrm_tf_tcam_free_input { #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX @@ -46149,7 +48157,7 @@ struct hwrm_tf_global_cfg_set_input { #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX @@ -46233,7 +48241,7 @@ struct hwrm_tf_global_cfg_get_input { #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX @@ -46308,7 +48316,7 @@ struct hwrm_tf_if_tbl_get_input { #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX @@ -46397,7 +48405,7 @@ struct hwrm_tf_if_tbl_set_input { #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX @@ -46484,7 +48492,7 @@ struct hwrm_tf_tbl_type_bulk_get_input { #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX @@ -48261,7 +50269,7 @@ struct hwrm_nvm_get_dir_info_output { ******************/ -/* hwrm_nvm_write_input (size:384b/48B) */ +/* hwrm_nvm_write_input (size:448b/56B) */ struct hwrm_nvm_write_input { /* The HWRM command request type. */ uint16_t req_type; @@ -48296,10 +50304,7 @@ struct hwrm_nvm_write_input { * This is where the source data is. */ uint64_t host_src_addr; - /* - * The Directory Entry Type (valid values are defined in the - * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). - */ + /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */ uint16_t dir_type; /* * Directory ordinal. @@ -48311,10 +50316,8 @@ struct hwrm_nvm_write_input { /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ uint16_t dir_attr; /* - * Length of data to write, in bytes.May be - * less than or equal to the allocated size for the directory entry. - * The data length stored in the directory entry will be updated to - * reflect this value once the write is complete. + * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry. + * The data length stored in the directory entry will be updated to reflect this value once the write is complete. */ uint32_t dir_data_length; /* Option. */ @@ -48327,17 +50330,41 @@ struct hwrm_nvm_write_input { #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ UINT32_C(0x1) /* - * The requested length of the allocated NVM for the item, in bytes. - * This value may be greater than or equal to the specified data length (dir_data_length). + * This flag indicates the sender wants to modify a continuous + * NVRAM area using a batch of this HWRM requests. The + * offset of a request must be continuous to the end of previous + * request's. Firmware does not update the directory entry until + * receiving the last request, which is indicated by the batch_last + * flag. This flag is set usually when a sender does not have a + * block of memory that is big enough to hold the entire NVRAM + * data for send at one time. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE \ + UINT32_C(0x2) + /* + * This flag can be used only when the batch_mode flag is set. It + * indicates this request is the last of batch requests. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST \ + UINT32_C(0x4) + /* + * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length). * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, which may - * be greater than the requested item length. - * The purpose for allocating more than the required number of bytes for - * an item's data is to pre-allocate extra storage (padding) to accommodate - * the potential future growth of an item (e.g. upgraded firmware with - * a size increase, log growth, expanded configuration data). + * The response will contain the actual allocated item length, which may be greater than the requested item length. + * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate + * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data). */ uint32_t dir_item_length; + /* + * 32-bit offset of data blob from where data is being written. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t offset; + /* + * Length of data to be written.Should be non-zero. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t len; uint32_t unused_0; } __rte_packed; @@ -48352,10 +50379,8 @@ struct hwrm_nvm_write_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Length of the allocated NVM for the item, in bytes. The value may be - * greater than or equal to the specified data length or the requested item length. - * The actual item length used when creating a new directory entry will - * be a multiple of an NVM block size. + * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length. + * The actual item length used when creating a new directory entry will be a multiple of an NVM block size. */ uint32_t dir_item_length; /* The directory index of the created or modified item. */ @@ -48699,10 +50724,7 @@ struct hwrm_nvm_get_dev_info_output { /* Total size, in bytes of the NVRAM device. */ uint32_t nvram_size; uint32_t reserved_size; - /* - * Available size that can be used, in bytes. Available size is the - * NVRAM size take away the used size and reserved size. - */ + /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */ uint32_t available_size; /* This field represents the major version of NVM cfg */ uint8_t nvm_cfg_ver_maj; @@ -48844,10 +50866,7 @@ struct hwrm_nvm_mod_dir_entry_input { * The (0-based) instance of this Directory Type. */ uint16_t dir_ordinal; - /* - * The Directory Entry Extension flags (see BNX_DIR_EXT_* for - * extension flag definitions). - */ + /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */ uint16_t dir_ext; /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */ uint16_t dir_attr; @@ -49016,10 +51035,8 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \ UINT32_C(0x1) /* - * If set to 1, then unspecified images, images not in the package file, - * will be safely deleted. - * When combined with erase_unused_space then unspecified images will be - * securely erased. + * If set to 1, then unspecified images, images not in the package file, will be safely deleted. + * When combined with erase_unused_space then unspecified images will be securely erased. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ UINT32_C(0x2) @@ -49116,13 +51133,19 @@ struct hwrm_nvm_install_update_cmd_err { */ uint8_t code; /* Unknown error */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) /* Unable to complete operation due to fragmentation */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR \ + UINT32_C(0x1) /* nvm is completely full. */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE \ + UINT32_C(0x2) + /* Firmware update failed due to Anti-rollback. */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \ + UINT32_C(0x3) #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \ - HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE + HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK uint8_t unused_0[7]; } __rte_packed; @@ -49404,10 +51427,7 @@ struct hwrm_nvm_set_variable_input { /* index for the 4th dimensions */ uint16_t index_3; uint8_t flags; - /* - * When this bit is 1, flush internal cache after this write operation - * (see hwrm_nvm_flush command.) - */ + /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */ #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \ UINT32_C(0x1) /* encryption method */ @@ -49589,6 +51609,84 @@ struct hwrm_nvm_validate_option_cmd_err { uint8_t unused_0[7]; } __rte_packed; +/******************* + * hwrm_nvm_defrag * + *******************/ + + +/* hwrm_nvm_defrag_input (size:192b/24B) */ +struct hwrm_nvm_defrag_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* This bit must be '1' to perform NVM defragmentation. */ + #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_nvm_defrag_output (size:128b/16B) */ +struct hwrm_nvm_defrag_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_nvm_defrag_cmd_err (size:64b/8B) */ +struct hwrm_nvm_defrag_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* NVM defragmentation could not be performed */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1) + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST \ + HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL + uint8_t unused_0[7]; +} __rte_packed; + /**************** * hwrm_oem_cmd * ****************/ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index bd57229968..dbc8a3c5bb 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1010,13 +1010,15 @@ ulp_context_initialized(struct bnxt_ulp_session_state *session, bool *init) * pointer, otherwise allocate a new session. */ static struct bnxt_ulp_session_state * -ulp_get_session(struct rte_pci_addr *pci_addr) +ulp_get_session(struct bnxt *bp, struct rte_pci_addr *pci_addr) { struct bnxt_ulp_session_state *session; + /* if multi root capability is enabled, then ignore the pci bus id */ STAILQ_FOREACH(session, &bnxt_ulp_session_list, next) { if (session->pci_info.domain == pci_addr->domain && - session->pci_info.bus == pci_addr->bus) { + (BNXT_MULTIROOT_EN(bp) || + session->pci_info.bus == pci_addr->bus)) { return session; } } @@ -1044,7 +1046,7 @@ ulp_session_init(struct bnxt *bp, pthread_mutex_lock(&bnxt_ulp_global_mutex); - session = ulp_get_session(pci_addr); + session = ulp_get_session(bp, pci_addr); if (!session) { /* Not Found the session Allocate a new one */ session = rte_zmalloc("bnxt_ulp_session", @@ -1547,7 +1549,7 @@ bnxt_ulp_port_deinit(struct bnxt *bp) pci_dev = RTE_DEV_TO_PCI(bp->eth_dev->device); pci_addr = &pci_dev->addr; pthread_mutex_lock(&bnxt_ulp_global_mutex); - session = ulp_get_session(pci_addr); + session = ulp_get_session(bp, pci_addr); pthread_mutex_unlock(&bnxt_ulp_global_mutex); /* session not found then just exit */ -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 03/19] net/bnxt: fix the out of boundary issue in hash list 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 01/19] net/bnxt: add NAT support for dest IP and port combination Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 02/19] net/bnxt: add support for multi root capability Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 04/19] net/bnxt: add clear on read support Venkat Duvvuru ` (15 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> The number of hash bucket list calculation is fixed and added check to limit the out of boundary condition Fixes: 0001cc58d362 ("net/bnxt: support generic hash table") Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c index 3c6e7fe924..84c83de35c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c @@ -16,20 +16,21 @@ int32_t ulp_bit_alloc_list_alloc(struct bit_alloc_list *blist, { uint64_t bentry; uint32_t idx = 0, jdx = 0; + uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES; /* Iterate all numbers that have all 1's */ do { bentry = blist->bdata[idx++]; - } while (bentry == -1UL && idx < blist->bsize); + } while (bentry == -1UL && idx <= bsize_64); - if (idx < blist->bsize) { + if (idx <= bsize_64) { if (bentry) jdx = __builtin_clzl(~bentry); *index = ((idx - 1) * ULP_INDEX_BITMAP_SIZE) + jdx; ULP_INDEX_BITMAP_SET(blist->bdata[(idx - 1)], jdx); return 0; } - jdx = (uint32_t)(blist->bsize * ULP_INDEX_BITMAP_SIZE); + jdx = (uint32_t)(bsize_64 * ULP_INDEX_BITMAP_SIZE); BNXT_TF_DBG(ERR, "bit allocator is full reached max:%x\n", jdx); return -1; } @@ -39,9 +40,10 @@ int32_t ulp_bit_alloc_list_dealloc(struct bit_alloc_list *blist, uint32_t index) { uint32_t idx = 0, jdx; + uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES; idx = index / ULP_INDEX_BITMAP_SIZE; - if (idx >= blist->bsize) { + if (idx >= bsize_64) { BNXT_TF_DBG(ERR, "invalid bit index %x:%x\n", idx, blist->bsize); return -EINVAL; @@ -127,7 +129,8 @@ ulp_gen_hash_tbl_list_init(struct ulp_hash_create_params *cparams, hash_tbl->hash_mask = size - 1; /* allocate the memory for the bit allocator */ - size = (cparams->num_key_entries / sizeof(uint64_t)) + 1; + size = (cparams->num_key_entries / sizeof(uint64_t)); + size = ULP_BYTE_ROUND_OFF_8(size); hash_tbl->bit_list.bsize = size; hash_tbl->bit_list.bdata = rte_zmalloc("Generic hash bit alloc", size, ULP_BUFFER_ALIGN_64_BYTE); @@ -311,7 +314,12 @@ ulp_gen_hash_tbl_list_add(struct ulp_gen_hash_tbl *hash_tbl, BNXT_TF_DBG(ERR, "Error in bit list alloc\n"); return -ENOMEM; } - + if (key_index > hash_tbl->num_key_entries) { + BNXT_TF_DBG(ERR, "reached max size %u:%u\n", key_index, + hash_tbl->num_key_entries); + ulp_bit_alloc_list_dealloc(&hash_tbl->bit_list, key_index); + return -ENOMEM; + } /* Update the hash entry */ ULP_HASH_BUCKET_MARK_INUSE(bucket, (uint16_t)key_index); -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 04/19] net/bnxt: add clear on read support 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (2 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 03/19] net/bnxt: fix the out of boundary issue in hash list Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 05/19] net/bnxt: add capability option for socket redirect Venkat Duvvuru ` (14 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Farah Smith, Kishore Padmanabha, Venkat Duvvuru From: Farah Smith <farah.smith@broadcom.com> Add clear on read stats support for Thor. Currently, the flow stats are not cleared after they are read from the FW. This patch adds support for clear on read. Since clear on read support is added for flow stats in Thor, the flow accumulation is enabled on Thor as well. Signed-off-by: Farah Smith <farah.smith@broadcom.com> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com> --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 34 ++++++++++++++++++++------ drivers/net/bnxt/tf_core/tf_msg.c | 24 +++++++++++++++--- drivers/net/bnxt/tf_core/tf_msg.h | 6 +++-- drivers/net/bnxt/tf_core/tf_tbl.c | 6 +++-- drivers/net/bnxt/tf_core/tf_tbl_sram.c | 13 ++++++++-- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 3 ++- 6 files changed, 67 insertions(+), 19 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 2a1e6ab97e..77981b5cdb 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1058,8 +1058,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 54 -#define HWRM_VERSION_STR "1.10.2.54" +#define HWRM_VERSION_RSVD 55 +#define HWRM_VERSION_STR "1.10.2.55" /**************** * hwrm_ver_get * @@ -46253,13 +46253,22 @@ struct hwrm_tf_tbl_type_get_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entry on read. + */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* @@ -48489,13 +48498,22 @@ struct hwrm_tf_tbl_type_bulk_get_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entries on read. + */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 0fbb2fe837..ea6e2af7ce 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -1851,7 +1851,8 @@ tf_msg_get_tbl_entry(struct tf *tfp, uint16_t hcapi_type, uint16_t size, uint8_t *data, - uint32_t index) + uint32_t index, + bool clear_on_read) { int rc; struct hwrm_tf_tbl_type_get_input req = { 0 }; @@ -1860,6 +1861,7 @@ tf_msg_get_tbl_entry(struct tf *tfp, uint8_t fw_session_id; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t flags = 0; /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); @@ -1889,10 +1891,16 @@ tf_msg_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } + flags = (dir == TF_DIR_TX ? + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX : + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX); + + if (clear_on_read) + flags |= HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ; /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); - req.flags = tfp_cpu_to_le_16(dir); + req.flags = tfp_cpu_to_le_16(flags); req.type = tfp_cpu_to_le_32(hcapi_type); req.index = tfp_cpu_to_le_32(index); @@ -2105,7 +2113,8 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint32_t starting_idx, uint16_t num_entries, uint16_t entry_sz_in_bytes, - uint64_t physical_mem_addr) + uint64_t physical_mem_addr, + bool clear_on_read) { int rc; struct tfp_send_msg_parms parms = { 0 }; @@ -2115,6 +2124,7 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint8_t fw_session_id; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t flags = 0; /* Retrieve the session information */ rc = tf_session_get_session(tfp, &tfs); @@ -2144,10 +2154,16 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } + flags = (dir == TF_DIR_TX ? + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX : + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX); + + if (clear_on_read) + flags |= HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ; /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); - req.flags = tfp_cpu_to_le_16(dir); + req.flags = tfp_cpu_to_le_16(flags); req.type = tfp_cpu_to_le_32(hcapi_type); req.start_index = tfp_cpu_to_le_32(starting_idx); req.num_entries = tfp_cpu_to_le_32(num_entries); diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index b26b15bfa3..718bc2f3b2 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -652,7 +652,8 @@ int tf_msg_get_tbl_entry(struct tf *tfp, uint16_t hcapi_type, uint16_t size, uint8_t *data, - uint32_t index); + uint32_t index, + bool clear_on_read); /* HWRM Tunneled messages */ @@ -704,7 +705,8 @@ int tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint32_t starting_idx, uint16_t num_entries, uint16_t entry_sz_in_bytes, - uint64_t physical_mem_addr); + uint64_t physical_mem_addr, + bool clear_on_read); /** * Sends Set message of a IF Table Type element to the firmware. diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 0a8720e7b6..12eca36491 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -441,7 +441,8 @@ tf_tbl_get(struct tf *tfp, hcapi_type, parms->data_sz_in_bytes, parms->data, - parms->idx); + parms->idx, + false); if (rc) { TFP_DRV_LOG(ERR, "%s, Get failed, type:%s, rc:%s\n", @@ -526,7 +527,8 @@ tf_tbl_bulk_get(struct tf *tfp, parms->starting_idx, parms->num_entries, parms->entry_sz_in_bytes, - parms->physical_mem_addr); + parms->physical_mem_addr, + false); if (rc) { TFP_DRV_LOG(ERR, "%s, Bulk get failed, type:%s, rc:%s\n", diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c index 636811bc2d..567f912dfa 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c +++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c @@ -539,6 +539,7 @@ tf_tbl_sram_get(struct tf *tfp, struct tf_tbl_sram_get_info_parms iparms = { 0 }; struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; void *sram_handle = NULL; + bool clear_on_read = false; TF_CHECK_PARMS3(tfp, parms, parms->data); @@ -608,6 +609,8 @@ tf_tbl_sram_get(struct tf *tfp, strerror(-rc)); return rc; } + if (parms->type == TF_TBL_TYPE_ACT_STATS_64) + clear_on_read = true; /* Get the entry */ rc = tf_msg_get_tbl_entry(tfp, @@ -615,7 +618,8 @@ tf_tbl_sram_get(struct tf *tfp, hcapi_type, parms->data_sz_in_bytes, parms->data, - parms->idx); + parms->idx, + clear_on_read); if (rc) { TFP_DRV_LOG(ERR, "%s, Get failed, type:%s, rc:%s\n", @@ -643,6 +647,7 @@ tf_tbl_sram_bulk_get(struct tf *tfp, struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; bool allocated = false; void *sram_handle = NULL; + bool clear_on_read = false; TF_CHECK_PARMS2(tfp, parms); @@ -728,6 +733,9 @@ tf_tbl_sram_bulk_get(struct tf *tfp, return rc; } + if (parms->type == TF_TBL_TYPE_ACT_STATS_64) + clear_on_read = true; + /* Get the entries */ rc = tf_msg_bulk_get_tbl_entry(tfp, parms->dir, @@ -735,7 +743,8 @@ tf_tbl_sram_bulk_get(struct tf *tfp, parms->starting_idx, parms->num_entries, parms->entry_sz_in_bytes, - parms->physical_mem_addr); + parms->physical_mem_addr, + clear_on_read); if (rc) { TFP_DRV_LOG(ERR, "%s, Bulk get failed, type:%s, rc:%s\n", diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index dbc8a3c5bb..f1763e2519 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1483,7 +1483,8 @@ bnxt_ulp_port_init(struct bnxt *bp) goto jump_to_error; } - if (devid != BNXT_ULP_DEVICE_ID_THOR && BNXT_ACCUM_STATS_EN(bp)) + /* set the accumulation of the stats */ + if (BNXT_ACCUM_STATS_EN(bp)) bp->ulp_ctx->cfg_data->accum_stats = true; BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init, accum_stats:%d\n", -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 05/19] net/bnxt: add capability option for socket redirect 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (3 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 04/19] net/bnxt: add clear on read support Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 06/19] net/bnxt: enable wildcard match for ingress flows Venkat Duvvuru ` (13 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Added support for socket redirect feature capability so applications can enable or disable this feature. This patch contains the template changes. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/bnxt.h | 13 -- drivers/net/bnxt/bnxt_ethdev.c | 203 ------------------ drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 11 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 6 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 10 +- .../generic_templates/ulp_template_db_enum.h | 8 +- .../generic_templates/ulp_template_db_tbl.c | 5 +- 7 files changed, 30 insertions(+), 226 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index e3e38ffa19..c65e360446 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -1054,19 +1054,6 @@ int32_t bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); int32_t bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); -void bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, - uint8_t *mac, uint8_t *parent_mac); -uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); -struct bnxt *bnxt_get_bp(uint16_t port); -uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, - enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_phy_port_id(uint16_t port); -uint16_t bnxt_get_vport(uint16_t port); -enum bnxt_ulp_intf_type -bnxt_get_interface_type(uint16_t port); int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev); void bnxt_cancel_fc_thread(struct bnxt *bp); diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index f385723a9f..bf034db336 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -5056,209 +5056,6 @@ static void bnxt_config_vf_req_fwd(struct bnxt *bp) BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); } -struct bnxt * -bnxt_get_bp(uint16_t port) -{ - struct bnxt *bp; - struct rte_eth_dev *dev; - - if (!rte_eth_dev_is_valid_port(port)) { - PMD_DRV_LOG(ERR, "Invalid port %d\n", port); - return NULL; - } - - dev = &rte_eth_devices[port]; - if (!is_bnxt_supported(dev)) { - PMD_DRV_LOG(ERR, "Device %d not supported\n", port); - return NULL; - } - - bp = (struct bnxt *)dev->data->dev_private; - if (!BNXT_TRUFLOW_EN(bp)) { - PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); - return NULL; - } - - return bp; -} - -uint16_t -bnxt_get_svif(uint16_t port_id, bool func_svif, - enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->svif; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return func_svif ? bp->func_svif : bp->port_svif; -} - -void -bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, - uint8_t *mac, uint8_t *parent_mac) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF && - type != BNXT_ULP_INTF_TYPE_PF) - return; - - eth_dev = &rte_eth_devices[port]; - bp = eth_dev->data->dev_private; - memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN); - - if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF) - memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN); -} - -uint16_t -bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF) - return 0; - - eth_dev = &rte_eth_devices[port]; - bp = eth_dev->data->dev_private; - - return bp->parent->vnic; -} -uint16_t -bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt_vnic_info *vnic; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->dflt_vnic_id; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - vnic = BNXT_GET_DEFAULT_VNIC(bp); - - return vnic->fw_vnic_id; -} - -uint16_t -bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->fw_fid; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return bp->fw_fid; -} - -enum bnxt_ulp_intf_type -bnxt_get_interface_type(uint16_t port) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) - return BNXT_ULP_INTF_TYPE_VF_REP; - - bp = eth_dev->data->dev_private; - if (BNXT_PF(bp)) - return BNXT_ULP_INTF_TYPE_PF; - else if (BNXT_VF_IS_TRUSTED(bp)) - return BNXT_ULP_INTF_TYPE_TRUSTED_VF; - else if (BNXT_VF(bp)) - return BNXT_ULP_INTF_TYPE_VF; - - return BNXT_ULP_INTF_TYPE_INVALID; -} - -uint16_t -bnxt_get_phy_port_id(uint16_t port_id) -{ - struct bnxt_representor *vfr; - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; -} - -uint16_t -bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->fw_fid - 1; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; -} - -uint16_t -bnxt_get_vport(uint16_t port_id) -{ - return (1 << bnxt_get_phy_port_id(port_id)); -} - static void bnxt_alloc_error_recovery_info(struct bnxt *bp) { struct bnxt_error_recovery_info *info = bp->recovery_info; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index f1763e2519..2ac1a8625f 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -301,13 +301,14 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, } int32_t -bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, uint8_t app_id, uint32_t dev_id) { struct bnxt_ulp_app_capabilities_info *info; uint32_t num = 0; uint16_t i; bool found = false; + struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx; if (ULP_APP_DEV_UNSUPPORTED_ENABLED(ulp_ctx->cfg_data->ulp_flags)) { BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", @@ -334,6 +335,12 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, if (info[i].flags & BNXT_ULP_APP_CAP_UNICAST_ONLY) ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_APP_UNICAST_ONLY; + if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) { + /* Enable socket direction only if MR is enabled in fw*/ + if (BNXT_MULTIROOT_EN(bp)) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_SOCKET_DIRECT; + } } if (!found) { BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", @@ -832,7 +839,7 @@ ulp_ctx_init(struct bnxt *bp, } BNXT_TF_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id); - rc = bnxt_ulp_cntxt_app_caps_init(bp->ulp_ctx, bp->app_id, devid); + rc = bnxt_ulp_cntxt_app_caps_init(bp, bp->app_id, devid); if (rc) { BNXT_TF_DBG(ERR, "Unable to set caps for app(%x)/dev(%x)\n", bp->app_id, devid); diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 006df9cbc5..68f1470c61 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -13,6 +13,7 @@ #include "rte_version.h" #include "rte_ethdev.h" +#include "bnxt.h" #include "ulp_template_db_enum.h" #include "ulp_tun.h" #include "bnxt_tf_common.h" @@ -33,12 +34,15 @@ #define BNXT_ULP_APP_DEV_UNSUPPORTED 0x4 #define BNXT_ULP_HIGH_AVAIL_ENABLED 0x8 #define BNXT_ULP_APP_UNICAST_ONLY 0x10 +#define BNXT_ULP_APP_SOCKET_DIRECT 0x20 + #define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED) #define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\ BNXT_ULP_SHARED_SESSION_ENABLED) #define ULP_APP_DEV_UNSUPPORTED_ENABLED(flag) ((flag) &\ BNXT_ULP_APP_DEV_UNSUPPORTED) #define ULP_HIGH_AVAIL_IS_ENABLED(flag) ((flag) & BNXT_ULP_HIGH_AVAIL_ENABLED) +#define ULP_SOCKET_DIRECT_IS_ENABLED(flag) ((flag) & BNXT_ULP_APP_SOCKET_DIRECT) enum bnxt_ulp_flow_mem_type { BNXT_ULP_FLOW_MEM_TYPE_INT = 0, @@ -287,7 +291,7 @@ struct bnxt_ulp_app_capabilities_info * bnxt_ulp_app_cap_list_get(uint32_t *num_entries); int32_t -bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, uint8_t app_id, uint32_t dev_id); struct bnxt_ulp_resource_resv_info * diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 2fec79a388..272195f6a2 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -115,9 +115,11 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FLOW_SIG_ID, params->flow_sig_id); + if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags)) + return; + /* update the WC Priority flag */ - if (!bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags) && - ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) { + if (ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) { enum ulp_ha_mgr_region region = ULP_HA_REGION_LOW; int32_t rc; @@ -129,6 +131,10 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG, 1); } + + /* Update the socket direct flag */ + if (ULP_SOCKET_DIRECT_IS_ENABLED(ulp_flags)) + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT, 1); } /* Function to create the rte flow. */ diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index fcd460e707..31a94c14dc 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Aug 26 17:43:36 2021 */ +/* date: Thu Sep 9 11:11:05 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -211,7 +211,8 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 71, BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72, BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73, - BNXT_ULP_CF_IDX_LAST = 74 + BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74, + BNXT_ULP_CF_IDX_LAST = 75 }; enum bnxt_ulp_cond_list_opc { @@ -582,7 +583,8 @@ enum bnxt_ulp_template_type { enum bnxt_ulp_app_cap { BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001, BNXT_ULP_APP_CAP_HOT_UPGRADE_EN = 0x00000002, - BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004 + BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004, + BNXT_ULP_APP_CAP_SOCKET_DIRECT = 0x00000008 }; enum bnxt_ulp_fdb_resource_flags { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 84be09b368..5383e2cd70 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Aug 26 17:43:36 2021 */ +/* date: Thu Sep 9 11:11:05 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -347,7 +347,8 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { .device_id = BNXT_ULP_DEVICE_ID_THOR, .flags = BNXT_ULP_APP_CAP_SHARED_EN | BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | - BNXT_ULP_APP_CAP_UNICAST_ONLY + BNXT_ULP_APP_CAP_UNICAST_ONLY | + BNXT_ULP_APP_CAP_SOCKET_DIRECT }, { .app_id = 2, -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 06/19] net/bnxt: enable wildcard match for ingress flows 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (4 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 05/19] net/bnxt: add capability option for socket redirect Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 07/19] net/bnxt: support inner IP header for GRE tunnel flows Venkat Duvvuru ` (12 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Enabled wildcard match support for ipv4 ingress flows. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- .../generic_templates/ulp_template_db_class.c | 1986 ++++++++--------- .../generic_templates/ulp_template_db_enum.h | 4 +- .../ulp_template_db_thor_class.c | 251 +-- 3 files changed, 1118 insertions(+), 1123 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c index ad3866243d..1d1e6463e0 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 6 11:15:47 2021 */ +/* date: Thu Sep 16 13:12:05 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -1016,7 +1016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55dd, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1031,7 +1031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1df1, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4104, + .flow_sig_id = 4104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1047,7 +1047,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e55, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1063,7 +1063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0649, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 6152, + .flow_sig_id = 6152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1080,7 +1080,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1011, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1095,7 +1095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40e9, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 16392, + .flow_sig_id = 16392UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1111,7 +1111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e99, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1127,7 +1127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06ad, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 24584, + .flow_sig_id = 24584UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1144,7 +1144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_38c7, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1160,7 +1160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00fb, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32776, + .flow_sig_id = 32776UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1177,7 +1177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_24d3, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1194,7 +1194,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_559b, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32840, + .flow_sig_id = 32840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1212,7 +1212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5003, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1229,7 +1229,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1837, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1247,7 +1247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bef, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1265,7 +1265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0403, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49224, + .flow_sig_id = 49224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1284,7 +1284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d3f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1300,7 +1300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0543, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131080, + .flow_sig_id = 131080UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1317,7 +1317,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_292b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1334,7 +1334,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59e3, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131144, + .flow_sig_id = 131144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1352,7 +1352,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d3b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1369,7 +1369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_254f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196616, + .flow_sig_id = 196616UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1387,7 +1387,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4917, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1405,7 +1405,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_113b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196680, + .flow_sig_id = 196680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1424,7 +1424,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55fd, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1440,7 +1440,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1dd1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 4104, + .flow_sig_id = 4104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1457,7 +1457,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e75, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1474,7 +1474,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0669, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 6152, + .flow_sig_id = 6152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1492,7 +1492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ba1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1509,7 +1509,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c69, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 12296, + .flow_sig_id = 12296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1527,7 +1527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0439, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1545,7 +1545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34e1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 14344, + .flow_sig_id = 14344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1564,7 +1564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0465, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1581,7 +1581,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_352d, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 20488, + .flow_sig_id = 20488UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1599,7 +1599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55b1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1617,7 +1617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1da5, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 22536, + .flow_sig_id = 22536UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1636,7 +1636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_32fd, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1654,7 +1654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_63a5, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 28680, + .flow_sig_id = 28680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1673,7 +1673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1b75, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1692,7 +1692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c3d, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 30728, + .flow_sig_id = 30728UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1712,7 +1712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1031, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1728,7 +1728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40c9, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 16392, + .flow_sig_id = 16392UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1745,7 +1745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3eb9, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1762,7 +1762,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_068d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24584, + .flow_sig_id = 24584UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1780,7 +1780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5039, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1797,7 +1797,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_180d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1815,7 +1815,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15fd, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1833,7 +1833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46b5, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 57352, + .flow_sig_id = 57352UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1852,7 +1852,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_303d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1869,7 +1869,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_60f5, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 81928, + .flow_sig_id = 81928UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1887,7 +1887,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ea5, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1905,7 +1905,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2689, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 90120, + .flow_sig_id = 90120UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1924,7 +1924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0771, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1942,7 +1942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3809, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1961,7 +1961,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35f9, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1980,7 +1980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66b1, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 122888, + .flow_sig_id = 122888UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2000,7 +2000,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_559d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2016,7 +2016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1db1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 4104, + .flow_sig_id = 4104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2033,7 +2033,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e15, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2050,7 +2050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0609, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 6152, + .flow_sig_id = 6152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2068,7 +2068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1bc1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2085,7 +2085,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c09, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 12296, + .flow_sig_id = 12296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2103,7 +2103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0459, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2121,7 +2121,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3481, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14344, + .flow_sig_id = 14344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2140,7 +2140,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0405, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2157,7 +2157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_354d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 20488, + .flow_sig_id = 20488UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2175,7 +2175,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55d1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2193,7 +2193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1dc5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 22536, + .flow_sig_id = 22536UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2212,7 +2212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_329d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2230,7 +2230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_63c5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 28680, + .flow_sig_id = 28680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2249,7 +2249,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1b15, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2268,7 +2268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c5d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 30728, + .flow_sig_id = 30728UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2288,7 +2288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1051, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2304,7 +2304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40a9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16392, + .flow_sig_id = 16392UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2321,7 +2321,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ed9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2338,7 +2338,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06ed, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 24584, + .flow_sig_id = 24584UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2356,7 +2356,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5059, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2373,7 +2373,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_186d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2391,7 +2391,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_159d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2409,7 +2409,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46d5, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 57352, + .flow_sig_id = 57352UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2428,7 +2428,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_305d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2445,7 +2445,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6095, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 81928, + .flow_sig_id = 81928UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2463,7 +2463,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ec5, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2481,7 +2481,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26e9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 90120, + .flow_sig_id = 90120UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2500,7 +2500,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0711, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2518,7 +2518,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3869, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2537,7 +2537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3599, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2556,7 +2556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66d1, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 122888, + .flow_sig_id = 122888UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2576,7 +2576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_38e7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2593,7 +2593,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00db, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32776, + .flow_sig_id = 32776UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2611,7 +2611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_24f3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2629,7 +2629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55bb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32840, + .flow_sig_id = 32840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2648,7 +2648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5023, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2666,7 +2666,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1817, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2685,7 +2685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bcf, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2704,7 +2704,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0423, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49224, + .flow_sig_id = 49224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2724,7 +2724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_58e3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2742,7 +2742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20d7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98312, + .flow_sig_id = 98312UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2761,7 +2761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_448f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2780,7 +2780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0ce3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98376, + .flow_sig_id = 98376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2800,7 +2800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_076b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2819,7 +2819,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3813, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2839,7 +2839,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5bcb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2859,7 +2859,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_243f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114760, + .flow_sig_id = 114760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2880,7 +2880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_144b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2898,7 +2898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4573, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163848, + .flow_sig_id = 163848UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2917,7 +2917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0057, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2936,7 +2936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_311f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163912, + .flow_sig_id = 163912UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2956,7 +2956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2b87, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2975,7 +2975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c4f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180232, + .flow_sig_id = 180232UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2995,7 +2995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1793, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3015,7 +3015,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_485b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180296, + .flow_sig_id = 180296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3036,7 +3036,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3447, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3055,7 +3055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_650f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229384, + .flow_sig_id = 229384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3075,7 +3075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2053, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3095,7 +3095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_511b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229448, + .flow_sig_id = 229448UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3116,7 +3116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4b83, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3136,7 +3136,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13f7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245768, + .flow_sig_id = 245768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3157,7 +3157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_37af, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3178,7 +3178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6857, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245832, + .flow_sig_id = 245832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3200,7 +3200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d1f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3217,7 +3217,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0563, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131080, + .flow_sig_id = 131080UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3235,7 +3235,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_290b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3253,7 +3253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59c3, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131144, + .flow_sig_id = 131144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3272,7 +3272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d1b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3290,7 +3290,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_256f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196616, + .flow_sig_id = 196616UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3309,7 +3309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4937, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3328,7 +3328,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_111b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196680, + .flow_sig_id = 196680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3348,7 +3348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f4b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3366,7 +3366,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_275f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393224, + .flow_sig_id = 393224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3385,7 +3385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4b67, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3404,7 +3404,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_134b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393288, + .flow_sig_id = 393288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3424,7 +3424,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1683, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3443,7 +3443,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_475b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458760, + .flow_sig_id = 458760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3463,7 +3463,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_02bf, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3483,7 +3483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3377, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458824, + .flow_sig_id = 458824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3504,7 +3504,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19db, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3522,7 +3522,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4a93, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655368, + .flow_sig_id = 655368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3541,7 +3541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_05f7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3560,7 +3560,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_368f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655432, + .flow_sig_id = 655432UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3580,7 +3580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39c7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3599,7 +3599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_022b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720904, + .flow_sig_id = 720904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3619,7 +3619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_25f3, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3639,7 +3639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_568b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720968, + .flow_sig_id = 720968UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3660,7 +3660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c37, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3679,7 +3679,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_041b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917512, + .flow_sig_id = 917512UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3699,7 +3699,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2823, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3719,7 +3719,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_58fb, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917576, + .flow_sig_id = 917576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3740,7 +3740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c33, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3760,7 +3760,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2407, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983048, + .flow_sig_id = 983048UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3781,7 +3781,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_482f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3802,7 +3802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1033, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983112, + .flow_sig_id = 983112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3824,7 +3824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3887, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3841,7 +3841,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00bb, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32776, + .flow_sig_id = 32776UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3859,7 +3859,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2493, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3877,7 +3877,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55db, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32840, + .flow_sig_id = 32840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3896,7 +3896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5043, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3914,7 +3914,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1877, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3933,7 +3933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3baf, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3952,7 +3952,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0443, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49224, + .flow_sig_id = 49224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3972,7 +3972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5883, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3990,7 +3990,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20b7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98312, + .flow_sig_id = 98312UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4009,7 +4009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_44ef, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4028,7 +4028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c83, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98376, + .flow_sig_id = 98376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4048,7 +4048,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_070b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4067,7 +4067,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3873, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4087,7 +4087,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5bab, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4107,7 +4107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_245f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114760, + .flow_sig_id = 114760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4128,7 +4128,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_142b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4146,7 +4146,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4513, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163848, + .flow_sig_id = 163848UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4165,7 +4165,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0037, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4184,7 +4184,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_317f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163912, + .flow_sig_id = 163912UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4204,7 +4204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2be7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4223,7 +4223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c2f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180232, + .flow_sig_id = 180232UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4243,7 +4243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_17f3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4263,7 +4263,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_483b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180296, + .flow_sig_id = 180296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4284,7 +4284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3427, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4303,7 +4303,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_656f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229384, + .flow_sig_id = 229384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4323,7 +4323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2033, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4343,7 +4343,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_517b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229448, + .flow_sig_id = 229448UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4364,7 +4364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4be3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4384,7 +4384,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1397, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245768, + .flow_sig_id = 245768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4405,7 +4405,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_37cf, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4426,7 +4426,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6837, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245832, + .flow_sig_id = 245832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4448,7 +4448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d7f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4465,7 +4465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0503, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131080, + .flow_sig_id = 131080UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4483,7 +4483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_296b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4501,7 +4501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59a3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131144, + .flow_sig_id = 131144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4520,7 +4520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d7b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4538,7 +4538,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_250f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196616, + .flow_sig_id = 196616UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4557,7 +4557,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4957, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4576,7 +4576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_117b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196680, + .flow_sig_id = 196680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4596,7 +4596,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f2b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4614,7 +4614,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_273f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393224, + .flow_sig_id = 393224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4633,7 +4633,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4b07, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4652,7 +4652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_132b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393288, + .flow_sig_id = 393288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4672,7 +4672,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_16e3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4691,7 +4691,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_473b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458760, + .flow_sig_id = 458760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4711,7 +4711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_02df, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4731,7 +4731,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3317, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458824, + .flow_sig_id = 458824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4752,7 +4752,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19bb, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4770,7 +4770,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4af3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655368, + .flow_sig_id = 655368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4789,7 +4789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0597, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4808,7 +4808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_36ef, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655432, + .flow_sig_id = 655432UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4828,7 +4828,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39a7, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4847,7 +4847,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_024b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720904, + .flow_sig_id = 720904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4867,7 +4867,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2593, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4887,7 +4887,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_56eb, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720968, + .flow_sig_id = 720968UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4908,7 +4908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c57, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4927,7 +4927,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_047b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917512, + .flow_sig_id = 917512UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4947,7 +4947,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2843, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4967,7 +4967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_589b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917576, + .flow_sig_id = 917576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4988,7 +4988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c53, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5008,7 +5008,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2467, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983048, + .flow_sig_id = 983048UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5029,7 +5029,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_484f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5050,7 +5050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1053, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983112, + .flow_sig_id = 983112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5072,7 +5072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ce1, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5086,7 +5086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4579, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5101,7 +5101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1735, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5115,7 +5115,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_45bd, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5130,7 +5130,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3feb, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5145,7 +5145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bf7, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5161,7 +5161,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5727, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5177,7 +5177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4333, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5194,7 +5194,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4453, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5209,7 +5209,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_304f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5225,7 +5225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_645f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5241,7 +5241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_504b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5258,7 +5258,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5cc1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5273,7 +5273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4559, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5289,7 +5289,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2285, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5305,7 +5305,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b1d, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5322,7 +5322,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b49, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5338,7 +5338,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c95, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5355,7 +5355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39c1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5372,7 +5372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2259, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5390,7 +5390,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1715, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5405,7 +5405,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_459d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5421,7 +5421,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_571d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5437,7 +5437,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cd1, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5454,7 +5454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3711, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5470,7 +5470,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6599, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5487,7 +5487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e55, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5504,7 +5504,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3cdd, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5522,7 +5522,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ca1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5537,7 +5537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4539, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5553,7 +5553,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_22e5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5569,7 +5569,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b7d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5586,7 +5586,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b29, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5602,7 +5602,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5cf5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5619,7 +5619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39a1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5636,7 +5636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2239, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5654,7 +5654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1775, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5669,7 +5669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_45fd, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5685,7 +5685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_577d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5701,7 +5701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cb1, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5718,7 +5718,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3771, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5734,7 +5734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_65f9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5751,7 +5751,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e35, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5768,7 +5768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3cbd, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5786,7 +5786,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3fcb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5802,7 +5802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bd7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5819,7 +5819,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5707, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5836,7 +5836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4313, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5854,7 +5854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5fc7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5871,7 +5871,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4bd3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5889,7 +5889,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e4f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5907,7 +5907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_632f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5926,7 +5926,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1baf, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5943,7 +5943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_07bb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5961,7 +5961,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_32eb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5979,7 +5979,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ef7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5998,7 +5998,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bab, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6016,7 +6016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_27b7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6035,7 +6035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52e7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6054,7 +6054,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ef3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6074,7 +6074,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4473, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6090,7 +6090,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_306f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6107,7 +6107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_647f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6124,7 +6124,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_506b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6142,7 +6142,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66af, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6159,7 +6159,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_525b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6177,7 +6177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1de7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6195,7 +6195,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0993, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6214,7 +6214,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_213f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6231,7 +6231,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d2b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6249,7 +6249,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_413b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6267,7 +6267,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2cd7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6286,7 +6286,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_436b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6304,7 +6304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2f07, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6323,7 +6323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6317, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6342,7 +6342,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4f03, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6362,7 +6362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3fab, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6378,7 +6378,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bb7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6395,7 +6395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5767, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6412,7 +6412,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4373, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6430,7 +6430,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5fa7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6447,7 +6447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4bb3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6465,7 +6465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e2f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6483,7 +6483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_634f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6502,7 +6502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1bcf, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6519,7 +6519,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_07db, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6537,7 +6537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_328b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6555,7 +6555,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1e97, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6574,7 +6574,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bcb, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6592,7 +6592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_27d7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6611,7 +6611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5287, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6630,7 +6630,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e93, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6650,7 +6650,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4413, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6666,7 +6666,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_300f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6683,7 +6683,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_641f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6700,7 +6700,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_500b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6718,7 +6718,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66cf, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6735,7 +6735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_523b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6753,7 +6753,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1d87, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6771,7 +6771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09f3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6790,7 +6790,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_215f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6807,7 +6807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d4b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6825,7 +6825,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_415b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6843,7 +6843,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2cb7, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6862,7 +6862,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_430b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6880,7 +6880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2f67, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6899,7 +6899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6377, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6918,7 +6918,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4f63, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6938,7 +6938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29b5, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -6953,7 +6953,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29ad, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -6968,7 +6968,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29b7, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -6984,7 +6984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1583, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7001,7 +7001,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29af, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7017,7 +7017,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_159b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7034,7 +7034,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2995, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7050,7 +7050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_298d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7066,7 +7066,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29f5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7082,7 +7082,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29ed, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7098,7 +7098,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2997, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7115,7 +7115,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15a3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7133,7 +7133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_298f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7150,7 +7150,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15bb, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7168,7 +7168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29f7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7185,7 +7185,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15c3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7203,7 +7203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29ef, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7220,7 +7220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15db, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7238,7 +7238,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1151, .class_tid = 1, .hdr_sig_id = 12, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 3, .app_sig = 0, .hdr_sig = { .bits = @@ -7255,7 +7255,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_315d, .class_tid = 1, .hdr_sig_id = 12, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 3, .app_sig = 0, .hdr_sig = { .bits = @@ -7273,7 +7273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3612, .class_tid = 2, .hdr_sig_id = 0, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -7292,7 +7292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66da, .class_tid = 2, .hdr_sig_id = 0, - .flow_sig_id = 81928, + .flow_sig_id = 81928UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -7312,7 +7312,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e082, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7332,7 +7332,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ab46, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7353,7 +7353,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c82a, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7374,7 +7374,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f9a2, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7396,7 +7396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d8ce, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 538184704, + .flow_sig_id = 538184704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7417,7 +7417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a2d2, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 538192896, + .flow_sig_id = 538192896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7439,7 +7439,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c076, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 540281856, + .flow_sig_id = 540281856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7461,7 +7461,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f1ee, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 540290048, + .flow_sig_id = 540290048UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7484,7 +7484,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a96e, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1075055616, + .flow_sig_id = 1075055616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7505,7 +7505,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dae6, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1075063808, + .flow_sig_id = 1075063808UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7527,7 +7527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c7aa, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1077152768, + .flow_sig_id = 1077152768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7549,7 +7549,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c26e, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1077160960, + .flow_sig_id = 1077160960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7572,7 +7572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a0fa, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1611926528, + .flow_sig_id = 1611926528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7594,7 +7594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d272, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1611934720, + .flow_sig_id = 1611934720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7617,7 +7617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fff6, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1614023680, + .flow_sig_id = 1614023680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7640,7 +7640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e16e, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1614031872, + .flow_sig_id = 1614031872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7664,7 +7664,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e165, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7684,7 +7684,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aaa1, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7705,7 +7705,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c9cd, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7726,7 +7726,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f845, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7748,7 +7748,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_90f9, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7769,7 +7769,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c371, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7791,7 +7791,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e19d, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7813,7 +7813,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d015, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7836,7 +7836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8c09, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7857,7 +7857,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_be89, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7879,7 +7879,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ddad, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7901,7 +7901,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cc2d, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7924,7 +7924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a4d9, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7946,7 +7946,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d759, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7969,7 +7969,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f27d, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7992,7 +7992,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e4fd, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8016,7 +8016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ecf6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8037,7 +8037,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a732, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8059,7 +8059,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c45e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8081,7 +8081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f5d6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8104,7 +8104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d4ba, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 538184704, + .flow_sig_id = 538184704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8126,7 +8126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aea6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 538192896, + .flow_sig_id = 538192896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8149,7 +8149,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cc02, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 540281856, + .flow_sig_id = 540281856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8172,7 +8172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fd9a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 540290048, + .flow_sig_id = 540290048UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8196,7 +8196,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a51a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1075055616, + .flow_sig_id = 1075055616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8218,7 +8218,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d692, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1075063808, + .flow_sig_id = 1075063808UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8241,7 +8241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cbde, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1077152768, + .flow_sig_id = 1077152768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8264,7 +8264,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce1a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1077160960, + .flow_sig_id = 1077160960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8288,7 +8288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ac8e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1611926528, + .flow_sig_id = 1611926528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8311,7 +8311,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_de06, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1611934720, + .flow_sig_id = 1611934720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8335,7 +8335,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f382, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1614023680, + .flow_sig_id = 1614023680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8359,7 +8359,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ed1a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1614031872, + .flow_sig_id = 1614031872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8384,7 +8384,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9d6a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8406,7 +8406,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cee2, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8429,7 +8429,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ec0e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8452,7 +8452,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dd86, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8476,7 +8476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_852e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2685668352, + .flow_sig_id = 2685668352UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8499,7 +8499,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b6a6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2685676544, + .flow_sig_id = 2685676544UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8523,7 +8523,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_eb82, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2687765504, + .flow_sig_id = 2687765504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8547,7 +8547,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c50a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2687773696, + .flow_sig_id = 2687773696UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8572,7 +8572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ccca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3222539264, + .flow_sig_id = 3222539264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8595,7 +8595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8706, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3222547456, + .flow_sig_id = 3222547456UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8619,7 +8619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d38e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3224636416, + .flow_sig_id = 3224636416UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8643,7 +8643,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d5ca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3224644608, + .flow_sig_id = 3224644608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8668,7 +8668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b48e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3759410176, + .flow_sig_id = 3759410176UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8692,7 +8692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8e8a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3759418368, + .flow_sig_id = 3759418368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8717,7 +8717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_db02, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3761507328, + .flow_sig_id = 3761507328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8742,7 +8742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dd8e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3761515520, + .flow_sig_id = 3761515520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8768,7 +8768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_819a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8790,7 +8790,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b31a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8813,7 +8813,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d03e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8836,7 +8836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c1be, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8860,7 +8860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_890e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4833152000, + .flow_sig_id = 4833152000UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8883,7 +8883,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ba8e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4833160192, + .flow_sig_id = 4833160192UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8907,7 +8907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dfaa, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4835249152, + .flow_sig_id = 4835249152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8931,7 +8931,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c93a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4835257344, + .flow_sig_id = 4835257344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8956,7 +8956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b11a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5370022912, + .flow_sig_id = 5370022912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8979,7 +8979,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8b4e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5370031104, + .flow_sig_id = 5370031104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9003,7 +9003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c79e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5372120064, + .flow_sig_id = 5372120064UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9027,7 +9027,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d9da, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5372128256, + .flow_sig_id = 5372128256UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9052,7 +9052,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b88e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5906893824, + .flow_sig_id = 5906893824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9076,7 +9076,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ea0e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5906902016, + .flow_sig_id = 5906902016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9101,7 +9101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cf0a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5908990976, + .flow_sig_id = 5908990976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9126,7 +9126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c18e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5908999168, + .flow_sig_id = 5908999168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9152,7 +9152,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a94a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9175,7 +9175,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_daca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9199,7 +9199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ffee, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9223,7 +9223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e96e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9248,7 +9248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_910e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6980635648, + .flow_sig_id = 6980635648UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9272,7 +9272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c28e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6980643840, + .flow_sig_id = 6980643840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9297,7 +9297,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e7aa, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6982732800, + .flow_sig_id = 6982732800UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9322,7 +9322,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d12a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6982740992, + .flow_sig_id = 6982740992UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9348,7 +9348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d8ca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7517506560, + .flow_sig_id = 7517506560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9372,7 +9372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_930e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7517514752, + .flow_sig_id = 7517514752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9397,7 +9397,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ef4e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7519603712, + .flow_sig_id = 7519603712UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9422,7 +9422,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e18a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7519611904, + .flow_sig_id = 7519611904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9448,7 +9448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c08e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8054377472, + .flow_sig_id = 8054377472UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9473,7 +9473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9a8a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8054385664, + .flow_sig_id = 8054385664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9499,7 +9499,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d70a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8056474624, + .flow_sig_id = 8056474624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9525,7 +9525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e90e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8056482816, + .flow_sig_id = 8056482816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9552,7 +9552,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_edd9, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9573,7 +9573,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a61d, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9595,7 +9595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c571, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9617,7 +9617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f4f9, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9640,7 +9640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9c45, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9662,7 +9662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cfcd, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9685,7 +9685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ed21, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9708,7 +9708,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dca9, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9732,7 +9732,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_80b5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9754,7 +9754,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b235, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9777,7 +9777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d111, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9800,7 +9800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c091, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9824,7 +9824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a865, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9847,7 +9847,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dbe5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9871,7 +9871,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fec1, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9895,7 +9895,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e841, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9920,7 +9920,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8e85, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8591248384, + .flow_sig_id = 8591248384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9942,7 +9942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b80d, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8591256576, + .flow_sig_id = 8591256576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9965,7 +9965,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_df65, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8593345536, + .flow_sig_id = 8593345536UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9988,7 +9988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ceed, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8593353728, + .flow_sig_id = 8593353728UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10012,7 +10012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9645, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10738732032, + .flow_sig_id = 10738732032UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10035,7 +10035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c1cd, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10738740224, + .flow_sig_id = 10738740224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10059,7 +10059,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e725, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10740829184, + .flow_sig_id = 10740829184UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10083,7 +10083,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d6ad, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10740837376, + .flow_sig_id = 10740837376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10108,7 +10108,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9aa5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12886215680, + .flow_sig_id = 12886215680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10131,7 +10131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b425, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12886223872, + .flow_sig_id = 12886223872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10155,7 +10155,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_eb05, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12888312832, + .flow_sig_id = 12888312832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10179,7 +10179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_da85, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12888321024, + .flow_sig_id = 12888321024UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10204,7 +10204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a265, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15033699328, + .flow_sig_id = 15033699328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10228,7 +10228,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dde5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15033707520, + .flow_sig_id = 15033707520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10253,7 +10253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f0c5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15035796480, + .flow_sig_id = 15035796480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10278,7 +10278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e245, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15035804672, + .flow_sig_id = 15035804672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10304,7 +10304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8b8f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17181182976, + .flow_sig_id = 17181182976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10326,7 +10326,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a517, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17181191168, + .flow_sig_id = 17181191168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10349,7 +10349,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d86b, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17183280128, + .flow_sig_id = 17183280128UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10372,7 +10372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cbf3, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17183288320, + .flow_sig_id = 17183288320UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10396,7 +10396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_934f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19328666624, + .flow_sig_id = 19328666624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10419,7 +10419,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c2c7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19328674816, + .flow_sig_id = 19328674816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10443,7 +10443,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e02b, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19330763776, + .flow_sig_id = 19330763776UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10467,7 +10467,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d3a3, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19330771968, + .flow_sig_id = 19330771968UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10492,7 +10492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_87a7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21476150272, + .flow_sig_id = 21476150272UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10515,7 +10515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b137, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21476158464, + .flow_sig_id = 21476158464UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10539,7 +10539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d403, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21478247424, + .flow_sig_id = 21478247424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10563,7 +10563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c793, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21478255616, + .flow_sig_id = 21478255616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10588,7 +10588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_af67, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23623633920, + .flow_sig_id = 23623633920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10612,7 +10612,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dee7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23623642112, + .flow_sig_id = 23623642112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10637,7 +10637,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fdc3, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23625731072, + .flow_sig_id = 23625731072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10662,7 +10662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ef43, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23625739264, + .flow_sig_id = 23625739264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10688,7 +10688,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8dbf, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25771117568, + .flow_sig_id = 25771117568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10711,7 +10711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_bf07, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25771125760, + .flow_sig_id = 25771125760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10735,7 +10735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d21f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25773214720, + .flow_sig_id = 25773214720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10759,7 +10759,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cde7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25773222912, + .flow_sig_id = 25773222912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10784,7 +10784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_956f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27918601216, + .flow_sig_id = 27918601216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10808,7 +10808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c4c7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27918609408, + .flow_sig_id = 27918609408UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10833,7 +10833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fbcf, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27920698368, + .flow_sig_id = 27920698368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10858,7 +10858,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d5a7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27920706560, + .flow_sig_id = 27920706560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10884,7 +10884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9957, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30066084864, + .flow_sig_id = 30066084864UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10908,7 +10908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cb27, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30066093056, + .flow_sig_id = 30066093056UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10933,7 +10933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ee37, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30068182016, + .flow_sig_id = 30068182016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10958,7 +10958,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d987, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30068190208, + .flow_sig_id = 30068190208UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10984,7 +10984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a107, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32213568512, + .flow_sig_id = 32213568512UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11009,7 +11009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d0e7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32213576704, + .flow_sig_id = 32213576704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11035,7 +11035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f7e7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32215665664, + .flow_sig_id = 32215665664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11061,7 +11061,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c827, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32215673856, + .flow_sig_id = 32215673856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11088,7 +11088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f76a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11109,7 +11109,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_bcae, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11131,7 +11131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dfc2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11153,7 +11153,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ee4a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11176,7 +11176,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cf26, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 538184704, + .flow_sig_id = 538184704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11198,7 +11198,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b53a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 538192896, + .flow_sig_id = 538192896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11221,7 +11221,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d79e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 540281856, + .flow_sig_id = 540281856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11244,7 +11244,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e606, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 540290048, + .flow_sig_id = 540290048UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11268,7 +11268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_be86, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1075055616, + .flow_sig_id = 1075055616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11290,7 +11290,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cd0e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1075063808, + .flow_sig_id = 1075063808UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11313,7 +11313,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d042, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1077152768, + .flow_sig_id = 1077152768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11336,7 +11336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d586, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1077160960, + .flow_sig_id = 1077160960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11360,7 +11360,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b712, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1611926528, + .flow_sig_id = 1611926528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11383,7 +11383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c59a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1611934720, + .flow_sig_id = 1611934720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11407,7 +11407,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e81e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1614023680, + .flow_sig_id = 1614023680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11431,7 +11431,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f686, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1614031872, + .flow_sig_id = 1614031872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11456,7 +11456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_86f6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11478,7 +11478,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d57e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11501,7 +11501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f792, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11524,7 +11524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c61a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11548,7 +11548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9eb2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2685668352, + .flow_sig_id = 2685668352UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11571,7 +11571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ad3a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2685676544, + .flow_sig_id = 2685676544UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11595,7 +11595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f01e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2687765504, + .flow_sig_id = 2687765504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11619,7 +11619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_de96, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2687773696, + .flow_sig_id = 2687773696UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11644,7 +11644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d756, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3222539264, + .flow_sig_id = 3222539264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11667,7 +11667,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9c9a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3222547456, + .flow_sig_id = 3222547456UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11691,7 +11691,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c812, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3224636416, + .flow_sig_id = 3224636416UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11715,7 +11715,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce56, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3224644608, + .flow_sig_id = 3224644608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11740,7 +11740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_af12, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3759410176, + .flow_sig_id = 3759410176UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11764,7 +11764,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9516, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3759418368, + .flow_sig_id = 3759418368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11789,7 +11789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c09e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3761507328, + .flow_sig_id = 3761507328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11814,7 +11814,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c612, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3761515520, + .flow_sig_id = 3761515520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11840,7 +11840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9a06, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11862,7 +11862,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a886, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11885,7 +11885,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cba2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11908,7 +11908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_da22, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11932,7 +11932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9292, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4833152000, + .flow_sig_id = 4833152000UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11955,7 +11955,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a112, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4833160192, + .flow_sig_id = 4833160192UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11979,7 +11979,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c436, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4835249152, + .flow_sig_id = 4835249152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12003,7 +12003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d2a6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4835257344, + .flow_sig_id = 4835257344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12028,7 +12028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aa86, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5370022912, + .flow_sig_id = 5370022912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12051,7 +12051,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_90d2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5370031104, + .flow_sig_id = 5370031104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12075,7 +12075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dc02, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5372120064, + .flow_sig_id = 5372120064UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12099,7 +12099,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c246, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5372128256, + .flow_sig_id = 5372128256UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12124,7 +12124,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a312, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5906893824, + .flow_sig_id = 5906893824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12148,7 +12148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f192, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5906902016, + .flow_sig_id = 5906902016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12173,7 +12173,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d496, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5908990976, + .flow_sig_id = 5908990976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12198,7 +12198,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_da12, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5908999168, + .flow_sig_id = 5908999168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12224,7 +12224,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b2d6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12247,7 +12247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c156, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12271,7 +12271,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e472, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12295,7 +12295,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f2f2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12320,7 +12320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8a92, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6980635648, + .flow_sig_id = 6980635648UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12344,7 +12344,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d912, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6980643840, + .flow_sig_id = 6980643840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12369,7 +12369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fc36, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6982732800, + .flow_sig_id = 6982732800UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12394,7 +12394,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cab6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6982740992, + .flow_sig_id = 6982740992UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12420,7 +12420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c356, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7517506560, + .flow_sig_id = 7517506560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12444,7 +12444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8892, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7517514752, + .flow_sig_id = 7517514752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12469,7 +12469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f4d2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7519603712, + .flow_sig_id = 7519603712UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12494,7 +12494,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fa16, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7519611904, + .flow_sig_id = 7519611904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12520,7 +12520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_db12, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8054377472, + .flow_sig_id = 8054377472UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12545,7 +12545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8116, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8054385664, + .flow_sig_id = 8054385664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12571,7 +12571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cc96, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8056474624, + .flow_sig_id = 8056474624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12597,7 +12597,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f292, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8056482816, + .flow_sig_id = 8056482816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12624,7 +12624,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e84d, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12645,7 +12645,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a389, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12667,7 +12667,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c0e5, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12689,7 +12689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f16d, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12712,7 +12712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_99d1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12734,7 +12734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ca59, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12757,7 +12757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e8b5, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12780,7 +12780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d93d, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12804,7 +12804,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8521, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12826,7 +12826,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b7a1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12849,7 +12849,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d485, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12872,7 +12872,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c505, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12896,7 +12896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_adf1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12919,7 +12919,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_de71, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12943,7 +12943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fb55, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12967,7 +12967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_edd5, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12992,7 +12992,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8b11, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8591248384, + .flow_sig_id = 8591248384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13014,7 +13014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_bd99, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8591256576, + .flow_sig_id = 8591256576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13037,7 +13037,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_daf1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8593345536, + .flow_sig_id = 8593345536UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13060,7 +13060,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cb79, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8593353728, + .flow_sig_id = 8593353728UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13084,7 +13084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_93d1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10738732032, + .flow_sig_id = 10738732032UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13107,7 +13107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c459, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10738740224, + .flow_sig_id = 10738740224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13131,7 +13131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e2b1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10740829184, + .flow_sig_id = 10740829184UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13155,7 +13155,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d339, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10740837376, + .flow_sig_id = 10740837376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13180,7 +13180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9f31, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12886215680, + .flow_sig_id = 12886215680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13203,7 +13203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b1b1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12886223872, + .flow_sig_id = 12886223872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13227,7 +13227,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ee91, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12888312832, + .flow_sig_id = 12888312832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13251,7 +13251,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_df11, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12888321024, + .flow_sig_id = 12888321024UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13276,7 +13276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a7f1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15033699328, + .flow_sig_id = 15033699328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13300,7 +13300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d871, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15033707520, + .flow_sig_id = 15033707520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13325,7 +13325,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f551, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15035796480, + .flow_sig_id = 15035796480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13350,7 +13350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e7d1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15035804672, + .flow_sig_id = 15035804672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13376,7 +13376,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8e1b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17181182976, + .flow_sig_id = 17181182976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13398,7 +13398,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a083, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17181191168, + .flow_sig_id = 17181191168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13421,7 +13421,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ddff, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17183280128, + .flow_sig_id = 17183280128UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13444,7 +13444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce67, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17183288320, + .flow_sig_id = 17183288320UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13468,7 +13468,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_96db, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19328666624, + .flow_sig_id = 19328666624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13491,7 +13491,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c753, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19328674816, + .flow_sig_id = 19328674816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13515,7 +13515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e5bf, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19330763776, + .flow_sig_id = 19330763776UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13539,7 +13539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d637, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19330771968, + .flow_sig_id = 19330771968UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13564,7 +13564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8233, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21476150272, + .flow_sig_id = 21476150272UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13587,7 +13587,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b4a3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21476158464, + .flow_sig_id = 21476158464UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13611,7 +13611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d197, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21478247424, + .flow_sig_id = 21478247424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13635,7 +13635,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c207, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21478255616, + .flow_sig_id = 21478255616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13660,7 +13660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aaf3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23623633920, + .flow_sig_id = 23623633920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13684,7 +13684,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_db73, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23623642112, + .flow_sig_id = 23623642112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13709,7 +13709,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f857, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23625731072, + .flow_sig_id = 23625731072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13734,7 +13734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ead7, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23625739264, + .flow_sig_id = 23625739264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13760,7 +13760,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_882b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25771117568, + .flow_sig_id = 25771117568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13783,7 +13783,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ba93, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25771125760, + .flow_sig_id = 25771125760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13807,7 +13807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d78b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25773214720, + .flow_sig_id = 25773214720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13831,7 +13831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c873, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25773222912, + .flow_sig_id = 25773222912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13856,7 +13856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_90fb, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27918601216, + .flow_sig_id = 27918601216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13880,7 +13880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c153, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27918609408, + .flow_sig_id = 27918609408UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13905,7 +13905,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fe5b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27920698368, + .flow_sig_id = 27920698368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13930,7 +13930,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d033, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27920706560, + .flow_sig_id = 27920706560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13956,7 +13956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9cc3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30066084864, + .flow_sig_id = 30066084864UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13980,7 +13980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ceb3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30066093056, + .flow_sig_id = 30066093056UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14005,7 +14005,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_eba3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30068182016, + .flow_sig_id = 30068182016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14030,7 +14030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dc13, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30068190208, + .flow_sig_id = 30068190208UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14056,7 +14056,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a493, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32213568512, + .flow_sig_id = 32213568512UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14081,7 +14081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d573, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32213576704, + .flow_sig_id = 32213576704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14107,7 +14107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f273, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32215665664, + .flow_sig_id = 32215665664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14133,7 +14133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cdb3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32215673856, + .flow_sig_id = 32215673856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14160,7 +14160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ff35, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14181,7 +14181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b4f1, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14203,7 +14203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d79d, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14225,7 +14225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e615, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14248,7 +14248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8ea9, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14270,7 +14270,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dd21, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14293,7 +14293,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ffcd, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14316,7 +14316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce45, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14340,7 +14340,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9259, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14362,7 +14362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a0d9, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14385,7 +14385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c3fd, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14408,7 +14408,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d27d, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14432,7 +14432,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ba89, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14455,7 +14455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c909, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14479,7 +14479,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ec2d, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14503,7 +14503,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_faad, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14528,7 +14528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34c6, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14543,7 +14543,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c22, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4100, + .flow_sig_id = 4100UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14559,7 +14559,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cbe, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14575,7 +14575,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_179a, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 6148, + .flow_sig_id = 6148UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14592,7 +14592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59be, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14607,7 +14607,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_515a, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 16388, + .flow_sig_id = 16388UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14623,7 +14623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c72, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14639,7 +14639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_171e, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 24580, + .flow_sig_id = 24580UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14656,7 +14656,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19c8, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14672,7 +14672,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_112c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32772, + .flow_sig_id = 32772UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14689,7 +14689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d68, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14706,7 +14706,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_444c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32836, + .flow_sig_id = 32836UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14724,7 +14724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e8c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14741,7 +14741,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09e0, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14759,7 +14759,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1af0, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14777,7 +14777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15d4, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49220, + .flow_sig_id = 49220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14796,7 +14796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1dd0, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14812,7 +14812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14f4, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131076, + .flow_sig_id = 131076UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14829,7 +14829,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_70b0, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14846,7 +14846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4854, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131140, + .flow_sig_id = 131140UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14864,7 +14864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3dd4, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14881,7 +14881,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34f8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196612, + .flow_sig_id = 196612UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14899,7 +14899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09e8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14917,7 +14917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_008c, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196676, + .flow_sig_id = 196676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14936,7 +14936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34e6, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14952,7 +14952,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c02, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4100, + .flow_sig_id = 4100UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14969,7 +14969,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c9e, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14986,7 +14986,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_17ba, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 6148, + .flow_sig_id = 6148UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15004,7 +15004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_429e, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15021,7 +15021,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5dba, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 12292, + .flow_sig_id = 12292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15039,7 +15039,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a16, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15057,7 +15057,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2532, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 14340, + .flow_sig_id = 14340UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15076,7 +15076,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2da2, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15093,7 +15093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_24fe, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 20484, + .flow_sig_id = 20484UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15111,7 +15111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_355a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15129,7 +15129,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c76, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 22532, + .flow_sig_id = 22532UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15148,7 +15148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13e6, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15166,7 +15166,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7276, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 28676, + .flow_sig_id = 28676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15185,7 +15185,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_42d2, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15204,7 +15204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5dee, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 30724, + .flow_sig_id = 30724UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15224,7 +15224,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59de, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15240,7 +15240,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_513a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 16388, + .flow_sig_id = 16388UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15257,7 +15257,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c12, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15274,7 +15274,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_177e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 24580, + .flow_sig_id = 24580UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15292,7 +15292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e92, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15309,7 +15309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09fe, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15327,7 +15327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c1a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15345,7 +15345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5746, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 57348, + .flow_sig_id = 57348UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15364,7 +15364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_79da, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15381,7 +15381,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7106, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 81924, + .flow_sig_id = 81924UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15399,7 +15399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c1e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15417,7 +15417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_377a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 90116, + .flow_sig_id = 90116UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15436,7 +15436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e9e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15454,7 +15454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29fa, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15473,7 +15473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14d2, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15492,7 +15492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7742, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 122884, + .flow_sig_id = 122884UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15512,7 +15512,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3706, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15528,7 +15528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0fe2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4100, + .flow_sig_id = 4100UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15545,7 +15545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1f7e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15562,7 +15562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_145a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 6148, + .flow_sig_id = 6148UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15580,7 +15580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_417e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15597,7 +15597,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e5a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 12292, + .flow_sig_id = 12292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15615,7 +15615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29f6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15633,7 +15633,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26d2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 14340, + .flow_sig_id = 14340UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15652,7 +15652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e42, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15669,7 +15669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_271e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 20484, + .flow_sig_id = 20484UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15687,7 +15687,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_36ba, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15705,7 +15705,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0f96, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 22532, + .flow_sig_id = 22532UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15724,7 +15724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1006, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15742,7 +15742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7196, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 28676, + .flow_sig_id = 28676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15761,7 +15761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4132, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15780,7 +15780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e0e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 30724, + .flow_sig_id = 30724UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15800,7 +15800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59fe, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15816,7 +15816,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_511a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 16388, + .flow_sig_id = 16388UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15833,7 +15833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c32, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15850,7 +15850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_175e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 24580, + .flow_sig_id = 24580UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15868,7 +15868,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0eb2, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15885,7 +15885,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09de, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15903,7 +15903,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c3a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15921,7 +15921,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5766, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 57348, + .flow_sig_id = 57348UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15940,7 +15940,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_79fa, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15957,7 +15957,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7126, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 81924, + .flow_sig_id = 81924UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15975,7 +15975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c3e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15993,7 +15993,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_375a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 90116, + .flow_sig_id = 90116UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16012,7 +16012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2ebe, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16030,7 +16030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29da, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16049,7 +16049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14f2, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16068,7 +16068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7762, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 122884, + .flow_sig_id = 122884UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16088,7 +16088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19e8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16105,7 +16105,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_110c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32772, + .flow_sig_id = 32772UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16123,7 +16123,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d48, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16141,7 +16141,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_446c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32836, + .flow_sig_id = 32836UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16160,7 +16160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0eac, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16178,7 +16178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09c0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16197,7 +16197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ad0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16216,7 +16216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15f4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49220, + .flow_sig_id = 49220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16236,7 +16236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39ec, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16254,7 +16254,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3100, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98308, + .flow_sig_id = 98308UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16273,7 +16273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0210, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16292,7 +16292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1d34, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98372, + .flow_sig_id = 98372UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16312,7 +16312,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2ea0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16331,7 +16331,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29c4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16351,7 +16351,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ad4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16371,7 +16371,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35e8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114756, + .flow_sig_id = 114756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16392,7 +16392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d80, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16410,7 +16410,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_54a4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163844, + .flow_sig_id = 163844UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16429,7 +16429,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29b4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16448,7 +16448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20c8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163908, + .flow_sig_id = 163908UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16468,7 +16468,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7244, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16487,7 +16487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d98, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180228, + .flow_sig_id = 180228UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16507,7 +16507,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e68, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16527,7 +16527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_598c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180292, + .flow_sig_id = 180292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16548,7 +16548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1248, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16567,7 +16567,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_74d8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229380, + .flow_sig_id = 229380UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16587,7 +16587,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_49a8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16607,7 +16607,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40cc, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229444, + .flow_sig_id = 229444UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16628,7 +16628,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b0c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16648,7 +16648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0220, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245764, + .flow_sig_id = 245764UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16669,7 +16669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1730, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16690,7 +16690,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7980, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245828, + .flow_sig_id = 245828UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16712,7 +16712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1db0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16729,7 +16729,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1494, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131076, + .flow_sig_id = 131076UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16747,7 +16747,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_70d0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16765,7 +16765,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4834, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131140, + .flow_sig_id = 131140UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16784,7 +16784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3db4, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16802,7 +16802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3498, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196612, + .flow_sig_id = 196612UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16821,7 +16821,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0988, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16840,7 +16840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00ec, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196676, + .flow_sig_id = 196676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16860,7 +16860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3f44, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16878,7 +16878,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_36a8, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393220, + .flow_sig_id = 393220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16897,7 +16897,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b58, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16916,7 +16916,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_02bc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393284, + .flow_sig_id = 393284UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16936,7 +16936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f48, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16955,7 +16955,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_56ac, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458756, + .flow_sig_id = 458756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16975,7 +16975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2b5c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16995,7 +16995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2280, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458820, + .flow_sig_id = 458820UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17016,7 +17016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4000, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17034,7 +17034,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5b64, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655364, + .flow_sig_id = 655364UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17053,7 +17053,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2c14, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17072,7 +17072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2778, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655428, + .flow_sig_id = 655428UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17092,7 +17092,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_18f8, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17111,7 +17111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13dc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720900, + .flow_sig_id = 720900UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17131,7 +17131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c18, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17151,7 +17151,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_477c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720964, + .flow_sig_id = 720964UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17172,7 +17172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1a88, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17191,7 +17191,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15ec, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917508, + .flow_sig_id = 917508UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17211,7 +17211,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e28, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17231,7 +17231,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_490c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917572, + .flow_sig_id = 917572UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17252,7 +17252,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a8c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17272,7 +17272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35f0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983044, + .flow_sig_id = 983044UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17293,7 +17293,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06e0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17314,7 +17314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01c4, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983108, + .flow_sig_id = 983108UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17336,7 +17336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1a08, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17353,7 +17353,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_12ec, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32772, + .flow_sig_id = 32772UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17371,7 +17371,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4ea8, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17389,7 +17389,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_478c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32836, + .flow_sig_id = 32836UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17408,7 +17408,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d4c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17426,7 +17426,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0a20, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17445,7 +17445,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1930, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17464,7 +17464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1614, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49220, + .flow_sig_id = 49220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17484,7 +17484,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a0c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17502,7 +17502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_32e0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98308, + .flow_sig_id = 98308UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17521,7 +17521,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01f0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17540,7 +17540,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ed4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98372, + .flow_sig_id = 98372UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17560,7 +17560,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2d40, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17579,7 +17579,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a24, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17599,7 +17599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3934, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17619,7 +17619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3608, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114756, + .flow_sig_id = 114756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17640,7 +17640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e60, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17658,7 +17658,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5744, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163844, + .flow_sig_id = 163844UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17677,7 +17677,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a54, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17696,7 +17696,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2328, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163908, + .flow_sig_id = 163908UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17716,7 +17716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_71a4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17735,7 +17735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e78, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180228, + .flow_sig_id = 180228UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17755,7 +17755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d88, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17775,7 +17775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5a6c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180292, + .flow_sig_id = 180292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17796,7 +17796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_11a8, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17815,7 +17815,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7738, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229380, + .flow_sig_id = 229380UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17835,7 +17835,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4a48, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17855,7 +17855,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_432c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229444, + .flow_sig_id = 229444UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17876,7 +17876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_08ec, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17896,7 +17896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01c0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245764, + .flow_sig_id = 245764UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17917,7 +17917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14d0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17938,7 +17938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7a60, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245828, + .flow_sig_id = 245828UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17960,7 +17960,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1d90, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17977,7 +17977,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14b4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131076, + .flow_sig_id = 131076UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17995,7 +17995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_70f0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18013,7 +18013,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4814, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131140, + .flow_sig_id = 131140UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18032,7 +18032,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d94, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18050,7 +18050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34b8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196612, + .flow_sig_id = 196612UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18069,7 +18069,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09a8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18088,7 +18088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00cc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196676, + .flow_sig_id = 196676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18108,7 +18108,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3f64, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18126,7 +18126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3688, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393220, + .flow_sig_id = 393220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18145,7 +18145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b78, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18164,7 +18164,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_029c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393284, + .flow_sig_id = 393284UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18184,7 +18184,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f68, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18203,7 +18203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_568c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458756, + .flow_sig_id = 458756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18223,7 +18223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2b7c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18243,7 +18243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_22a0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458820, + .flow_sig_id = 458820UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18264,7 +18264,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4020, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18282,7 +18282,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5b44, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655364, + .flow_sig_id = 655364UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18301,7 +18301,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2c34, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18320,7 +18320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2758, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655428, + .flow_sig_id = 655428UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18340,7 +18340,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_18d8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18359,7 +18359,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13fc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720900, + .flow_sig_id = 720900UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18379,7 +18379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c38, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18399,7 +18399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_475c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720964, + .flow_sig_id = 720964UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18420,7 +18420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1aa8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18439,7 +18439,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15cc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917508, + .flow_sig_id = 917508UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18459,7 +18459,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e08, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18479,7 +18479,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_492c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917572, + .flow_sig_id = 917572UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18500,7 +18500,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3aac, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18520,7 +18520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35d0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983044, + .flow_sig_id = 983044UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18541,7 +18541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06c0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18562,7 +18562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01e4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983108, + .flow_sig_id = 983108UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18584,7 +18584,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d32, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18598,7 +18598,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_54aa, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18613,7 +18613,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0686, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18627,7 +18627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_540e, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18642,7 +18642,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e3c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18657,7 +18657,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a20, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18673,7 +18673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46f0, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18689,7 +18689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52e4, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18706,7 +18706,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55e4, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18721,7 +18721,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_21f8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18737,7 +18737,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_75e8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18753,7 +18753,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_41fc, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18770,7 +18770,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d12, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18785,7 +18785,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_548a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18801,7 +18801,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3356, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18817,7 +18817,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ace, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18834,7 +18834,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1a9a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18850,7 +18850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d46, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18867,7 +18867,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2812, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18884,7 +18884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_338a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18902,7 +18902,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06e6, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18917,7 +18917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_546e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18933,7 +18933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46ee, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18949,7 +18949,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d22, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18966,7 +18966,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26e2, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18982,7 +18982,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_746a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18999,7 +18999,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1fa6, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19016,7 +19016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2d2e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19034,7 +19034,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4ef2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19049,7 +19049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_576a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19065,7 +19065,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_30b6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19081,7 +19081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_192e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19098,7 +19098,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_197a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19114,7 +19114,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4ea6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19131,7 +19131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bf2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19148,7 +19148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_306a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19166,7 +19166,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06c6, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19181,7 +19181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_544e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19197,7 +19197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46ce, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19213,7 +19213,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d02, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19230,7 +19230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26c2, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19246,7 +19246,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_744a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19263,7 +19263,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1f86, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19280,7 +19280,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2d0e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19298,7 +19298,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e1c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19314,7 +19314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a00, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19331,7 +19331,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46d0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19348,7 +19348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52c4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19366,7 +19366,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e10, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19383,7 +19383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5a04, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19401,7 +19401,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1f98, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19419,7 +19419,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_72f8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19438,7 +19438,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0a78, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19455,7 +19455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_166c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19473,7 +19473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_233c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19491,7 +19491,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0f20, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19510,7 +19510,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a7c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19528,7 +19528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3660, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19547,7 +19547,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4330, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19566,7 +19566,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2f24, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19586,7 +19586,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5584, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19602,7 +19602,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2198, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19619,7 +19619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7588, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19636,7 +19636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_419c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19654,7 +19654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7758, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19671,7 +19671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_43ac, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19689,7 +19689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c10, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19707,7 +19707,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1864, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19726,7 +19726,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_30c8, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19743,7 +19743,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cdc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19761,7 +19761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_50cc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19779,7 +19779,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d20, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19798,7 +19798,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_529c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19816,7 +19816,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ef0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19835,7 +19835,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_72e0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19854,7 +19854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ef4, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19874,7 +19874,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2dfc, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19890,7 +19890,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39e0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19907,7 +19907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4530, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19924,7 +19924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5124, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19942,7 +19942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4df0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19959,7 +19959,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59e4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19977,7 +19977,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c78, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19995,7 +19995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7118, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20014,7 +20014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0998, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20031,7 +20031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_158c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20049,7 +20049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20dc, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20067,7 +20067,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0cc0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20086,7 +20086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_299c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20104,7 +20104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3580, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20123,7 +20123,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40d0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20142,7 +20142,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2cc4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20162,7 +20162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55a4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20178,7 +20178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_21b8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20195,7 +20195,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_75a8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20212,7 +20212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_41bc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20230,7 +20230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7778, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20247,7 +20247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_438c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20265,7 +20265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c30, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20283,7 +20283,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1844, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20302,7 +20302,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_30e8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20319,7 +20319,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cfc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20337,7 +20337,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_50ec, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20355,7 +20355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d00, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20374,7 +20374,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52bc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20392,7 +20392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ed0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20411,7 +20411,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_72c0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20430,7 +20430,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ed4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20450,7 +20450,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3866, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20465,7 +20465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_381e, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20480,7 +20480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3860, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20496,7 +20496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0454, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20513,7 +20513,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3818, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20529,7 +20529,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_042c, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20546,7 +20546,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3846, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20562,7 +20562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_387e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20578,7 +20578,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ba6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20594,7 +20594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_385e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20610,7 +20610,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3840, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20627,7 +20627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0474, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20645,7 +20645,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3878, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20662,7 +20662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_044c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20680,7 +20680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ba0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20697,7 +20697,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0794, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20715,7 +20715,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3858, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20732,7 +20732,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_046c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index 31a94c14dc..8706e45f28 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 11:11:05 2021 */ +/* date: Thu Sep 9 12:11:08 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -48,7 +48,7 @@ #define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2323 #define ULP_THOR_CLASS_IDENT_LIST_SIZE 38 #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313 -#define ULP_THOR_CLASS_COND_LIST_SIZE 55 +#define ULP_THOR_CLASS_COND_LIST_SIZE 54 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 95205a2421..54bc032b0c 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Aug 25 16:41:37 2021 */ +/* date: Thu Sep 9 12:11:08 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -18,9 +18,9 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .num_tbls = 28, .start_tbl_idx = 0, .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 0, - .cond_nums = 1 } + .cond_nums = 0 } }, /* class_tid: 2, ingress */ [2] = { @@ -29,7 +29,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 28, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 } }, /* class_tid: 3, egress */ @@ -39,7 +39,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 52, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 0 } }, /* class_tid: 4, ingress */ @@ -49,7 +49,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 70, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 } }, /* class_tid: 5, egress */ @@ -59,7 +59,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 91, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 } } }; @@ -74,7 +74,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -96,7 +96,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 5, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -117,7 +117,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -136,7 +136,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -149,7 +149,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -176,7 +176,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -196,7 +196,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -209,7 +209,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 4, + .cond_start_idx = 3, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -228,7 +228,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 5, + .cond_start_idx = 4, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -240,7 +240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 6, + .cond_start_idx = 5, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -259,7 +259,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 7, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -277,7 +277,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 7, + .cond_start_idx = 6, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -307,7 +307,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -328,7 +328,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -349,7 +349,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -368,7 +368,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 6, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -381,7 +381,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 9, + .cond_start_idx = 8, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, @@ -398,7 +398,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 10, + .cond_start_idx = 9, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, @@ -415,7 +415,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 11, + .cond_start_idx = 10, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -443,7 +443,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 13, + .cond_start_idx = 12, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -473,7 +473,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -494,7 +494,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 14, + .cond_start_idx = 13, .cond_nums = 3 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -519,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, + .cond_start_idx = 16, .cond_nums = 3 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -544,7 +544,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 19, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -569,7 +569,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 22, + .cond_start_idx = 21, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -594,7 +594,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 23, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -619,7 +619,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 25, + .cond_start_idx = 24, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -644,7 +644,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 27, + .cond_start_idx = 26, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -670,7 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -691,7 +691,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -710,7 +710,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -723,7 +723,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -750,7 +750,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -770,7 +770,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -783,7 +783,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 30, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -802,7 +802,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, + .cond_start_idx = 30, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -815,7 +815,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -842,7 +842,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -862,7 +862,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -875,7 +875,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, + .cond_start_idx = 32, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -894,7 +894,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 33, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -906,7 +906,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 34, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -925,7 +925,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -943,7 +943,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -973,7 +973,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -994,7 +994,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -1016,7 +1016,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1035,7 +1035,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1048,7 +1048,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 36, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, @@ -1065,7 +1065,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1093,7 +1093,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1114,7 +1114,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1140,7 +1140,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1159,7 +1159,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -1172,7 +1172,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 40, + .cond_start_idx = 39, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1191,7 +1191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 41, + .cond_start_idx = 40, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1203,7 +1203,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 42, + .cond_start_idx = 41, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -1222,7 +1222,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -1240,7 +1240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1270,7 +1270,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1291,7 +1291,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -1312,7 +1312,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1331,7 +1331,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1344,7 +1344,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 44, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, @@ -1361,7 +1361,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 44, + .cond_start_idx = 43, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1389,7 +1389,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1419,7 +1419,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1440,7 +1440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1465,7 +1465,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 47, + .cond_start_idx = 46, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1490,7 +1490,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1517,7 +1517,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, @@ -1536,7 +1536,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1558,7 +1558,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1577,7 +1577,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1590,7 +1590,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1619,7 +1619,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1640,7 +1640,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -1657,7 +1657,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -1676,7 +1676,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -1696,7 +1696,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1716,7 +1716,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -1729,7 +1729,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 50, + .cond_start_idx = 49, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1748,7 +1748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 50, + .cond_start_idx = 49, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1761,7 +1761,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, @@ -1780,7 +1780,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1802,7 +1802,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1821,7 +1821,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1834,7 +1834,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1861,7 +1861,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1882,7 +1882,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1899,7 +1899,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1918,7 +1918,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, @@ -1938,7 +1938,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1960,7 +1960,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1979,7 +1979,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1992,7 +1992,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -2019,7 +2019,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2040,7 +2040,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, @@ -2057,7 +2057,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, @@ -2076,7 +2076,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2095,7 +2095,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF, @@ -2114,7 +2114,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2133,7 +2133,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -2146,7 +2146,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, @@ -2165,7 +2165,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2188,7 +2188,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0, @@ -2207,7 +2207,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, @@ -2227,7 +2227,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2246,7 +2246,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2265,7 +2265,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -2278,7 +2278,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -2306,7 +2306,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, @@ -2323,7 +2323,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -2350,7 +2350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2373,7 +2373,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2391,7 +2391,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -2406,11 +2406,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { }; struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { - /* cond_reject: thor, class_tid: 1 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH - }, /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */ { .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 07/19] net/bnxt: support inner IP header for GRE tunnel flows 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (5 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 06/19] net/bnxt: enable wildcard match for ingress flows Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 08/19] net/bnxt: get TruFlow version Venkat Duvvuru ` (11 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> This change allows adding IP header matches for GRE flows that does not specify outer IP header in the flow match pattern. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 7 ++++--- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 40da953f06..605c29223c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -1119,7 +1119,8 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, /* Set the ipv4 header bitmap and computed l3 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) { + ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6) || + ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV4); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1); inner_flag = 1; @@ -1245,7 +1246,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, /* Set the ipv6 header bitmap and computed l3 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) { + ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6) || + ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV6); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1); inner_flag = 1; @@ -2127,7 +2129,6 @@ ulp_rte_vxlan_decap_act_handler(const struct rte_flow_action *action_item BNXT_ULP_ACT_BIT_VXLAN_DECAP); /* Update computational field with tunnel decap info */ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN_DECAP, 1); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1); return BNXT_TF_RC_SUCCESS; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index d3bfb8c12d..7d1bc06a3e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -27,7 +27,7 @@ #define BNXT_ULP_PROTO_HDR_UDP_NUM 4 #define BNXT_ULP_PROTO_HDR_TCP_NUM 9 #define BNXT_ULP_PROTO_HDR_VXLAN_NUM 4 -#define BNXT_ULP_PROTO_HDR_GRE_NUM 6 +#define BNXT_ULP_PROTO_HDR_GRE_NUM 2 #define BNXT_ULP_PROTO_HDR_ICMP_NUM 5 #define BNXT_ULP_PROTO_HDR_MAX 128 #define BNXT_ULP_PROTO_HDR_ENCAP_MAX 64 -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 08/19] net/bnxt: get TruFlow version 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (6 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 07/19] net/bnxt: support inner IP header for GRE tunnel flows Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 09/19] net/bnxt: increase flow scale for Thor Venkat Duvvuru ` (10 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru From: Jay Ding <jay.ding@broadcom.com> Implement tf_get_version that returns TruFlow version numbers and CFA resources capbilities. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com> --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 15 ++-- drivers/net/bnxt/tf_core/tf_core.c | 29 ++++++++ drivers/net/bnxt/tf_core/tf_core.h | 75 ++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device.h | 50 ++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p4.c | 65 +++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p4.h | 79 +++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p58.c | 65 +++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p58.h | 87 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_msg.c | 35 ++++++++++ drivers/net/bnxt/tf_core/tf_msg.h | 19 ++++++ 10 files changed, 513 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 77981b5cdb..6d04e39e48 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1058,8 +1058,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 55 -#define HWRM_VERSION_STR "1.10.2.55" +#define HWRM_VERSION_RSVD 58 +#define HWRM_VERSION_STR "1.10.2.58" /**************** * hwrm_ver_get * @@ -45178,7 +45178,7 @@ struct hwrm_tf_version_get_input { uint64_t resp_addr; } __rte_packed; -/* hwrm_tf_version_get_output (size:128b/16B) */ +/* hwrm_tf_version_get_output (size:256b/32B) */ struct hwrm_tf_version_get_output { /* The specific error status for the command. */ uint16_t error_code; @@ -45195,7 +45195,14 @@ struct hwrm_tf_version_get_output { /* Version Update number. */ uint8_t update; /* unused. */ - uint8_t unused0[4]; + uint8_t unused0[5]; + /* + * This field is used to indicate device's capabilities and + * configurations. + */ + uint64_t dev_caps_cfg; + /* unused. */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 936102c804..86dfec0eb4 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1802,3 +1802,32 @@ int tf_get_session_info(struct tf *tfp, return 0; } + +int tf_get_version(struct tf *tfp, + struct tf_get_version_parms *parms) +{ + int rc; + struct tf_dev_info dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_WH && + parms->device_type != TF_DEVICE_TYPE_THOR && + parms->device_type != TF_DEVICE_TYPE_SR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + rc = tf_msg_get_version(parms->bp, &dev, parms); + if (rc) + return rc; + + return 0; +} diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index fb02c2b161..ba9881c69d 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2363,4 +2363,79 @@ struct tf_get_if_tbl_entry_parms { int tf_get_if_tbl_entry(struct tf *tfp, struct tf_get_if_tbl_entry_parms *parms); +/** + * tf_get_version parameters definition. + */ +struct tf_get_version_parms { + /** + * [in] device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] bp + * The pointer to the parent bp struct. This is only used for HWRM + * message passing within the portability layer. The type is struct + * bnxt. + */ + void *bp; + + /* [out] major + * + * Version Major number. + */ + uint8_t major; + + /* [out] minor + * + * Version Minor number. + */ + uint8_t minor; + + /* [out] update + * + * Version Update number. + */ + uint8_t update; + + /** + * [out] dev_ident_caps + * + * fw available identifier resource list + */ + uint32_t dev_ident_caps; + + /** + * [out] dev_tbl_caps + * + * fw available table resource list + */ + uint32_t dev_tbl_caps; + + /** + * [out] dev_tcam_caps + * + * fw available tcam resource list + */ + uint32_t dev_tcam_caps; + + /** + * [out] dev_em_caps + * + * fw available em resource list + */ + uint32_t dev_em_caps; +}; + +/** + * Get tf fw version + * + * Used to retrieve Truflow fw version information. + * + * Returns success or failure code. + */ +int tf_get_version(struct tf *tfp, + struct tf_get_version_parms *parms); #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 9b0c037db0..88bd4515ff 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -6,6 +6,7 @@ #ifndef _TF_DEVICE_H_ #define _TF_DEVICE_H_ +#include "cfa_resource_types.h" #include "tf_core.h" #include "tf_identifier.h" #include "tf_tbl.h" @@ -36,6 +37,21 @@ struct tf_dev_info { const struct tf_dev_ops *ops; }; +/** + * This structure can be used to translate the CFA resource type to TF type. + */ +struct tf_hcapi_resource_map { + /** + * Truflow module type associated with this resource type. + */ + enum tf_module_type module_type; + + /** + * Bitmap of TF sub-type for the element. + */ + uint32_t type_caps; +}; + /** * @page device Device * @@ -1037,6 +1053,34 @@ struct tf_dev_ops { */ uint64_t (*tf_dev_cfa_key_hash)(uint64_t *key_data, uint16_t bitlen); + + /** + * Translate the CFA resource type to Truflow type + * + * [in] hcapi_types + * CFA resource type bitmap + * + * [out] ident_types + * Pointer to identifier type bitmap + * + * [out] tcam_types + * Pointer to tcam type bitmap + * + * [out] tbl_types + * Pointer to table type bitmap + * + * [out] em_types + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_map_hcapi_caps)(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps); }; /** @@ -1047,4 +1091,10 @@ extern const struct tf_dev_ops tf_dev_ops_p4; extern const struct tf_dev_ops tf_dev_ops_p58_init; extern const struct tf_dev_ops tf_dev_ops_p58; +/** + * Supported device resource type mapping structures + */ +extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1]; +extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1]; + #endif /* _TF_DEVICE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 826cd0cdbc..8089785b82 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -271,6 +271,67 @@ static bool tf_dev_p4_is_sram_managed(struct tf *tfp __rte_unused, { return false; } + +/** + * Device specific function that maps the hcapi resource types + * to Truflow type. + * + * [in] hcapi_caps + * CFA resource type bitmap + * + * [out] ident_caps + * Pointer to identifier type bitmap + * + * [out] tcam_caps + * Pointer to tcam type bitmap + * + * [out] tbl_caps + * Pointer to table type bitmap + * + * [out] em_caps + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p4_map_hcapi_caps(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps) +{ + uint32_t i; + + *ident_caps = 0; + *tcam_caps = 0; + *tbl_caps = 0; + *em_caps = 0; + + for (i = 0; i <= CFA_RESOURCE_TYPE_P4_LAST; i++) { + if (hcapi_caps & 1ULL << i) { + switch (tf_hcapi_res_map_p4[i].module_type) { + case TF_MODULE_TYPE_IDENTIFIER: + *ident_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_TABLE: + *tbl_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_TCAM: + *tcam_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_EM: + *em_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + default: + return -EINVAL; + } + } + } + + return 0; +} + /** * Truflow P4 device specific functions */ @@ -321,6 +382,7 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = NULL, + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps }; /** @@ -382,5 +444,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = tf_dev_p4_word_align, - .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash + .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index c1357913f1..e84c0f9e83 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -157,4 +157,83 @@ struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = { TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK }, }; + +const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { + [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW + }, + [CFA_RESOURCE_TYPE_P4_PROF_FUNC] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC + }, + [CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF + }, + [CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW + }, + [CFA_RESOURCE_TYPE_P4_PROF_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM + }, + [CFA_RESOURCE_TYPE_P4_WC_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM + }, + [CFA_RESOURCE_TYPE_P4_SP_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_SP_TCAM + }, + [CFA_RESOURCE_TYPE_P4_NAT_IPV4] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_MODIFY_IPV4 + }, + [CFA_RESOURCE_TYPE_P4_METER_PROF] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF + }, + [CFA_RESOURCE_TYPE_P4_METER] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST + }, + [CFA_RESOURCE_TYPE_P4_MIRROR] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG + }, + [CFA_RESOURCE_TYPE_P4_FULL_ACTION] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_FULL_ACT_RECORD + }, + [CFA_RESOURCE_TYPE_P4_MCG] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MCAST_GROUPS + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_8B + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_16B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_16B + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_64B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_64B + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4 + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6 + }, + [CFA_RESOURCE_TYPE_P4_COUNTER_64B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64 + }, + [CFA_RESOURCE_TYPE_P4_EM_REC] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD + }, + [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_TBL_SCOPE + }, +}; + #endif /* _TF_DEVICE_P4_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 47d7836a58..03e72b90f5 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -45,6 +45,7 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { [CFA_RESOURCE_TYPE_P58_WC_FKB] = "wc_fkb ", [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = "veb ", [CFA_RESOURCE_TYPE_P58_METADATA] = "metadata", + [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = "meter_dc", }; /** @@ -336,6 +337,66 @@ static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused, return 0; } +/** + * Device specific function that maps the hcapi resource types + * to Truflow type. + * + * [in] hcapi_caps + * CFA resource type bitmap + * + * [out] ident_caps + * Pointer to identifier type bitmap + * + * [out] tcam_caps + * Pointer to tcam type bitmap + * + * [out] tbl_caps + * Pointer to table type bitmap + * + * [out] em_caps + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_map_hcapi_caps(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps) +{ + uint32_t i; + + *ident_caps = 0; + *tcam_caps = 0; + *tbl_caps = 0; + *em_caps = 0; + + for (i = 0; i <= CFA_RESOURCE_TYPE_P58_LAST; i++) { + if (hcapi_caps & 1ULL << i) { + switch (tf_hcapi_res_map_p58[i].module_type) { + case TF_MODULE_TYPE_IDENTIFIER: + *ident_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_TABLE: + *tbl_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_TCAM: + *tcam_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_EM: + *em_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + default: + return -EINVAL; + } + } + } + + return 0; +} + /** * Truflow P58 device specific functions */ @@ -386,6 +447,7 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = NULL, + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps }; /** @@ -448,5 +510,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = tf_dev_p58_word_align, - .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash + .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index 3e8759f2df..f6e66936f3 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -209,4 +209,91 @@ struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = { TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_INTERVAL_CFG }, }; + +const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { + [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW + }, + [CFA_RESOURCE_TYPE_P58_PROF_FUNC] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC + }, + [CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF + }, + [CFA_RESOURCE_TYPE_P58_EM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW + }, + [CFA_RESOURCE_TYPE_P58_PROF_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM + }, + [CFA_RESOURCE_TYPE_P58_WC_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM + }, + [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_VEB_TCAM + }, + [CFA_RESOURCE_TYPE_P58_EM_FKB] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_EM_FKB + }, + [CFA_RESOURCE_TYPE_P58_WC_FKB] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_WC_FKB + }, + [CFA_RESOURCE_TYPE_P58_METER_PROF] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF + }, + [CFA_RESOURCE_TYPE_P58_METER] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST + }, + [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_DROP_CNT + }, + [CFA_RESOURCE_TYPE_P58_MIRROR] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG + }, + [CFA_RESOURCE_TYPE_P58_METADATA] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METADATA + }, + /* Resources in bank 1 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_FULL_ACT_RECORD + | 1 << TF_TBL_TYPE_COMPACT_ACT_RECORD + }, + /* Resources in bank 2 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_ACT_ENCAP_8B | + 1 << TF_TBL_TYPE_ACT_ENCAP_16B | + 1 << TF_TBL_TYPE_ACT_ENCAP_32B | + 1 << TF_TBL_TYPE_ACT_ENCAP_64B | + 1 << TF_TBL_TYPE_ACT_MODIFY_8B | + 1 << TF_TBL_TYPE_ACT_MODIFY_16B | + 1 << TF_TBL_TYPE_ACT_MODIFY_32B | + 1 << TF_TBL_TYPE_ACT_MODIFY_64B + + }, + /* Resources in bank 0 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_ACT_SP_SMAC | + 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4 | + 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6 + }, + /* Resources in bank 3 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64 + }, + [CFA_RESOURCE_TYPE_P58_EM_REC] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD + }, +}; #endif /* _TF_DEVICE_P58_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index ea6e2af7ce..25bf026658 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -2306,3 +2306,38 @@ tf_msg_set_if_tbl_entry(struct tf *tfp, return 0; } + +int +tf_msg_get_version(struct bnxt *bp, + struct tf_dev_info *dev, + struct tf_get_version_parms *params) + +{ + int rc; + struct hwrm_tf_version_get_input req = { 0 }; + struct hwrm_tf_version_get_output resp = { 0 }; + struct tfp_send_msg_parms parms = { 0 }; + + /* Populate the request */ + parms.tf_type = HWRM_TF_VERSION_GET, + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(bp, + &parms); + + params->major = resp.major; + params->minor = resp.minor; + params->update = resp.update; + + dev->ops->tf_dev_map_hcapi_caps(resp.dev_caps_cfg, + ¶ms->dev_ident_caps, + ¶ms->dev_tcam_caps, + ¶ms->dev_tbl_caps, + ¶ms->dev_em_caps); + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 718bc2f3b2..08d20cdd7a 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -738,4 +738,23 @@ int tf_msg_set_if_tbl_entry(struct tf *tfp, int tf_msg_get_if_tbl_entry(struct tf *tfp, struct tf_if_tbl_get_parms *params); +/** + * Send get version request to the firmware. + * + * [in] bp + * Pointer to bnxt handle + * + * [in] dev + * Pointer to the associated device + * + * [in/out] parms + * Pointer to the version info parameter + * + * Returns: + * 0 on Success else internal Truflow error + */ +int +tf_msg_get_version(struct bnxt *bp, + struct tf_dev_info *dev, + struct tf_get_version_parms *parms); #endif /* _TF_MSG_H_ */ -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 09/19] net/bnxt: increase flow scale for Thor 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (7 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 08/19] net/bnxt: get TruFlow version Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 10/19] net/bnxt: remove accumulation of stats devargs argument Venkat Duvvuru ` (9 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Shahaji Bhosle, Kishore Padmanabha, Venkat Duvvuru From: Shahaji Bhosle <sbhosle@broadcom.com> * Updated defines and data types to allow 256 VFRs. * Increased the encap record cache to support 256 to 4K entries. So VxLAN connections can be scaled to 4K entries. Signed-off-by: Shahaji Bhosle <sbhosle@broadcom.com> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/bnxt.h | 6 +++++- drivers/net/bnxt/bnxt_cpr.c | 2 +- drivers/net/bnxt/bnxt_ethdev.c | 18 +++++++++--------- drivers/net/bnxt/bnxt_reps.c | 3 +-- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 2 +- .../generic_templates/ulp_template_db_tbl.c | 8 ++++---- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 6 +++--- 7 files changed, 24 insertions(+), 21 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index c65e360446..5c064fd119 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -240,7 +240,11 @@ struct bnxt_parent_info { struct bnxt_pf_info { #define BNXT_FIRST_PF_FID 1 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) -#define BNXT_MAX_VF_REPS 64 +#define BNXT_MAX_VF_REPS_WH 64 +#define BNXT_MAX_VF_REPS_TH 256 +#define BNXT_MAX_VF_REPS(bp) \ + (BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_TH : \ + BNXT_MAX_VF_REPS_WH) #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) #define BNXT_FIRST_VF_FID 128 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) diff --git a/drivers/net/bnxt/bnxt_cpr.c b/drivers/net/bnxt/bnxt_cpr.c index 63ff02a198..6bb70d516e 100644 --- a/drivers/net/bnxt/bnxt_cpr.c +++ b/drivers/net/bnxt/bnxt_cpr.c @@ -74,7 +74,7 @@ bnxt_process_default_vnic_change(struct bnxt *bp, BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT; PMD_DRV_LOG(INFO, "async event received vf_id 0x%x\n", vf_fid); - for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) { + for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS(bp); vf_id++) { eth_dev = bp->rep_info[vf_id].vfr_eth_dev; if (!eth_dev) continue; diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index bf034db336..8c72ab8fd1 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1179,7 +1179,7 @@ void bnxt_print_link_info(struct rte_eth_dev *eth_dev) struct rte_eth_link *link = ð_dev->data->dev_link; if (link->link_status) - PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", + PMD_DRV_LOG(DEBUG, "Port %d Link Up - speed %u Mbps - %s\n", eth_dev->data->port_id, (uint32_t)link->link_speed, (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? @@ -6034,7 +6034,7 @@ static int bnxt_init_rep_info(struct bnxt *bp) return 0; bp->rep_info = rte_zmalloc("bnxt_rep_info", - sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, + sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS(bp), 0); if (!bp->rep_info) { PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); @@ -6076,7 +6076,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, { struct rte_eth_dev *vf_rep_eth_dev; char name[RTE_ETH_NAME_MAX_LEN]; - struct bnxt *backing_bp; + struct bnxt *backing_bp = backing_eth_dev->data->dev_private; + uint16_t max_vf_reps = BNXT_MAX_VF_REPS(backing_bp); + uint16_t num_rep; int i, ret = 0; struct rte_kvargs *kvlist = NULL; @@ -6089,9 +6091,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, return -ENOTSUP; } num_rep = eth_da->nb_representor_ports; - if (num_rep > BNXT_MAX_VF_REPS) { + if (num_rep > max_vf_reps) { PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", - num_rep, BNXT_MAX_VF_REPS); + num_rep, max_vf_reps); return -EINVAL; } @@ -6102,8 +6104,6 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, return -EINVAL; } - backing_bp = backing_eth_dev->data->dev_private; - if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { PMD_DRV_LOG(ERR, "Not a PF or trusted VF. No Representor support\n"); @@ -6123,9 +6123,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, .parent_dev = backing_eth_dev }; - if (representor.vf_id >= BNXT_MAX_VF_REPS) { + if (representor.vf_id >= max_vf_reps) { PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", - representor.vf_id, BNXT_MAX_VF_REPS); + representor.vf_id, max_vf_reps); continue; } diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c index b7e88e013a..988f5a33a7 100644 --- a/drivers/net/bnxt/bnxt_reps.c +++ b/drivers/net/bnxt/bnxt_reps.c @@ -210,7 +210,6 @@ int bnxt_representor_init(struct rte_eth_dev *eth_dev, void *params) eth_dev->data->dev_link.link_status = link->link_status; eth_dev->data->dev_link.link_autoneg = link->link_autoneg; - PMD_DRV_LOG(INFO, "calling bnxt_print_link_info\n"); bnxt_print_link_info(eth_dev); PMD_DRV_LOG(INFO, @@ -821,7 +820,7 @@ int bnxt_rep_stop_all(struct bnxt *bp) if (!bp->rep_info) return 0; - for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) { + for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS(bp); vf_id++) { rep_eth_dev = bp->rep_info[vf_id].vfr_eth_dev; if (!rep_eth_dev) continue; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 68f1470c61..960a5a0c93 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -262,7 +262,7 @@ bnxt_ulp_cntxt_ptr2_ulp_flags_get(struct bnxt_ulp_context *ulp_ctx, uint32_t *flags); int32_t -bnxt_ulp_get_df_rule_info(uint8_t port_id, struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_get_df_rule_info(uint16_t port_id, struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_df_rule_info *info); struct bnxt_ulp_vfr_rule_info* diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 5383e2cd70..e43e341927 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 11:11:05 2021 */ +/* date: Thu Sep 16 11:49:55 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -164,12 +164,12 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE", - .result_num_entries = 256, + .name = "EGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE", + .result_num_entries = 4096, .result_num_bytes = 6, .key_num_bytes = 17, .num_buckets = 8, - .hash_tbl_entries = 1024, + .hash_tbl_entries = 16384, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index d8336d164e..01233c0f5e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -441,7 +441,7 @@ void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global) { struct bnxt_ulp_df_rule_info *info; - uint8_t port_id; + uint16_t port_id; if (!BNXT_TRUFLOW_EN(bp) || BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev)) @@ -505,7 +505,7 @@ int32_t bnxt_ulp_create_df_rules(struct bnxt *bp) { struct bnxt_ulp_df_rule_info *info; - uint8_t port_id; + uint16_t port_id; int rc = 0; if (!BNXT_TRUFLOW_EN(bp) || @@ -562,7 +562,7 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev) struct rte_eth_dev *parent_dev = vfr->parent_dev; struct bnxt *bp = parent_dev->data->dev_private; uint16_t vfr_port_id = vfr_ethdev->data->port_id; - uint8_t port_id; + uint16_t port_id; int rc; if (!bp || !BNXT_TRUFLOW_EN(bp)) -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 10/19] net/bnxt: remove accumulation of stats devargs argument 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (8 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 09/19] net/bnxt: increase flow scale for Thor Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 11/19] net/bnxt: fix clang compiler warnings Venkat Duvvuru ` (8 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> The accumulation of flow counters is not determined by the application device arguments instead it is dictated by the platform capabilities whether to do software based accumulation or not. Change-Id: I7275a0ed6ab089358e0a95f43d6291ec65ebe030 Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> --- drivers/net/bnxt/bnxt.h | 3 -- drivers/net/bnxt/bnxt_ethdev.c | 53 ---------------------------- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 8 ----- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 1 - drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 12 +++---- 5 files changed, 4 insertions(+), 73 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 5c064fd119..5cc4a5afae 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -718,11 +718,8 @@ struct bnxt { uint32_t flags2; #define BNXT_FLAGS2_PTP_TIMESYNC_ENABLED BIT(0) #define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1) -#define BNXT_FLAGS2_ACCUM_STATS_EN BIT(2) #define BNXT_P5_PTP_TIMESYNC_ENABLED(bp) \ ((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED) -#define BNXT_ACCUM_STATS_EN(bp) \ - ((bp)->flags2 & BNXT_FLAGS2_ACCUM_STATS_EN) uint16_t chip_num; #define CHIP_NUM_58818 0xd818 diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 8c72ab8fd1..070f69d8e9 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -87,7 +87,6 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { { .vendor_id = 0, /* sentinel */ }, }; -#define BNXT_DEVARG_ACCUM_STATS "accum-stats" #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" #define BNXT_DEVARG_REPRESENTOR "representor" @@ -101,7 +100,6 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { static const char *const bnxt_dev_args[] = { BNXT_DEVARG_REPRESENTOR, - BNXT_DEVARG_ACCUM_STATS, BNXT_DEVARG_FLOW_XSTAT, BNXT_DEVARG_MAX_NUM_KFLOWS, BNXT_DEVARG_REP_BASED_PF, @@ -114,12 +112,6 @@ static const char *const bnxt_dev_args[] = { NULL }; -/* - * accum-stats == false to disable flow counter accumulation - * accum-stats == true to enable flow counter accumulation - */ -#define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1) - /* * app-id = an non-negative 8-bit number */ @@ -5299,45 +5291,6 @@ static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) return 0; } -static int -bnxt_parse_devarg_accum_stats(__rte_unused const char *key, - const char *value, void *opaque_arg) -{ - struct bnxt *bp = opaque_arg; - unsigned long accum_stats; - char *end = NULL; - - if (!value || !opaque_arg) { - PMD_DRV_LOG(ERR, - "Invalid parameter passed to accum-stats devargs.\n"); - return -EINVAL; - } - - accum_stats = strtoul(value, &end, 10); - if (end == NULL || *end != '\0' || - (accum_stats == ULONG_MAX && errno == ERANGE)) { - PMD_DRV_LOG(ERR, - "Invalid parameter passed to accum-stats devargs.\n"); - return -EINVAL; - } - - if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) { - PMD_DRV_LOG(ERR, - "Invalid value passed to accum-stats devargs.\n"); - return -EINVAL; - } - - if (accum_stats) { - bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN; - PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n"); - } else { - bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN; - PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n"); - } - - return 0; -} - static int bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, const char *value, void *opaque_arg) @@ -5690,12 +5643,6 @@ bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) if (ret) goto err; - /* - * Handler for "accum-stats" devarg. - * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1" - */ - rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS, - bnxt_parse_devarg_accum_stats, bp); /* * Handler for "max_num_kflows" devarg. * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 2ac1a8625f..7deacd1f3e 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1490,14 +1490,6 @@ bnxt_ulp_port_init(struct bnxt *bp) goto jump_to_error; } - /* set the accumulation of the stats */ - if (BNXT_ACCUM_STATS_EN(bp)) - bp->ulp_ctx->cfg_data->accum_stats = true; - - BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init, accum_stats:%d\n", - bp->eth_dev->data->port_id, - bp->ulp_ctx->cfg_data->accum_stats); - /* set the unicast mode */ if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(bp->ulp_ctx, &ulp_flags)) { BNXT_TF_DBG(ERR, "Error in getting ULP context flags\n"); diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 960a5a0c93..17c6898196 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -92,7 +92,6 @@ struct bnxt_ulp_data { #define BNXT_ULP_TUN_ENTRY_INVALID -1 #define BNXT_ULP_MAX_TUN_CACHE_ENTRIES 16 struct bnxt_tun_cache_entry tun_tbl[BNXT_ULP_MAX_TUN_CACHE_ENTRIES]; - bool accum_stats; uint8_t app_id; uint8_t num_shared_clients; struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES]; diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c index d6b4f93d31..92243083b5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c @@ -396,21 +396,17 @@ static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt, return rc; } - /* TBD - Get PKT/BYTE COUNT SHIFT/MASK from Template */ + /* PKT/BYTE COUNT SHIFT/MASK are device specific */ sw_cntr_indx = hw_cntr_id - fc_info->shadow_hw_tbl[dir].start_idx; sw_acc_tbl_entry = &fc_info->sw_acc_tbl[dir][sw_cntr_indx]; + /* Some dpdk applications may accumulate the flow counters while some * may not. In cases where the application is accumulating the counters * the PMD need not do the accumulation itself and viceversa to report * the correct flow counters. */ - if (ctxt->cfg_data->accum_stats) { - sw_acc_tbl_entry->pkt_count += FLOW_CNTR_PKTS(stats, dparms); - sw_acc_tbl_entry->byte_count += FLOW_CNTR_BYTES(stats, dparms); - } else { - sw_acc_tbl_entry->pkt_count = FLOW_CNTR_PKTS(stats, dparms); - sw_acc_tbl_entry->byte_count = FLOW_CNTR_BYTES(stats, dparms); - } + sw_acc_tbl_entry->pkt_count += FLOW_CNTR_PKTS(stats, dparms); + sw_acc_tbl_entry->byte_count += FLOW_CNTR_BYTES(stats, dparms); /* Update the parent counters if it is child flow */ if (sw_acc_tbl_entry->pc_flow_idx & FLOW_CNTR_PC_FLOW_VALID) { -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 11/19] net/bnxt: fix clang compiler warnings 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (9 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 10/19] net/bnxt: remove accumulation of stats devargs argument Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 12/19] net/bnxt: updated the log messages Venkat Duvvuru ` (7 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Shahaji Bhosle, Venkat Duvvuru From: Shahaji Bhosle <sbhosle@broadcom.com> Typecast flow_item type, action_item type and the ENUMs to uint32_t before comparing. Fixes: 53a0d4f7663 ("net/bnxt: support flow API item parsing") Signed-off-by: Shahaji Bhosle <sbhosle@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 605c29223c..d21c088d59 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -137,10 +137,10 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[], /* Parse all the items in the pattern */ while (item && item->type != RTE_FLOW_ITEM_TYPE_END) { - if (item->type >= (uint32_t) + if (item->type >= (typeof(item->type)) BNXT_RTE_FLOW_ITEM_TYPE_END) { if (item->type >= - (uint32_t)BNXT_RTE_FLOW_ITEM_TYPE_LAST) + (typeof(item->type))BNXT_RTE_FLOW_ITEM_TYPE_LAST) goto hdr_parser_error; /* get the header information */ hdr_info = &ulp_vendor_hdr_info[item->type - @@ -186,9 +186,9 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[], /* Parse all the items in the pattern */ while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) { if (action_item->type >= - (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_END) { + (typeof(action_item->type))BNXT_RTE_FLOW_ACTION_TYPE_END) { if (action_item->type >= - (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_LAST) + (typeof(action_item->type))BNXT_RTE_FLOW_ACTION_TYPE_LAST) goto act_parser_error; /* get the header information from bnxt actinfo table */ hdr_info = &ulp_vendor_act_info[action_item->type - -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 12/19] net/bnxt: updated the log messages 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (10 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 11/19] net/bnxt: fix clang compiler warnings Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 13/19] net/bnxt: add support for socket redirect feature Venkat Duvvuru ` (6 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Some of the error level log messages are made debug level messages. When Truflow is not enabled then Truflow init error messages are moved to debug level instead. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 24 ++++++++++++------------ drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 7deacd1f3e..21f71d6445 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1396,16 +1396,16 @@ bnxt_ulp_port_init(struct bnxt *bp) uint32_t ulp_flags; int32_t rc = 0; - if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { - BNXT_TF_DBG(ERR, - "Skip ulp init for port: %d, not a TVF or PF\n", + if (!BNXT_TRUFLOW_EN(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ulp init for port: %d, TF is not enabled\n", bp->eth_dev->data->port_id); return rc; } - if (!BNXT_TRUFLOW_EN(bp)) { - BNXT_TF_DBG(ERR, - "Skip ulp init for port: %d, truflow is not enabled\n", + if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ulp init for port: %d, not a TVF or PF\n", bp->eth_dev->data->port_id); return rc; } @@ -1520,16 +1520,16 @@ bnxt_ulp_port_deinit(struct bnxt *bp) struct rte_pci_device *pci_dev; struct rte_pci_addr *pci_addr; - if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { - BNXT_TF_DBG(ERR, - "Skip ULP deinit port:%d, not a TVF or PF\n", + if (!BNXT_TRUFLOW_EN(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ULP deinit for port:%d, TF is not enabled\n", bp->eth_dev->data->port_id); return; } - if (!BNXT_TRUFLOW_EN(bp)) { - BNXT_TF_DBG(ERR, - "Skip ULP deinit for port:%d, truflow is not enabled\n", + if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ULP deinit port:%d, not a TVF or PF\n", bp->eth_dev->data->port_id); return; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index 01233c0f5e..8790d7ac0d 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -323,7 +323,7 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev, ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); if (!ulp_ctx) { BNXT_TF_DBG(ERR, - "ULP context is not initialized. Failed to create dflt flow.\n"); + "ULP is not init'ed. Fail to create dflt flow.\n"); return -EINVAL; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c index 79dc869e64..9968311c44 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c @@ -470,7 +470,7 @@ ulp_flow_db_init(struct bnxt_ulp_context *ulp_ctxt) } /* All good so return. */ - BNXT_TF_DBG(INFO, "FlowDB initialized with %d flows.\n", + BNXT_TF_DBG(DEBUG, "FlowDB initialized with %d flows.\n", flow_tbl->num_flows); return 0; error_free: diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c index 271520e1d3..9dffaef73b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c @@ -116,7 +116,7 @@ ulp_mark_db_init(struct bnxt_ulp_context *ctxt) mark_tbl->gfid_mask = (mark_tbl->gfid_num_entries / 2) - 1; mark_tbl->gfid_type_bit = (mark_tbl->gfid_num_entries / 2); - BNXT_TF_DBG(DEBUG, "GFID Max = 0x%08x\nGFID MASK = 0x%08x\n", + BNXT_TF_DBG(DEBUG, "GFID Max = 0x%08x GFID MASK = 0x%08x\n", mark_tbl->gfid_num_entries - 1, mark_tbl->gfid_mask); -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 13/19] net/bnxt: add support for socket redirect feature 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (11 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 12/19] net/bnxt: updated the log messages Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 14/19] net/bnxt: delete the VF pair before VF representor alloc Venkat Duvvuru ` (5 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Added support for socket redirect feature. This feature allows to ignore the incoming interface and use other fields in the packet to identify the flow and forward. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 2 + drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 23 +- .../generic_templates/ulp_template_db_enum.h | 71 +- .../generic_templates/ulp_template_db_tbl.c | 3917 +++++++++++++---- .../ulp_template_db_thor_act.c | 150 +- .../ulp_template_db_thor_class.c | 660 +-- .../ulp_template_db_wh_plus_act.c | 242 +- .../ulp_template_db_wh_plus_class.c | 222 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 5 + 9 files changed, 3699 insertions(+), 1593 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 21f71d6445..14be079eaa 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -340,6 +340,8 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, if (BNXT_MULTIROOT_EN(bp)) ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_APP_SOCKET_DIRECT; + BNXT_TF_DBG(DEBUG, + "Socket Direct feature is enabled"); } } if (!found) { diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 272195f6a2..55885d1b8c 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -133,8 +133,27 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, } /* Update the socket direct flag */ - if (ULP_SOCKET_DIRECT_IS_ENABLED(ulp_flags)) - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT, 1); + if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_SVIF_IGNORE)) { + uint32_t ifindex; + uint16_t vport; + + /* Get the port db ifindex */ + if (ulp_port_db_dev_port_to_ulp_index(params->ulp_ctx, + params->port_id, + &ifindex)) { + BNXT_TF_DBG(ERR, "Invalid port id %u\n", + params->port_id); + return; + } + /* Update the phy port of the other interface */ + if (ulp_port_db_vport_get(params->ulp_ctx, ifindex, &vport)) { + BNXT_TF_DBG(ERR, "Invalid port if index %u\n", ifindex); + return; + } + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT_VPORT, + (vport == 1) ? 2 : 1); + } } /* Function to create the rte flow. */ diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index 8706e45f28..c01ae1601d 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,15 +3,15 @@ * All rights reserved. */ -/* date: Thu Sep 9 12:11:08 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ -#define BNXT_ULP_REGFILE_MAX_SZ 42 +#define BNXT_ULP_REGFILE_MAX_SZ 46 #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 -#define BNXT_ULP_GEN_TBL_MAX_SZ 16 +#define BNXT_ULP_GEN_TBL_MAX_SZ 18 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 65536 #define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 993 #define BNXT_ULP_CLASS_HID_LOW_PRIME 6701 @@ -26,11 +26,11 @@ #define BNXT_ULP_ACT_HID_SHFTR 27 #define BNXT_ULP_ACT_HID_SHFTL 26 #define BNXT_ULP_ACT_HID_MASK 2047 -#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8 -#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110 -#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50 -#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 277 -#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8 +#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 16 +#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 132 +#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 140 +#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 409 +#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 12 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 @@ -114,7 +114,8 @@ enum bnxt_ulp_hdr_bit { BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000, BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000, BNXT_ULP_HDR_BIT_F2 = 0x0000000000080000, - BNXT_ULP_HDR_BIT_LAST = 0x0000000000100000 + BNXT_ULP_HDR_BIT_SVIF_IGNORE = 0x0000000000100000, + BNXT_ULP_HDR_BIT_LAST = 0x0000000000200000 }; enum bnxt_ulp_accept_opc { @@ -212,7 +213,8 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72, BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73, BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74, - BNXT_ULP_CF_IDX_LAST = 75 + BNXT_ULP_CF_IDX_SOCKET_DIRECT_VPORT = 75, + BNXT_ULP_CF_IDX_LAST = 76 }; enum bnxt_ulp_cond_list_opc { @@ -427,21 +429,31 @@ enum bnxt_ulp_glb_rf_idx { BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 37, BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 38, BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 39, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 40, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 41, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 42, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 43, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 44, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 45, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 46, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 47, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 48, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 49, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 50, - BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 51, - BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 52, - BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 53, - BNXT_ULP_GLB_RF_IDX_LAST = 54 + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3 = 40, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 41, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 42, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 43, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 44, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 45, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 46, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 47, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3 = 48, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4 = 49, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5 = 50, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6 = 51, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7 = 52, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8 = 53, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9 = 54, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10 = 55, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 56, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 57, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 58, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 59, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2 = 60, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 61, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 62, + BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 63, + BNXT_ULP_GLB_RF_IDX_LAST = 64 }; enum bnxt_ulp_hdr_type { @@ -555,7 +567,11 @@ enum bnxt_ulp_rf_idx { BNXT_ULP_RF_IDX_PHY_PORT = 39, BNXT_ULP_RF_IDX_METADATA_PROF = 40, BNXT_ULP_RF_IDX_MODIFY_PTR = 41, - BNXT_ULP_RF_IDX_LAST = 42 + BNXT_ULP_RF_IDX_SOCK_DIR_SVIF = 42, + BNXT_ULP_RF_IDX_SOCK_DIR_PARIF = 43, + BNXT_ULP_RF_IDX_SOCK_DIR_ACT_PTR = 44, + BNXT_ULP_RF_IDX_SOCK_DIR_PARENT_MAC = 45, + BNXT_ULP_RF_IDX_LAST = 46 }; enum bnxt_ulp_shared_session { @@ -627,7 +643,8 @@ enum bnxt_ulp_resource_sub_type { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE = 6, - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7 + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE = 8 }; enum bnxt_ulp_act_prop_sz { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index e43e341927..d5aea4d456 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 16 11:49:55 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -171,6 +171,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { .num_buckets = 8, .hash_tbl_entries = 16384, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GEN_TABLE_SOCKET_DIRECT_CACHE", + .result_num_entries = 16, + .result_num_bytes = 14, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GEN_TABLE_SOCKET_DIRECT_CACHE", + .result_num_entries = 16, + .result_num_bytes = 14, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; @@ -371,6 +391,33 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY | + BNXT_ULP_APP_CAP_SOCKET_DIRECT + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY } }; @@ -439,6 +486,70 @@ struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 1024 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 128 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 1024 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 128 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 1024 } }; @@ -472,6 +583,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -560,6 +679,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -624,14 +751,6 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, - .direction = TF_DIR_RX - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX @@ -672,6 +791,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -760,6 +887,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -824,14 +959,6 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, - .direction = TF_DIR_RX - }, - { - .app_id = 2, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX @@ -843,509 +970,717 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, .direction = TF_DIR_RX - } -}; - -/* List of global tf resources required to be reserved per app/device */ -struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { + }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX + }, + { + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_METADATA, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0, - .direction = TF_DIR_TX + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, .direction = TF_DIR_RX }, { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, + .direction = TF_DIR_RX + }, + { + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, + .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX + } +}; + +/* List of global tf resources required to be reserved per app/device */ +struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { + { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1353,7 +1688,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1361,7 +1696,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, @@ -1369,7 +1704,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1377,7 +1712,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1385,7 +1720,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1393,7 +1728,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1401,7 +1736,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1409,7 +1744,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, @@ -1417,7 +1752,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1425,7 +1760,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1433,7 +1768,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1441,7 +1776,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, @@ -1449,7 +1784,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1457,7 +1792,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1465,7 +1800,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1473,7 +1808,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1481,7 +1816,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1489,7 +1824,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1497,7 +1832,15 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1505,7 +1848,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1513,7 +1856,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1521,7 +1864,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1529,7 +1872,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1537,7 +1880,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1545,23 +1888,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6, - .direction = TF_DIR_RX - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7, - .direction = TF_DIR_RX - }, - { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1569,7 +1896,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1577,7 +1904,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1585,7 +1912,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1593,7 +1920,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1601,7 +1928,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1609,7 +1936,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1617,7 +1944,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1625,7 +1952,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1633,427 +1960,2171 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .direction = TF_DIR_TX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_METADATA, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0, + .direction = TF_DIR_TX + }, + { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + } +}; + +/* List of tf resources required to be reserved per app/device */ +struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 422 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 191 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 6912 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 1023 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 511 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 15 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, + .count = 255 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 422 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 960 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 88 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 13168 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 292 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 148 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 191 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 6912 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 1023 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 511 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 223 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 255 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 488 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, + .count = 511 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 292 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 144 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 960 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 928 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 15232 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 5 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 31 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 2048 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 64 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 128 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4096 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 16384 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 5 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 2048 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 100 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 128 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4096 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 16384 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_METADATA, + .count = 1 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 16 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 528 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 256 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 512 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 256 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1, - .direction = TF_DIR_RX + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 }, { - .app_id = 3, + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2, - .direction = TF_DIR_RX + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 }, { - .app_id = 3, + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3, - .direction = TF_DIR_RX - } -}; - -/* List of tf resources required to be reserved per app/device */ -struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 6912 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 511 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 15 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, - .count = 255 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 88 + .count = 64 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 13168 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 148 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 6912 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 511 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 223 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 255 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 488 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .count = 511 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 144 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 928 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 15232 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 272 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2061,15 +4132,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 32 + .count = 16 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2077,759 +4148,815 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 528 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 8192 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 5 + .count = 256 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 31 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 2048 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 64 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 272 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4096 + .count = 512 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 16384 + .count = 1024 }, { - .app_id = 0, + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 272 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 512 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 8192 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 5 + .count = 256 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 2048 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 100 + .count = 4 }, { - .app_id = 0, + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 272 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4096 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 16384 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_METADATA, - .count = 1 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 422 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 4 + .count = 191 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 4 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 4 + .count = 192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 128 + .count = 8192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 128 + .count = 7168 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 4 + .count = 1023 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 4 + .count = 511 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 4 + .count = 15 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, - .count = 4 + .count = 255 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 422 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 960 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 88 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 13168 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 292 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 148 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 4 + .count = 191 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 4 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 4 + .count = 192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 128 + .count = 8192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 128 + .count = 7168 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 4 + .count = 1023 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 4 + .count = 511 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 4 + .count = 223 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 4 + .count = 255 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 4 + .count = 488 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .count = 4 + .count = 511 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 292 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 144 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 960 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 928 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 15232 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 16 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 528 + .count = 4096 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 256 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, + .count = 1024 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 2048 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 6144 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 4 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 4 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 4 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 512 + .count = 4096 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 256 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, + .count = 1024 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 2048 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 6144 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2837,7 +4964,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2845,7 +4972,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2853,7 +4980,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2861,7 +4988,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2869,7 +4996,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2877,7 +5004,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2885,7 +5012,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2893,7 +5020,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2901,7 +5028,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2909,7 +5036,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2917,7 +5044,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -2925,7 +5052,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -2933,7 +5060,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -2941,15 +5068,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 64 + .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -2957,7 +5084,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2965,7 +5092,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2973,7 +5100,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2981,7 +5108,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2989,7 +5116,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2997,7 +5124,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3005,7 +5132,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3013,7 +5140,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3021,7 +5148,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3029,7 +5156,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3037,7 +5164,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3045,7 +5172,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3053,7 +5180,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3061,7 +5188,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3069,7 +5196,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3077,7 +5204,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3085,7 +5212,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3093,7 +5220,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -3101,7 +5228,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3109,7 +5236,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3117,7 +5244,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3125,7 +5252,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3133,7 +5260,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 16 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3141,7 +5268,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3149,7 +5276,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 528 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3157,7 +5284,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 256 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3165,7 +5292,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3173,7 +5300,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3181,7 +5308,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3189,7 +5316,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3197,7 +5324,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3205,7 +5332,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3213,15 +5340,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 512 + .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -3229,7 +5356,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3237,7 +5364,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3245,7 +5372,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3253,7 +5380,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3261,7 +5388,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3269,7 +5396,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3277,7 +5404,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 512 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3285,7 +5412,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 256 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3293,7 +5420,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3301,7 +5428,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3309,7 +5436,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3317,7 +5444,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3325,7 +5452,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3333,7 +5460,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3341,7 +5468,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3349,7 +5476,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -3357,596 +5484,532 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 7168 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 511 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 15 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, - .count = 255 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 88 + .count = 64 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 13168 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 148 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 7168 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 511 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 223 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 255 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 488 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .count = 511 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 144 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 928 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 15232 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 16 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 4096 + .count = 528 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 256 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 2048 + .count = 512 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 6144 + .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 128 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 128 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 4096 + .count = 512 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 256 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 2048 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 6144 + .count = 1024 } }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c index e49c1151d3..8869ab1c33 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Aug 17 12:16:42 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -1575,8 +1575,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}, + (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1607,7 +1607,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, + ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_DECAP_FUNC_NONE} @@ -1666,8 +1666,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1692,7 +1692,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, + ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1747,7 +1747,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, + ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_DECAP_FUNC_NONE} @@ -1806,8 +1806,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1832,7 +1832,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, + ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2149,7 +2149,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2168,7 +2168,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2187,7 +2187,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2206,7 +2206,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2373,8 +2373,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2393,8 +2393,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2413,8 +2413,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2433,8 +2433,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 3, , table: mod_record.ing_no_ttl */ @@ -2526,7 +2526,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2545,7 +2545,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2564,7 +2564,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2583,7 +2583,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2737,8 +2737,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2757,8 +2757,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2777,8 +2777,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2797,8 +2797,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 3, , table: int_full_act_record.0 */ @@ -3593,7 +3593,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3612,7 +3612,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3631,7 +3631,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3650,7 +3650,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3817,8 +3817,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -3837,8 +3837,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -3857,8 +3857,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -3877,8 +3877,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 5, , table: mod_record.ing_no_ttl */ @@ -3970,7 +3970,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3989,7 +3989,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4008,7 +4008,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4027,7 +4027,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4181,8 +4181,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4201,8 +4201,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4221,8 +4221,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4241,8 +4241,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 5, , table: int_full_act_record.0 */ @@ -4526,8 +4526,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4546,8 +4546,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4566,8 +4566,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4586,8 +4586,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4833,8 +4833,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4853,8 +4853,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4873,8 +4873,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4893,8 +4893,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 54bc032b0c..2d464fb7c4 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 12:11:08 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -3232,8 +3232,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -3302,7 +3302,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -3492,7 +3492,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -3871,8 +3871,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -3987,8 +3987,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -4821,8 +4821,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -4835,8 +4835,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -4959,8 +4959,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -4973,8 +4973,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5037,8 +5037,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -5051,8 +5051,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5091,8 +5091,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -5105,8 +5105,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5153,8 +5153,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5358,8 +5358,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5383,8 +5383,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5542,8 +5542,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -5612,7 +5612,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -5659,7 +5659,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_VALID_YES}, + ULP_THOR_SYM_L4_HDR_VALID_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_VALID_IGNORE} @@ -5749,7 +5749,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L3_HDR_TYPE_IPV6} @@ -5830,7 +5830,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -6209,8 +6209,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -6734,7 +6734,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L3_HDR_TYPE_IPV6} @@ -6815,7 +6815,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_TL2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_TL2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_TL2_VTAG_PRESENT_NO} @@ -6900,8 +6900,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -7018,8 +7018,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -7852,8 +7852,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -7866,8 +7866,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7990,8 +7990,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8004,8 +8004,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8056,8 +8056,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8070,8 +8070,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8110,8 +8110,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8124,8 +8124,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8187,8 +8187,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8383,8 +8383,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8397,8 +8397,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8413,8 +8413,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8427,8 +8427,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9359,8 +9359,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9373,8 +9373,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9497,8 +9497,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9511,8 +9511,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9575,8 +9575,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9589,8 +9589,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9629,8 +9629,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9643,8 +9643,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9694,8 +9694,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9901,8 +9901,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9928,8 +9928,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10860,8 +10860,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -10874,8 +10874,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10998,8 +10998,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -11012,8 +11012,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -11064,8 +11064,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -11078,8 +11078,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -11118,8 +11118,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -11132,8 +11132,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -11195,8 +11195,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12335,8 +12335,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12349,8 +12349,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12473,8 +12473,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12487,8 +12487,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12551,8 +12551,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12565,8 +12565,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12605,8 +12605,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12619,8 +12619,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12670,8 +12670,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -13810,8 +13810,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -13824,8 +13824,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -13948,8 +13948,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -13962,8 +13962,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14712,8 +14712,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -14726,8 +14726,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14778,8 +14778,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -14792,8 +14792,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14832,8 +14832,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -14846,8 +14846,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14909,8 +14909,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -15093,8 +15093,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -15107,8 +15107,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -15123,8 +15123,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -15137,8 +15137,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -15345,8 +15345,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -15359,8 +15359,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16219,8 +16219,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16233,8 +16233,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16297,8 +16297,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16311,8 +16311,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16351,8 +16351,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16365,8 +16365,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16416,8 +16416,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16600,8 +16600,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16614,8 +16614,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16630,8 +16630,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16644,8 +16644,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16852,8 +16852,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16866,8 +16866,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -18434,7 +18434,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_I_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -19848,8 +19848,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -19862,8 +19862,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -19970,8 +19970,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -19984,8 +19984,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20168,8 +20168,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -20182,8 +20182,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20222,8 +20222,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -20236,8 +20236,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20284,8 +20284,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20489,8 +20489,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20514,8 +20514,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -22120,8 +22120,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22134,8 +22134,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22242,8 +22242,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22256,8 +22256,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22428,8 +22428,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22442,8 +22442,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22482,8 +22482,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22496,8 +22496,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22559,8 +22559,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22755,8 +22755,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22769,8 +22769,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22785,8 +22785,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22799,8 +22799,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -23041,7 +23041,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -23231,7 +23231,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -24532,8 +24532,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24546,8 +24546,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24562,8 +24562,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24576,8 +24576,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24700,8 +24700,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24714,8 +24714,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24778,8 +24778,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24792,8 +24792,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24832,8 +24832,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24846,8 +24846,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24894,8 +24894,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -25099,8 +25099,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -25124,8 +25124,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -25345,7 +25345,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -25469,7 +25469,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L3_HDR_TYPE_IPV6} @@ -25548,7 +25548,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -26210,7 +26210,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -27511,8 +27511,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -27525,8 +27525,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -27541,8 +27541,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -27555,8 +27555,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -27679,8 +27679,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -27693,8 +27693,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -27856,8 +27856,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -28052,8 +28052,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -28066,8 +28066,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -28082,8 +28082,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -28096,8 +28096,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29016,8 +29016,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -29030,8 +29030,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29046,8 +29046,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -29060,8 +29060,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29184,8 +29184,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -29198,8 +29198,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29361,8 +29361,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -30489,8 +30489,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -30503,8 +30503,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -30519,8 +30519,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -30533,8 +30533,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -30657,8 +30657,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -30671,8 +30671,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -34679,8 +34679,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -35206,8 +35206,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -36920,8 +36920,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}, + (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, @@ -36991,8 +36991,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff}, + (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff, @@ -38986,8 +38986,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}, + (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff, @@ -39570,8 +39570,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c index 4a2d201c2d..16a921e6c8 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Aug 25 14:37:06 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -1210,8 +1210,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1239,8 +1239,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1295,7 +1295,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_NONE} @@ -1346,8 +1346,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1481,8 +1481,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1510,8 +1510,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1566,7 +1566,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_NONE} @@ -1893,7 +1893,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1} + 1} }, { .description = "drop", @@ -2088,7 +2088,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1} + 1} }, { .description = "drop", @@ -2222,8 +2222,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2_POST, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - (1 >> 8) & 0xff, - 1 & 0xff} + (1 >> 8) & 0xff, + 1 & 0xff} }, /* act_tid: 3, , table: int_flow_counter_tbl.0 */ { @@ -2418,8 +2418,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2447,8 +2447,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2503,7 +2503,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -2662,8 +2662,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2691,8 +2691,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2747,7 +2747,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -3853,8 +3853,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3882,8 +3882,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3938,7 +3938,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -4097,8 +4097,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4126,8 +4126,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4182,7 +4182,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -4415,8 +4415,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4435,8 +4435,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4455,8 +4455,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4475,8 +4475,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4495,8 +4495,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4515,8 +4515,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4535,8 +4535,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4555,8 +4555,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4575,8 +4575,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4595,8 +4595,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4615,8 +4615,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4635,8 +4635,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4672,8 +4672,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4692,8 +4692,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4712,8 +4712,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4732,8 +4732,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4752,8 +4752,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4772,8 +4772,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4792,8 +4792,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4812,8 +4812,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4832,8 +4832,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 6, , table: int_full_act_record.0 */ @@ -5264,8 +5264,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5284,8 +5284,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5304,8 +5304,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5324,8 +5324,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5344,8 +5344,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5364,8 +5364,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5384,8 +5384,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5404,8 +5404,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5424,8 +5424,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5444,8 +5444,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5464,8 +5464,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5484,8 +5484,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5521,8 +5521,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5541,8 +5541,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5561,8 +5561,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5581,8 +5581,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5601,8 +5601,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5621,8 +5621,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5641,8 +5641,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5661,8 +5661,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5681,8 +5681,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c index 4b9cb7fd5b..d1c3ebe065 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Aug 11 16:00:16 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -2198,8 +2198,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -2218,8 +2218,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2261,8 +2261,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -2281,8 +2281,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2550,8 +2550,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -2570,8 +2570,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2631,8 +2631,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -2701,7 +2701,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -3258,8 +3258,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -3383,7 +3383,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -3942,8 +3942,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -4702,8 +4702,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -4778,8 +4778,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4803,8 +4803,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4827,8 +4827,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4980,8 +4980,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5005,8 +5005,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5029,8 +5029,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5182,8 +5182,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5207,8 +5207,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5231,8 +5231,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5398,8 +5398,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5423,8 +5423,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5447,8 +5447,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6746,7 +6746,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L3_HDR_TYPE_IPV4}, + ULP_WP_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L3_HDR_TYPE_IPV6} @@ -7714,8 +7714,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -7734,8 +7734,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7777,8 +7777,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -7797,8 +7797,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8066,8 +8066,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8086,8 +8086,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8147,8 +8147,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -8217,7 +8217,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -8774,8 +8774,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -8899,7 +8899,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -9458,8 +9458,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -9576,8 +9576,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -9652,8 +9652,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9677,8 +9677,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9701,8 +9701,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9854,8 +9854,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9879,8 +9879,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9903,8 +9903,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10056,8 +10056,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10081,8 +10081,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10105,8 +10105,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10272,8 +10272,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10297,8 +10297,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10321,8 +10321,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12392,8 +12392,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -12409,8 +12409,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, @@ -12544,8 +12544,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -12561,8 +12561,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, @@ -13715,7 +13715,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_LOOPBACK_PARIF}, + ULP_WP_SYM_LOOPBACK_PARIF}, .field_src3 = BNXT_ULP_FIELD_SRC_CF, .field_opr3 = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, @@ -13887,8 +13887,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -13904,8 +13904,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, @@ -14039,8 +14039,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -14056,8 +14056,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index d21c088d59..2ec3279239 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -685,6 +685,11 @@ ulp_rte_phy_port_hdr_handler(const struct rte_flow_item *item, hdr_field->size = sizeof(svif); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SVIF_FLAG, rte_be_to_cpu_16(svif)); + if (!mask) { + ULP_BITMAP_SET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_SVIF_IGNORE); + memset(hdr_field->mask, 0xFF, sizeof(mask)); + } return BNXT_TF_RC_SUCCESS; } -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 14/19] net/bnxt: delete the VF pair before VF representor alloc 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (12 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 13/19] net/bnxt: add support for socket redirect feature Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 15/19] net/bnxt: add new API TruFlow get SRAM resources Venkat Duvvuru ` (4 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> When the VF representor interface is created, the VF pair relationship is established between the VF and it is representor. If the pair already exists then the pair needs to be deleted before allocation. This could happen if the application is abruptly killed and restarted. If the deletion of an existing VF rep is not done then hw pipeline is not cleaned and a new allocation shall leave the hw in inconsistent state. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com> --- drivers/net/bnxt/bnxt_hwrm.c | 28 ++++++++++++++++++++++++++++ drivers/net/bnxt/bnxt_hwrm.h | 1 + drivers/net/bnxt/bnxt_reps.c | 6 ++++++ 3 files changed, 35 insertions(+) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index c7041143a3..f8c27fe316 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -6025,6 +6025,34 @@ int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid, return rc; } +int bnxt_hwrm_cfa_pair_exists(struct bnxt *bp, struct bnxt_representor *rep_bp) +{ + struct hwrm_cfa_pair_info_output *resp = bp->hwrm_cmd_resp_addr; + struct hwrm_cfa_pair_info_input req = {0}; + int rc = 0; + + if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) { + PMD_DRV_LOG(DEBUG, + "Not a PF or trusted VF. Command not supported\n"); + return 0; + } + + HWRM_PREP(&req, HWRM_CFA_PAIR_INFO, BNXT_USE_CHIMP_MB); + snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d", + bp->eth_dev->data->name, rep_bp->vf_id); + req.flags = + rte_cpu_to_le_32(HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE); + + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); + HWRM_CHECK_RESULT(); + if (rc == HWRM_ERR_CODE_SUCCESS && strlen(resp->pair_name)) { + HWRM_UNLOCK(); + return !rc; + } + HWRM_UNLOCK(); + return rc; +} + int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp) { struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr; diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h index 6dc23b93ac..33e6ba99d5 100644 --- a/drivers/net/bnxt/bnxt_hwrm.h +++ b/drivers/net/bnxt/bnxt_hwrm.h @@ -294,6 +294,7 @@ int bnxt_clear_one_vnic_filter(struct bnxt *bp, void bnxt_free_vf_info(struct bnxt *bp); int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid, uint16_t *first_vf_id); +int bnxt_hwrm_cfa_pair_exists(struct bnxt *bp, struct bnxt_representor *rep_bp); int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep); int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep); int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp); diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c index 988f5a33a7..111d226a59 100644 --- a/drivers/net/bnxt/bnxt_reps.c +++ b/drivers/net/bnxt/bnxt_reps.c @@ -315,6 +315,12 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev) BNXT_TF_DBG(ERR, "Invalid arguments\n"); return 0; } + /* update the port id so you can backtrack to ethdev */ + vfr->dpdk_port_id = vfr_ethdev->data->port_id; + + /* If pair is present, then delete the pair */ + if (bnxt_hwrm_cfa_pair_exists(parent_bp, vfr)) + (void)bnxt_hwrm_cfa_pair_free(parent_bp, vfr); /* Update the ULP portdata base with the new VFR interface */ rc = ulp_port_db_dev_port_intf_update(parent_bp->ulp_ctx, vfr_ethdev); -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 15/19] net/bnxt: add new API TruFlow get SRAM resources 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (13 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 14/19] net/bnxt: delete the VF pair before VF representor alloc Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 16/19] net/bnxt: add TruFlow and AFM SRAM partitioning support Venkat Duvvuru ` (3 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru From: Jay Ding <jay.ding@broadcom.com> Implement tf_get_sram_resources to return SRAM partition information, including bank count and SRAM profile number. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 11 ++- drivers/net/bnxt/tf_core/tf_core.c | 86 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_core.h | 63 +++++++++++++++++ drivers/net/bnxt/tf_core/tf_device.h | 20 ++++++ drivers/net/bnxt/tf_core/tf_device_p4.c | 6 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 53 ++++++++++++++- drivers/net/bnxt/tf_core/tf_msg.c | 28 ++------ drivers/net/bnxt/tf_core/tf_msg.h | 6 +- drivers/net/bnxt/tf_core/tf_rm.c | 3 +- drivers/net/bnxt/tf_core/tf_sram_mgr.h | 10 --- 10 files changed, 245 insertions(+), 41 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 6d04e39e48..1a46f34249 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1058,8 +1058,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 58 -#define HWRM_VERSION_STR "1.10.2.58" +#define HWRM_VERSION_RSVD 64 +#define HWRM_VERSION_STR "1.10.2.64" /**************** * hwrm_ver_get * @@ -45817,8 +45817,13 @@ struct hwrm_tf_session_resc_qcaps_output { * qcaps_size. */ uint16_t size; + /* + * SRAM profile number that sets the partition of SRAM memory + * between TF and AFM within the 4 internal memory banks (Thor). + */ + uint8_t sram_profile; /* unused. */ - uint16_t unused0; + uint8_t unused0; /* unused. */ uint8_t unused1[7]; /* diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 86dfec0eb4..346d220c87 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1831,3 +1831,89 @@ int tf_get_version(struct tf *tfp, return 0; } + +int tf_query_sram_resources(struct tf *tfp, + struct tf_query_sram_resources_parms *parms) +{ + int rc; + struct tf_dev_info dev; + uint16_t max_types; + struct tfp_calloc_parms cparms; + struct tf_rm_resc_req_entry *query; + enum tf_rm_resc_resv_strategy resv_strategy; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_THOR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + if (dev.ops->tf_dev_get_max_types == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return -EOPNOTSUPP; + } + + /* Need device max number of elements for the RM QCAPS */ + rc = dev.ops->tf_dev_get_max_types(tfp, &max_types); + if (rc) { + TFP_DRV_LOG(ERR, + "Get SRAM resc info failed, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Allocate memory for RM QCAPS request */ + cparms.nitems = max_types; + cparms.size = sizeof(struct tf_rm_resc_req_entry); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) + return rc; + + query = (struct tf_rm_resc_req_entry *)cparms.mem_va; + tfp->bp = parms->bp; + + /* Get Firmware Capabilities */ + rc = tf_msg_session_resc_qcaps(tfp, + &dev, + parms->dir, + max_types, + query, + &resv_strategy, + &parms->sram_profile); + if (rc) + return rc; + + if (dev.ops->tf_dev_get_sram_resources == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return -EOPNOTSUPP; + } + + rc = dev.ops->tf_dev_get_sram_resources((void *)query, + parms->bank_resc_count, + &parms->dynamic_sram_capable); + if (rc) { + TFP_DRV_LOG(ERR, + "Get SRAM resc info failed, rc:%s\n", + strerror(-rc)); + return rc; + } + + return 0; +} diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index ba9881c69d..078fd278a1 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -75,6 +75,17 @@ enum tf_wc_num_slice { TF_WC_TCAM_8_SLICE_PER_ROW = 8, }; +/** + * Bank identifier + */ +enum tf_sram_bank_id { + TF_SRAM_BANK_ID_0, /**< SRAM Bank 0 id */ + TF_SRAM_BANK_ID_1, /**< SRAM Bank 1 id */ + TF_SRAM_BANK_ID_2, /**< SRAM Bank 2 id */ + TF_SRAM_BANK_ID_3, /**< SRAM Bank 3 id */ + TF_SRAM_BANK_ID_MAX /**< SRAM Bank index limit */ +}; + /** * EEM record AR helper * @@ -2438,4 +2449,56 @@ struct tf_get_version_parms { */ int tf_get_version(struct tf *tfp, struct tf_get_version_parms *parms); + +/** + * tf_query_sram_resources parameter definition + */ +struct tf_query_sram_resources_parms { + /** + * [in] device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] bp + * The pointer to the parent bp struct. This is only used for HWRM + * message passing within the portability layer. The type is struct + * bnxt. + */ + void *bp; + + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + + /** + * [out] Bank resource count in 8 bytes entry + */ + + uint32_t bank_resc_count[TF_SRAM_BANK_ID_MAX]; + + /** + * [out] Dynamic SRAM Enable + */ + bool dynamic_sram_capable; + + /** + * [out] SRAM profile + */ + uint8_t sram_profile; +}; + +/** + * Get SRAM resources information + * + * Used to retrieve sram bank partition information + * + * Returns success or failure code. + */ +int tf_query_sram_resources(struct tf *tfp, + struct tf_query_sram_resources_parms *parms); + #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 88bd4515ff..9360eb1358 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1081,6 +1081,26 @@ struct tf_dev_ops { uint32_t *tcam_caps, uint32_t *tbl_caps, uint32_t *em_caps); + + /** + * Device specific function that retrieve the sram resource + * + * [in] query + * Point to resources query result + * + * [out] sram_bank_caps + * Pointer to SRAM bank capabilities + * + * [out] dynamic_sram_capable + * Pointer to dynamic sram capable + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_sram_resources)(void *query, + uint32_t *sram_bank_caps, + bool *dynamic_sram_capable); }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 8089785b82..cf0e919f9f 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -382,7 +382,8 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = NULL, - .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, + .tf_dev_get_sram_resources = NULL }; /** @@ -445,5 +446,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = tf_dev_p4_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, - .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, + .tf_dev_get_sram_resources = NULL }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 03e72b90f5..4687fa65dd 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -397,6 +397,53 @@ static int tf_dev_p58_map_hcapi_caps(uint64_t hcapi_caps, return 0; } +/** + * Device specific function that retrieve the sram resource + * + * [in] query + * Point to resources query result + * + * [out] sram_bank_caps + * Pointer to SRAM bank capabilities + * + * [out] dynamic_sram_capable + * Pointer to dynamic sram capable + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_get_sram_resources(void *q, + uint32_t *sram_bank_caps, + bool *dynamic_sram_capable) +{ + uint32_t i; + struct tf_rm_resc_req_entry *query = q; + + for (i = 0; i < CFA_RESOURCE_TYPE_P58_LAST + 1; i++) { + switch (query[i].type) { + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_0: + sram_bank_caps[0] = query[i].max; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_1: + sram_bank_caps[1] = query[i].max; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_2: + sram_bank_caps[2] = query[i].max; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_3: + sram_bank_caps[3] = query[i].max; + break; + default: + break; + } + } + + *dynamic_sram_capable = false; + + return 0; +} + /** * Truflow P58 device specific functions */ @@ -447,7 +494,8 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = NULL, - .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources }; /** @@ -511,5 +559,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = tf_dev_p58_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, - .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources }; diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 25bf026658..fbc96d374c 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -380,39 +380,20 @@ tf_msg_session_resc_qcaps(struct tf *tfp, enum tf_dir dir, uint16_t size, struct tf_rm_resc_req_entry *query, - enum tf_rm_resc_resv_strategy *resv_strategy) + enum tf_rm_resc_resv_strategy *resv_strategy, + uint8_t *sram_profile) { int rc; int i; struct tfp_send_msg_parms parms = { 0 }; struct hwrm_tf_session_resc_qcaps_input req = { 0 }; struct hwrm_tf_session_resc_qcaps_output resp = { 0 }; - uint8_t fw_session_id; struct tf_msg_dma_buf qcaps_buf = { 0 }; struct tf_rm_resc_req_entry *data; int dma_size; - struct tf_session *tfs; - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to lookup session, rc:%s\n", - strerror(-rc)); - return rc; - } TF_CHECK_PARMS3(tfp, query, resv_strategy); - rc = tf_session_get_fw_session_id(tfp, &fw_session_id); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Unable to lookup FW id, rc:%s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - /* Prepare DMA buffer */ dma_size = size * sizeof(struct tf_rm_resc_req_entry); rc = tf_msg_alloc_dma_buf(&qcaps_buf, dma_size); @@ -420,7 +401,7 @@ tf_msg_session_resc_qcaps(struct tf *tfp, return rc; /* Populate the request */ - req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); + req.fw_session_id = 0; req.flags = tfp_cpu_to_le_16(dir); req.qcaps_size = size; req.qcaps_addr = tfp_cpu_to_le_64(qcaps_buf.pa_addr); @@ -460,6 +441,9 @@ tf_msg_session_resc_qcaps(struct tf *tfp, *resv_strategy = resp.flags & HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK; + if (sram_profile != NULL) + *sram_profile = resp.sram_profile; + cleanup: tf_msg_free_dma_buf(&qcaps_buf); diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 08d20cdd7a..188b361d71 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -158,6 +158,9 @@ int tf_msg_session_qcfg(struct tf *tfp); * [out] resv_strategy * Pointer to the reservation strategy * + * [out] sram_profile + * Pointer to the sram profile + * * Returns: * 0 on Success else internal Truflow error */ @@ -166,7 +169,8 @@ int tf_msg_session_resc_qcaps(struct tf *tfp, enum tf_dir dir, uint16_t size, struct tf_rm_resc_req_entry *query, - enum tf_rm_resc_resv_strategy *resv_strategy); + enum tf_rm_resc_resv_strategy *resv_strategy, + uint8_t *sram_profile); /** * Sends session HW resource allocation request to TF Firmware diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index dd537aaece..d2045921b9 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -551,7 +551,8 @@ tf_rm_create_db(struct tf *tfp, parms->dir, max_types, query, - &resv_strategy); + &resv_strategy, + NULL); if (rc) return rc; diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h index 4abe3fb468..eb2156456a 100644 --- a/drivers/net/bnxt/tf_core/tf_sram_mgr.h +++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h @@ -28,16 +28,6 @@ #define TF_SRAM_MGR_BLOCK_SZ_BYTES 64 #define TF_SRAM_MGR_MIN_SLICE_BYTES 8 -/** - * Bank identifier - */ -enum tf_sram_bank_id { - TF_SRAM_BANK_ID_0, /**< SRAM Bank 0 id */ - TF_SRAM_BANK_ID_1, /**< SRAM Bank 1 id */ - TF_SRAM_BANK_ID_2, /**< SRAM Bank 2 id */ - TF_SRAM_BANK_ID_3, /**< SRAM Bank 3 id */ - TF_SRAM_BANK_ID_MAX /**< SRAM Bank index limit */ -}; /** * TF slice size. -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 16/19] net/bnxt: add TruFlow and AFM SRAM partitioning support 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (14 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 15/19] net/bnxt: add new API TruFlow get SRAM resources Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 17/19] net/bnxt: add Tx TruFlow table config for p4 Venkat Duvvuru ` (2 subsequent siblings) 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru From: Jay Ding <jay.ding@broadcom.com> Implement set/get_sram_policy which support both rx/tx direction truflow type the specific SRAM bank. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> --- drivers/net/bnxt/tf_core/tf_core.c | 82 ++++++ drivers/net/bnxt/tf_core/tf_core.h | 66 ++++- drivers/net/bnxt/tf_core/tf_device.c | 7 +- drivers/net/bnxt/tf_core/tf_device.h | 34 ++- drivers/net/bnxt/tf_core/tf_device_p4.c | 8 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 311 ++++++++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p58.h | 118 +-------- drivers/net/bnxt/tf_core/tf_tbl.c | 2 +- 8 files changed, 503 insertions(+), 125 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 346d220c87..90ff93946b 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1917,3 +1917,85 @@ int tf_query_sram_resources(struct tf *tfp, return 0; } + +int tf_set_sram_policy(struct tf *tfp, + struct tf_set_sram_policy_parms *parms) +{ + int rc = 0; + struct tf_dev_info dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_THOR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + if (dev.ops->tf_dev_set_sram_policy == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + rc = dev.ops->tf_dev_set_sram_policy(parms->dir, parms->bank_id); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: SRAM policy set failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + return rc; +} + +int tf_get_sram_policy(struct tf *tfp, + struct tf_get_sram_policy_parms *parms) +{ + int rc = 0; + struct tf_dev_info dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_THOR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + if (dev.ops->tf_dev_get_sram_policy == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + rc = dev.ops->tf_dev_get_sram_policy(parms->dir, parms->bank_id); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: SRAM policy get failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 078fd278a1..b2886355fa 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2455,7 +2455,7 @@ int tf_get_version(struct tf *tfp, */ struct tf_query_sram_resources_parms { /** - * [in] device type + * [in] Device type * * Device type for the session. */ @@ -2501,4 +2501,68 @@ struct tf_query_sram_resources_parms { int tf_query_sram_resources(struct tf *tfp, struct tf_query_sram_resources_parms *parms); +/** + * tf_set_sram_policy parameter definition + */ +struct tf_set_sram_policy_parms { + /** + * [in] Device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + + /** + * [in] Array of Bank id for each truflow tbl type + */ + uint8_t *bank_id; +}; + +/** + * Set SRAM policy + * + * Used to assign SRAM bank index to all truflow table type. + * + * Returns success or failure code. + */ +int tf_set_sram_policy(struct tf *tfp, + struct tf_set_sram_policy_parms *parms); + +/** + * tf_get_sram_policy parameter definition + */ +struct tf_get_sram_policy_parms { + /** + * [in] Device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + + /** + * [out] Array of Bank id for each truflow tbl type + */ + uint8_t bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1]; +}; + +/** + * Get SRAM policy + * + * Used to get the assigned bank of table types. + * + * Returns success or failure code. + */ +int tf_get_sram_policy(struct tf *tfp, + struct tf_get_sram_policy_parms *parms); + #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 25a7166bbb..40db546604 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -415,11 +415,14 @@ tf_dev_bind_p58(struct tf *tfp, } rsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX, - tf_tbl_p58, + tf_tbl_p58[TF_DIR_RX], + (uint16_t *)resources->tbl_cnt); + rsv_cnt += tf_dev_reservation_check(TF_TBL_TYPE_MAX, + tf_tbl_p58[TF_DIR_TX], (uint16_t *)resources->tbl_cnt); if (rsv_cnt) { tbl_cfg.num_elements = TF_TBL_TYPE_MAX; - tbl_cfg.cfg = tf_tbl_p58; + tbl_cfg.cfg = tf_tbl_p58[TF_DIR_RX]; tbl_cfg.resources = resources; rc = tf_tbl_bind(tfp, &tbl_cfg); if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 9360eb1358..3d5de988c4 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1083,7 +1083,7 @@ struct tf_dev_ops { uint32_t *em_caps); /** - * Device specific function that retrieve the sram resource + * Device specific function that retrieves the sram resource * * [in] query * Point to resources query result @@ -1101,6 +1101,38 @@ struct tf_dev_ops { int (*tf_dev_get_sram_resources)(void *query, uint32_t *sram_bank_caps, bool *dynamic_sram_capable); + + /** + * Device specific function that sets the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [in] band_id + * SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_set_sram_policy)(enum tf_dir dir, + uint8_t *bank_id); + + /** + * Device specific function that gets the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [in] band_id + * pointer to SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_sram_policy)(enum tf_dir dir, + uint8_t *bank_id); }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index cf0e919f9f..244bd08914 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -383,7 +383,9 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = NULL, .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, - .tf_dev_get_sram_resources = NULL + .tf_dev_get_sram_resources = NULL, + .tf_dev_set_sram_policy = NULL, + .tf_dev_get_sram_policy = NULL, }; /** @@ -447,5 +449,7 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_word_align = tf_dev_p4_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, - .tf_dev_get_sram_resources = NULL + .tf_dev_get_sram_resources = NULL, + .tf_dev_set_sram_policy = NULL, + .tf_dev_get_sram_policy = NULL, }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 4687fa65dd..3c1c3a2de1 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -48,6 +48,235 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = "meter_dc", }; +struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { + [TF_DIR_RX][TF_TBL_TYPE_EM_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_WC_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_DROP_CNT] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METADATA] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, + 0, 0 + }, + /* Policy - ARs in bank 1 */ + [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 8, + }, + /* Policy - Encaps in bank 2 */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - Modify in bank 2 with Encaps */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - SP in bank 0 */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 8, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 2, + }, + /* Policy - Stats in bank 3 */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_EM_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_WC_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_DROP_CNT] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METADATA] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, + 0, 0 + }, + /* Policy - ARs in bank 1 */ + [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 8, + }, + /* Policy - Encaps in bank 2 */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - Modify in bank 2 with Encaps */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - SP in bank 0 */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 2, + }, + /* Policy - Stats in bank 3 */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, + .slices = 8, + }, +}; + /** * Device specific function that retrieves the MAX number of HCAPI * types the device supports. @@ -444,6 +673,80 @@ static int tf_dev_p58_get_sram_resources(void *q, return 0; } +int sram_bank_hcapi_type[] = { + CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + CFA_RESOURCE_TYPE_P58_SRAM_BANK_3 +}; + +/** + * Device specific function that set the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [in] band_id + * SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_set_sram_policy(enum tf_dir dir, + uint8_t *bank_id) +{ + struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; + uint8_t type; + uint8_t parent[TF_SRAM_BANK_ID_MAX] = { 0xFF, 0xFF, 0xFF, 0xFF }; + + for (type = TF_TBL_TYPE_FULL_ACT_RECORD; + type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++) { + if (bank_id[type] > 3) + return -EINVAL; + + rm_cfg[type].hcapi_type = sram_bank_hcapi_type[bank_id[type]]; + if (parent[bank_id[type]] == 0xFF) { + parent[bank_id[type]] = type; + rm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT; + rm_cfg[type].parent_subtype = 0; + if (rm_cfg[type].slices == 0) + rm_cfg[type].slices = 1; + } else { + rm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD; + rm_cfg[type].parent_subtype = parent[bank_id[type]]; + } + } + + return 0; +} + +/** + * Device specific function that get the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [out] band_id + * pointer to SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_get_sram_policy(enum tf_dir dir, + uint8_t *bank_id) +{ + struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; + uint8_t type; + + for (type = TF_TBL_TYPE_FULL_ACT_RECORD; + type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++) + bank_id[type] = rm_cfg[type].hcapi_type - CFA_RESOURCE_TYPE_P58_SRAM_BANK_0; + + return 0; +} + /** * Truflow P58 device specific functions */ @@ -495,7 +798,9 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = NULL, .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, - .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources, + .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy, + .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy, }; /** @@ -560,5 +865,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_word_align = tf_dev_p58_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, - .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources, + .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy, + .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy, }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index f6e66936f3..61c856b767 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -12,6 +12,8 @@ #include "tf_if_tbl.h" #include "tf_global_cfg.h" +extern struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX]; + struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = { [TF_IDENT_TYPE_L2_CTXT_HIGH] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH, @@ -58,122 +60,6 @@ struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = { }, }; -struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { - [TF_TBL_TYPE_EM_FKB] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, - 0, 0 - }, - [TF_TBL_TYPE_WC_FKB] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, - 0, 0 - }, - [TF_TBL_TYPE_METER_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, - 0, 0 - }, - [TF_TBL_TYPE_METER_INST] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, - 0, 0 - }, - [TF_TBL_TYPE_METER_DROP_CNT] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, - 0, 0 - }, - [TF_TBL_TYPE_MIRROR_CONFIG] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, - 0, 0 - }, - [TF_TBL_TYPE_METADATA] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, - 0, 0 - }, - /* Policy - ARs in bank 1 */ - [TF_TBL_TYPE_FULL_ACT_RECORD] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 4, - }, - [TF_TBL_TYPE_COMPACT_ACT_RECORD] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 8, - }, - /* Policy - Encaps in bank 2 */ - [TF_TBL_TYPE_ACT_ENCAP_8B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 8, - }, - [TF_TBL_TYPE_ACT_ENCAP_16B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 4, - }, - [TF_TBL_TYPE_ACT_ENCAP_32B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 2, - }, - [TF_TBL_TYPE_ACT_ENCAP_64B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, - }, - /* Policy - Modify in bank 2 with Encaps */ - [TF_TBL_TYPE_ACT_MODIFY_8B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 8, - }, - [TF_TBL_TYPE_ACT_MODIFY_16B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 4, - }, - [TF_TBL_TYPE_ACT_MODIFY_32B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 2, - }, - [TF_TBL_TYPE_ACT_MODIFY_64B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, - }, - /* Policy - SP in bank 0 */ - [TF_TBL_TYPE_ACT_SP_SMAC] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 8, - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 4, - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 2, - }, - /* Policy - Stats in bank 3 */ - [TF_TBL_TYPE_ACT_STATS_64] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, - .slices = 8, - }, -}; - struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_EM_RECORD] = { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC, diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 12eca36491..3fb22b52ac 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -58,10 +58,10 @@ tf_tbl_bind(struct tf *tfp, db_cfg.num_elements = parms->num_elements; db_cfg.module = TF_MODULE_TYPE_TABLE; db_cfg.num_elements = parms->num_elements; - db_cfg.cfg = parms->cfg; for (d = 0; d < TF_DIR_MAX; d++) { db_cfg.dir = d; + db_cfg.cfg = &parms->cfg[d ? TF_TBL_TYPE_MAX : 0]; db_cfg.alloc_cnt = parms->resources->tbl_cnt[d].cnt; db_cfg.rm_db = (void *)&tbl_db->tbl_db[d]; if (tf_session_is_shared_session(tfs) && -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 17/19] net/bnxt: add Tx TruFlow table config for p4 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (15 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 16/19] net/bnxt: add TruFlow and AFM SRAM partitioning support Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 18/19] net/bnxt: remove 2-slice WC entries for scale Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 19/19] net/bnxt: check for mismatch of control and physical port Venkat Duvvuru 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru From: Jay Ding <jay.ding@broadcom.com> Add TX direction TruFlow table type config to be compatible with other devices. For P4, the TX cfg is duplicated from RX. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/tf_core/tf_device.c | 4 +- drivers/net/bnxt/tf_core/tf_device_p4.c | 107 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p4.h | 58 +------------ 3 files changed, 111 insertions(+), 58 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 40db546604..4c416270b6 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -131,11 +131,11 @@ tf_dev_bind_p4(struct tf *tfp, } rsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX, - tf_tbl_p4, + tf_tbl_p4[TF_DIR_RX], (uint16_t *)resources->tbl_cnt); if (rsv_cnt) { tbl_cfg.num_elements = TF_TBL_TYPE_MAX; - tbl_cfg.cfg = tf_tbl_p4; + tbl_cfg.cfg = tf_tbl_p4[TF_DIR_RX]; tbl_cfg.resources = resources; rc = tf_tbl_bind(tfp, &tbl_cfg); if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 244bd08914..a6a59b8a07 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -59,6 +59,113 @@ const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = "tb_scope", }; +struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { + [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_MCAST_GROUPS] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_MCAST_GROUPS] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, + 0, 0 + }, +}; + /** * Device specific function that retrieves the MAX number of HCAPI * types the device supports. diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index e84c0f9e83..86de525995 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -12,6 +12,8 @@ #include "tf_if_tbl.h" #include "tf_global_cfg.h" +extern struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX]; + struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = { [TF_IDENT_TYPE_L2_CTXT_HIGH] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH, @@ -58,62 +60,6 @@ struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = { }, }; -struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = { - [TF_TBL_TYPE_FULL_ACT_RECORD] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, - 0, 0 - }, - [TF_TBL_TYPE_MCAST_GROUPS] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_8B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_16B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_64B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, - 0, 0 - }, - [TF_TBL_TYPE_ACT_STATS_64] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_MODIFY_IPV4] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, - 0, 0 - }, - [TF_TBL_TYPE_METER_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, - 0, 0 - }, - [TF_TBL_TYPE_METER_INST] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, - 0, 0 - }, - [TF_TBL_TYPE_MIRROR_CONFIG] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, - 0, 0 - }, - -}; - struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_TBL_SCOPE] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE, -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 18/19] net/bnxt: remove 2-slice WC entries for scale 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (16 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 17/19] net/bnxt: add Tx TruFlow table config for p4 Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 19/19] net/bnxt: check for mismatch of control and physical port Venkat Duvvuru 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Mike Baucom, Venkat Duvvuru From: Mike Baucom <michael.baucom@broadcom.com> The type-5 WC IPv6 flows were removed in order to increase the scale for app-id=3. The app no longer supports 2-slice WC entries. Signed-off-by: Mike Baucom <michael.baucom@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 14be079eaa..d40d726c58 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -461,7 +461,7 @@ ulp_ctx_shared_session_open(struct bnxt *bp, parms.shadow_copy = true; parms.bp = bp; - if (app_id == 0 || app_id == 3) + if (app_id == 0) parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW; else parms.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW; @@ -583,7 +583,7 @@ ulp_ctx_session_open(struct bnxt *bp, return rc; params.bp = bp; - if (app_id == 0 || app_id == 3) + if (app_id == 0) params.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW; else params.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW; -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v2 19/19] net/bnxt: check for mismatch of control and physical port 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru ` (17 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 18/19] net/bnxt: remove 2-slice WC entries for scale Venkat Duvvuru @ 2021-10-26 5:05 ` Venkat Duvvuru 18 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-10-26 5:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> During the parsing of the ingress port ignore for a flow, added check to match the control port and the physical port that is configured to be ignored. If they do not match then the configuration to setup the svif ignore shall fail. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_port_db.c | 23 +++++++++++++++++++++++ drivers/net/bnxt/tf_ulp/ulp_port_db.h | 13 +++++++++++++ drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 12 ++++++++++++ 3 files changed, 48 insertions(+) diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c index 5e7c1d1c17..f8ffb567b5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c @@ -679,3 +679,26 @@ ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt, } return -EINVAL; } + +/* + * Api to get the phy port for a given port id. + * + * ulp_ctxt [in] Ptr to ulp context + * port_id [in] device port id + * phy_port [out] phy_port of the dpdk port_id + * + * Returns 0 on success or negative number on failure. + */ +int32_t +ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id, uint16_t *phy_port) +{ + struct ulp_func_if_info *info; + + info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id); + if (info) { + *phy_port = info->phy_port_id; + return 0; + } + return -EINVAL; +} diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h index 740c186e12..b112f1a216 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h @@ -314,4 +314,17 @@ int32_t ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt, uint32_t port_id, uint8_t **vnic); +/* + * Api to get the phy port for a given port id. + * + * ulp_ctxt [in] Ptr to ulp context + * port_id [in] device port id + * phy_port [out] phy_port of the dpdk port_id + * + * Returns 0 on success or negative number on failure. + */ +int32_t +ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id, uint16_t *phy_port); + #endif /* _ULP_PORT_DB_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 2ec3279239..f4274dd634 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -686,6 +686,18 @@ ulp_rte_phy_port_hdr_handler(const struct rte_flow_item *item, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SVIF_FLAG, rte_be_to_cpu_16(svif)); if (!mask) { + uint32_t port_id = 0; + uint16_t phy_port = 0; + + /* Validate the control port */ + port_id = ULP_COMP_FLD_IDX_RD(params, + BNXT_ULP_CF_IDX_DEV_PORT_ID); + if (ulp_port_db_phy_port_get(params->ulp_ctx, + port_id, &phy_port) || + (uint16_t)port_spec->index != phy_port) { + BNXT_TF_DBG(ERR, "Mismatch of control and phy_port\n"); + return BNXT_TF_RC_PARSE_ERR; + } ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF_IGNORE); memset(hdr_field->mask, 0xFF, sizeof(mask)); -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow 2021-10-01 5:59 [dpdk-dev] [PATCH 0/9] fixes and enhancements to Truflow Venkat Duvvuru ` (9 preceding siblings ...) 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 01/20] net/bnxt: add NAT support for dest IP and port combination Venkat Duvvuru ` (20 more replies) 10 siblings, 21 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Venkat Duvvuru Enhancements include: * Scaling numbers on Thor * Inner IP header support for GRE tunnel flows * Enable wildcard match for ingress flows * Add clear on read for flow stats on Thor * Add nat support for dest IP and port combination * Remove 2-slice WC support * Add support for socket redirect feature * Add new API TruFlow get SRAM resources * Remove accumulation of stats devargs argument * Add TruFlow and AFM SRAM partitioning support V2: * Compilation fixes * Remove 2-slice WC support * Add support for socket redirect feature * Add new API TruFlow get SRAM resources * Remove accumulation of stats devargs argument * Add TruFlow and AFM SRAM partitioning support V3: * Added one more patch (use enum for bank ID) Farah Smith (1): net/bnxt: add clear on read support Jay Ding (5): net/bnxt: get TruFlow version net/bnxt: add new API TruFlow get SRAM resources net/bnxt: add TruFlow and AFM SRAM partitioning support net/bnxt: add Tx TruFlow table config for p4 device net/bnxt: use enum for bank ID Kishore Padmanabha (11): net/bnxt: add NAT support for dest IP and port combination net/bnxt: add support for multi root capability net/bnxt: fix the out of boundary issue in hash list net/bnxt: add capability option for socket redirect net/bnxt: enable wildcard match for ingress flows net/bnxt: support inner IP header for GRE tunnel flows net/bnxt: remove accumulation of stats devargs argument net/bnxt: updated the log messages net/bnxt: add support for socket direct feature net/bnxt: delete the VF pair before VF representor alloc net/bnxt: check for mismatch of control and physical port Mike Baucom (1): net/bnxt: remove 2-slice WC entries for scale Shahaji Bhosle (2): net/bnxt: increase flow scale for Thor net/bnxt: fix clang compiler warnings drivers/net/bnxt/bnxt.h | 25 +- drivers/net/bnxt/bnxt_cpr.c | 2 +- drivers/net/bnxt/bnxt_ethdev.c | 274 +- drivers/net/bnxt/bnxt_hwrm.c | 36 + drivers/net/bnxt/bnxt_hwrm.h | 1 + drivers/net/bnxt/bnxt_reps.c | 9 +- drivers/net/bnxt/hsi_struct_def_dpdk.h | 2970 +++++++++++-- drivers/net/bnxt/tf_core/tf_core.c | 197 + drivers/net/bnxt/tf_core/tf_core.h | 202 + drivers/net/bnxt/tf_core/tf_device.c | 11 +- drivers/net/bnxt/tf_core/tf_device.h | 102 + drivers/net/bnxt/tf_core/tf_device_p4.c | 178 +- drivers/net/bnxt/tf_core/tf_device_p4.h | 137 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 421 +- drivers/net/bnxt/tf_core/tf_device_p58.h | 205 +- drivers/net/bnxt/tf_core/tf_msg.c | 87 +- drivers/net/bnxt/tf_core/tf_msg.h | 31 +- drivers/net/bnxt/tf_core/tf_rm.c | 3 +- drivers/net/bnxt/tf_core/tf_sram_mgr.h | 10 - drivers/net/bnxt/tf_core/tf_tbl.c | 83 +- drivers/net/bnxt/tf_core/tf_tbl_sram.c | 13 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 58 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 9 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 29 +- .../generic_templates/ulp_template_db_act.c | 376 +- .../generic_templates/ulp_template_db_class.c | 1986 ++++----- .../generic_templates/ulp_template_db_enum.h | 91 +- .../generic_templates/ulp_template_db_tbl.c | 3946 +++++++++++++---- .../ulp_template_db_thor_act.c | 150 +- .../ulp_template_db_thor_class.c | 909 ++-- .../ulp_template_db_wh_plus_act.c | 336 +- .../ulp_template_db_wh_plus_class.c | 222 +- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 8 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 12 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 20 +- drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_port_db.c | 23 + drivers/net/bnxt/tf_ulp/ulp_port_db.h | 13 + drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 32 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +- 41 files changed, 9292 insertions(+), 3931 deletions(-) -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 01/20] net/bnxt: add NAT support for dest IP and port combination 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 02/20] net/bnxt: add support for multi root capability Venkat Duvvuru ` (19 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> * Added support for NAT action for the destination IP and port combination for the Thor platform. This is not supported for Whitney platform. * Consolidated the encapsulation and NAT entries for scaling flows with NAT actions. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- .../generic_templates/ulp_template_db_act.c | 376 +++++++++++------- .../generic_templates/ulp_template_db_enum.h | 18 +- .../generic_templates/ulp_template_db_tbl.c | 14 +- .../ulp_template_db_thor_class.c | 2 +- .../ulp_template_db_wh_plus_act.c | 96 +++-- 5 files changed, 317 insertions(+), 189 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c index 0da6070d7d..ce878d8e02 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon May 17 15:30:41 2021 */ +/* date: Wed Aug 25 14:37:06 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -47,59 +47,67 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { [BNXT_ULP_ACT_HID_04bc] = 30, [BNXT_ULP_ACT_HID_00a9] = 31, [BNXT_ULP_ACT_HID_020f] = 32, - [BNXT_ULP_ACT_HID_04a9] = 33, - [BNXT_ULP_ACT_HID_01fc] = 34, - [BNXT_ULP_ACT_HID_04be] = 35, - [BNXT_ULP_ACT_HID_00ab] = 36, - [BNXT_ULP_ACT_HID_0211] = 37, - [BNXT_ULP_ACT_HID_04ab] = 38, - [BNXT_ULP_ACT_HID_01fe] = 39, - [BNXT_ULP_ACT_HID_0667] = 40, - [BNXT_ULP_ACT_HID_0254] = 41, - [BNXT_ULP_ACT_HID_03ba] = 42, - [BNXT_ULP_ACT_HID_0654] = 43, - [BNXT_ULP_ACT_HID_03a7] = 44, - [BNXT_ULP_ACT_HID_0669] = 45, - [BNXT_ULP_ACT_HID_0256] = 46, - [BNXT_ULP_ACT_HID_03bc] = 47, - [BNXT_ULP_ACT_HID_0656] = 48, - [BNXT_ULP_ACT_HID_03a9] = 49, - [BNXT_ULP_ACT_HID_021b] = 50, - [BNXT_ULP_ACT_HID_021c] = 51, - [BNXT_ULP_ACT_HID_021e] = 52, - [BNXT_ULP_ACT_HID_063f] = 53, - [BNXT_ULP_ACT_HID_0510] = 54, - [BNXT_ULP_ACT_HID_03c6] = 55, - [BNXT_ULP_ACT_HID_0082] = 56, - [BNXT_ULP_ACT_HID_06bb] = 57, - [BNXT_ULP_ACT_HID_021d] = 58, - [BNXT_ULP_ACT_HID_0641] = 59, - [BNXT_ULP_ACT_HID_0512] = 60, - [BNXT_ULP_ACT_HID_03c8] = 61, - [BNXT_ULP_ACT_HID_0084] = 62, - [BNXT_ULP_ACT_HID_06bd] = 63, - [BNXT_ULP_ACT_HID_06d7] = 64, - [BNXT_ULP_ACT_HID_02c4] = 65, - [BNXT_ULP_ACT_HID_042a] = 66, - [BNXT_ULP_ACT_HID_06c4] = 67, - [BNXT_ULP_ACT_HID_0417] = 68, - [BNXT_ULP_ACT_HID_06d9] = 69, - [BNXT_ULP_ACT_HID_02c6] = 70, - [BNXT_ULP_ACT_HID_042c] = 71, - [BNXT_ULP_ACT_HID_06c6] = 72, - [BNXT_ULP_ACT_HID_0419] = 73, - [BNXT_ULP_ACT_HID_0119] = 74, - [BNXT_ULP_ACT_HID_046f] = 75, - [BNXT_ULP_ACT_HID_05d5] = 76, - [BNXT_ULP_ACT_HID_0106] = 77, - [BNXT_ULP_ACT_HID_05c2] = 78, - [BNXT_ULP_ACT_HID_011b] = 79, - [BNXT_ULP_ACT_HID_0471] = 80, - [BNXT_ULP_ACT_HID_05d7] = 81, - [BNXT_ULP_ACT_HID_0108] = 82, - [BNXT_ULP_ACT_HID_05c4] = 83, - [BNXT_ULP_ACT_HID_00a2] = 84, - [BNXT_ULP_ACT_HID_00a4] = 85 + [BNXT_ULP_ACT_HID_0153] = 33, + [BNXT_ULP_ACT_HID_04a9] = 34, + [BNXT_ULP_ACT_HID_01fc] = 35, + [BNXT_ULP_ACT_HID_04be] = 36, + [BNXT_ULP_ACT_HID_00ab] = 37, + [BNXT_ULP_ACT_HID_0211] = 38, + [BNXT_ULP_ACT_HID_0155] = 39, + [BNXT_ULP_ACT_HID_04ab] = 40, + [BNXT_ULP_ACT_HID_01fe] = 41, + [BNXT_ULP_ACT_HID_0667] = 42, + [BNXT_ULP_ACT_HID_0254] = 43, + [BNXT_ULP_ACT_HID_03ba] = 44, + [BNXT_ULP_ACT_HID_02fe] = 45, + [BNXT_ULP_ACT_HID_0654] = 46, + [BNXT_ULP_ACT_HID_03a7] = 47, + [BNXT_ULP_ACT_HID_0669] = 48, + [BNXT_ULP_ACT_HID_0256] = 49, + [BNXT_ULP_ACT_HID_03bc] = 50, + [BNXT_ULP_ACT_HID_0300] = 51, + [BNXT_ULP_ACT_HID_0656] = 52, + [BNXT_ULP_ACT_HID_03a9] = 53, + [BNXT_ULP_ACT_HID_021b] = 54, + [BNXT_ULP_ACT_HID_021c] = 55, + [BNXT_ULP_ACT_HID_021e] = 56, + [BNXT_ULP_ACT_HID_063f] = 57, + [BNXT_ULP_ACT_HID_0510] = 58, + [BNXT_ULP_ACT_HID_03c6] = 59, + [BNXT_ULP_ACT_HID_0082] = 60, + [BNXT_ULP_ACT_HID_06bb] = 61, + [BNXT_ULP_ACT_HID_021d] = 62, + [BNXT_ULP_ACT_HID_0641] = 63, + [BNXT_ULP_ACT_HID_0512] = 64, + [BNXT_ULP_ACT_HID_03c8] = 65, + [BNXT_ULP_ACT_HID_0084] = 66, + [BNXT_ULP_ACT_HID_06bd] = 67, + [BNXT_ULP_ACT_HID_06d7] = 68, + [BNXT_ULP_ACT_HID_02c4] = 69, + [BNXT_ULP_ACT_HID_042a] = 70, + [BNXT_ULP_ACT_HID_036e] = 71, + [BNXT_ULP_ACT_HID_06c4] = 72, + [BNXT_ULP_ACT_HID_0417] = 73, + [BNXT_ULP_ACT_HID_06d9] = 74, + [BNXT_ULP_ACT_HID_02c6] = 75, + [BNXT_ULP_ACT_HID_042c] = 76, + [BNXT_ULP_ACT_HID_0370] = 77, + [BNXT_ULP_ACT_HID_06c6] = 78, + [BNXT_ULP_ACT_HID_0419] = 79, + [BNXT_ULP_ACT_HID_0119] = 80, + [BNXT_ULP_ACT_HID_046f] = 81, + [BNXT_ULP_ACT_HID_05d5] = 82, + [BNXT_ULP_ACT_HID_0519] = 83, + [BNXT_ULP_ACT_HID_0106] = 84, + [BNXT_ULP_ACT_HID_05c2] = 85, + [BNXT_ULP_ACT_HID_011b] = 86, + [BNXT_ULP_ACT_HID_0471] = 87, + [BNXT_ULP_ACT_HID_05d7] = 88, + [BNXT_ULP_ACT_HID_051b] = 89, + [BNXT_ULP_ACT_HID_0108] = 90, + [BNXT_ULP_ACT_HID_05c4] = 91, + [BNXT_ULP_ACT_HID_00a2] = 92, + [BNXT_ULP_ACT_HID_00a4] = 93 }; /* Array for the act matcher list */ @@ -429,22 +437,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 3 }, [33] = { - .act_hid = BNXT_ULP_ACT_HID_04a9, + .act_hid = BNXT_ULP_ACT_HID_0153, .act_pattern_id = 3, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [34] = { - .act_hid = BNXT_ULP_ACT_HID_01fc, + .act_hid = BNXT_ULP_ACT_HID_04a9, .act_pattern_id = 4, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | @@ -452,40 +458,63 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 3 }, [35] = { - .act_hid = BNXT_ULP_ACT_HID_04be, + .act_hid = BNXT_ULP_ACT_HID_01fc, .act_pattern_id = 5, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [36] = { - .act_hid = BNXT_ULP_ACT_HID_00ab, + .act_hid = BNXT_ULP_ACT_HID_04be, .act_pattern_id = 6, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [37] = { - .act_hid = BNXT_ULP_ACT_HID_0211, + .act_hid = BNXT_ULP_ACT_HID_00ab, .act_pattern_id = 7, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [38] = { - .act_hid = BNXT_ULP_ACT_HID_04ab, + .act_hid = BNXT_ULP_ACT_HID_0211, .act_pattern_id = 8, .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [39] = { + .act_hid = BNXT_ULP_ACT_HID_0155, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [40] = { + .act_hid = BNXT_ULP_ACT_HID_04ab, + .act_pattern_id = 10, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -494,9 +523,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [39] = { + [41] = { .act_hid = BNXT_ULP_ACT_HID_01fe, - .act_pattern_id = 9, + .act_pattern_id = 11, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -507,9 +536,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [40] = { + [42] = { .act_hid = BNXT_ULP_ACT_HID_0667, - .act_pattern_id = 10, + .act_pattern_id = 12, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -517,9 +546,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [41] = { + [43] = { .act_hid = BNXT_ULP_ACT_HID_0254, - .act_pattern_id = 11, + .act_pattern_id = 13, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -528,9 +557,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [42] = { + [44] = { .act_hid = BNXT_ULP_ACT_HID_03ba, - .act_pattern_id = 12, + .act_pattern_id = 14, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -538,9 +567,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [43] = { + [45] = { + .act_hid = BNXT_ULP_ACT_HID_02fe, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [46] = { .act_hid = BNXT_ULP_ACT_HID_0654, - .act_pattern_id = 13, + .act_pattern_id = 16, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -550,9 +590,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [44] = { + [47] = { .act_hid = BNXT_ULP_ACT_HID_03a7, - .act_pattern_id = 14, + .act_pattern_id = 17, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -563,9 +603,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [45] = { + [48] = { .act_hid = BNXT_ULP_ACT_HID_0669, - .act_pattern_id = 15, + .act_pattern_id = 18, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -574,9 +614,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [46] = { + [49] = { .act_hid = BNXT_ULP_ACT_HID_0256, - .act_pattern_id = 16, + .act_pattern_id = 19, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -586,9 +626,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [47] = { + [50] = { .act_hid = BNXT_ULP_ACT_HID_03bc, - .act_pattern_id = 17, + .act_pattern_id = 20, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -597,9 +637,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [48] = { + [51] = { + .act_hid = BNXT_ULP_ACT_HID_0300, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [52] = { .act_hid = BNXT_ULP_ACT_HID_0656, - .act_pattern_id = 18, + .act_pattern_id = 22, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -610,9 +662,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [49] = { + [53] = { .act_hid = BNXT_ULP_ACT_HID_03a9, - .act_pattern_id = 19, + .act_pattern_id = 23, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -624,7 +676,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [50] = { + [54] = { .act_hid = BNXT_ULP_ACT_HID_021b, .act_pattern_id = 0, .app_sig = 0, @@ -632,7 +684,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [51] = { + [55] = { .act_hid = BNXT_ULP_ACT_HID_021c, .act_pattern_id = 1, .app_sig = 0, @@ -641,7 +693,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [52] = { + [56] = { .act_hid = BNXT_ULP_ACT_HID_021e, .act_pattern_id = 2, .app_sig = 0, @@ -651,7 +703,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [53] = { + [57] = { .act_hid = BNXT_ULP_ACT_HID_063f, .act_pattern_id = 3, .app_sig = 0, @@ -662,7 +714,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [54] = { + [58] = { .act_hid = BNXT_ULP_ACT_HID_0510, .act_pattern_id = 4, .app_sig = 0, @@ -672,7 +724,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [55] = { + [59] = { .act_hid = BNXT_ULP_ACT_HID_03c6, .act_pattern_id = 5, .app_sig = 0, @@ -681,7 +733,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [56] = { + [60] = { .act_hid = BNXT_ULP_ACT_HID_0082, .act_pattern_id = 6, .app_sig = 0, @@ -693,7 +745,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [57] = { + [61] = { .act_hid = BNXT_ULP_ACT_HID_06bb, .act_pattern_id = 7, .app_sig = 0, @@ -704,7 +756,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [58] = { + [62] = { .act_hid = BNXT_ULP_ACT_HID_021d, .act_pattern_id = 8, .app_sig = 0, @@ -713,7 +765,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [59] = { + [63] = { .act_hid = BNXT_ULP_ACT_HID_0641, .act_pattern_id = 9, .app_sig = 0, @@ -725,7 +777,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [60] = { + [64] = { .act_hid = BNXT_ULP_ACT_HID_0512, .act_pattern_id = 10, .app_sig = 0, @@ -736,7 +788,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [61] = { + [65] = { .act_hid = BNXT_ULP_ACT_HID_03c8, .act_pattern_id = 11, .app_sig = 0, @@ -746,7 +798,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [62] = { + [66] = { .act_hid = BNXT_ULP_ACT_HID_0084, .act_pattern_id = 12, .app_sig = 0, @@ -759,7 +811,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [63] = { + [67] = { .act_hid = BNXT_ULP_ACT_HID_06bd, .act_pattern_id = 13, .app_sig = 0, @@ -771,7 +823,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [64] = { + [68] = { .act_hid = BNXT_ULP_ACT_HID_06d7, .act_pattern_id = 0, .app_sig = 0, @@ -780,7 +832,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [65] = { + [69] = { .act_hid = BNXT_ULP_ACT_HID_02c4, .act_pattern_id = 1, .app_sig = 0, @@ -790,7 +842,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [66] = { + [70] = { .act_hid = BNXT_ULP_ACT_HID_042a, .act_pattern_id = 2, .app_sig = 0, @@ -799,10 +851,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [67] = { - .act_hid = BNXT_ULP_ACT_HID_06c4, + [71] = { + .act_hid = BNXT_ULP_ACT_HID_036e, .act_pattern_id = 3, .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [72] = { + .act_hid = BNXT_ULP_ACT_HID_06c4, + .act_pattern_id = 4, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | @@ -810,9 +872,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [68] = { + [73] = { .act_hid = BNXT_ULP_ACT_HID_0417, - .act_pattern_id = 4, + .act_pattern_id = 5, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -822,9 +884,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [69] = { + [74] = { .act_hid = BNXT_ULP_ACT_HID_06d9, - .act_pattern_id = 5, + .act_pattern_id = 6, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -832,9 +894,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [70] = { + [75] = { .act_hid = BNXT_ULP_ACT_HID_02c6, - .act_pattern_id = 6, + .act_pattern_id = 7, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -843,9 +905,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [71] = { + [76] = { .act_hid = BNXT_ULP_ACT_HID_042c, - .act_pattern_id = 7, + .act_pattern_id = 8, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -853,9 +915,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [72] = { + [77] = { + .act_hid = BNXT_ULP_ACT_HID_0370, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [78] = { .act_hid = BNXT_ULP_ACT_HID_06c6, - .act_pattern_id = 8, + .act_pattern_id = 10, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -865,9 +938,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [73] = { + [79] = { .act_hid = BNXT_ULP_ACT_HID_0419, - .act_pattern_id = 9, + .act_pattern_id = 11, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -878,9 +951,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [74] = { + [80] = { .act_hid = BNXT_ULP_ACT_HID_0119, - .act_pattern_id = 10, + .act_pattern_id = 12, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -888,9 +961,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [75] = { + [81] = { .act_hid = BNXT_ULP_ACT_HID_046f, - .act_pattern_id = 11, + .act_pattern_id = 13, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -899,9 +972,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [76] = { + [82] = { .act_hid = BNXT_ULP_ACT_HID_05d5, - .act_pattern_id = 12, + .act_pattern_id = 14, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -909,9 +982,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [77] = { + [83] = { + .act_hid = BNXT_ULP_ACT_HID_0519, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [84] = { .act_hid = BNXT_ULP_ACT_HID_0106, - .act_pattern_id = 13, + .act_pattern_id = 16, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -921,9 +1005,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [78] = { + [85] = { .act_hid = BNXT_ULP_ACT_HID_05c2, - .act_pattern_id = 14, + .act_pattern_id = 17, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -934,9 +1018,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [79] = { + [86] = { .act_hid = BNXT_ULP_ACT_HID_011b, - .act_pattern_id = 15, + .act_pattern_id = 18, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -945,9 +1029,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [80] = { + [87] = { .act_hid = BNXT_ULP_ACT_HID_0471, - .act_pattern_id = 16, + .act_pattern_id = 19, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -957,9 +1041,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [81] = { + [88] = { .act_hid = BNXT_ULP_ACT_HID_05d7, - .act_pattern_id = 17, + .act_pattern_id = 20, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -968,9 +1052,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [82] = { + [89] = { + .act_hid = BNXT_ULP_ACT_HID_051b, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [90] = { .act_hid = BNXT_ULP_ACT_HID_0108, - .act_pattern_id = 18, + .act_pattern_id = 22, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -981,9 +1077,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [83] = { + [91] = { .act_hid = BNXT_ULP_ACT_HID_05c4, - .act_pattern_id = 19, + .act_pattern_id = 23, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -995,7 +1091,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [84] = { + [92] = { .act_hid = BNXT_ULP_ACT_HID_00a2, .act_pattern_id = 0, .app_sig = 0, @@ -1004,7 +1100,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [85] = { + [93] = { .act_hid = BNXT_ULP_ACT_HID_00a4, .act_pattern_id = 1, .app_sig = 0, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index c016e1940a..fcd460e707 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 20 17:59:14 2021 */ +/* date: Thu Aug 26 17:43:36 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -20,7 +20,7 @@ #define BNXT_ULP_CLASS_HID_SHFTL 28 #define BNXT_ULP_CLASS_HID_MASK 65535 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 -#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86 +#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 94 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 #define BNXT_ULP_ACT_HID_HIGH_PRIME 3793 #define BNXT_ULP_ACT_HID_SHFTR 27 @@ -29,7 +29,7 @@ #define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110 #define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50 -#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278 +#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 277 #define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 @@ -50,11 +50,11 @@ #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313 #define ULP_THOR_CLASS_COND_LIST_SIZE 55 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 -#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35 +#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1 #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536 -#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39 +#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 41 #define ULP_THOR_ACT_TMPL_LIST_SIZE 7 #define ULP_THOR_ACT_TBL_LIST_SIZE 36 #define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16 @@ -2224,21 +2224,25 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_04bc = 0x04bc, BNXT_ULP_ACT_HID_00a9 = 0x00a9, BNXT_ULP_ACT_HID_020f = 0x020f, + BNXT_ULP_ACT_HID_0153 = 0x0153, BNXT_ULP_ACT_HID_04a9 = 0x04a9, BNXT_ULP_ACT_HID_01fc = 0x01fc, BNXT_ULP_ACT_HID_04be = 0x04be, BNXT_ULP_ACT_HID_00ab = 0x00ab, BNXT_ULP_ACT_HID_0211 = 0x0211, + BNXT_ULP_ACT_HID_0155 = 0x0155, BNXT_ULP_ACT_HID_04ab = 0x04ab, BNXT_ULP_ACT_HID_01fe = 0x01fe, BNXT_ULP_ACT_HID_0667 = 0x0667, BNXT_ULP_ACT_HID_0254 = 0x0254, BNXT_ULP_ACT_HID_03ba = 0x03ba, + BNXT_ULP_ACT_HID_02fe = 0x02fe, BNXT_ULP_ACT_HID_0654 = 0x0654, BNXT_ULP_ACT_HID_03a7 = 0x03a7, BNXT_ULP_ACT_HID_0669 = 0x0669, BNXT_ULP_ACT_HID_0256 = 0x0256, BNXT_ULP_ACT_HID_03bc = 0x03bc, + BNXT_ULP_ACT_HID_0300 = 0x0300, BNXT_ULP_ACT_HID_0656 = 0x0656, BNXT_ULP_ACT_HID_03a9 = 0x03a9, BNXT_ULP_ACT_HID_021b = 0x021b, @@ -2258,21 +2262,25 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_06d7 = 0x06d7, BNXT_ULP_ACT_HID_02c4 = 0x02c4, BNXT_ULP_ACT_HID_042a = 0x042a, + BNXT_ULP_ACT_HID_036e = 0x036e, BNXT_ULP_ACT_HID_06c4 = 0x06c4, BNXT_ULP_ACT_HID_0417 = 0x0417, BNXT_ULP_ACT_HID_06d9 = 0x06d9, BNXT_ULP_ACT_HID_02c6 = 0x02c6, BNXT_ULP_ACT_HID_042c = 0x042c, + BNXT_ULP_ACT_HID_0370 = 0x0370, BNXT_ULP_ACT_HID_06c6 = 0x06c6, BNXT_ULP_ACT_HID_0419 = 0x0419, BNXT_ULP_ACT_HID_0119 = 0x0119, BNXT_ULP_ACT_HID_046f = 0x046f, BNXT_ULP_ACT_HID_05d5 = 0x05d5, + BNXT_ULP_ACT_HID_0519 = 0x0519, BNXT_ULP_ACT_HID_0106 = 0x0106, BNXT_ULP_ACT_HID_05c2 = 0x05c2, BNXT_ULP_ACT_HID_011b = 0x011b, BNXT_ULP_ACT_HID_0471 = 0x0471, BNXT_ULP_ACT_HID_05d7 = 0x05d7, + BNXT_ULP_ACT_HID_051b = 0x051b, BNXT_ULP_ACT_HID_0108 = 0x0108, BNXT_ULP_ACT_HID_05c4 = 0x05c4, BNXT_ULP_ACT_HID_00a2 = 0x00a2, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 684fa66f48..84be09b368 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Aug 17 12:16:42 2021 */ +/* date: Thu Aug 26 17:43:36 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -2121,7 +2121,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 2048 }, { .app_id = 0, @@ -2249,7 +2249,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 2048 }, { .app_id = 0, @@ -2263,14 +2263,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, - .count = 32 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 272 diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 68c1e292b2..95205a2421 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 20 18:05:25 2021 */ +/* date: Wed Aug 25 16:41:37 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c index 578ede8bba..4a2d201c2d 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Jun 1 16:05:30 2021 */ +/* date: Wed Aug 25 14:37:06 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -35,7 +35,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { /* act_tid: 3, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, + .num_tbls = 7, .start_tbl_idx = 12, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, @@ -46,30 +46,30 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, - .start_tbl_idx = 18, + .start_tbl_idx = 19, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 20, + .cond_start_idx = 21, .cond_nums = 0 } }, /* act_tid: 5, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 23, + .num_tbls = 7, + .start_tbl_idx = 24, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 28, + .cond_start_idx = 29, .cond_nums = 0 } }, /* act_tid: 6, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, - .start_tbl_idx = 29, + .start_tbl_idx = 31, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 0 } } }; @@ -322,6 +322,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 34, .result_num_fields = 2 }, + { /* act_tid: 3, , table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 15, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, { /* act_tid: 3, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, @@ -332,7 +343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 15, + .cond_start_idx = 16, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -351,7 +362,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 16, + .cond_start_idx = 17, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, @@ -370,7 +381,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, + .cond_start_idx = 18, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, @@ -389,7 +400,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, @@ -410,7 +421,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 18, + .cond_start_idx = 19, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -429,7 +440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 19, + .cond_start_idx = 20, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -449,7 +460,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 21, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -468,7 +479,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 21, + .cond_start_idx = 22, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -489,7 +500,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 23, + .cond_start_idx = 24, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -508,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 25, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -528,7 +539,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 26, + .cond_start_idx = 27, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -538,6 +549,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 11 }, + { /* act_tid: 5, , table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 29, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, { /* act_tid: 5, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, @@ -548,7 +570,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 28, + .cond_start_idx = 30, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -567,7 +589,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, + .cond_start_idx = 31, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, @@ -586,7 +608,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 32, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, @@ -605,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 33, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, @@ -626,7 +648,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, + .cond_start_idx = 33, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -645,7 +667,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, + .cond_start_idx = 34, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -665,7 +687,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -684,7 +706,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 36, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, @@ -705,7 +727,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 37, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, @@ -726,7 +748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 38, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -747,7 +769,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 39, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -766,7 +788,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, + .cond_start_idx = 40, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -844,6 +866,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, + /* cond_execute: act_tid: 3, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, @@ -900,6 +927,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN }, + /* cond_execute: act_tid: 5, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 02/20] net/bnxt: add support for multi root capability 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 01/20] net/bnxt: add NAT support for dest IP and port combination Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 03/20] net/bnxt: fix the out of boundary issue in hash list Venkat Duvvuru ` (18 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Update driver to read the multi root capability and ignore pci address check while creating ulp session when multi root capability is enabled in the hardware. DPDK HSI version updated from 1.10.1.70 to 1.10.2.54. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/bnxt.h | 3 + drivers/net/bnxt/bnxt_hwrm.c | 8 + drivers/net/bnxt/hsi_struct_def_dpdk.h | 2682 +++++++++++++++++++++--- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 10 +- 4 files changed, 2407 insertions(+), 296 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 6743cf92b0..e3e38ffa19 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -723,6 +723,9 @@ struct bnxt { uint16_t chip_num; #define CHIP_NUM_58818 0xd818 #define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818) +#define BNXT_FLAGS2_MULTIROOT_EN BIT(4) +#define BNXT_MULTIROOT_EN(bp) \ + ((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN) uint32_t fw_cap; #define BNXT_FW_CAP_HOT_RESET BIT(0) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 181e607d7b..c7041143a3 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -3394,6 +3394,7 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp) { struct hwrm_func_qcfg_input req = {0}; struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; + uint16_t flags; int rc; if (!BNXT_VF_IS_TRUSTED(bp)) @@ -3417,6 +3418,13 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp) bp->parent->fid = rte_le_to_cpu_16(resp->fid); bp->parent->port_id = rte_le_to_cpu_16(resp->port_id); + flags = rte_le_to_cpu_16(resp->flags); + /* check for the multi-root support */ + if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) { + bp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN; + PMD_DRV_LOG(DEBUG, "PF enabled with multi root capability\n"); + } + HWRM_UNLOCK(); return 0; diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 4d7efb19f4..2a1e6ab97e 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -657,6 +657,8 @@ struct cmd_nums { #define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0) /* PTP - Query extended PTP configuration. */ #define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1) + /* The command is used to allocate KTLS crypto key contexts. */ + #define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -1056,8 +1058,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 44 -#define HWRM_VERSION_STR "1.10.2.44" +#define HWRM_VERSION_RSVD 54 +#define HWRM_VERSION_STR "1.10.2.54" /**************** * hwrm_ver_get * @@ -1357,6 +1359,12 @@ struct hwrm_ver_get_output { */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \ UINT32_C(0x4000) + /* + * If set to 1, then firmware supports secure boot. + * If set to 0, then firmware doesn't support secure boot. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE \ + UINT32_C(0x8000) /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. @@ -8283,8 +8291,14 @@ struct hwrm_async_event_cmpl_reset_notify { /* Fast reset */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \ (UINT32_C(0x4) << 8) + /* + * Reset was a result of a firmware activation. That is, the + * fw_activation flag was set in a FW_RESET operation. + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION \ + (UINT32_C(0x5) << 8) #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION /* * Minimum time before driver should attempt access - units 100ms ticks. * Range 0-65535 @@ -10244,8 +10258,21 @@ struct hwrm_async_event_cmpl_error_report_base { */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \ UINT32_C(0x2) + /* + * There was a low level error with an NVM write or erase. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM \ + UINT32_C(0x3) + /* + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD } __rte_packed; /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ @@ -10386,6 +10413,162 @@ struct hwrm_async_event_cmpl_error_report_invalid_signal { HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL } __rte_packed; +/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_nvm { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Indicates the address where error was detected */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK \ + UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT \ + 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * There was a low level error with an NVM operation. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR + /* The specific type of NVM error */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT \ + 8 + /* + * There was a low level error with an NVM write operation. + * Verification of written data did not match. + * event_data2 will be the failing address. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE \ + (UINT32_C(0x1) << 8) + /* + * There was a low level error with an NVM erase operation. + * All the bits were not erased. + * event_data2 will be the failing address. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE \ + (UINT32_C(0x2) << 8) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT \ + 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD +} __rte_packed; + /* metadata_base_msg (size:64b/8B) */ struct metadata_base_msg { uint16_t md_type_link; @@ -11204,6 +11387,18 @@ struct hwrm_func_vf_cfg_input { */ #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ UINT32_C(0x800) + /* + * This bit must be '1' for the num_tx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the num_rx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS \ + UINT32_C(0x2000) /* * The maximum transmission unit requested on the function. * The HWRM should make sure that the mtu of @@ -11353,7 +11548,10 @@ struct hwrm_func_vf_cfg_input { uint16_t num_stat_ctxs; /* The number of HW ring groups requested for the VF. */ uint16_t num_hw_ring_grps; - uint8_t unused_0[4]; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; } __rte_packed; /* hwrm_func_vf_cfg_output (size:128b/16B) */ @@ -11423,7 +11621,7 @@ struct hwrm_func_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcaps_output (size:704b/88B) */ +/* hwrm_func_qcaps_output (size:768b/96B) */ struct hwrm_func_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -11787,7 +11985,13 @@ struct hwrm_func_qcaps_output { * (max_tx_rings) to the function. */ uint16_t max_sp_tx_rings; - uint8_t unused_0[2]; + /* + * The maximum number of MSI-X vectors that may be allocated across + * all VFs for the function. This is valid only on the PF with SR-IOV + * enabled. Returns zero if this command is called on a PF with + * SR-IOV disabled or on a VF. + */ + uint16_t max_msix_vfs; uint32_t flags_ext; /* * If 1, the device can be configured to set the ECN bits in the @@ -11965,7 +12169,12 @@ struct hwrm_func_qcaps_output { * to the primate processor block. */ #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10) - uint8_t unused_1; + /* + * Maximum number of Key Contexts supported per HWRM + * function call for allocating Key Contexts. + */ + uint16_t max_key_ctxs_alloc; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12023,7 +12232,7 @@ struct hwrm_func_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcfg_output (size:832b/104B) */ +/* hwrm_func_qcfg_output (size:896b/112B) */ struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -12614,7 +12823,11 @@ struct hwrm_func_qcfg_output { * value is used if ring MTU is not specified. */ uint16_t host_mtu; - uint8_t unused_3; + /* Number of Tx Key Contexts allocated. */ + uint16_t alloc_tx_key_ctxs; + /* Number of Rx Key Contexts allocated. */ + uint16_t alloc_rx_key_ctxs; + uint8_t unused_3[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12630,7 +12843,7 @@ struct hwrm_func_qcfg_output { *****************/ -/* hwrm_func_cfg_input (size:832b/104B) */ +/* hwrm_func_cfg_input (size:896b/112B) */ struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -13076,6 +13289,18 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \ UINT32_C(0x20000000) + /* + * This bit must be '1' for the number of Tx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS \ + UINT32_C(0x40000000) + /* + * This bit must be '1' for the number of Rx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS \ + UINT32_C(0x80000000) /* * This field can be used by the admin PF to configure * mtu of foster PFs. @@ -13527,6 +13752,11 @@ struct hwrm_func_cfg_input { * ring that is assigned to a function has a valid mtu. */ uint16_t host_mtu; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; + uint8_t unused_0[4]; } __rte_packed; /* hwrm_func_cfg_output (size:128b/16B) */ @@ -14103,6 +14333,13 @@ struct hwrm_func_drv_rgtr_input { */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \ UINT32_C(0x100) + /* + * When this bit is 1, the function's driver is indicating the + * support of handling the NPAR 1.2 feature where the s-tag may be + * a value other than 0x8100 or 0x88a8. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \ + UINT32_C(0x200) uint32_t enables; /* * This bit must be '1' for the os_type field to be @@ -14664,7 +14901,7 @@ struct hwrm_func_resource_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_resource_qcaps_output (size:448b/56B) */ +/* hwrm_func_resource_qcaps_output (size:512b/64B) */ struct hwrm_func_resource_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -14739,6 +14976,14 @@ struct hwrm_func_resource_qcaps_output { */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output @@ -14755,7 +15000,7 @@ struct hwrm_func_resource_qcaps_output { *****************************/ -/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ +/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ struct hwrm_func_vf_resource_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -14829,6 +15074,14 @@ struct hwrm_func_vf_resource_cfg_input { */ #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; uint8_t unused_0[2]; } __rte_packed; @@ -14858,7 +15111,11 @@ struct hwrm_func_vf_resource_cfg_output { uint16_t reserved_stat_ctx; /* Reserved number of ring groups */ uint16_t reserved_hw_ring_grps; - uint8_t unused_0[7]; + /* Actual number of Tx Key Contexts reserved */ + uint16_t reserved_tx_key_ctxs; + /* Actual number of Rx Key Contexts reserved */ + uint16_t reserved_rx_key_ctxs; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18132,7 +18389,7 @@ struct hwrm_error_recovery_qcfg_output { /*************************** * hwrm_func_echo_response * - ****************************/ + ***************************/ /* hwrm_func_echo_response_input (size:192b/24B) */ @@ -18190,13 +18447,13 @@ struct hwrm_func_echo_response_output { uint8_t valid; } __rte_packed; -/*********************** - * hwrm_func_vlan_qcfg * - ***********************/ +/************************** + * hwrm_func_ptp_pin_qcfg * + **************************/ -/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ -struct hwrm_func_vlan_qcfg_input { +/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_pin_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18225,18 +18482,11 @@ struct hwrm_func_vlan_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[6]; + uint8_t unused_0[8]; } __rte_packed; -/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ -struct hwrm_func_vlan_qcfg_output { +/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18245,32 +18495,94 @@ struct hwrm_func_vlan_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint64_t unused_0; - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * The number of TSIO pins that are configured on this board + * Up to 4 pins can be returned in the response. */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; + uint8_t num_pins; + /* Pin state */ + uint8_t state; /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * When this bit is '1', TSIO pin 0 is enabled. + * When this bit is '0', TSIO pin 0 is disabled. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd2; - /* Future use. */ - uint32_t rsvd3; - uint8_t unused_3[3]; + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED \ + UINT32_C(0x1) + /* + * When this bit is '1', TSIO pin 1 is enabled. + * When this bit is '0', TSIO pin 1 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED \ + UINT32_C(0x2) + /* + * When this bit is '1', TSIO pin 2 is enabled. + * When this bit is '0', TSIO pin 2 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED \ + UINT32_C(0x4) + /* + * When this bit is '1', TSIO pin 3 is enabled. + * When this bit is '0', TSIO pin 3 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED \ + UINT32_C(0x8) + /* Type of function for Pin #0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT + /* Type of function for Pin #1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT + /* Type of function for Pin #2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT + /* Type of function for Pin #3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18281,13 +18593,13 @@ struct hwrm_func_vlan_qcfg_output { uint8_t valid; } __rte_packed; -/********************** - * hwrm_func_vlan_cfg * - **********************/ +/************************* + * hwrm_func_ptp_pin_cfg * + *************************/ -/* hwrm_func_vlan_cfg_input (size:384b/48B) */ -struct hwrm_func_vlan_cfg_input { +/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_pin_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18316,74 +18628,148 @@ struct hwrm_func_vlan_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[2]; uint32_t enables; /* - * This bit must be '1' for the stag_vid field to be + * This bit must be '1' for the pin0_state field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE \ + UINT32_C(0x1) /* - * This bit must be '1' for the ctag_vid field to be + * This bit must be '1' for the pin0_usage field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE \ + UINT32_C(0x2) /* - * This bit must be '1' for the stag_pcp field to be + * This bit must be '1' for the pin1_state field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE \ + UINT32_C(0x4) /* - * This bit must be '1' for the ctag_pcp field to be + * This bit must be '1' for the pin1_usage field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE \ + UINT32_C(0x8) /* - * This bit must be '1' for the stag_tpid field to be + * This bit must be '1' for the pin2_state field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE \ + UINT32_C(0x10) /* - * This bit must be '1' for the ctag_tpid field to be + * This bit must be '1' for the pin2_usage field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE \ + UINT32_C(0x20) /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * This bit must be '1' for the pin3_state field to be + * configured. */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE \ + UINT32_C(0x40) /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * This bit must be '1' for the pin3_usage field to be + * configured. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd1; - /* Future use. */ - uint32_t rsvd2; - uint8_t unused_3[4]; + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE \ + UINT32_C(0x80) + /* Enable or disable functionality of Pin #0. */ + uint8_t pin0_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED + /* Configure function for TSIO pin#0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #1. */ + uint8_t pin1_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED + /* Configure function for TSIO pin#1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #2. */ + uint8_t pin2_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED + /* Configure function for TSIO pin#2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #3. */ + uint8_t pin3_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED + /* Configure function for TSIO pin#3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0[4]; } __rte_packed; -/* hwrm_func_vlan_cfg_output (size:128b/16B) */ -struct hwrm_func_vlan_cfg_output { +/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18403,13 +18789,812 @@ struct hwrm_func_vlan_cfg_output { uint8_t valid; } __rte_packed; -/******************************* - * hwrm_func_vf_vnic_ids_query * - *******************************/ +/********************* + * hwrm_func_ptp_cfg * + *********************/ -/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ -struct hwrm_func_vf_vnic_ids_query_input { +/* hwrm_func_ptp_cfg_input (size:320b/40B) */ +struct hwrm_func_ptp_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the ptp_pps_event field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT \ + UINT32_C(0x1) + /* + * This bit must be '1' for the ptp_freq_adj_dll_source field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the ptp_freq_adj_dll_phase field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the ptp_freq_adj_ext_period field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD \ + UINT32_C(0x8) + /* + * This bit must be '1' for the ptp_freq_adj_ext_up field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP \ + UINT32_C(0x10) + /* + * This bit must be '1' for the ptp_freq_adj_ext_phase field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE \ + UINT32_C(0x20) + /* This field is used to enable interrupt for a specific PPS event. */ + uint8_t ptp_pps_event; + /* + * When this bit is set to '1', interrupt is enabled for internal + * PPS event. Latches timestamp on PPS_OUT TSIO Pin. If user does + * not configure PPS_OUT on a TSIO pin, then firmware will allocate + * PPS_OUT to an unallocated pin. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL \ + UINT32_C(0x1) + /* + * When this bit is set to '1', interrupt is enabled for external + * PPS event. Latches timestamp on PPS_IN TSIO pin. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL \ + UINT32_C(0x2) + /* + * This field is used to set the source signal used to discipline + * PHC (PTP Hardware Clock) + */ + uint8_t ptp_freq_adj_dll_source; + /* No source is selected. Use servo to discipline PHC */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE \ + UINT32_C(0x0) + /* TSIO Pin #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 \ + UINT32_C(0x1) + /* TSIO Pin #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 \ + UINT32_C(0x2) + /* TSIO Pin #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 \ + UINT32_C(0x3) + /* TSIO Pin #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 \ + UINT32_C(0x4) + /* Port #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 \ + UINT32_C(0x5) + /* Port #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 \ + UINT32_C(0x6) + /* Port #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 \ + UINT32_C(0x7) + /* Port #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 \ + UINT32_C(0x8) + /* Invalid signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID \ + UINT32_C(0xff) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID + /* + * This field is used to provide phase adjustment for DLL + * used to discipline PHC (PTP Hardware clock) + */ + uint8_t ptp_freq_adj_dll_phase; + /* No Phase adjustment. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE \ + UINT32_C(0x0) + /* 4Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K \ + UINT32_C(0x1) + /* 8Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K \ + UINT32_C(0x2) + /* 10Mhz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M \ + UINT32_C(0x3) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M + uint8_t unused_0[3]; + /* + * Period in nanoseconds (ns) for external signal + * input. + */ + uint32_t ptp_freq_adj_ext_period; + /* + * Up time in nanoseconds (ns) of the duty cycle + * of the external signal. This value should be + * less than ptp_freq_adj_ext_period. + */ + uint32_t ptp_freq_adj_ext_up; + /* + * Phase value is provided. This field provides the + * least significant 32 bits of the phase input. The + * most significant 16 bits come from + * ptp_freq_adj_ext_phase_upper field. Setting this + * field requires setting ptp_freq_adj_ext_period + * field as well to identify the external signal + * pin. + */ + uint32_t ptp_freq_adj_ext_phase_lower; + /* + * Phase value is provided. The lower 16 bits of this field is used + * with the 32 bit value from ptp_freq_adj_ext_phase_lower + * to provide a 48 bit value input for Phase. + */ + uint32_t ptp_freq_adj_ext_phase_upper; +} __rte_packed; + +/* hwrm_func_ptp_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ts_query * + **************************/ + + +/* hwrm_func_ptp_ts_query_input (size:192b/24B) */ +struct hwrm_func_ptp_ts_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* If set, the response includes PPS event timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1) + /* If set, the response includes PTM timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_ptp_ts_query_output (size:320b/40B) */ +struct hwrm_func_ptp_ts_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Timestamp value of last PPS event latched. */ + uint64_t pps_event_ts; + /* PTM local timestamp value. */ + uint64_t ptm_res_local_ts; + /* PTM Master timestamp value. */ + uint64_t ptm_pmstr_ts; + /* PTM Master propagation delay */ + uint32_t ptm_mstr_prop_dly; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_func_ptp_ext_cfg * + *************************/ + + +/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_ext_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the phc_master_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the phc_sec_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the phc_sec_mode field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the failover_timer field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER \ + UINT32_C(0x8) + /* + * This field is used to configure the Master function. Only this + * function can modify or condition the PHC. Only driver calls from + * this function are allowed to adjust frequency of PHC or configure + * PPS functionality. + * If driver does not specify this FID, then firmware will auto select + * the first function that makes the call to modify PHC as the Master. + */ + uint16_t phc_master_fid; + /* + * This field is used to configure the secondary function. This + * function becomes the Master function in case of failover from + * Master function. + * If driver does not specify this FID, firmware will auto select + * the last non-master function to make a call to condition PHC as + * secondary. + */ + uint16_t phc_sec_fid; + /* + * This field is used to configure conditions under which a function + * can become a secondary function. + */ + uint8_t phc_sec_mode; + /* + * Immediately failover to the current secondary function. If there + * is no secondary function available, failover does not happen. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0) + /* + * All functions (PF and VF) can be used during auto selection + * of a secondary function. This is not used in case of admin + * configured secondary function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1) + /* + * Only PF's can be selected as a secondary function during auto + * selection. This is not used in case of admin configured secondary + * function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2) + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_LAST \ + HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY + uint8_t unused_0; + /* + * This field indicates the failover time is milliseconds. If the + * timeout expires, firmware will failover PTP configurability from + * current master to secondary fid. + * 0 - Failover timer is automatically selected based on the last + * adjFreq() call. If adjFreq() is not called for 3 * (last interval) + * the failover kicks in. For example, if last interval between + * adjFreq() calls was 2 seconds and the next adjFreq() is not made for + * at least 6 seconds, then secondary takes over as master to condition + * PHC. Firmware rounds up the failover timer to be a multiple of 250 + * ms. Firmware checks every 250 ms to see if timer expired. + * 0xFFFFFFFF - If driver specifies this value, then failover never + * happens. Admin or auto selected Master will always be used for + * conditioning PHC. + * X - If driver specifies any other value, this is admin indicated + * failover timeout. If no adjFreq() call is made within this timeout + * value, then failover happens. This value should be a multiple of + * 250 ms. Firmware checks every 250 ms to see if timer expired. + */ + uint32_t failover_timer; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_ext_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ext_qcfg * + **************************/ + + +/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_ext_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ +struct hwrm_func_ptp_ext_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Firmware returns the current PHC master function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_master_fid; + /* + * Firmware returns the current PHC secondary function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_sec_fid; + /* + * Firmware returns the last non-master/non-secondary function to + * make a call to condition PHC. + */ + uint16_t phc_active_fid0; + /* + * Firmware returns the second last non-master/non-secondary function + * to make a call to condition PHC. + */ + uint16_t phc_active_fid1; + /* + * Timestamp indicating the last time a failover happened. The master + * and secondary functions in the failover event is indicated in the + * next two fields. + */ + uint32_t last_failover_event; + /* + * Last failover happened from this function. This was the master + * function at the time of failover. + */ + uint16_t from_fid; + /* + * Last failover happened to this function. This was the secondary + * function at the time of failover. + */ + uint16_t to_fid; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_func_key_ctx_alloc * + ***************************/ + + +/* hwrm_func_key_ctx_alloc_input (size:320b/40B) */ +struct hwrm_func_key_ctx_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Function ID. */ + uint16_t fid; + /* Number of Key Contexts to be allocated. */ + uint16_t num_key_ctxs; + /* DMA buffer size in bytes. */ + uint32_t dma_bufr_size_bytes; + /* Key Context type. */ + uint8_t key_ctx_type; + /* Tx Key Context. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0) + /* Rx KTLS Context. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1) + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST \ + HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX + uint8_t unused_0[7]; + /* Host DMA address to send back KTLS context IDs. */ + uint64_t host_dma_addr; +} __rte_packed; + +/* hwrm_func_key_ctx_alloc_output (size:128b/16B) */ +struct hwrm_func_key_ctx_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Actual number of Key Contexts allocated. */ + uint16_t num_key_ctxs_allocated; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_func_vlan_qcfg * + ***********************/ + + +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ +struct hwrm_func_vlan_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ +struct hwrm_func_vlan_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint64_t unused_0; + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd2; + /* Future use. */ + uint32_t rsvd3; + uint8_t unused_3[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_vlan_cfg * + **********************/ + + +/* hwrm_func_vlan_cfg_input (size:384b/48B) */ +struct hwrm_func_vlan_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[2]; + uint32_t enables; + /* + * This bit must be '1' for the stag_vid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) + /* + * This bit must be '1' for the ctag_vid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) + /* + * This bit must be '1' for the stag_pcp field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) + /* + * This bit must be '1' for the ctag_pcp field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) + /* + * This bit must be '1' for the stag_tpid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) + /* + * This bit must be '1' for the ctag_tpid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd1; + /* Future use. */ + uint32_t rsvd2; + uint8_t unused_3[4]; +} __rte_packed; + +/* hwrm_func_vlan_cfg_output (size:128b/16B) */ +struct hwrm_func_vlan_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_func_vf_vnic_ids_query * + *******************************/ + + +/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ +struct hwrm_func_vf_vnic_ids_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -19128,7 +20313,7 @@ struct hwrm_func_spd_cfg_input { UINT32_C(0x10) /* * Ethertype value used in the encapsulated SPD packet header. - * The user must choose a value that is not conflicting with + * The user must chooose a value that is not conflicting with * publicly defined ethertype values. By default, the ethertype * value of 0xffff is used if there is no user specified value. */ @@ -19387,7 +20572,7 @@ struct hwrm_func_spd_qcfg_output { uint8_t unused_1; /* * Ethertype value used in the encapsulated SPD packet header. - * The user must choose a value that is not conflicting with + * The user must chooose a value that is not conflicting with * publicly defined ethertype values. By default, the ethertype * value of 0xffff is used if there is no user specified value. */ @@ -21398,6 +22583,12 @@ struct hwrm_port_mac_cfg_input { */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \ UINT32_C(0x200) + /* + * This bit must be '1' for the ptp_adj_phase field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE \ + UINT32_C(0x400) /* Port ID of port that is to be configured. */ uint16_t port_id; /* @@ -21590,7 +22781,12 @@ struct hwrm_port_mac_cfg_input { * of sync timer updates (measured in parts per billion). */ int32_t ptp_freq_adj_ppb; - uint8_t unused_1[4]; + /* + * This unsigned field specifies the phase offset to be applied + * to the PHC (PTP Hardware Clock). This field is specified in + * nanoseconds. + */ + uint32_t ptp_adj_phase; } __rte_packed; /* hwrm_port_mac_cfg_output (size:128b/16B) */ @@ -21991,7 +23187,7 @@ struct hwrm_port_mac_ptp_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ +/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ struct hwrm_port_mac_ptp_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -22024,10 +23220,23 @@ struct hwrm_port_mac_ptp_qcfg_output { */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ UINT32_C(0x8) + /* + * When this bit is set to '1', two specific registers for current + * time (ts_ref_clock_reg_lower and ts_ref_clock_reg_upper) are + * directly accessible by the host. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK \ + UINT32_C(0x10) uint8_t unused_0[3]; - /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for RX. */ uint32_t rx_ts_reg_off_seq_id; @@ -22045,9 +23254,15 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t rx_ts_reg_off_fifo_adv; /* PTP timestamp granularity for RX. */ uint32_t rx_ts_reg_off_granularity; - /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for TX. */ uint32_t tx_ts_reg_off_seq_id; @@ -22055,6 +23270,10 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t tx_ts_reg_off_fifo; /* PTP timestamp granularity for TX. */ uint32_t tx_ts_reg_off_granularity; + /* Offset of register to get lower 32 bits of current time. */ + uint32_t ts_ref_clock_reg_lower; + /* Offset of register to get upper 32 bits of current time. */ + uint32_t ts_ref_clock_reg_upper; uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output @@ -22578,7 +23797,7 @@ struct tx_port_stats_ext { } __rte_packed; /* Port Rx Statistics extended Format */ -/* rx_port_stats_ext (size:3648b/456B) */ +/* rx_port_stats_ext (size:3776b/472B) */ struct rx_port_stats_ext { /* Number of times link state changed to down */ uint64_t link_down_events; @@ -22697,6 +23916,13 @@ struct rx_port_stats_ext { uint64_t rx_discard_packets_cos6; /* Total number of rx discard packets count on cos queue 7 */ uint64_t rx_discard_packets_cos7; + /* Total number of FEC blocks corrected by the FEC function in the PHY */ + uint64_t rx_fec_corrected_blocks; + /* + * Total number of FEC blocks determined to be uncorrectable by the + * FEC function in the PHY + */ + uint64_t rx_fec_uncorrectable_blocks; } __rte_packed; /* @@ -25981,6 +27207,309 @@ struct hwrm_port_tx_fir_qcfg_output { uint8_t valid; } __rte_packed; +/*********************** + * hwrm_port_ep_tx_cfg * + ***********************/ + + +/* hwrm_port_ep_tx_cfg_input (size:256b/32B) */ +struct hwrm_port_ep_tx_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* When this bit is '1', the value in the ep0_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1) + /* When this bit is '1', the value in the ep0_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2) + /* When this bit is '1', the value in the ep1_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4) + /* When this bit is '1', the value in the ep1_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8) + /* When this bit is '1', the value in the ep2_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10) + /* When this bit is '1', the value in the ep2_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20) + /* When this bit is '1', the value in the ep3_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40) + /* When this bit is '1', the value in the ep3_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80) + /* A port index, from 0 to the number of front panel ports, minus 1. */ + uint8_t port_id; + uint8_t unused; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set of + * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of + * the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_output (size:128b/16B) */ +struct hwrm_port_ep_tx_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_cmd_err (size:64b/8B) */ +struct hwrm_port_ep_tx_cfg_cmd_err { + /* + * command specific error codes for the cmd_err field in + * hwrm_err_output + */ + uint8_t code; + /* Unknown error. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* The port ID is invalid */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID \ + UINT32_C(0x1) + /* One of the PCIe endpoints configured is not active. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE \ + UINT32_C(0x2) + /* A minimum bandwidth is out of range. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE \ + UINT32_C(0x3) + /* + * One endpoint's minimum bandwidth is more than its maximum + * bandwidth. + */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX \ + UINT32_C(0x4) + /* The sum of the minimum bandwidths on the port is more than 100%. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM \ + UINT32_C(0x5) + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_LAST \ + HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM + uint8_t unused_0[7]; +} __rte_packed; + +/************************ + * hwrm_port_ep_tx_qcfg * + ************************/ + + +/* hwrm_port_ep_tx_qcfg_input (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The port whose endpoint rate limits are queried. */ + uint8_t port_id; + uint8_t unused[7]; +} __rte_packed; + +/* hwrm_port_ep_tx_qcfg_output (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /*********************** * hwrm_queue_qportcfg * ***********************/ @@ -26097,6 +27626,13 @@ struct hwrm_queue_qportcfg_output { */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ UINT32_C(0x1) + /* + * If this flag is set to '1', then service_profile will carry + * either lossy/lossless type and the new service_profile_type + * field will be used to determine if the queue is for L2/ROCE/CNP. + */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE \ + UINT32_C(0x2) /* * Bitmask indicating which queues can be configured by the * hwrm_queue_pfcenable_cfg command. @@ -30204,67 +31740,221 @@ struct hwrm_queue_vlanpri2pri_qcfg_input { * to configure VLAN priority to user priority mapping on this port. */ uint8_t port_id; - uint8_t unused_0[7]; -} __rte_packed; - -/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ -struct hwrm_queue_vlanpri2pri_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ +struct hwrm_queue_vlanpri2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * User priority assigned to VLAN priority 0. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri0_user_pri_id; + /* + * User priority assigned to VLAN priority 1. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri1_user_pri_id; + /* + * User priority assigned to VLAN priority 2. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri2_user_pri_id; + /* + * User priority assigned to VLAN priority 3. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri3_user_pri_id; + /* + * User priority assigned to VLAN priority 4. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri4_user_pri_id; + /* + * User priority assigned to VLAN priority 5. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri5_user_pri_id; + /* + * User priority assigned to VLAN priority 6. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri6_user_pri_id; + /* + * User priority assigned to VLAN priority 7. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri7_user_pri_id; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_queue_vlanpri2pri_cfg * + ******************************/ + + +/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ +struct hwrm_queue_vlanpri2pri_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vlanpri0_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the vlanpri1_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the vlanpri2_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vlanpri3_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the vlanpri4_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the vlanpri5_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the vlanpri6_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the vlanpri7_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ + UINT32_C(0x80) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure VLAN priority to user priority mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[3]; /* - * User priority assigned to VLAN priority 0. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 0. This value can only + * be changed before traffic has started. */ uint8_t vlanpri0_user_pri_id; /* - * User priority assigned to VLAN priority 1. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 1. This value can only + * be changed before traffic has started. */ uint8_t vlanpri1_user_pri_id; /* - * User priority assigned to VLAN priority 2. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 2. This value can only + * be changed before traffic has started. */ uint8_t vlanpri2_user_pri_id; /* - * User priority assigned to VLAN priority 3. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 3. This value can only + * be changed before traffic has started. */ uint8_t vlanpri3_user_pri_id; /* - * User priority assigned to VLAN priority 4. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 4. This value can only + * be changed before traffic has started. */ uint8_t vlanpri4_user_pri_id; /* - * User priority assigned to VLAN priority 5. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 5. This value can only + * be changed before traffic has started. */ uint8_t vlanpri5_user_pri_id; /* - * User priority assigned to VLAN priority 6. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 6. This value can only + * be changed before traffic has started. */ uint8_t vlanpri6_user_pri_id; /* - * User priority assigned to VLAN priority 7. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 7. This value can only + * be changed before traffic has started. */ uint8_t vlanpri7_user_pri_id; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_vlanpri2pri_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -30276,13 +31966,13 @@ struct hwrm_queue_vlanpri2pri_qcfg_output { uint8_t valid; } __rte_packed; -/****************************** - * hwrm_queue_vlanpri2pri_cfg * - ******************************/ +/************************* + * hwrm_queue_global_cfg * + *************************/ -/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ -struct hwrm_queue_vlanpri2pri_cfg_input { +/* hwrm_queue_global_cfg_input (size:192b/24B) */ +struct hwrm_queue_global_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30311,106 +32001,142 @@ struct hwrm_queue_vlanpri2pri_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the vlanpri0_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ - UINT32_C(0x1) - /* - * This bit must be '1' for the vlanpri1_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ - UINT32_C(0x2) /* - * This bit must be '1' for the vlanpri2_user_pri_id field to be - * configured. + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ - UINT32_C(0x4) + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0) /* - * This bit must be '1' for the vlanpri3_user_pri_id field to be - * configured. + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ - UINT32_C(0x8) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT + uint8_t unused_0; + uint16_t enables; + /* This bit must be '1' when the mode field is configured. */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1) /* - * This bit must be '1' for the vlanpri4_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 0 + * (g0_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ - UINT32_C(0x10) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2) /* - * This bit must be '1' for the vlanpri5_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 1 + * (g1_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ - UINT32_C(0x20) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4) /* - * This bit must be '1' for the vlanpri6_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 2 + * (g2_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ - UINT32_C(0x40) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8) /* - * This bit must be '1' for the vlanpri7_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 3 + * (g3_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ - UINT32_C(0x80) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW \ + UINT32_C(0x10) /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure VLAN priority to user priority mapping on this port. + * Specifies the maximum receive rate, as a percentage of total link + * bandwidth, of the receive traffic through queue group 0. A value + * of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. */ - uint8_t port_id; - uint8_t unused_0[3]; + uint8_t g0_max_bw; /* - * User priority assigned to VLAN priority 0. This value can only - * be changed before traffic has started. + * Specifies the maximum rate of the traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. */ - uint8_t vlanpri0_user_pri_id; + uint8_t g1_max_bw; /* - * User priority assigned to VLAN priority 1. This value can only - * be changed before traffic has started. + * Specifies the maximum rate of the traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. */ - uint8_t vlanpri1_user_pri_id; + uint8_t g2_max_bw; /* - * User priority assigned to VLAN priority 2. This value can only - * be changed before traffic has started. + * Specifies the maximum receive rate, in Mbps, of the receive traffic + * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0 + * indicates no rate limit. */ - uint8_t vlanpri2_user_pri_id; + uint8_t g3_max_bw; +} __rte_packed; + +/* hwrm_queue_global_cfg_output (size:128b/16B) */ +struct hwrm_queue_global_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * User priority assigned to VLAN priority 3. This value can only - * be changed before traffic has started. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint8_t vlanpri3_user_pri_id; + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_queue_global_qcfg * + **************************/ + + +/* hwrm_queue_global_qcfg_input (size:128b/16B) */ +struct hwrm_queue_global_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * User priority assigned to VLAN priority 4. This value can only - * be changed before traffic has started. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint8_t vlanpri4_user_pri_id; + uint16_t cmpl_ring; /* - * User priority assigned to VLAN priority 5. This value can only - * be changed before traffic has started. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t vlanpri5_user_pri_id; + uint16_t seq_id; /* - * User priority assigned to VLAN priority 6. This value can only - * be changed before traffic has started. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint8_t vlanpri6_user_pri_id; + uint16_t target_id; /* - * User priority assigned to VLAN priority 7. This value can only - * be changed before traffic has started. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint8_t vlanpri7_user_pri_id; + uint64_t resp_addr; } __rte_packed; -/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_vlanpri2pri_cfg_output { +/* hwrm_queue_global_qcfg_output (size:320b/40B) */ +struct hwrm_queue_global_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30419,7 +32145,95 @@ struct hwrm_queue_vlanpri2pri_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Port or PCIe endpoint id to be mapped for buffer pool 0. */ + uint8_t buffer_pool_id0_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 1. */ + uint8_t buffer_pool_id1_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 2. */ + uint8_t buffer_pool_id2_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 3. */ + uint8_t buffer_pool_id3_map; + /* Size of buffer pool 0 (KBytes). */ + uint32_t buffer_pool_id0_size; + /* Size of buffer pool 1 (KBytes). */ + uint32_t buffer_pool_id1_size; + /* Size of buffer pool 2 (KBytes). */ + uint32_t buffer_pool_id2_size; + /* Size of buffer pool 3 (KBytes). */ + uint32_t buffer_pool_id3_size; + uint16_t flags; + /* + * Enumeration denoting whether the rx buffer pool mapping is + * per port or per PCIe endpoint + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING \ + UINT32_C(0x1) + /* + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a port. + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT \ + UINT32_C(0x0) + /* + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a PCIe endpoint. + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT \ + UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT + /* + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. + */ + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0) + /* + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT + uint8_t unused_0; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 0. The rate limit is a percentage of total link bandwidth. A + * value of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. + */ + uint8_t g0_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g1_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g2_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 3 (for port 3 or PCIe endpoint 3). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g3_max_bw; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -31324,6 +33138,13 @@ struct hwrm_vnic_qcaps_output { */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \ UINT32_C(0x1000) + /* + * When this bit is set '1', it indicates that firmware returns + * INVALID_PARAM error, if host drivers choose invalid hash type + * bit combinations in vnic_rss_cfg. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP \ + UINT32_C(0x2000) /* * This field advertises the maximum concurrent TPA aggregations * supported by the VNIC on new devices that support TPA v2. @@ -31674,7 +33495,34 @@ struct hwrm_vnic_rss_cfg_input { uint64_t hash_key_tbl_addr; /* Index to the rss indirection table. */ uint16_t rss_ctx_idx; - uint8_t unused_1[6]; + uint8_t flags; + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to add to the current + * hash. Zeroes designate the hash_type state bits that should remain + * unchanged, if possible. If this constraint on the existing state + * cannot be satisfied, then the implementation should preference + * adding other headers so as to honor the request to add the + * specified headers. It is an error to set this flag concurrently + * with hash_type_exclude. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to remove from the + * current hash. Zeroes designate the hash_type state bits that + * should remain unchanged, if possible. If this constraint on the + * existing state cannot be satisfied, then the implementation should + * preference removing other headers so as to honor the request to + * remove the specified headers. It is an error to set this flag + * concurrently with hash_type_include. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE \ + UINT32_C(0x2) + uint8_t unused_1[5]; } __rte_packed; /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ @@ -43062,6 +44910,161 @@ struct hwrm_cfa_tflib_output { uint8_t valid; } __rte_packed; +/********************************** + * hwrm_cfa_lag_group_member_rgtr * + **********************************/ + + +/* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t mode; + /* + * Transmit only on the active port. Automatically failover + * to backup port. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP \ + UINT32_C(0x1) + /* + * Transmit based on packet header ntuple hash. Packet with only + * layer 2 headers will hash using the destination MAC, source MAC + * and Ethertype fields. Packets with layer 3 (IP) headers will + * hash using the destination MAC, source MAC, IP protocol/next + * header, source IP address and destination IP address. Packets + * with layer 4 (TCP/UDP) headers will hash using the destination + * MAC, source MAC, IP protocol/next header, source IP address, + * destination IP address, source port and destination port fields. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR \ + UINT32_C(0x2) + /* Transmit packets on all specified ports. */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST \ + UINT32_C(0x3) + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST \ + HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST + /* + * Supports up to 5 ports. bit0 = port 0, bit1 = port 1, + * bit2 = port 2, bit3 = port 4, bit4 = loopback port + */ + uint8_t port_bitmap; + /* Specify the active port when active-backup mode is specified */ + uint8_t active_port; + uint8_t unused_0[5]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************************ + * hwrm_cfa_lag_group_member_unrgtr * + ************************************/ + + +/* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /*********** * hwrm_tf * ***********/ @@ -43263,8 +45266,13 @@ struct hwrm_tf_session_open_output { * the newly created session. */ uint32_t fw_session_client_id; + /* This field is used to return the status of fw session to host. */ uint32_t flags; - /* Indicates if the shared session has been created. */ + /* + * Indicates if the shared session has been created. Shared seesion + * should be the first session created ever. Its fw_rm_client_id + * should be 1. The AFM session's fw_rm_client_id is 0. + */ #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \ UINT32_C(0x1) /* @@ -43745,7 +45753,7 @@ struct hwrm_tf_session_resc_qcaps_input { #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX @@ -43860,7 +45868,7 @@ struct hwrm_tf_session_resc_alloc_input { #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX @@ -43959,7 +45967,7 @@ struct hwrm_tf_session_resc_free_input { #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX @@ -44043,7 +46051,7 @@ struct hwrm_tf_session_resc_flush_input { #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX @@ -44248,7 +46256,7 @@ struct hwrm_tf_tbl_type_get_input { #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX @@ -44337,7 +46345,7 @@ struct hwrm_tf_tbl_type_set_input { #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX @@ -44819,7 +46827,7 @@ struct hwrm_tf_ext_em_qcaps_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \ @@ -44997,7 +47005,7 @@ struct hwrm_tf_ext_em_op_input { #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX @@ -45104,7 +47112,7 @@ struct hwrm_tf_ext_em_cfg_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \ @@ -45309,7 +47317,7 @@ struct hwrm_tf_ext_em_qcfg_input { #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX @@ -45335,7 +47343,7 @@ struct hwrm_tf_ext_em_qcfg_output { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ @@ -45475,7 +47483,7 @@ struct hwrm_tf_em_insert_input { #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX @@ -45556,7 +47564,7 @@ struct hwrm_tf_em_hash_insert_input { #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX @@ -45637,13 +47645,13 @@ struct hwrm_tf_em_delete_input { #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX /* Unused0 */ uint16_t unused0; - /* EM internal flow hanndle. */ + /* EM internal flow handle. */ uint64_t flow_handle; /* EM Key value */ uint64_t em_key[8]; @@ -45785,7 +47793,7 @@ struct hwrm_tf_tcam_set_input { #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX @@ -45887,7 +47895,7 @@ struct hwrm_tf_tcam_get_input { #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX @@ -45983,7 +47991,7 @@ struct hwrm_tf_tcam_move_input { #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX @@ -46066,7 +48074,7 @@ struct hwrm_tf_tcam_free_input { #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX @@ -46149,7 +48157,7 @@ struct hwrm_tf_global_cfg_set_input { #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX @@ -46233,7 +48241,7 @@ struct hwrm_tf_global_cfg_get_input { #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX @@ -46308,7 +48316,7 @@ struct hwrm_tf_if_tbl_get_input { #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX @@ -46397,7 +48405,7 @@ struct hwrm_tf_if_tbl_set_input { #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX @@ -46484,7 +48492,7 @@ struct hwrm_tf_tbl_type_bulk_get_input { #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX @@ -48261,7 +50269,7 @@ struct hwrm_nvm_get_dir_info_output { ******************/ -/* hwrm_nvm_write_input (size:384b/48B) */ +/* hwrm_nvm_write_input (size:448b/56B) */ struct hwrm_nvm_write_input { /* The HWRM command request type. */ uint16_t req_type; @@ -48296,10 +50304,7 @@ struct hwrm_nvm_write_input { * This is where the source data is. */ uint64_t host_src_addr; - /* - * The Directory Entry Type (valid values are defined in the - * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). - */ + /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */ uint16_t dir_type; /* * Directory ordinal. @@ -48311,10 +50316,8 @@ struct hwrm_nvm_write_input { /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ uint16_t dir_attr; /* - * Length of data to write, in bytes.May be - * less than or equal to the allocated size for the directory entry. - * The data length stored in the directory entry will be updated to - * reflect this value once the write is complete. + * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry. + * The data length stored in the directory entry will be updated to reflect this value once the write is complete. */ uint32_t dir_data_length; /* Option. */ @@ -48327,17 +50330,41 @@ struct hwrm_nvm_write_input { #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ UINT32_C(0x1) /* - * The requested length of the allocated NVM for the item, in bytes. - * This value may be greater than or equal to the specified data length (dir_data_length). + * This flag indicates the sender wants to modify a continuous + * NVRAM area using a batch of this HWRM requests. The + * offset of a request must be continuous to the end of previous + * request's. Firmware does not update the directory entry until + * receiving the last request, which is indicated by the batch_last + * flag. This flag is set usually when a sender does not have a + * block of memory that is big enough to hold the entire NVRAM + * data for send at one time. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE \ + UINT32_C(0x2) + /* + * This flag can be used only when the batch_mode flag is set. It + * indicates this request is the last of batch requests. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST \ + UINT32_C(0x4) + /* + * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length). * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, which may - * be greater than the requested item length. - * The purpose for allocating more than the required number of bytes for - * an item's data is to pre-allocate extra storage (padding) to accommodate - * the potential future growth of an item (e.g. upgraded firmware with - * a size increase, log growth, expanded configuration data). + * The response will contain the actual allocated item length, which may be greater than the requested item length. + * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate + * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data). */ uint32_t dir_item_length; + /* + * 32-bit offset of data blob from where data is being written. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t offset; + /* + * Length of data to be written.Should be non-zero. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t len; uint32_t unused_0; } __rte_packed; @@ -48352,10 +50379,8 @@ struct hwrm_nvm_write_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Length of the allocated NVM for the item, in bytes. The value may be - * greater than or equal to the specified data length or the requested item length. - * The actual item length used when creating a new directory entry will - * be a multiple of an NVM block size. + * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length. + * The actual item length used when creating a new directory entry will be a multiple of an NVM block size. */ uint32_t dir_item_length; /* The directory index of the created or modified item. */ @@ -48699,10 +50724,7 @@ struct hwrm_nvm_get_dev_info_output { /* Total size, in bytes of the NVRAM device. */ uint32_t nvram_size; uint32_t reserved_size; - /* - * Available size that can be used, in bytes. Available size is the - * NVRAM size take away the used size and reserved size. - */ + /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */ uint32_t available_size; /* This field represents the major version of NVM cfg */ uint8_t nvm_cfg_ver_maj; @@ -48844,10 +50866,7 @@ struct hwrm_nvm_mod_dir_entry_input { * The (0-based) instance of this Directory Type. */ uint16_t dir_ordinal; - /* - * The Directory Entry Extension flags (see BNX_DIR_EXT_* for - * extension flag definitions). - */ + /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */ uint16_t dir_ext; /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */ uint16_t dir_attr; @@ -49016,10 +51035,8 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \ UINT32_C(0x1) /* - * If set to 1, then unspecified images, images not in the package file, - * will be safely deleted. - * When combined with erase_unused_space then unspecified images will be - * securely erased. + * If set to 1, then unspecified images, images not in the package file, will be safely deleted. + * When combined with erase_unused_space then unspecified images will be securely erased. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ UINT32_C(0x2) @@ -49116,13 +51133,19 @@ struct hwrm_nvm_install_update_cmd_err { */ uint8_t code; /* Unknown error */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) /* Unable to complete operation due to fragmentation */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR \ + UINT32_C(0x1) /* nvm is completely full. */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE \ + UINT32_C(0x2) + /* Firmware update failed due to Anti-rollback. */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \ + UINT32_C(0x3) #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \ - HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE + HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK uint8_t unused_0[7]; } __rte_packed; @@ -49404,10 +51427,7 @@ struct hwrm_nvm_set_variable_input { /* index for the 4th dimensions */ uint16_t index_3; uint8_t flags; - /* - * When this bit is 1, flush internal cache after this write operation - * (see hwrm_nvm_flush command.) - */ + /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */ #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \ UINT32_C(0x1) /* encryption method */ @@ -49589,6 +51609,84 @@ struct hwrm_nvm_validate_option_cmd_err { uint8_t unused_0[7]; } __rte_packed; +/******************* + * hwrm_nvm_defrag * + *******************/ + + +/* hwrm_nvm_defrag_input (size:192b/24B) */ +struct hwrm_nvm_defrag_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* This bit must be '1' to perform NVM defragmentation. */ + #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_nvm_defrag_output (size:128b/16B) */ +struct hwrm_nvm_defrag_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_nvm_defrag_cmd_err (size:64b/8B) */ +struct hwrm_nvm_defrag_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* NVM defragmentation could not be performed */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1) + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST \ + HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL + uint8_t unused_0[7]; +} __rte_packed; + /**************** * hwrm_oem_cmd * ****************/ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index bd57229968..dbc8a3c5bb 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1010,13 +1010,15 @@ ulp_context_initialized(struct bnxt_ulp_session_state *session, bool *init) * pointer, otherwise allocate a new session. */ static struct bnxt_ulp_session_state * -ulp_get_session(struct rte_pci_addr *pci_addr) +ulp_get_session(struct bnxt *bp, struct rte_pci_addr *pci_addr) { struct bnxt_ulp_session_state *session; + /* if multi root capability is enabled, then ignore the pci bus id */ STAILQ_FOREACH(session, &bnxt_ulp_session_list, next) { if (session->pci_info.domain == pci_addr->domain && - session->pci_info.bus == pci_addr->bus) { + (BNXT_MULTIROOT_EN(bp) || + session->pci_info.bus == pci_addr->bus)) { return session; } } @@ -1044,7 +1046,7 @@ ulp_session_init(struct bnxt *bp, pthread_mutex_lock(&bnxt_ulp_global_mutex); - session = ulp_get_session(pci_addr); + session = ulp_get_session(bp, pci_addr); if (!session) { /* Not Found the session Allocate a new one */ session = rte_zmalloc("bnxt_ulp_session", @@ -1547,7 +1549,7 @@ bnxt_ulp_port_deinit(struct bnxt *bp) pci_dev = RTE_DEV_TO_PCI(bp->eth_dev->device); pci_addr = &pci_dev->addr; pthread_mutex_lock(&bnxt_ulp_global_mutex); - session = ulp_get_session(pci_addr); + session = ulp_get_session(bp, pci_addr); pthread_mutex_unlock(&bnxt_ulp_global_mutex); /* session not found then just exit */ -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 03/20] net/bnxt: fix the out of boundary issue in hash list 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 01/20] net/bnxt: add NAT support for dest IP and port combination Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 02/20] net/bnxt: add support for multi root capability Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 04/20] net/bnxt: add clear on read support Venkat Duvvuru ` (17 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> The number of hash bucket list calculation is fixed and added check to limit the out of boundary condition Fixes: 0001cc58d362 ("net/bnxt: support generic hash table") Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c index 3c6e7fe924..84c83de35c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c @@ -16,20 +16,21 @@ int32_t ulp_bit_alloc_list_alloc(struct bit_alloc_list *blist, { uint64_t bentry; uint32_t idx = 0, jdx = 0; + uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES; /* Iterate all numbers that have all 1's */ do { bentry = blist->bdata[idx++]; - } while (bentry == -1UL && idx < blist->bsize); + } while (bentry == -1UL && idx <= bsize_64); - if (idx < blist->bsize) { + if (idx <= bsize_64) { if (bentry) jdx = __builtin_clzl(~bentry); *index = ((idx - 1) * ULP_INDEX_BITMAP_SIZE) + jdx; ULP_INDEX_BITMAP_SET(blist->bdata[(idx - 1)], jdx); return 0; } - jdx = (uint32_t)(blist->bsize * ULP_INDEX_BITMAP_SIZE); + jdx = (uint32_t)(bsize_64 * ULP_INDEX_BITMAP_SIZE); BNXT_TF_DBG(ERR, "bit allocator is full reached max:%x\n", jdx); return -1; } @@ -39,9 +40,10 @@ int32_t ulp_bit_alloc_list_dealloc(struct bit_alloc_list *blist, uint32_t index) { uint32_t idx = 0, jdx; + uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES; idx = index / ULP_INDEX_BITMAP_SIZE; - if (idx >= blist->bsize) { + if (idx >= bsize_64) { BNXT_TF_DBG(ERR, "invalid bit index %x:%x\n", idx, blist->bsize); return -EINVAL; @@ -127,7 +129,8 @@ ulp_gen_hash_tbl_list_init(struct ulp_hash_create_params *cparams, hash_tbl->hash_mask = size - 1; /* allocate the memory for the bit allocator */ - size = (cparams->num_key_entries / sizeof(uint64_t)) + 1; + size = (cparams->num_key_entries / sizeof(uint64_t)); + size = ULP_BYTE_ROUND_OFF_8(size); hash_tbl->bit_list.bsize = size; hash_tbl->bit_list.bdata = rte_zmalloc("Generic hash bit alloc", size, ULP_BUFFER_ALIGN_64_BYTE); @@ -311,7 +314,12 @@ ulp_gen_hash_tbl_list_add(struct ulp_gen_hash_tbl *hash_tbl, BNXT_TF_DBG(ERR, "Error in bit list alloc\n"); return -ENOMEM; } - + if (key_index > hash_tbl->num_key_entries) { + BNXT_TF_DBG(ERR, "reached max size %u:%u\n", key_index, + hash_tbl->num_key_entries); + ulp_bit_alloc_list_dealloc(&hash_tbl->bit_list, key_index); + return -ENOMEM; + } /* Update the hash entry */ ULP_HASH_BUCKET_MARK_INUSE(bucket, (uint16_t)key_index); -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 04/20] net/bnxt: add clear on read support 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (2 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 03/20] net/bnxt: fix the out of boundary issue in hash list Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 05/20] net/bnxt: add capability option for socket redirect Venkat Duvvuru ` (16 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Farah Smith, Kishore Padmanabha, Venkat Duvvuru From: Farah Smith <farah.smith@broadcom.com> Add clear on read stats support for Thor. Currently, the flow stats are not cleared after they are read from the FW. This patch adds support for clear on read. Since clear on read support is added for flow stats in Thor, the flow accumulation is enabled on Thor as well. Signed-off-by: Farah Smith <farah.smith@broadcom.com> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com> --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 34 ++++++++++++++++++++------ drivers/net/bnxt/tf_core/tf_msg.c | 24 +++++++++++++++--- drivers/net/bnxt/tf_core/tf_msg.h | 6 +++-- drivers/net/bnxt/tf_core/tf_tbl.c | 6 +++-- drivers/net/bnxt/tf_core/tf_tbl_sram.c | 13 ++++++++-- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 3 ++- 6 files changed, 67 insertions(+), 19 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 2a1e6ab97e..77981b5cdb 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1058,8 +1058,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 54 -#define HWRM_VERSION_STR "1.10.2.54" +#define HWRM_VERSION_RSVD 55 +#define HWRM_VERSION_STR "1.10.2.55" /**************** * hwrm_ver_get * @@ -46253,13 +46253,22 @@ struct hwrm_tf_tbl_type_get_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entry on read. + */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* @@ -48489,13 +48498,22 @@ struct hwrm_tf_tbl_type_bulk_get_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entries on read. + */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 0fbb2fe837..ea6e2af7ce 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -1851,7 +1851,8 @@ tf_msg_get_tbl_entry(struct tf *tfp, uint16_t hcapi_type, uint16_t size, uint8_t *data, - uint32_t index) + uint32_t index, + bool clear_on_read) { int rc; struct hwrm_tf_tbl_type_get_input req = { 0 }; @@ -1860,6 +1861,7 @@ tf_msg_get_tbl_entry(struct tf *tfp, uint8_t fw_session_id; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t flags = 0; /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); @@ -1889,10 +1891,16 @@ tf_msg_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } + flags = (dir == TF_DIR_TX ? + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX : + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX); + + if (clear_on_read) + flags |= HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ; /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); - req.flags = tfp_cpu_to_le_16(dir); + req.flags = tfp_cpu_to_le_16(flags); req.type = tfp_cpu_to_le_32(hcapi_type); req.index = tfp_cpu_to_le_32(index); @@ -2105,7 +2113,8 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint32_t starting_idx, uint16_t num_entries, uint16_t entry_sz_in_bytes, - uint64_t physical_mem_addr) + uint64_t physical_mem_addr, + bool clear_on_read) { int rc; struct tfp_send_msg_parms parms = { 0 }; @@ -2115,6 +2124,7 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint8_t fw_session_id; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t flags = 0; /* Retrieve the session information */ rc = tf_session_get_session(tfp, &tfs); @@ -2144,10 +2154,16 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } + flags = (dir == TF_DIR_TX ? + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX : + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX); + + if (clear_on_read) + flags |= HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ; /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); - req.flags = tfp_cpu_to_le_16(dir); + req.flags = tfp_cpu_to_le_16(flags); req.type = tfp_cpu_to_le_32(hcapi_type); req.start_index = tfp_cpu_to_le_32(starting_idx); req.num_entries = tfp_cpu_to_le_32(num_entries); diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index b26b15bfa3..718bc2f3b2 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -652,7 +652,8 @@ int tf_msg_get_tbl_entry(struct tf *tfp, uint16_t hcapi_type, uint16_t size, uint8_t *data, - uint32_t index); + uint32_t index, + bool clear_on_read); /* HWRM Tunneled messages */ @@ -704,7 +705,8 @@ int tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint32_t starting_idx, uint16_t num_entries, uint16_t entry_sz_in_bytes, - uint64_t physical_mem_addr); + uint64_t physical_mem_addr, + bool clear_on_read); /** * Sends Set message of a IF Table Type element to the firmware. diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 0a8720e7b6..12eca36491 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -441,7 +441,8 @@ tf_tbl_get(struct tf *tfp, hcapi_type, parms->data_sz_in_bytes, parms->data, - parms->idx); + parms->idx, + false); if (rc) { TFP_DRV_LOG(ERR, "%s, Get failed, type:%s, rc:%s\n", @@ -526,7 +527,8 @@ tf_tbl_bulk_get(struct tf *tfp, parms->starting_idx, parms->num_entries, parms->entry_sz_in_bytes, - parms->physical_mem_addr); + parms->physical_mem_addr, + false); if (rc) { TFP_DRV_LOG(ERR, "%s, Bulk get failed, type:%s, rc:%s\n", diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c index 636811bc2d..567f912dfa 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c +++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c @@ -539,6 +539,7 @@ tf_tbl_sram_get(struct tf *tfp, struct tf_tbl_sram_get_info_parms iparms = { 0 }; struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; void *sram_handle = NULL; + bool clear_on_read = false; TF_CHECK_PARMS3(tfp, parms, parms->data); @@ -608,6 +609,8 @@ tf_tbl_sram_get(struct tf *tfp, strerror(-rc)); return rc; } + if (parms->type == TF_TBL_TYPE_ACT_STATS_64) + clear_on_read = true; /* Get the entry */ rc = tf_msg_get_tbl_entry(tfp, @@ -615,7 +618,8 @@ tf_tbl_sram_get(struct tf *tfp, hcapi_type, parms->data_sz_in_bytes, parms->data, - parms->idx); + parms->idx, + clear_on_read); if (rc) { TFP_DRV_LOG(ERR, "%s, Get failed, type:%s, rc:%s\n", @@ -643,6 +647,7 @@ tf_tbl_sram_bulk_get(struct tf *tfp, struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; bool allocated = false; void *sram_handle = NULL; + bool clear_on_read = false; TF_CHECK_PARMS2(tfp, parms); @@ -728,6 +733,9 @@ tf_tbl_sram_bulk_get(struct tf *tfp, return rc; } + if (parms->type == TF_TBL_TYPE_ACT_STATS_64) + clear_on_read = true; + /* Get the entries */ rc = tf_msg_bulk_get_tbl_entry(tfp, parms->dir, @@ -735,7 +743,8 @@ tf_tbl_sram_bulk_get(struct tf *tfp, parms->starting_idx, parms->num_entries, parms->entry_sz_in_bytes, - parms->physical_mem_addr); + parms->physical_mem_addr, + clear_on_read); if (rc) { TFP_DRV_LOG(ERR, "%s, Bulk get failed, type:%s, rc:%s\n", diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index dbc8a3c5bb..f1763e2519 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1483,7 +1483,8 @@ bnxt_ulp_port_init(struct bnxt *bp) goto jump_to_error; } - if (devid != BNXT_ULP_DEVICE_ID_THOR && BNXT_ACCUM_STATS_EN(bp)) + /* set the accumulation of the stats */ + if (BNXT_ACCUM_STATS_EN(bp)) bp->ulp_ctx->cfg_data->accum_stats = true; BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init, accum_stats:%d\n", -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 05/20] net/bnxt: add capability option for socket redirect 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (3 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 04/20] net/bnxt: add clear on read support Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 06/20] net/bnxt: enable wildcard match for ingress flows Venkat Duvvuru ` (15 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Added support for socket redirect feature capability so applications can enable or disable this feature. This patch contains the template changes. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/bnxt.h | 13 -- drivers/net/bnxt/bnxt_ethdev.c | 203 ------------------ drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 11 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 6 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 10 +- .../generic_templates/ulp_template_db_enum.h | 8 +- .../generic_templates/ulp_template_db_tbl.c | 5 +- 7 files changed, 30 insertions(+), 226 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index e3e38ffa19..c65e360446 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -1054,19 +1054,6 @@ int32_t bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); int32_t bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); -void bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, - uint8_t *mac, uint8_t *parent_mac); -uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); -struct bnxt *bnxt_get_bp(uint16_t port); -uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, - enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_phy_port_id(uint16_t port); -uint16_t bnxt_get_vport(uint16_t port); -enum bnxt_ulp_intf_type -bnxt_get_interface_type(uint16_t port); int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev); void bnxt_cancel_fc_thread(struct bnxt *bp); diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index f385723a9f..bf034db336 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -5056,209 +5056,6 @@ static void bnxt_config_vf_req_fwd(struct bnxt *bp) BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); } -struct bnxt * -bnxt_get_bp(uint16_t port) -{ - struct bnxt *bp; - struct rte_eth_dev *dev; - - if (!rte_eth_dev_is_valid_port(port)) { - PMD_DRV_LOG(ERR, "Invalid port %d\n", port); - return NULL; - } - - dev = &rte_eth_devices[port]; - if (!is_bnxt_supported(dev)) { - PMD_DRV_LOG(ERR, "Device %d not supported\n", port); - return NULL; - } - - bp = (struct bnxt *)dev->data->dev_private; - if (!BNXT_TRUFLOW_EN(bp)) { - PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); - return NULL; - } - - return bp; -} - -uint16_t -bnxt_get_svif(uint16_t port_id, bool func_svif, - enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->svif; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return func_svif ? bp->func_svif : bp->port_svif; -} - -void -bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, - uint8_t *mac, uint8_t *parent_mac) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF && - type != BNXT_ULP_INTF_TYPE_PF) - return; - - eth_dev = &rte_eth_devices[port]; - bp = eth_dev->data->dev_private; - memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN); - - if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF) - memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN); -} - -uint16_t -bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF) - return 0; - - eth_dev = &rte_eth_devices[port]; - bp = eth_dev->data->dev_private; - - return bp->parent->vnic; -} -uint16_t -bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt_vnic_info *vnic; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->dflt_vnic_id; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - vnic = BNXT_GET_DEFAULT_VNIC(bp); - - return vnic->fw_vnic_id; -} - -uint16_t -bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->fw_fid; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return bp->fw_fid; -} - -enum bnxt_ulp_intf_type -bnxt_get_interface_type(uint16_t port) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) - return BNXT_ULP_INTF_TYPE_VF_REP; - - bp = eth_dev->data->dev_private; - if (BNXT_PF(bp)) - return BNXT_ULP_INTF_TYPE_PF; - else if (BNXT_VF_IS_TRUSTED(bp)) - return BNXT_ULP_INTF_TYPE_TRUSTED_VF; - else if (BNXT_VF(bp)) - return BNXT_ULP_INTF_TYPE_VF; - - return BNXT_ULP_INTF_TYPE_INVALID; -} - -uint16_t -bnxt_get_phy_port_id(uint16_t port_id) -{ - struct bnxt_representor *vfr; - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; -} - -uint16_t -bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->fw_fid - 1; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; -} - -uint16_t -bnxt_get_vport(uint16_t port_id) -{ - return (1 << bnxt_get_phy_port_id(port_id)); -} - static void bnxt_alloc_error_recovery_info(struct bnxt *bp) { struct bnxt_error_recovery_info *info = bp->recovery_info; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index f1763e2519..2ac1a8625f 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -301,13 +301,14 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, } int32_t -bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, uint8_t app_id, uint32_t dev_id) { struct bnxt_ulp_app_capabilities_info *info; uint32_t num = 0; uint16_t i; bool found = false; + struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx; if (ULP_APP_DEV_UNSUPPORTED_ENABLED(ulp_ctx->cfg_data->ulp_flags)) { BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", @@ -334,6 +335,12 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, if (info[i].flags & BNXT_ULP_APP_CAP_UNICAST_ONLY) ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_APP_UNICAST_ONLY; + if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) { + /* Enable socket direction only if MR is enabled in fw*/ + if (BNXT_MULTIROOT_EN(bp)) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_SOCKET_DIRECT; + } } if (!found) { BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", @@ -832,7 +839,7 @@ ulp_ctx_init(struct bnxt *bp, } BNXT_TF_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id); - rc = bnxt_ulp_cntxt_app_caps_init(bp->ulp_ctx, bp->app_id, devid); + rc = bnxt_ulp_cntxt_app_caps_init(bp, bp->app_id, devid); if (rc) { BNXT_TF_DBG(ERR, "Unable to set caps for app(%x)/dev(%x)\n", bp->app_id, devid); diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 006df9cbc5..68f1470c61 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -13,6 +13,7 @@ #include "rte_version.h" #include "rte_ethdev.h" +#include "bnxt.h" #include "ulp_template_db_enum.h" #include "ulp_tun.h" #include "bnxt_tf_common.h" @@ -33,12 +34,15 @@ #define BNXT_ULP_APP_DEV_UNSUPPORTED 0x4 #define BNXT_ULP_HIGH_AVAIL_ENABLED 0x8 #define BNXT_ULP_APP_UNICAST_ONLY 0x10 +#define BNXT_ULP_APP_SOCKET_DIRECT 0x20 + #define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED) #define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\ BNXT_ULP_SHARED_SESSION_ENABLED) #define ULP_APP_DEV_UNSUPPORTED_ENABLED(flag) ((flag) &\ BNXT_ULP_APP_DEV_UNSUPPORTED) #define ULP_HIGH_AVAIL_IS_ENABLED(flag) ((flag) & BNXT_ULP_HIGH_AVAIL_ENABLED) +#define ULP_SOCKET_DIRECT_IS_ENABLED(flag) ((flag) & BNXT_ULP_APP_SOCKET_DIRECT) enum bnxt_ulp_flow_mem_type { BNXT_ULP_FLOW_MEM_TYPE_INT = 0, @@ -287,7 +291,7 @@ struct bnxt_ulp_app_capabilities_info * bnxt_ulp_app_cap_list_get(uint32_t *num_entries); int32_t -bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, uint8_t app_id, uint32_t dev_id); struct bnxt_ulp_resource_resv_info * diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 2fec79a388..272195f6a2 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -115,9 +115,11 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FLOW_SIG_ID, params->flow_sig_id); + if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags)) + return; + /* update the WC Priority flag */ - if (!bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags) && - ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) { + if (ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) { enum ulp_ha_mgr_region region = ULP_HA_REGION_LOW; int32_t rc; @@ -129,6 +131,10 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG, 1); } + + /* Update the socket direct flag */ + if (ULP_SOCKET_DIRECT_IS_ENABLED(ulp_flags)) + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT, 1); } /* Function to create the rte flow. */ diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index fcd460e707..31a94c14dc 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Aug 26 17:43:36 2021 */ +/* date: Thu Sep 9 11:11:05 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -211,7 +211,8 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 71, BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72, BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73, - BNXT_ULP_CF_IDX_LAST = 74 + BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74, + BNXT_ULP_CF_IDX_LAST = 75 }; enum bnxt_ulp_cond_list_opc { @@ -582,7 +583,8 @@ enum bnxt_ulp_template_type { enum bnxt_ulp_app_cap { BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001, BNXT_ULP_APP_CAP_HOT_UPGRADE_EN = 0x00000002, - BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004 + BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004, + BNXT_ULP_APP_CAP_SOCKET_DIRECT = 0x00000008 }; enum bnxt_ulp_fdb_resource_flags { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 84be09b368..5383e2cd70 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Aug 26 17:43:36 2021 */ +/* date: Thu Sep 9 11:11:05 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -347,7 +347,8 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { .device_id = BNXT_ULP_DEVICE_ID_THOR, .flags = BNXT_ULP_APP_CAP_SHARED_EN | BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | - BNXT_ULP_APP_CAP_UNICAST_ONLY + BNXT_ULP_APP_CAP_UNICAST_ONLY | + BNXT_ULP_APP_CAP_SOCKET_DIRECT }, { .app_id = 2, -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 06/20] net/bnxt: enable wildcard match for ingress flows 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (4 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 05/20] net/bnxt: add capability option for socket redirect Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 07/20] net/bnxt: support inner IP header for GRE tunnel flows Venkat Duvvuru ` (14 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Enabled wildcard match support for ipv4 ingress flows. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- .../generic_templates/ulp_template_db_class.c | 1986 ++++++++--------- .../generic_templates/ulp_template_db_enum.h | 4 +- .../ulp_template_db_thor_class.c | 251 +-- 3 files changed, 1118 insertions(+), 1123 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c index ad3866243d..1d1e6463e0 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 6 11:15:47 2021 */ +/* date: Thu Sep 16 13:12:05 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -1016,7 +1016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55dd, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1031,7 +1031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1df1, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4104, + .flow_sig_id = 4104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1047,7 +1047,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e55, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1063,7 +1063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0649, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 6152, + .flow_sig_id = 6152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1080,7 +1080,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1011, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1095,7 +1095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40e9, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 16392, + .flow_sig_id = 16392UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1111,7 +1111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e99, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1127,7 +1127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06ad, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 24584, + .flow_sig_id = 24584UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1144,7 +1144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_38c7, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1160,7 +1160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00fb, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32776, + .flow_sig_id = 32776UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1177,7 +1177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_24d3, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1194,7 +1194,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_559b, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32840, + .flow_sig_id = 32840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1212,7 +1212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5003, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1229,7 +1229,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1837, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1247,7 +1247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bef, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1265,7 +1265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0403, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49224, + .flow_sig_id = 49224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1284,7 +1284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d3f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1300,7 +1300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0543, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131080, + .flow_sig_id = 131080UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1317,7 +1317,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_292b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1334,7 +1334,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59e3, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131144, + .flow_sig_id = 131144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1352,7 +1352,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d3b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1369,7 +1369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_254f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196616, + .flow_sig_id = 196616UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1387,7 +1387,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4917, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1405,7 +1405,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_113b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196680, + .flow_sig_id = 196680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1424,7 +1424,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55fd, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1440,7 +1440,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1dd1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 4104, + .flow_sig_id = 4104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1457,7 +1457,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e75, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1474,7 +1474,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0669, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 6152, + .flow_sig_id = 6152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1492,7 +1492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ba1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1509,7 +1509,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c69, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 12296, + .flow_sig_id = 12296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1527,7 +1527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0439, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1545,7 +1545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34e1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 14344, + .flow_sig_id = 14344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1564,7 +1564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0465, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1581,7 +1581,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_352d, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 20488, + .flow_sig_id = 20488UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1599,7 +1599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55b1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1617,7 +1617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1da5, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 22536, + .flow_sig_id = 22536UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1636,7 +1636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_32fd, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1654,7 +1654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_63a5, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 28680, + .flow_sig_id = 28680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1673,7 +1673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1b75, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1692,7 +1692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c3d, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 30728, + .flow_sig_id = 30728UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1712,7 +1712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1031, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1728,7 +1728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40c9, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 16392, + .flow_sig_id = 16392UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1745,7 +1745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3eb9, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1762,7 +1762,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_068d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24584, + .flow_sig_id = 24584UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1780,7 +1780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5039, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1797,7 +1797,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_180d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1815,7 +1815,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15fd, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1833,7 +1833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46b5, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 57352, + .flow_sig_id = 57352UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1852,7 +1852,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_303d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1869,7 +1869,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_60f5, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 81928, + .flow_sig_id = 81928UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1887,7 +1887,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ea5, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1905,7 +1905,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2689, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 90120, + .flow_sig_id = 90120UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1924,7 +1924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0771, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1942,7 +1942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3809, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1961,7 +1961,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35f9, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1980,7 +1980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66b1, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 122888, + .flow_sig_id = 122888UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2000,7 +2000,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_559d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2016,7 +2016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1db1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 4104, + .flow_sig_id = 4104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2033,7 +2033,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e15, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2050,7 +2050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0609, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 6152, + .flow_sig_id = 6152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2068,7 +2068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1bc1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2085,7 +2085,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c09, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 12296, + .flow_sig_id = 12296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2103,7 +2103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0459, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2121,7 +2121,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3481, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14344, + .flow_sig_id = 14344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2140,7 +2140,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0405, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2157,7 +2157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_354d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 20488, + .flow_sig_id = 20488UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2175,7 +2175,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55d1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2193,7 +2193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1dc5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 22536, + .flow_sig_id = 22536UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2212,7 +2212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_329d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2230,7 +2230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_63c5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 28680, + .flow_sig_id = 28680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2249,7 +2249,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1b15, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2268,7 +2268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c5d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 30728, + .flow_sig_id = 30728UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2288,7 +2288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1051, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2304,7 +2304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40a9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16392, + .flow_sig_id = 16392UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2321,7 +2321,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ed9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2338,7 +2338,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06ed, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 24584, + .flow_sig_id = 24584UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2356,7 +2356,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5059, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2373,7 +2373,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_186d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2391,7 +2391,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_159d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2409,7 +2409,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46d5, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 57352, + .flow_sig_id = 57352UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2428,7 +2428,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_305d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2445,7 +2445,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6095, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 81928, + .flow_sig_id = 81928UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2463,7 +2463,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ec5, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2481,7 +2481,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26e9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 90120, + .flow_sig_id = 90120UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2500,7 +2500,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0711, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2518,7 +2518,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3869, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2537,7 +2537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3599, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2556,7 +2556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66d1, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 122888, + .flow_sig_id = 122888UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2576,7 +2576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_38e7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2593,7 +2593,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00db, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32776, + .flow_sig_id = 32776UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2611,7 +2611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_24f3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2629,7 +2629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55bb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32840, + .flow_sig_id = 32840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2648,7 +2648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5023, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2666,7 +2666,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1817, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2685,7 +2685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bcf, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2704,7 +2704,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0423, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49224, + .flow_sig_id = 49224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2724,7 +2724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_58e3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2742,7 +2742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20d7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98312, + .flow_sig_id = 98312UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2761,7 +2761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_448f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2780,7 +2780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0ce3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98376, + .flow_sig_id = 98376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2800,7 +2800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_076b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2819,7 +2819,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3813, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2839,7 +2839,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5bcb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2859,7 +2859,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_243f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114760, + .flow_sig_id = 114760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2880,7 +2880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_144b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2898,7 +2898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4573, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163848, + .flow_sig_id = 163848UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2917,7 +2917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0057, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2936,7 +2936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_311f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163912, + .flow_sig_id = 163912UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2956,7 +2956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2b87, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2975,7 +2975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c4f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180232, + .flow_sig_id = 180232UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2995,7 +2995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1793, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3015,7 +3015,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_485b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180296, + .flow_sig_id = 180296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3036,7 +3036,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3447, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3055,7 +3055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_650f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229384, + .flow_sig_id = 229384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3075,7 +3075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2053, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3095,7 +3095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_511b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229448, + .flow_sig_id = 229448UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3116,7 +3116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4b83, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3136,7 +3136,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13f7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245768, + .flow_sig_id = 245768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3157,7 +3157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_37af, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3178,7 +3178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6857, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245832, + .flow_sig_id = 245832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3200,7 +3200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d1f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3217,7 +3217,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0563, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131080, + .flow_sig_id = 131080UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3235,7 +3235,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_290b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3253,7 +3253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59c3, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131144, + .flow_sig_id = 131144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3272,7 +3272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d1b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3290,7 +3290,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_256f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196616, + .flow_sig_id = 196616UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3309,7 +3309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4937, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3328,7 +3328,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_111b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196680, + .flow_sig_id = 196680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3348,7 +3348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f4b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3366,7 +3366,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_275f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393224, + .flow_sig_id = 393224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3385,7 +3385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4b67, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3404,7 +3404,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_134b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393288, + .flow_sig_id = 393288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3424,7 +3424,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1683, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3443,7 +3443,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_475b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458760, + .flow_sig_id = 458760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3463,7 +3463,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_02bf, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3483,7 +3483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3377, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458824, + .flow_sig_id = 458824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3504,7 +3504,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19db, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3522,7 +3522,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4a93, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655368, + .flow_sig_id = 655368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3541,7 +3541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_05f7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3560,7 +3560,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_368f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655432, + .flow_sig_id = 655432UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3580,7 +3580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39c7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3599,7 +3599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_022b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720904, + .flow_sig_id = 720904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3619,7 +3619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_25f3, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3639,7 +3639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_568b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720968, + .flow_sig_id = 720968UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3660,7 +3660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c37, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3679,7 +3679,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_041b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917512, + .flow_sig_id = 917512UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3699,7 +3699,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2823, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3719,7 +3719,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_58fb, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917576, + .flow_sig_id = 917576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3740,7 +3740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c33, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3760,7 +3760,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2407, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983048, + .flow_sig_id = 983048UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3781,7 +3781,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_482f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3802,7 +3802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1033, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983112, + .flow_sig_id = 983112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3824,7 +3824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3887, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3841,7 +3841,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00bb, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32776, + .flow_sig_id = 32776UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3859,7 +3859,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2493, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3877,7 +3877,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55db, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32840, + .flow_sig_id = 32840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3896,7 +3896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5043, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3914,7 +3914,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1877, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3933,7 +3933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3baf, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3952,7 +3952,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0443, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49224, + .flow_sig_id = 49224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3972,7 +3972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5883, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3990,7 +3990,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20b7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98312, + .flow_sig_id = 98312UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4009,7 +4009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_44ef, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4028,7 +4028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c83, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98376, + .flow_sig_id = 98376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4048,7 +4048,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_070b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4067,7 +4067,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3873, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4087,7 +4087,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5bab, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4107,7 +4107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_245f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114760, + .flow_sig_id = 114760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4128,7 +4128,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_142b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4146,7 +4146,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4513, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163848, + .flow_sig_id = 163848UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4165,7 +4165,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0037, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4184,7 +4184,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_317f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163912, + .flow_sig_id = 163912UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4204,7 +4204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2be7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4223,7 +4223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c2f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180232, + .flow_sig_id = 180232UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4243,7 +4243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_17f3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4263,7 +4263,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_483b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180296, + .flow_sig_id = 180296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4284,7 +4284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3427, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4303,7 +4303,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_656f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229384, + .flow_sig_id = 229384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4323,7 +4323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2033, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4343,7 +4343,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_517b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229448, + .flow_sig_id = 229448UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4364,7 +4364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4be3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4384,7 +4384,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1397, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245768, + .flow_sig_id = 245768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4405,7 +4405,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_37cf, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4426,7 +4426,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6837, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245832, + .flow_sig_id = 245832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4448,7 +4448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d7f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4465,7 +4465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0503, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131080, + .flow_sig_id = 131080UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4483,7 +4483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_296b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4501,7 +4501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59a3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131144, + .flow_sig_id = 131144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4520,7 +4520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d7b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4538,7 +4538,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_250f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196616, + .flow_sig_id = 196616UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4557,7 +4557,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4957, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4576,7 +4576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_117b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196680, + .flow_sig_id = 196680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4596,7 +4596,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f2b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4614,7 +4614,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_273f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393224, + .flow_sig_id = 393224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4633,7 +4633,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4b07, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4652,7 +4652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_132b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393288, + .flow_sig_id = 393288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4672,7 +4672,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_16e3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4691,7 +4691,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_473b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458760, + .flow_sig_id = 458760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4711,7 +4711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_02df, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4731,7 +4731,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3317, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458824, + .flow_sig_id = 458824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4752,7 +4752,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19bb, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4770,7 +4770,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4af3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655368, + .flow_sig_id = 655368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4789,7 +4789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0597, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4808,7 +4808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_36ef, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655432, + .flow_sig_id = 655432UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4828,7 +4828,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39a7, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4847,7 +4847,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_024b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720904, + .flow_sig_id = 720904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4867,7 +4867,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2593, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4887,7 +4887,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_56eb, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720968, + .flow_sig_id = 720968UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4908,7 +4908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c57, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4927,7 +4927,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_047b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917512, + .flow_sig_id = 917512UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4947,7 +4947,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2843, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4967,7 +4967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_589b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917576, + .flow_sig_id = 917576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4988,7 +4988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c53, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5008,7 +5008,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2467, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983048, + .flow_sig_id = 983048UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5029,7 +5029,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_484f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5050,7 +5050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1053, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983112, + .flow_sig_id = 983112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5072,7 +5072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ce1, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5086,7 +5086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4579, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5101,7 +5101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1735, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5115,7 +5115,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_45bd, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5130,7 +5130,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3feb, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5145,7 +5145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bf7, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5161,7 +5161,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5727, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5177,7 +5177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4333, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5194,7 +5194,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4453, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5209,7 +5209,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_304f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5225,7 +5225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_645f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5241,7 +5241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_504b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5258,7 +5258,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5cc1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5273,7 +5273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4559, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5289,7 +5289,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2285, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5305,7 +5305,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b1d, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5322,7 +5322,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b49, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5338,7 +5338,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c95, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5355,7 +5355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39c1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5372,7 +5372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2259, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5390,7 +5390,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1715, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5405,7 +5405,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_459d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5421,7 +5421,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_571d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5437,7 +5437,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cd1, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5454,7 +5454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3711, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5470,7 +5470,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6599, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5487,7 +5487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e55, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5504,7 +5504,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3cdd, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5522,7 +5522,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ca1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5537,7 +5537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4539, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5553,7 +5553,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_22e5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5569,7 +5569,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b7d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5586,7 +5586,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b29, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5602,7 +5602,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5cf5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5619,7 +5619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39a1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5636,7 +5636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2239, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5654,7 +5654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1775, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5669,7 +5669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_45fd, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5685,7 +5685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_577d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5701,7 +5701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cb1, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5718,7 +5718,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3771, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5734,7 +5734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_65f9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5751,7 +5751,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e35, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5768,7 +5768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3cbd, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5786,7 +5786,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3fcb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5802,7 +5802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bd7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5819,7 +5819,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5707, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5836,7 +5836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4313, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5854,7 +5854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5fc7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5871,7 +5871,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4bd3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5889,7 +5889,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e4f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5907,7 +5907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_632f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5926,7 +5926,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1baf, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5943,7 +5943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_07bb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5961,7 +5961,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_32eb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5979,7 +5979,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ef7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5998,7 +5998,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bab, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6016,7 +6016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_27b7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6035,7 +6035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52e7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6054,7 +6054,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ef3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6074,7 +6074,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4473, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6090,7 +6090,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_306f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6107,7 +6107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_647f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6124,7 +6124,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_506b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6142,7 +6142,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66af, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6159,7 +6159,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_525b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6177,7 +6177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1de7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6195,7 +6195,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0993, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6214,7 +6214,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_213f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6231,7 +6231,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d2b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6249,7 +6249,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_413b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6267,7 +6267,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2cd7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6286,7 +6286,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_436b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6304,7 +6304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2f07, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6323,7 +6323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6317, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6342,7 +6342,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4f03, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6362,7 +6362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3fab, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6378,7 +6378,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bb7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6395,7 +6395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5767, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6412,7 +6412,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4373, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6430,7 +6430,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5fa7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6447,7 +6447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4bb3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6465,7 +6465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e2f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6483,7 +6483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_634f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6502,7 +6502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1bcf, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6519,7 +6519,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_07db, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6537,7 +6537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_328b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6555,7 +6555,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1e97, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6574,7 +6574,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bcb, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6592,7 +6592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_27d7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6611,7 +6611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5287, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6630,7 +6630,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e93, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6650,7 +6650,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4413, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6666,7 +6666,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_300f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6683,7 +6683,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_641f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6700,7 +6700,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_500b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6718,7 +6718,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66cf, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6735,7 +6735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_523b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6753,7 +6753,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1d87, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6771,7 +6771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09f3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6790,7 +6790,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_215f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6807,7 +6807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d4b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6825,7 +6825,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_415b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6843,7 +6843,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2cb7, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6862,7 +6862,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_430b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6880,7 +6880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2f67, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6899,7 +6899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6377, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6918,7 +6918,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4f63, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6938,7 +6938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29b5, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -6953,7 +6953,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29ad, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -6968,7 +6968,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29b7, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -6984,7 +6984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1583, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7001,7 +7001,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29af, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7017,7 +7017,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_159b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7034,7 +7034,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2995, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7050,7 +7050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_298d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7066,7 +7066,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29f5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7082,7 +7082,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29ed, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7098,7 +7098,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2997, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7115,7 +7115,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15a3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7133,7 +7133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_298f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7150,7 +7150,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15bb, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7168,7 +7168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29f7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7185,7 +7185,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15c3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7203,7 +7203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29ef, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7220,7 +7220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15db, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7238,7 +7238,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1151, .class_tid = 1, .hdr_sig_id = 12, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 3, .app_sig = 0, .hdr_sig = { .bits = @@ -7255,7 +7255,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_315d, .class_tid = 1, .hdr_sig_id = 12, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 3, .app_sig = 0, .hdr_sig = { .bits = @@ -7273,7 +7273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3612, .class_tid = 2, .hdr_sig_id = 0, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -7292,7 +7292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66da, .class_tid = 2, .hdr_sig_id = 0, - .flow_sig_id = 81928, + .flow_sig_id = 81928UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -7312,7 +7312,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e082, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7332,7 +7332,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ab46, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7353,7 +7353,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c82a, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7374,7 +7374,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f9a2, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7396,7 +7396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d8ce, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 538184704, + .flow_sig_id = 538184704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7417,7 +7417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a2d2, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 538192896, + .flow_sig_id = 538192896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7439,7 +7439,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c076, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 540281856, + .flow_sig_id = 540281856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7461,7 +7461,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f1ee, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 540290048, + .flow_sig_id = 540290048UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7484,7 +7484,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a96e, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1075055616, + .flow_sig_id = 1075055616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7505,7 +7505,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dae6, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1075063808, + .flow_sig_id = 1075063808UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7527,7 +7527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c7aa, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1077152768, + .flow_sig_id = 1077152768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7549,7 +7549,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c26e, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1077160960, + .flow_sig_id = 1077160960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7572,7 +7572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a0fa, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1611926528, + .flow_sig_id = 1611926528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7594,7 +7594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d272, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1611934720, + .flow_sig_id = 1611934720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7617,7 +7617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fff6, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1614023680, + .flow_sig_id = 1614023680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7640,7 +7640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e16e, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1614031872, + .flow_sig_id = 1614031872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7664,7 +7664,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e165, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7684,7 +7684,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aaa1, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7705,7 +7705,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c9cd, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7726,7 +7726,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f845, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7748,7 +7748,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_90f9, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7769,7 +7769,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c371, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7791,7 +7791,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e19d, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7813,7 +7813,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d015, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7836,7 +7836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8c09, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7857,7 +7857,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_be89, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7879,7 +7879,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ddad, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7901,7 +7901,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cc2d, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7924,7 +7924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a4d9, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7946,7 +7946,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d759, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7969,7 +7969,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f27d, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7992,7 +7992,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e4fd, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8016,7 +8016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ecf6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8037,7 +8037,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a732, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8059,7 +8059,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c45e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8081,7 +8081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f5d6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8104,7 +8104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d4ba, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 538184704, + .flow_sig_id = 538184704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8126,7 +8126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aea6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 538192896, + .flow_sig_id = 538192896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8149,7 +8149,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cc02, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 540281856, + .flow_sig_id = 540281856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8172,7 +8172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fd9a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 540290048, + .flow_sig_id = 540290048UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8196,7 +8196,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a51a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1075055616, + .flow_sig_id = 1075055616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8218,7 +8218,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d692, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1075063808, + .flow_sig_id = 1075063808UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8241,7 +8241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cbde, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1077152768, + .flow_sig_id = 1077152768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8264,7 +8264,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce1a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1077160960, + .flow_sig_id = 1077160960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8288,7 +8288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ac8e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1611926528, + .flow_sig_id = 1611926528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8311,7 +8311,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_de06, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1611934720, + .flow_sig_id = 1611934720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8335,7 +8335,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f382, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1614023680, + .flow_sig_id = 1614023680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8359,7 +8359,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ed1a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1614031872, + .flow_sig_id = 1614031872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8384,7 +8384,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9d6a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8406,7 +8406,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cee2, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8429,7 +8429,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ec0e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8452,7 +8452,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dd86, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8476,7 +8476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_852e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2685668352, + .flow_sig_id = 2685668352UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8499,7 +8499,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b6a6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2685676544, + .flow_sig_id = 2685676544UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8523,7 +8523,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_eb82, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2687765504, + .flow_sig_id = 2687765504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8547,7 +8547,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c50a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2687773696, + .flow_sig_id = 2687773696UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8572,7 +8572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ccca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3222539264, + .flow_sig_id = 3222539264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8595,7 +8595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8706, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3222547456, + .flow_sig_id = 3222547456UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8619,7 +8619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d38e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3224636416, + .flow_sig_id = 3224636416UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8643,7 +8643,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d5ca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3224644608, + .flow_sig_id = 3224644608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8668,7 +8668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b48e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3759410176, + .flow_sig_id = 3759410176UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8692,7 +8692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8e8a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3759418368, + .flow_sig_id = 3759418368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8717,7 +8717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_db02, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3761507328, + .flow_sig_id = 3761507328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8742,7 +8742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dd8e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3761515520, + .flow_sig_id = 3761515520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8768,7 +8768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_819a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8790,7 +8790,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b31a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8813,7 +8813,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d03e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8836,7 +8836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c1be, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8860,7 +8860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_890e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4833152000, + .flow_sig_id = 4833152000UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8883,7 +8883,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ba8e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4833160192, + .flow_sig_id = 4833160192UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8907,7 +8907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dfaa, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4835249152, + .flow_sig_id = 4835249152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8931,7 +8931,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c93a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4835257344, + .flow_sig_id = 4835257344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8956,7 +8956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b11a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5370022912, + .flow_sig_id = 5370022912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8979,7 +8979,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8b4e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5370031104, + .flow_sig_id = 5370031104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9003,7 +9003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c79e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5372120064, + .flow_sig_id = 5372120064UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9027,7 +9027,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d9da, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5372128256, + .flow_sig_id = 5372128256UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9052,7 +9052,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b88e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5906893824, + .flow_sig_id = 5906893824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9076,7 +9076,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ea0e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5906902016, + .flow_sig_id = 5906902016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9101,7 +9101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cf0a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5908990976, + .flow_sig_id = 5908990976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9126,7 +9126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c18e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5908999168, + .flow_sig_id = 5908999168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9152,7 +9152,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a94a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9175,7 +9175,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_daca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9199,7 +9199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ffee, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9223,7 +9223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e96e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9248,7 +9248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_910e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6980635648, + .flow_sig_id = 6980635648UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9272,7 +9272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c28e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6980643840, + .flow_sig_id = 6980643840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9297,7 +9297,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e7aa, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6982732800, + .flow_sig_id = 6982732800UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9322,7 +9322,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d12a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6982740992, + .flow_sig_id = 6982740992UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9348,7 +9348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d8ca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7517506560, + .flow_sig_id = 7517506560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9372,7 +9372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_930e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7517514752, + .flow_sig_id = 7517514752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9397,7 +9397,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ef4e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7519603712, + .flow_sig_id = 7519603712UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9422,7 +9422,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e18a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7519611904, + .flow_sig_id = 7519611904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9448,7 +9448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c08e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8054377472, + .flow_sig_id = 8054377472UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9473,7 +9473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9a8a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8054385664, + .flow_sig_id = 8054385664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9499,7 +9499,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d70a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8056474624, + .flow_sig_id = 8056474624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9525,7 +9525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e90e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8056482816, + .flow_sig_id = 8056482816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9552,7 +9552,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_edd9, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9573,7 +9573,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a61d, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9595,7 +9595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c571, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9617,7 +9617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f4f9, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9640,7 +9640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9c45, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9662,7 +9662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cfcd, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9685,7 +9685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ed21, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9708,7 +9708,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dca9, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9732,7 +9732,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_80b5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9754,7 +9754,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b235, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9777,7 +9777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d111, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9800,7 +9800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c091, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9824,7 +9824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a865, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9847,7 +9847,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dbe5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9871,7 +9871,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fec1, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9895,7 +9895,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e841, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9920,7 +9920,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8e85, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8591248384, + .flow_sig_id = 8591248384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9942,7 +9942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b80d, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8591256576, + .flow_sig_id = 8591256576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9965,7 +9965,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_df65, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8593345536, + .flow_sig_id = 8593345536UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9988,7 +9988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ceed, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8593353728, + .flow_sig_id = 8593353728UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10012,7 +10012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9645, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10738732032, + .flow_sig_id = 10738732032UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10035,7 +10035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c1cd, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10738740224, + .flow_sig_id = 10738740224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10059,7 +10059,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e725, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10740829184, + .flow_sig_id = 10740829184UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10083,7 +10083,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d6ad, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10740837376, + .flow_sig_id = 10740837376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10108,7 +10108,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9aa5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12886215680, + .flow_sig_id = 12886215680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10131,7 +10131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b425, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12886223872, + .flow_sig_id = 12886223872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10155,7 +10155,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_eb05, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12888312832, + .flow_sig_id = 12888312832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10179,7 +10179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_da85, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12888321024, + .flow_sig_id = 12888321024UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10204,7 +10204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a265, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15033699328, + .flow_sig_id = 15033699328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10228,7 +10228,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dde5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15033707520, + .flow_sig_id = 15033707520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10253,7 +10253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f0c5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15035796480, + .flow_sig_id = 15035796480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10278,7 +10278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e245, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15035804672, + .flow_sig_id = 15035804672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10304,7 +10304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8b8f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17181182976, + .flow_sig_id = 17181182976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10326,7 +10326,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a517, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17181191168, + .flow_sig_id = 17181191168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10349,7 +10349,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d86b, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17183280128, + .flow_sig_id = 17183280128UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10372,7 +10372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cbf3, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17183288320, + .flow_sig_id = 17183288320UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10396,7 +10396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_934f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19328666624, + .flow_sig_id = 19328666624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10419,7 +10419,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c2c7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19328674816, + .flow_sig_id = 19328674816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10443,7 +10443,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e02b, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19330763776, + .flow_sig_id = 19330763776UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10467,7 +10467,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d3a3, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19330771968, + .flow_sig_id = 19330771968UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10492,7 +10492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_87a7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21476150272, + .flow_sig_id = 21476150272UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10515,7 +10515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b137, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21476158464, + .flow_sig_id = 21476158464UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10539,7 +10539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d403, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21478247424, + .flow_sig_id = 21478247424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10563,7 +10563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c793, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21478255616, + .flow_sig_id = 21478255616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10588,7 +10588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_af67, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23623633920, + .flow_sig_id = 23623633920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10612,7 +10612,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dee7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23623642112, + .flow_sig_id = 23623642112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10637,7 +10637,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fdc3, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23625731072, + .flow_sig_id = 23625731072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10662,7 +10662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ef43, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23625739264, + .flow_sig_id = 23625739264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10688,7 +10688,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8dbf, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25771117568, + .flow_sig_id = 25771117568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10711,7 +10711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_bf07, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25771125760, + .flow_sig_id = 25771125760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10735,7 +10735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d21f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25773214720, + .flow_sig_id = 25773214720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10759,7 +10759,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cde7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25773222912, + .flow_sig_id = 25773222912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10784,7 +10784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_956f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27918601216, + .flow_sig_id = 27918601216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10808,7 +10808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c4c7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27918609408, + .flow_sig_id = 27918609408UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10833,7 +10833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fbcf, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27920698368, + .flow_sig_id = 27920698368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10858,7 +10858,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d5a7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27920706560, + .flow_sig_id = 27920706560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10884,7 +10884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9957, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30066084864, + .flow_sig_id = 30066084864UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10908,7 +10908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cb27, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30066093056, + .flow_sig_id = 30066093056UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10933,7 +10933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ee37, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30068182016, + .flow_sig_id = 30068182016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10958,7 +10958,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d987, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30068190208, + .flow_sig_id = 30068190208UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10984,7 +10984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a107, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32213568512, + .flow_sig_id = 32213568512UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11009,7 +11009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d0e7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32213576704, + .flow_sig_id = 32213576704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11035,7 +11035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f7e7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32215665664, + .flow_sig_id = 32215665664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11061,7 +11061,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c827, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32215673856, + .flow_sig_id = 32215673856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11088,7 +11088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f76a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11109,7 +11109,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_bcae, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11131,7 +11131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dfc2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11153,7 +11153,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ee4a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11176,7 +11176,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cf26, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 538184704, + .flow_sig_id = 538184704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11198,7 +11198,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b53a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 538192896, + .flow_sig_id = 538192896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11221,7 +11221,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d79e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 540281856, + .flow_sig_id = 540281856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11244,7 +11244,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e606, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 540290048, + .flow_sig_id = 540290048UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11268,7 +11268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_be86, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1075055616, + .flow_sig_id = 1075055616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11290,7 +11290,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cd0e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1075063808, + .flow_sig_id = 1075063808UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11313,7 +11313,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d042, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1077152768, + .flow_sig_id = 1077152768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11336,7 +11336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d586, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1077160960, + .flow_sig_id = 1077160960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11360,7 +11360,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b712, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1611926528, + .flow_sig_id = 1611926528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11383,7 +11383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c59a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1611934720, + .flow_sig_id = 1611934720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11407,7 +11407,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e81e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1614023680, + .flow_sig_id = 1614023680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11431,7 +11431,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f686, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1614031872, + .flow_sig_id = 1614031872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11456,7 +11456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_86f6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11478,7 +11478,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d57e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11501,7 +11501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f792, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11524,7 +11524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c61a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11548,7 +11548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9eb2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2685668352, + .flow_sig_id = 2685668352UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11571,7 +11571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ad3a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2685676544, + .flow_sig_id = 2685676544UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11595,7 +11595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f01e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2687765504, + .flow_sig_id = 2687765504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11619,7 +11619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_de96, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2687773696, + .flow_sig_id = 2687773696UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11644,7 +11644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d756, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3222539264, + .flow_sig_id = 3222539264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11667,7 +11667,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9c9a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3222547456, + .flow_sig_id = 3222547456UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11691,7 +11691,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c812, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3224636416, + .flow_sig_id = 3224636416UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11715,7 +11715,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce56, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3224644608, + .flow_sig_id = 3224644608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11740,7 +11740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_af12, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3759410176, + .flow_sig_id = 3759410176UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11764,7 +11764,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9516, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3759418368, + .flow_sig_id = 3759418368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11789,7 +11789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c09e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3761507328, + .flow_sig_id = 3761507328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11814,7 +11814,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c612, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3761515520, + .flow_sig_id = 3761515520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11840,7 +11840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9a06, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11862,7 +11862,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a886, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11885,7 +11885,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cba2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11908,7 +11908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_da22, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11932,7 +11932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9292, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4833152000, + .flow_sig_id = 4833152000UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11955,7 +11955,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a112, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4833160192, + .flow_sig_id = 4833160192UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11979,7 +11979,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c436, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4835249152, + .flow_sig_id = 4835249152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12003,7 +12003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d2a6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4835257344, + .flow_sig_id = 4835257344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12028,7 +12028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aa86, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5370022912, + .flow_sig_id = 5370022912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12051,7 +12051,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_90d2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5370031104, + .flow_sig_id = 5370031104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12075,7 +12075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dc02, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5372120064, + .flow_sig_id = 5372120064UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12099,7 +12099,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c246, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5372128256, + .flow_sig_id = 5372128256UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12124,7 +12124,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a312, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5906893824, + .flow_sig_id = 5906893824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12148,7 +12148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f192, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5906902016, + .flow_sig_id = 5906902016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12173,7 +12173,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d496, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5908990976, + .flow_sig_id = 5908990976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12198,7 +12198,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_da12, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5908999168, + .flow_sig_id = 5908999168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12224,7 +12224,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b2d6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12247,7 +12247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c156, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12271,7 +12271,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e472, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12295,7 +12295,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f2f2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12320,7 +12320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8a92, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6980635648, + .flow_sig_id = 6980635648UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12344,7 +12344,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d912, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6980643840, + .flow_sig_id = 6980643840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12369,7 +12369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fc36, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6982732800, + .flow_sig_id = 6982732800UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12394,7 +12394,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cab6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6982740992, + .flow_sig_id = 6982740992UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12420,7 +12420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c356, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7517506560, + .flow_sig_id = 7517506560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12444,7 +12444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8892, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7517514752, + .flow_sig_id = 7517514752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12469,7 +12469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f4d2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7519603712, + .flow_sig_id = 7519603712UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12494,7 +12494,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fa16, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7519611904, + .flow_sig_id = 7519611904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12520,7 +12520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_db12, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8054377472, + .flow_sig_id = 8054377472UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12545,7 +12545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8116, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8054385664, + .flow_sig_id = 8054385664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12571,7 +12571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cc96, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8056474624, + .flow_sig_id = 8056474624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12597,7 +12597,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f292, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8056482816, + .flow_sig_id = 8056482816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12624,7 +12624,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e84d, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12645,7 +12645,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a389, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12667,7 +12667,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c0e5, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12689,7 +12689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f16d, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12712,7 +12712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_99d1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12734,7 +12734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ca59, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12757,7 +12757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e8b5, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12780,7 +12780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d93d, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12804,7 +12804,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8521, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12826,7 +12826,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b7a1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12849,7 +12849,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d485, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12872,7 +12872,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c505, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12896,7 +12896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_adf1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12919,7 +12919,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_de71, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12943,7 +12943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fb55, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12967,7 +12967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_edd5, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12992,7 +12992,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8b11, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8591248384, + .flow_sig_id = 8591248384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13014,7 +13014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_bd99, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8591256576, + .flow_sig_id = 8591256576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13037,7 +13037,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_daf1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8593345536, + .flow_sig_id = 8593345536UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13060,7 +13060,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cb79, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8593353728, + .flow_sig_id = 8593353728UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13084,7 +13084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_93d1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10738732032, + .flow_sig_id = 10738732032UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13107,7 +13107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c459, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10738740224, + .flow_sig_id = 10738740224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13131,7 +13131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e2b1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10740829184, + .flow_sig_id = 10740829184UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13155,7 +13155,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d339, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10740837376, + .flow_sig_id = 10740837376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13180,7 +13180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9f31, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12886215680, + .flow_sig_id = 12886215680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13203,7 +13203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b1b1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12886223872, + .flow_sig_id = 12886223872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13227,7 +13227,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ee91, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12888312832, + .flow_sig_id = 12888312832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13251,7 +13251,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_df11, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12888321024, + .flow_sig_id = 12888321024UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13276,7 +13276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a7f1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15033699328, + .flow_sig_id = 15033699328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13300,7 +13300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d871, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15033707520, + .flow_sig_id = 15033707520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13325,7 +13325,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f551, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15035796480, + .flow_sig_id = 15035796480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13350,7 +13350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e7d1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15035804672, + .flow_sig_id = 15035804672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13376,7 +13376,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8e1b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17181182976, + .flow_sig_id = 17181182976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13398,7 +13398,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a083, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17181191168, + .flow_sig_id = 17181191168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13421,7 +13421,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ddff, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17183280128, + .flow_sig_id = 17183280128UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13444,7 +13444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce67, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17183288320, + .flow_sig_id = 17183288320UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13468,7 +13468,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_96db, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19328666624, + .flow_sig_id = 19328666624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13491,7 +13491,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c753, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19328674816, + .flow_sig_id = 19328674816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13515,7 +13515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e5bf, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19330763776, + .flow_sig_id = 19330763776UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13539,7 +13539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d637, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19330771968, + .flow_sig_id = 19330771968UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13564,7 +13564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8233, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21476150272, + .flow_sig_id = 21476150272UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13587,7 +13587,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b4a3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21476158464, + .flow_sig_id = 21476158464UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13611,7 +13611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d197, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21478247424, + .flow_sig_id = 21478247424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13635,7 +13635,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c207, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21478255616, + .flow_sig_id = 21478255616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13660,7 +13660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aaf3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23623633920, + .flow_sig_id = 23623633920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13684,7 +13684,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_db73, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23623642112, + .flow_sig_id = 23623642112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13709,7 +13709,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f857, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23625731072, + .flow_sig_id = 23625731072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13734,7 +13734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ead7, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23625739264, + .flow_sig_id = 23625739264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13760,7 +13760,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_882b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25771117568, + .flow_sig_id = 25771117568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13783,7 +13783,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ba93, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25771125760, + .flow_sig_id = 25771125760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13807,7 +13807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d78b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25773214720, + .flow_sig_id = 25773214720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13831,7 +13831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c873, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25773222912, + .flow_sig_id = 25773222912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13856,7 +13856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_90fb, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27918601216, + .flow_sig_id = 27918601216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13880,7 +13880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c153, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27918609408, + .flow_sig_id = 27918609408UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13905,7 +13905,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fe5b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27920698368, + .flow_sig_id = 27920698368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13930,7 +13930,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d033, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27920706560, + .flow_sig_id = 27920706560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13956,7 +13956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9cc3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30066084864, + .flow_sig_id = 30066084864UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13980,7 +13980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ceb3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30066093056, + .flow_sig_id = 30066093056UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14005,7 +14005,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_eba3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30068182016, + .flow_sig_id = 30068182016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14030,7 +14030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dc13, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30068190208, + .flow_sig_id = 30068190208UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14056,7 +14056,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a493, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32213568512, + .flow_sig_id = 32213568512UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14081,7 +14081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d573, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32213576704, + .flow_sig_id = 32213576704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14107,7 +14107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f273, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32215665664, + .flow_sig_id = 32215665664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14133,7 +14133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cdb3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32215673856, + .flow_sig_id = 32215673856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14160,7 +14160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ff35, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14181,7 +14181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b4f1, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14203,7 +14203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d79d, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14225,7 +14225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e615, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14248,7 +14248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8ea9, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14270,7 +14270,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dd21, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14293,7 +14293,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ffcd, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14316,7 +14316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce45, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14340,7 +14340,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9259, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14362,7 +14362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a0d9, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14385,7 +14385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c3fd, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14408,7 +14408,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d27d, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14432,7 +14432,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ba89, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14455,7 +14455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c909, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14479,7 +14479,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ec2d, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14503,7 +14503,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_faad, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14528,7 +14528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34c6, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14543,7 +14543,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c22, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4100, + .flow_sig_id = 4100UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14559,7 +14559,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cbe, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14575,7 +14575,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_179a, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 6148, + .flow_sig_id = 6148UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14592,7 +14592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59be, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14607,7 +14607,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_515a, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 16388, + .flow_sig_id = 16388UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14623,7 +14623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c72, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14639,7 +14639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_171e, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 24580, + .flow_sig_id = 24580UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14656,7 +14656,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19c8, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14672,7 +14672,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_112c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32772, + .flow_sig_id = 32772UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14689,7 +14689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d68, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14706,7 +14706,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_444c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32836, + .flow_sig_id = 32836UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14724,7 +14724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e8c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14741,7 +14741,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09e0, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14759,7 +14759,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1af0, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14777,7 +14777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15d4, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49220, + .flow_sig_id = 49220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14796,7 +14796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1dd0, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14812,7 +14812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14f4, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131076, + .flow_sig_id = 131076UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14829,7 +14829,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_70b0, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14846,7 +14846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4854, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131140, + .flow_sig_id = 131140UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14864,7 +14864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3dd4, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14881,7 +14881,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34f8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196612, + .flow_sig_id = 196612UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14899,7 +14899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09e8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14917,7 +14917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_008c, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196676, + .flow_sig_id = 196676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14936,7 +14936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34e6, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14952,7 +14952,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c02, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4100, + .flow_sig_id = 4100UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14969,7 +14969,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c9e, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14986,7 +14986,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_17ba, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 6148, + .flow_sig_id = 6148UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15004,7 +15004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_429e, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15021,7 +15021,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5dba, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 12292, + .flow_sig_id = 12292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15039,7 +15039,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a16, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15057,7 +15057,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2532, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 14340, + .flow_sig_id = 14340UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15076,7 +15076,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2da2, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15093,7 +15093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_24fe, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 20484, + .flow_sig_id = 20484UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15111,7 +15111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_355a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15129,7 +15129,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c76, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 22532, + .flow_sig_id = 22532UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15148,7 +15148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13e6, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15166,7 +15166,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7276, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 28676, + .flow_sig_id = 28676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15185,7 +15185,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_42d2, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15204,7 +15204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5dee, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 30724, + .flow_sig_id = 30724UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15224,7 +15224,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59de, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15240,7 +15240,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_513a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 16388, + .flow_sig_id = 16388UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15257,7 +15257,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c12, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15274,7 +15274,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_177e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 24580, + .flow_sig_id = 24580UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15292,7 +15292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e92, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15309,7 +15309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09fe, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15327,7 +15327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c1a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15345,7 +15345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5746, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 57348, + .flow_sig_id = 57348UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15364,7 +15364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_79da, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15381,7 +15381,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7106, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 81924, + .flow_sig_id = 81924UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15399,7 +15399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c1e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15417,7 +15417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_377a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 90116, + .flow_sig_id = 90116UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15436,7 +15436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e9e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15454,7 +15454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29fa, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15473,7 +15473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14d2, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15492,7 +15492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7742, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 122884, + .flow_sig_id = 122884UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15512,7 +15512,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3706, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15528,7 +15528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0fe2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4100, + .flow_sig_id = 4100UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15545,7 +15545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1f7e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15562,7 +15562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_145a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 6148, + .flow_sig_id = 6148UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15580,7 +15580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_417e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15597,7 +15597,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e5a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 12292, + .flow_sig_id = 12292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15615,7 +15615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29f6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15633,7 +15633,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26d2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 14340, + .flow_sig_id = 14340UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15652,7 +15652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e42, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15669,7 +15669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_271e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 20484, + .flow_sig_id = 20484UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15687,7 +15687,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_36ba, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15705,7 +15705,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0f96, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 22532, + .flow_sig_id = 22532UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15724,7 +15724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1006, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15742,7 +15742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7196, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 28676, + .flow_sig_id = 28676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15761,7 +15761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4132, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15780,7 +15780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e0e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 30724, + .flow_sig_id = 30724UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15800,7 +15800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59fe, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15816,7 +15816,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_511a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 16388, + .flow_sig_id = 16388UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15833,7 +15833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c32, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15850,7 +15850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_175e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 24580, + .flow_sig_id = 24580UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15868,7 +15868,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0eb2, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15885,7 +15885,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09de, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15903,7 +15903,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c3a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15921,7 +15921,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5766, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 57348, + .flow_sig_id = 57348UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15940,7 +15940,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_79fa, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15957,7 +15957,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7126, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 81924, + .flow_sig_id = 81924UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15975,7 +15975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c3e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15993,7 +15993,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_375a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 90116, + .flow_sig_id = 90116UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16012,7 +16012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2ebe, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16030,7 +16030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29da, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16049,7 +16049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14f2, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16068,7 +16068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7762, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 122884, + .flow_sig_id = 122884UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16088,7 +16088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19e8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16105,7 +16105,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_110c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32772, + .flow_sig_id = 32772UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16123,7 +16123,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d48, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16141,7 +16141,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_446c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32836, + .flow_sig_id = 32836UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16160,7 +16160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0eac, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16178,7 +16178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09c0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16197,7 +16197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ad0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16216,7 +16216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15f4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49220, + .flow_sig_id = 49220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16236,7 +16236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39ec, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16254,7 +16254,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3100, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98308, + .flow_sig_id = 98308UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16273,7 +16273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0210, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16292,7 +16292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1d34, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98372, + .flow_sig_id = 98372UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16312,7 +16312,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2ea0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16331,7 +16331,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29c4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16351,7 +16351,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ad4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16371,7 +16371,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35e8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114756, + .flow_sig_id = 114756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16392,7 +16392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d80, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16410,7 +16410,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_54a4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163844, + .flow_sig_id = 163844UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16429,7 +16429,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29b4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16448,7 +16448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20c8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163908, + .flow_sig_id = 163908UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16468,7 +16468,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7244, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16487,7 +16487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d98, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180228, + .flow_sig_id = 180228UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16507,7 +16507,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e68, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16527,7 +16527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_598c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180292, + .flow_sig_id = 180292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16548,7 +16548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1248, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16567,7 +16567,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_74d8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229380, + .flow_sig_id = 229380UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16587,7 +16587,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_49a8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16607,7 +16607,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40cc, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229444, + .flow_sig_id = 229444UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16628,7 +16628,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b0c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16648,7 +16648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0220, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245764, + .flow_sig_id = 245764UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16669,7 +16669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1730, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16690,7 +16690,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7980, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245828, + .flow_sig_id = 245828UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16712,7 +16712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1db0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16729,7 +16729,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1494, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131076, + .flow_sig_id = 131076UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16747,7 +16747,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_70d0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16765,7 +16765,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4834, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131140, + .flow_sig_id = 131140UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16784,7 +16784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3db4, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16802,7 +16802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3498, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196612, + .flow_sig_id = 196612UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16821,7 +16821,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0988, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16840,7 +16840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00ec, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196676, + .flow_sig_id = 196676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16860,7 +16860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3f44, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16878,7 +16878,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_36a8, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393220, + .flow_sig_id = 393220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16897,7 +16897,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b58, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16916,7 +16916,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_02bc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393284, + .flow_sig_id = 393284UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16936,7 +16936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f48, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16955,7 +16955,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_56ac, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458756, + .flow_sig_id = 458756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16975,7 +16975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2b5c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16995,7 +16995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2280, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458820, + .flow_sig_id = 458820UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17016,7 +17016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4000, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17034,7 +17034,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5b64, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655364, + .flow_sig_id = 655364UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17053,7 +17053,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2c14, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17072,7 +17072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2778, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655428, + .flow_sig_id = 655428UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17092,7 +17092,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_18f8, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17111,7 +17111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13dc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720900, + .flow_sig_id = 720900UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17131,7 +17131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c18, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17151,7 +17151,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_477c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720964, + .flow_sig_id = 720964UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17172,7 +17172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1a88, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17191,7 +17191,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15ec, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917508, + .flow_sig_id = 917508UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17211,7 +17211,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e28, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17231,7 +17231,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_490c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917572, + .flow_sig_id = 917572UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17252,7 +17252,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a8c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17272,7 +17272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35f0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983044, + .flow_sig_id = 983044UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17293,7 +17293,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06e0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17314,7 +17314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01c4, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983108, + .flow_sig_id = 983108UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17336,7 +17336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1a08, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17353,7 +17353,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_12ec, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32772, + .flow_sig_id = 32772UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17371,7 +17371,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4ea8, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17389,7 +17389,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_478c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32836, + .flow_sig_id = 32836UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17408,7 +17408,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d4c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17426,7 +17426,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0a20, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17445,7 +17445,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1930, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17464,7 +17464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1614, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49220, + .flow_sig_id = 49220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17484,7 +17484,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a0c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17502,7 +17502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_32e0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98308, + .flow_sig_id = 98308UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17521,7 +17521,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01f0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17540,7 +17540,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ed4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98372, + .flow_sig_id = 98372UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17560,7 +17560,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2d40, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17579,7 +17579,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a24, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17599,7 +17599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3934, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17619,7 +17619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3608, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114756, + .flow_sig_id = 114756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17640,7 +17640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e60, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17658,7 +17658,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5744, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163844, + .flow_sig_id = 163844UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17677,7 +17677,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a54, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17696,7 +17696,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2328, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163908, + .flow_sig_id = 163908UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17716,7 +17716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_71a4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17735,7 +17735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e78, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180228, + .flow_sig_id = 180228UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17755,7 +17755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d88, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17775,7 +17775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5a6c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180292, + .flow_sig_id = 180292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17796,7 +17796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_11a8, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17815,7 +17815,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7738, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229380, + .flow_sig_id = 229380UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17835,7 +17835,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4a48, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17855,7 +17855,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_432c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229444, + .flow_sig_id = 229444UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17876,7 +17876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_08ec, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17896,7 +17896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01c0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245764, + .flow_sig_id = 245764UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17917,7 +17917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14d0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17938,7 +17938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7a60, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245828, + .flow_sig_id = 245828UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17960,7 +17960,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1d90, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17977,7 +17977,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14b4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131076, + .flow_sig_id = 131076UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17995,7 +17995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_70f0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18013,7 +18013,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4814, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131140, + .flow_sig_id = 131140UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18032,7 +18032,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d94, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18050,7 +18050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34b8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196612, + .flow_sig_id = 196612UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18069,7 +18069,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09a8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18088,7 +18088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00cc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196676, + .flow_sig_id = 196676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18108,7 +18108,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3f64, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18126,7 +18126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3688, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393220, + .flow_sig_id = 393220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18145,7 +18145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b78, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18164,7 +18164,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_029c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393284, + .flow_sig_id = 393284UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18184,7 +18184,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f68, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18203,7 +18203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_568c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458756, + .flow_sig_id = 458756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18223,7 +18223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2b7c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18243,7 +18243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_22a0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458820, + .flow_sig_id = 458820UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18264,7 +18264,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4020, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18282,7 +18282,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5b44, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655364, + .flow_sig_id = 655364UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18301,7 +18301,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2c34, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18320,7 +18320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2758, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655428, + .flow_sig_id = 655428UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18340,7 +18340,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_18d8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18359,7 +18359,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13fc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720900, + .flow_sig_id = 720900UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18379,7 +18379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c38, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18399,7 +18399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_475c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720964, + .flow_sig_id = 720964UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18420,7 +18420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1aa8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18439,7 +18439,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15cc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917508, + .flow_sig_id = 917508UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18459,7 +18459,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e08, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18479,7 +18479,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_492c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917572, + .flow_sig_id = 917572UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18500,7 +18500,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3aac, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18520,7 +18520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35d0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983044, + .flow_sig_id = 983044UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18541,7 +18541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06c0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18562,7 +18562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01e4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983108, + .flow_sig_id = 983108UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18584,7 +18584,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d32, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18598,7 +18598,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_54aa, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18613,7 +18613,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0686, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18627,7 +18627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_540e, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18642,7 +18642,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e3c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18657,7 +18657,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a20, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18673,7 +18673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46f0, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18689,7 +18689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52e4, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18706,7 +18706,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55e4, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18721,7 +18721,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_21f8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18737,7 +18737,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_75e8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18753,7 +18753,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_41fc, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18770,7 +18770,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d12, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18785,7 +18785,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_548a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18801,7 +18801,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3356, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18817,7 +18817,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ace, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18834,7 +18834,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1a9a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18850,7 +18850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d46, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18867,7 +18867,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2812, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18884,7 +18884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_338a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18902,7 +18902,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06e6, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18917,7 +18917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_546e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18933,7 +18933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46ee, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18949,7 +18949,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d22, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18966,7 +18966,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26e2, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18982,7 +18982,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_746a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18999,7 +18999,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1fa6, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19016,7 +19016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2d2e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19034,7 +19034,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4ef2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19049,7 +19049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_576a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19065,7 +19065,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_30b6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19081,7 +19081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_192e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19098,7 +19098,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_197a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19114,7 +19114,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4ea6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19131,7 +19131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bf2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19148,7 +19148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_306a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19166,7 +19166,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06c6, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19181,7 +19181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_544e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19197,7 +19197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46ce, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19213,7 +19213,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d02, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19230,7 +19230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26c2, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19246,7 +19246,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_744a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19263,7 +19263,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1f86, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19280,7 +19280,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2d0e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19298,7 +19298,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e1c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19314,7 +19314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a00, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19331,7 +19331,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46d0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19348,7 +19348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52c4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19366,7 +19366,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e10, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19383,7 +19383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5a04, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19401,7 +19401,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1f98, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19419,7 +19419,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_72f8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19438,7 +19438,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0a78, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19455,7 +19455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_166c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19473,7 +19473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_233c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19491,7 +19491,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0f20, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19510,7 +19510,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a7c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19528,7 +19528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3660, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19547,7 +19547,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4330, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19566,7 +19566,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2f24, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19586,7 +19586,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5584, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19602,7 +19602,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2198, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19619,7 +19619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7588, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19636,7 +19636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_419c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19654,7 +19654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7758, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19671,7 +19671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_43ac, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19689,7 +19689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c10, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19707,7 +19707,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1864, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19726,7 +19726,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_30c8, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19743,7 +19743,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cdc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19761,7 +19761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_50cc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19779,7 +19779,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d20, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19798,7 +19798,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_529c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19816,7 +19816,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ef0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19835,7 +19835,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_72e0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19854,7 +19854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ef4, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19874,7 +19874,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2dfc, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19890,7 +19890,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39e0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19907,7 +19907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4530, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19924,7 +19924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5124, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19942,7 +19942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4df0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19959,7 +19959,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59e4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19977,7 +19977,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c78, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19995,7 +19995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7118, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20014,7 +20014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0998, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20031,7 +20031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_158c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20049,7 +20049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20dc, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20067,7 +20067,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0cc0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20086,7 +20086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_299c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20104,7 +20104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3580, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20123,7 +20123,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40d0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20142,7 +20142,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2cc4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20162,7 +20162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55a4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20178,7 +20178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_21b8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20195,7 +20195,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_75a8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20212,7 +20212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_41bc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20230,7 +20230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7778, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20247,7 +20247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_438c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20265,7 +20265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c30, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20283,7 +20283,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1844, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20302,7 +20302,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_30e8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20319,7 +20319,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cfc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20337,7 +20337,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_50ec, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20355,7 +20355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d00, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20374,7 +20374,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52bc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20392,7 +20392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ed0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20411,7 +20411,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_72c0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20430,7 +20430,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ed4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20450,7 +20450,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3866, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20465,7 +20465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_381e, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20480,7 +20480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3860, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20496,7 +20496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0454, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20513,7 +20513,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3818, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20529,7 +20529,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_042c, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20546,7 +20546,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3846, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20562,7 +20562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_387e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20578,7 +20578,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ba6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20594,7 +20594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_385e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20610,7 +20610,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3840, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20627,7 +20627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0474, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20645,7 +20645,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3878, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20662,7 +20662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_044c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20680,7 +20680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ba0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20697,7 +20697,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0794, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20715,7 +20715,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3858, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20732,7 +20732,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_046c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index 31a94c14dc..8706e45f28 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 11:11:05 2021 */ +/* date: Thu Sep 9 12:11:08 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -48,7 +48,7 @@ #define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2323 #define ULP_THOR_CLASS_IDENT_LIST_SIZE 38 #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313 -#define ULP_THOR_CLASS_COND_LIST_SIZE 55 +#define ULP_THOR_CLASS_COND_LIST_SIZE 54 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 95205a2421..54bc032b0c 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Aug 25 16:41:37 2021 */ +/* date: Thu Sep 9 12:11:08 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -18,9 +18,9 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .num_tbls = 28, .start_tbl_idx = 0, .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 0, - .cond_nums = 1 } + .cond_nums = 0 } }, /* class_tid: 2, ingress */ [2] = { @@ -29,7 +29,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 28, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 } }, /* class_tid: 3, egress */ @@ -39,7 +39,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 52, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 0 } }, /* class_tid: 4, ingress */ @@ -49,7 +49,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 70, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 } }, /* class_tid: 5, egress */ @@ -59,7 +59,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 91, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 } } }; @@ -74,7 +74,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -96,7 +96,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 5, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -117,7 +117,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -136,7 +136,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -149,7 +149,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -176,7 +176,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -196,7 +196,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -209,7 +209,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 4, + .cond_start_idx = 3, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -228,7 +228,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 5, + .cond_start_idx = 4, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -240,7 +240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 6, + .cond_start_idx = 5, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -259,7 +259,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 7, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -277,7 +277,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 7, + .cond_start_idx = 6, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -307,7 +307,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -328,7 +328,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -349,7 +349,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -368,7 +368,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 6, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -381,7 +381,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 9, + .cond_start_idx = 8, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, @@ -398,7 +398,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 10, + .cond_start_idx = 9, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, @@ -415,7 +415,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 11, + .cond_start_idx = 10, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -443,7 +443,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 13, + .cond_start_idx = 12, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -473,7 +473,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -494,7 +494,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 14, + .cond_start_idx = 13, .cond_nums = 3 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -519,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, + .cond_start_idx = 16, .cond_nums = 3 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -544,7 +544,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 19, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -569,7 +569,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 22, + .cond_start_idx = 21, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -594,7 +594,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 23, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -619,7 +619,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 25, + .cond_start_idx = 24, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -644,7 +644,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 27, + .cond_start_idx = 26, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -670,7 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -691,7 +691,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -710,7 +710,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -723,7 +723,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -750,7 +750,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -770,7 +770,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -783,7 +783,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 30, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -802,7 +802,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, + .cond_start_idx = 30, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -815,7 +815,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -842,7 +842,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -862,7 +862,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -875,7 +875,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, + .cond_start_idx = 32, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -894,7 +894,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 33, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -906,7 +906,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 34, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -925,7 +925,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -943,7 +943,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -973,7 +973,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -994,7 +994,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -1016,7 +1016,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1035,7 +1035,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1048,7 +1048,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 36, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, @@ -1065,7 +1065,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1093,7 +1093,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1114,7 +1114,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1140,7 +1140,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1159,7 +1159,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -1172,7 +1172,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 40, + .cond_start_idx = 39, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1191,7 +1191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 41, + .cond_start_idx = 40, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1203,7 +1203,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 42, + .cond_start_idx = 41, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -1222,7 +1222,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -1240,7 +1240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1270,7 +1270,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1291,7 +1291,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -1312,7 +1312,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1331,7 +1331,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1344,7 +1344,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 44, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, @@ -1361,7 +1361,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 44, + .cond_start_idx = 43, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1389,7 +1389,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1419,7 +1419,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1440,7 +1440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1465,7 +1465,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 47, + .cond_start_idx = 46, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1490,7 +1490,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1517,7 +1517,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, @@ -1536,7 +1536,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1558,7 +1558,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1577,7 +1577,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1590,7 +1590,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1619,7 +1619,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1640,7 +1640,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -1657,7 +1657,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -1676,7 +1676,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -1696,7 +1696,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1716,7 +1716,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -1729,7 +1729,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 50, + .cond_start_idx = 49, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1748,7 +1748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 50, + .cond_start_idx = 49, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1761,7 +1761,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, @@ -1780,7 +1780,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1802,7 +1802,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1821,7 +1821,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1834,7 +1834,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1861,7 +1861,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1882,7 +1882,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1899,7 +1899,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1918,7 +1918,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, @@ -1938,7 +1938,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1960,7 +1960,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1979,7 +1979,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1992,7 +1992,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -2019,7 +2019,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2040,7 +2040,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, @@ -2057,7 +2057,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, @@ -2076,7 +2076,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2095,7 +2095,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF, @@ -2114,7 +2114,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2133,7 +2133,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -2146,7 +2146,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, @@ -2165,7 +2165,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2188,7 +2188,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0, @@ -2207,7 +2207,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, @@ -2227,7 +2227,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2246,7 +2246,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2265,7 +2265,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -2278,7 +2278,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -2306,7 +2306,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, @@ -2323,7 +2323,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -2350,7 +2350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2373,7 +2373,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2391,7 +2391,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -2406,11 +2406,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { }; struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { - /* cond_reject: thor, class_tid: 1 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH - }, /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */ { .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 07/20] net/bnxt: support inner IP header for GRE tunnel flows 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (5 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 06/20] net/bnxt: enable wildcard match for ingress flows Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 08/20] net/bnxt: get TruFlow version Venkat Duvvuru ` (13 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> This change allows adding IP header matches for GRE flows that does not specify outer IP header in the flow match pattern. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 7 ++++--- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 40da953f06..605c29223c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -1119,7 +1119,8 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, /* Set the ipv4 header bitmap and computed l3 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) { + ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6) || + ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV4); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1); inner_flag = 1; @@ -1245,7 +1246,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, /* Set the ipv6 header bitmap and computed l3 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) { + ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6) || + ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV6); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1); inner_flag = 1; @@ -2127,7 +2129,6 @@ ulp_rte_vxlan_decap_act_handler(const struct rte_flow_action *action_item BNXT_ULP_ACT_BIT_VXLAN_DECAP); /* Update computational field with tunnel decap info */ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN_DECAP, 1); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1); return BNXT_TF_RC_SUCCESS; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index d3bfb8c12d..7d1bc06a3e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -27,7 +27,7 @@ #define BNXT_ULP_PROTO_HDR_UDP_NUM 4 #define BNXT_ULP_PROTO_HDR_TCP_NUM 9 #define BNXT_ULP_PROTO_HDR_VXLAN_NUM 4 -#define BNXT_ULP_PROTO_HDR_GRE_NUM 6 +#define BNXT_ULP_PROTO_HDR_GRE_NUM 2 #define BNXT_ULP_PROTO_HDR_ICMP_NUM 5 #define BNXT_ULP_PROTO_HDR_MAX 128 #define BNXT_ULP_PROTO_HDR_ENCAP_MAX 64 -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 08/20] net/bnxt: get TruFlow version 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (6 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 07/20] net/bnxt: support inner IP header for GRE tunnel flows Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 09/20] net/bnxt: increase flow scale for Thor Venkat Duvvuru ` (12 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru From: Jay Ding <jay.ding@broadcom.com> Implement tf_get_version that returns TruFlow version numbers and CFA resources capbilities. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com> --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 15 ++-- drivers/net/bnxt/tf_core/tf_core.c | 29 ++++++++ drivers/net/bnxt/tf_core/tf_core.h | 75 ++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device.h | 50 ++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p4.c | 65 +++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p4.h | 79 +++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p58.c | 65 +++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p58.h | 87 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_msg.c | 35 ++++++++++ drivers/net/bnxt/tf_core/tf_msg.h | 19 ++++++ 10 files changed, 513 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 77981b5cdb..6d04e39e48 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1058,8 +1058,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 55 -#define HWRM_VERSION_STR "1.10.2.55" +#define HWRM_VERSION_RSVD 58 +#define HWRM_VERSION_STR "1.10.2.58" /**************** * hwrm_ver_get * @@ -45178,7 +45178,7 @@ struct hwrm_tf_version_get_input { uint64_t resp_addr; } __rte_packed; -/* hwrm_tf_version_get_output (size:128b/16B) */ +/* hwrm_tf_version_get_output (size:256b/32B) */ struct hwrm_tf_version_get_output { /* The specific error status for the command. */ uint16_t error_code; @@ -45195,7 +45195,14 @@ struct hwrm_tf_version_get_output { /* Version Update number. */ uint8_t update; /* unused. */ - uint8_t unused0[4]; + uint8_t unused0[5]; + /* + * This field is used to indicate device's capabilities and + * configurations. + */ + uint64_t dev_caps_cfg; + /* unused. */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 936102c804..86dfec0eb4 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1802,3 +1802,32 @@ int tf_get_session_info(struct tf *tfp, return 0; } + +int tf_get_version(struct tf *tfp, + struct tf_get_version_parms *parms) +{ + int rc; + struct tf_dev_info dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_WH && + parms->device_type != TF_DEVICE_TYPE_THOR && + parms->device_type != TF_DEVICE_TYPE_SR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + rc = tf_msg_get_version(parms->bp, &dev, parms); + if (rc) + return rc; + + return 0; +} diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index fb02c2b161..ba9881c69d 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2363,4 +2363,79 @@ struct tf_get_if_tbl_entry_parms { int tf_get_if_tbl_entry(struct tf *tfp, struct tf_get_if_tbl_entry_parms *parms); +/** + * tf_get_version parameters definition. + */ +struct tf_get_version_parms { + /** + * [in] device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] bp + * The pointer to the parent bp struct. This is only used for HWRM + * message passing within the portability layer. The type is struct + * bnxt. + */ + void *bp; + + /* [out] major + * + * Version Major number. + */ + uint8_t major; + + /* [out] minor + * + * Version Minor number. + */ + uint8_t minor; + + /* [out] update + * + * Version Update number. + */ + uint8_t update; + + /** + * [out] dev_ident_caps + * + * fw available identifier resource list + */ + uint32_t dev_ident_caps; + + /** + * [out] dev_tbl_caps + * + * fw available table resource list + */ + uint32_t dev_tbl_caps; + + /** + * [out] dev_tcam_caps + * + * fw available tcam resource list + */ + uint32_t dev_tcam_caps; + + /** + * [out] dev_em_caps + * + * fw available em resource list + */ + uint32_t dev_em_caps; +}; + +/** + * Get tf fw version + * + * Used to retrieve Truflow fw version information. + * + * Returns success or failure code. + */ +int tf_get_version(struct tf *tfp, + struct tf_get_version_parms *parms); #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 9b0c037db0..88bd4515ff 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -6,6 +6,7 @@ #ifndef _TF_DEVICE_H_ #define _TF_DEVICE_H_ +#include "cfa_resource_types.h" #include "tf_core.h" #include "tf_identifier.h" #include "tf_tbl.h" @@ -36,6 +37,21 @@ struct tf_dev_info { const struct tf_dev_ops *ops; }; +/** + * This structure can be used to translate the CFA resource type to TF type. + */ +struct tf_hcapi_resource_map { + /** + * Truflow module type associated with this resource type. + */ + enum tf_module_type module_type; + + /** + * Bitmap of TF sub-type for the element. + */ + uint32_t type_caps; +}; + /** * @page device Device * @@ -1037,6 +1053,34 @@ struct tf_dev_ops { */ uint64_t (*tf_dev_cfa_key_hash)(uint64_t *key_data, uint16_t bitlen); + + /** + * Translate the CFA resource type to Truflow type + * + * [in] hcapi_types + * CFA resource type bitmap + * + * [out] ident_types + * Pointer to identifier type bitmap + * + * [out] tcam_types + * Pointer to tcam type bitmap + * + * [out] tbl_types + * Pointer to table type bitmap + * + * [out] em_types + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_map_hcapi_caps)(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps); }; /** @@ -1047,4 +1091,10 @@ extern const struct tf_dev_ops tf_dev_ops_p4; extern const struct tf_dev_ops tf_dev_ops_p58_init; extern const struct tf_dev_ops tf_dev_ops_p58; +/** + * Supported device resource type mapping structures + */ +extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1]; +extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1]; + #endif /* _TF_DEVICE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 826cd0cdbc..8089785b82 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -271,6 +271,67 @@ static bool tf_dev_p4_is_sram_managed(struct tf *tfp __rte_unused, { return false; } + +/** + * Device specific function that maps the hcapi resource types + * to Truflow type. + * + * [in] hcapi_caps + * CFA resource type bitmap + * + * [out] ident_caps + * Pointer to identifier type bitmap + * + * [out] tcam_caps + * Pointer to tcam type bitmap + * + * [out] tbl_caps + * Pointer to table type bitmap + * + * [out] em_caps + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p4_map_hcapi_caps(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps) +{ + uint32_t i; + + *ident_caps = 0; + *tcam_caps = 0; + *tbl_caps = 0; + *em_caps = 0; + + for (i = 0; i <= CFA_RESOURCE_TYPE_P4_LAST; i++) { + if (hcapi_caps & 1ULL << i) { + switch (tf_hcapi_res_map_p4[i].module_type) { + case TF_MODULE_TYPE_IDENTIFIER: + *ident_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_TABLE: + *tbl_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_TCAM: + *tcam_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_EM: + *em_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + default: + return -EINVAL; + } + } + } + + return 0; +} + /** * Truflow P4 device specific functions */ @@ -321,6 +382,7 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = NULL, + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps }; /** @@ -382,5 +444,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = tf_dev_p4_word_align, - .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash + .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index c1357913f1..e84c0f9e83 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -157,4 +157,83 @@ struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = { TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK }, }; + +const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { + [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW + }, + [CFA_RESOURCE_TYPE_P4_PROF_FUNC] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC + }, + [CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF + }, + [CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW + }, + [CFA_RESOURCE_TYPE_P4_PROF_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM + }, + [CFA_RESOURCE_TYPE_P4_WC_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM + }, + [CFA_RESOURCE_TYPE_P4_SP_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_SP_TCAM + }, + [CFA_RESOURCE_TYPE_P4_NAT_IPV4] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_MODIFY_IPV4 + }, + [CFA_RESOURCE_TYPE_P4_METER_PROF] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF + }, + [CFA_RESOURCE_TYPE_P4_METER] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST + }, + [CFA_RESOURCE_TYPE_P4_MIRROR] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG + }, + [CFA_RESOURCE_TYPE_P4_FULL_ACTION] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_FULL_ACT_RECORD + }, + [CFA_RESOURCE_TYPE_P4_MCG] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MCAST_GROUPS + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_8B + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_16B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_16B + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_64B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_64B + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4 + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6 + }, + [CFA_RESOURCE_TYPE_P4_COUNTER_64B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64 + }, + [CFA_RESOURCE_TYPE_P4_EM_REC] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD + }, + [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_TBL_SCOPE + }, +}; + #endif /* _TF_DEVICE_P4_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 47d7836a58..03e72b90f5 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -45,6 +45,7 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { [CFA_RESOURCE_TYPE_P58_WC_FKB] = "wc_fkb ", [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = "veb ", [CFA_RESOURCE_TYPE_P58_METADATA] = "metadata", + [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = "meter_dc", }; /** @@ -336,6 +337,66 @@ static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused, return 0; } +/** + * Device specific function that maps the hcapi resource types + * to Truflow type. + * + * [in] hcapi_caps + * CFA resource type bitmap + * + * [out] ident_caps + * Pointer to identifier type bitmap + * + * [out] tcam_caps + * Pointer to tcam type bitmap + * + * [out] tbl_caps + * Pointer to table type bitmap + * + * [out] em_caps + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_map_hcapi_caps(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps) +{ + uint32_t i; + + *ident_caps = 0; + *tcam_caps = 0; + *tbl_caps = 0; + *em_caps = 0; + + for (i = 0; i <= CFA_RESOURCE_TYPE_P58_LAST; i++) { + if (hcapi_caps & 1ULL << i) { + switch (tf_hcapi_res_map_p58[i].module_type) { + case TF_MODULE_TYPE_IDENTIFIER: + *ident_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_TABLE: + *tbl_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_TCAM: + *tcam_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_EM: + *em_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + default: + return -EINVAL; + } + } + } + + return 0; +} + /** * Truflow P58 device specific functions */ @@ -386,6 +447,7 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = NULL, + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps }; /** @@ -448,5 +510,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = tf_dev_p58_word_align, - .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash + .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index 3e8759f2df..f6e66936f3 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -209,4 +209,91 @@ struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = { TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_INTERVAL_CFG }, }; + +const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { + [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW + }, + [CFA_RESOURCE_TYPE_P58_PROF_FUNC] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC + }, + [CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF + }, + [CFA_RESOURCE_TYPE_P58_EM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW + }, + [CFA_RESOURCE_TYPE_P58_PROF_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM + }, + [CFA_RESOURCE_TYPE_P58_WC_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM + }, + [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_VEB_TCAM + }, + [CFA_RESOURCE_TYPE_P58_EM_FKB] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_EM_FKB + }, + [CFA_RESOURCE_TYPE_P58_WC_FKB] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_WC_FKB + }, + [CFA_RESOURCE_TYPE_P58_METER_PROF] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF + }, + [CFA_RESOURCE_TYPE_P58_METER] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST + }, + [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_DROP_CNT + }, + [CFA_RESOURCE_TYPE_P58_MIRROR] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG + }, + [CFA_RESOURCE_TYPE_P58_METADATA] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METADATA + }, + /* Resources in bank 1 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_FULL_ACT_RECORD + | 1 << TF_TBL_TYPE_COMPACT_ACT_RECORD + }, + /* Resources in bank 2 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_ACT_ENCAP_8B | + 1 << TF_TBL_TYPE_ACT_ENCAP_16B | + 1 << TF_TBL_TYPE_ACT_ENCAP_32B | + 1 << TF_TBL_TYPE_ACT_ENCAP_64B | + 1 << TF_TBL_TYPE_ACT_MODIFY_8B | + 1 << TF_TBL_TYPE_ACT_MODIFY_16B | + 1 << TF_TBL_TYPE_ACT_MODIFY_32B | + 1 << TF_TBL_TYPE_ACT_MODIFY_64B + + }, + /* Resources in bank 0 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_ACT_SP_SMAC | + 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4 | + 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6 + }, + /* Resources in bank 3 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64 + }, + [CFA_RESOURCE_TYPE_P58_EM_REC] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD + }, +}; #endif /* _TF_DEVICE_P58_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index ea6e2af7ce..25bf026658 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -2306,3 +2306,38 @@ tf_msg_set_if_tbl_entry(struct tf *tfp, return 0; } + +int +tf_msg_get_version(struct bnxt *bp, + struct tf_dev_info *dev, + struct tf_get_version_parms *params) + +{ + int rc; + struct hwrm_tf_version_get_input req = { 0 }; + struct hwrm_tf_version_get_output resp = { 0 }; + struct tfp_send_msg_parms parms = { 0 }; + + /* Populate the request */ + parms.tf_type = HWRM_TF_VERSION_GET, + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(bp, + &parms); + + params->major = resp.major; + params->minor = resp.minor; + params->update = resp.update; + + dev->ops->tf_dev_map_hcapi_caps(resp.dev_caps_cfg, + ¶ms->dev_ident_caps, + ¶ms->dev_tcam_caps, + ¶ms->dev_tbl_caps, + ¶ms->dev_em_caps); + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 718bc2f3b2..08d20cdd7a 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -738,4 +738,23 @@ int tf_msg_set_if_tbl_entry(struct tf *tfp, int tf_msg_get_if_tbl_entry(struct tf *tfp, struct tf_if_tbl_get_parms *params); +/** + * Send get version request to the firmware. + * + * [in] bp + * Pointer to bnxt handle + * + * [in] dev + * Pointer to the associated device + * + * [in/out] parms + * Pointer to the version info parameter + * + * Returns: + * 0 on Success else internal Truflow error + */ +int +tf_msg_get_version(struct bnxt *bp, + struct tf_dev_info *dev, + struct tf_get_version_parms *parms); #endif /* _TF_MSG_H_ */ -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 09/20] net/bnxt: increase flow scale for Thor 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (7 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 08/20] net/bnxt: get TruFlow version Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 10/20] net/bnxt: remove accumulation of stats devargs argument Venkat Duvvuru ` (11 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Shahaji Bhosle, Kishore Padmanabha, Venkat Duvvuru From: Shahaji Bhosle <sbhosle@broadcom.com> * Updated defines and data types to allow 256 VFRs. * Increased the encap record cache to support 256 to 4K entries. So VxLAN connections can be scaled to 4K entries. Signed-off-by: Shahaji Bhosle <sbhosle@broadcom.com> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/bnxt.h | 6 +++++- drivers/net/bnxt/bnxt_cpr.c | 2 +- drivers/net/bnxt/bnxt_ethdev.c | 18 +++++++++--------- drivers/net/bnxt/bnxt_reps.c | 3 +-- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 2 +- .../generic_templates/ulp_template_db_tbl.c | 8 ++++---- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 6 +++--- 7 files changed, 24 insertions(+), 21 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index c65e360446..5c064fd119 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -240,7 +240,11 @@ struct bnxt_parent_info { struct bnxt_pf_info { #define BNXT_FIRST_PF_FID 1 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) -#define BNXT_MAX_VF_REPS 64 +#define BNXT_MAX_VF_REPS_WH 64 +#define BNXT_MAX_VF_REPS_TH 256 +#define BNXT_MAX_VF_REPS(bp) \ + (BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_TH : \ + BNXT_MAX_VF_REPS_WH) #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) #define BNXT_FIRST_VF_FID 128 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) diff --git a/drivers/net/bnxt/bnxt_cpr.c b/drivers/net/bnxt/bnxt_cpr.c index 63ff02a198..6bb70d516e 100644 --- a/drivers/net/bnxt/bnxt_cpr.c +++ b/drivers/net/bnxt/bnxt_cpr.c @@ -74,7 +74,7 @@ bnxt_process_default_vnic_change(struct bnxt *bp, BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT; PMD_DRV_LOG(INFO, "async event received vf_id 0x%x\n", vf_fid); - for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) { + for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS(bp); vf_id++) { eth_dev = bp->rep_info[vf_id].vfr_eth_dev; if (!eth_dev) continue; diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index bf034db336..8c72ab8fd1 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1179,7 +1179,7 @@ void bnxt_print_link_info(struct rte_eth_dev *eth_dev) struct rte_eth_link *link = ð_dev->data->dev_link; if (link->link_status) - PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", + PMD_DRV_LOG(DEBUG, "Port %d Link Up - speed %u Mbps - %s\n", eth_dev->data->port_id, (uint32_t)link->link_speed, (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? @@ -6034,7 +6034,7 @@ static int bnxt_init_rep_info(struct bnxt *bp) return 0; bp->rep_info = rte_zmalloc("bnxt_rep_info", - sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, + sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS(bp), 0); if (!bp->rep_info) { PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); @@ -6076,7 +6076,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, { struct rte_eth_dev *vf_rep_eth_dev; char name[RTE_ETH_NAME_MAX_LEN]; - struct bnxt *backing_bp; + struct bnxt *backing_bp = backing_eth_dev->data->dev_private; + uint16_t max_vf_reps = BNXT_MAX_VF_REPS(backing_bp); + uint16_t num_rep; int i, ret = 0; struct rte_kvargs *kvlist = NULL; @@ -6089,9 +6091,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, return -ENOTSUP; } num_rep = eth_da->nb_representor_ports; - if (num_rep > BNXT_MAX_VF_REPS) { + if (num_rep > max_vf_reps) { PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", - num_rep, BNXT_MAX_VF_REPS); + num_rep, max_vf_reps); return -EINVAL; } @@ -6102,8 +6104,6 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, return -EINVAL; } - backing_bp = backing_eth_dev->data->dev_private; - if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { PMD_DRV_LOG(ERR, "Not a PF or trusted VF. No Representor support\n"); @@ -6123,9 +6123,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, .parent_dev = backing_eth_dev }; - if (representor.vf_id >= BNXT_MAX_VF_REPS) { + if (representor.vf_id >= max_vf_reps) { PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", - representor.vf_id, BNXT_MAX_VF_REPS); + representor.vf_id, max_vf_reps); continue; } diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c index b7e88e013a..988f5a33a7 100644 --- a/drivers/net/bnxt/bnxt_reps.c +++ b/drivers/net/bnxt/bnxt_reps.c @@ -210,7 +210,6 @@ int bnxt_representor_init(struct rte_eth_dev *eth_dev, void *params) eth_dev->data->dev_link.link_status = link->link_status; eth_dev->data->dev_link.link_autoneg = link->link_autoneg; - PMD_DRV_LOG(INFO, "calling bnxt_print_link_info\n"); bnxt_print_link_info(eth_dev); PMD_DRV_LOG(INFO, @@ -821,7 +820,7 @@ int bnxt_rep_stop_all(struct bnxt *bp) if (!bp->rep_info) return 0; - for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) { + for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS(bp); vf_id++) { rep_eth_dev = bp->rep_info[vf_id].vfr_eth_dev; if (!rep_eth_dev) continue; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 68f1470c61..960a5a0c93 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -262,7 +262,7 @@ bnxt_ulp_cntxt_ptr2_ulp_flags_get(struct bnxt_ulp_context *ulp_ctx, uint32_t *flags); int32_t -bnxt_ulp_get_df_rule_info(uint8_t port_id, struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_get_df_rule_info(uint16_t port_id, struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_df_rule_info *info); struct bnxt_ulp_vfr_rule_info* diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 5383e2cd70..e43e341927 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 11:11:05 2021 */ +/* date: Thu Sep 16 11:49:55 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -164,12 +164,12 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE", - .result_num_entries = 256, + .name = "EGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE", + .result_num_entries = 4096, .result_num_bytes = 6, .key_num_bytes = 17, .num_buckets = 8, - .hash_tbl_entries = 1024, + .hash_tbl_entries = 16384, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index d8336d164e..01233c0f5e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -441,7 +441,7 @@ void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global) { struct bnxt_ulp_df_rule_info *info; - uint8_t port_id; + uint16_t port_id; if (!BNXT_TRUFLOW_EN(bp) || BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev)) @@ -505,7 +505,7 @@ int32_t bnxt_ulp_create_df_rules(struct bnxt *bp) { struct bnxt_ulp_df_rule_info *info; - uint8_t port_id; + uint16_t port_id; int rc = 0; if (!BNXT_TRUFLOW_EN(bp) || @@ -562,7 +562,7 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev) struct rte_eth_dev *parent_dev = vfr->parent_dev; struct bnxt *bp = parent_dev->data->dev_private; uint16_t vfr_port_id = vfr_ethdev->data->port_id; - uint8_t port_id; + uint16_t port_id; int rc; if (!bp || !BNXT_TRUFLOW_EN(bp)) -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 10/20] net/bnxt: remove accumulation of stats devargs argument 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (8 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 09/20] net/bnxt: increase flow scale for Thor Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 11/20] net/bnxt: fix clang compiler warnings Venkat Duvvuru ` (10 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> The accumulation of flow counters is not determined by the application device arguments instead it is dictated by the platform capabilities whether to do software based accumulation or not. Change-Id: I7275a0ed6ab089358e0a95f43d6291ec65ebe030 Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> --- drivers/net/bnxt/bnxt.h | 3 -- drivers/net/bnxt/bnxt_ethdev.c | 53 ---------------------------- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 8 ----- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 1 - drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 12 +++---- 5 files changed, 4 insertions(+), 73 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 5c064fd119..5cc4a5afae 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -718,11 +718,8 @@ struct bnxt { uint32_t flags2; #define BNXT_FLAGS2_PTP_TIMESYNC_ENABLED BIT(0) #define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1) -#define BNXT_FLAGS2_ACCUM_STATS_EN BIT(2) #define BNXT_P5_PTP_TIMESYNC_ENABLED(bp) \ ((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED) -#define BNXT_ACCUM_STATS_EN(bp) \ - ((bp)->flags2 & BNXT_FLAGS2_ACCUM_STATS_EN) uint16_t chip_num; #define CHIP_NUM_58818 0xd818 diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 8c72ab8fd1..070f69d8e9 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -87,7 +87,6 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { { .vendor_id = 0, /* sentinel */ }, }; -#define BNXT_DEVARG_ACCUM_STATS "accum-stats" #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" #define BNXT_DEVARG_REPRESENTOR "representor" @@ -101,7 +100,6 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { static const char *const bnxt_dev_args[] = { BNXT_DEVARG_REPRESENTOR, - BNXT_DEVARG_ACCUM_STATS, BNXT_DEVARG_FLOW_XSTAT, BNXT_DEVARG_MAX_NUM_KFLOWS, BNXT_DEVARG_REP_BASED_PF, @@ -114,12 +112,6 @@ static const char *const bnxt_dev_args[] = { NULL }; -/* - * accum-stats == false to disable flow counter accumulation - * accum-stats == true to enable flow counter accumulation - */ -#define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1) - /* * app-id = an non-negative 8-bit number */ @@ -5299,45 +5291,6 @@ static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) return 0; } -static int -bnxt_parse_devarg_accum_stats(__rte_unused const char *key, - const char *value, void *opaque_arg) -{ - struct bnxt *bp = opaque_arg; - unsigned long accum_stats; - char *end = NULL; - - if (!value || !opaque_arg) { - PMD_DRV_LOG(ERR, - "Invalid parameter passed to accum-stats devargs.\n"); - return -EINVAL; - } - - accum_stats = strtoul(value, &end, 10); - if (end == NULL || *end != '\0' || - (accum_stats == ULONG_MAX && errno == ERANGE)) { - PMD_DRV_LOG(ERR, - "Invalid parameter passed to accum-stats devargs.\n"); - return -EINVAL; - } - - if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) { - PMD_DRV_LOG(ERR, - "Invalid value passed to accum-stats devargs.\n"); - return -EINVAL; - } - - if (accum_stats) { - bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN; - PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n"); - } else { - bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN; - PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n"); - } - - return 0; -} - static int bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, const char *value, void *opaque_arg) @@ -5690,12 +5643,6 @@ bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) if (ret) goto err; - /* - * Handler for "accum-stats" devarg. - * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1" - */ - rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS, - bnxt_parse_devarg_accum_stats, bp); /* * Handler for "max_num_kflows" devarg. * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 2ac1a8625f..7deacd1f3e 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1490,14 +1490,6 @@ bnxt_ulp_port_init(struct bnxt *bp) goto jump_to_error; } - /* set the accumulation of the stats */ - if (BNXT_ACCUM_STATS_EN(bp)) - bp->ulp_ctx->cfg_data->accum_stats = true; - - BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init, accum_stats:%d\n", - bp->eth_dev->data->port_id, - bp->ulp_ctx->cfg_data->accum_stats); - /* set the unicast mode */ if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(bp->ulp_ctx, &ulp_flags)) { BNXT_TF_DBG(ERR, "Error in getting ULP context flags\n"); diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 960a5a0c93..17c6898196 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -92,7 +92,6 @@ struct bnxt_ulp_data { #define BNXT_ULP_TUN_ENTRY_INVALID -1 #define BNXT_ULP_MAX_TUN_CACHE_ENTRIES 16 struct bnxt_tun_cache_entry tun_tbl[BNXT_ULP_MAX_TUN_CACHE_ENTRIES]; - bool accum_stats; uint8_t app_id; uint8_t num_shared_clients; struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES]; diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c index d6b4f93d31..92243083b5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c @@ -396,21 +396,17 @@ static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt, return rc; } - /* TBD - Get PKT/BYTE COUNT SHIFT/MASK from Template */ + /* PKT/BYTE COUNT SHIFT/MASK are device specific */ sw_cntr_indx = hw_cntr_id - fc_info->shadow_hw_tbl[dir].start_idx; sw_acc_tbl_entry = &fc_info->sw_acc_tbl[dir][sw_cntr_indx]; + /* Some dpdk applications may accumulate the flow counters while some * may not. In cases where the application is accumulating the counters * the PMD need not do the accumulation itself and viceversa to report * the correct flow counters. */ - if (ctxt->cfg_data->accum_stats) { - sw_acc_tbl_entry->pkt_count += FLOW_CNTR_PKTS(stats, dparms); - sw_acc_tbl_entry->byte_count += FLOW_CNTR_BYTES(stats, dparms); - } else { - sw_acc_tbl_entry->pkt_count = FLOW_CNTR_PKTS(stats, dparms); - sw_acc_tbl_entry->byte_count = FLOW_CNTR_BYTES(stats, dparms); - } + sw_acc_tbl_entry->pkt_count += FLOW_CNTR_PKTS(stats, dparms); + sw_acc_tbl_entry->byte_count += FLOW_CNTR_BYTES(stats, dparms); /* Update the parent counters if it is child flow */ if (sw_acc_tbl_entry->pc_flow_idx & FLOW_CNTR_PC_FLOW_VALID) { -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 11/20] net/bnxt: fix clang compiler warnings 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (9 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 10/20] net/bnxt: remove accumulation of stats devargs argument Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 12/20] net/bnxt: updated the log messages Venkat Duvvuru ` (9 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Shahaji Bhosle, Venkat Duvvuru From: Shahaji Bhosle <sbhosle@broadcom.com> Typecast flow_item type, action_item type and the ENUMs to uint32_t before comparing. Fixes: 53a0d4f7663 ("net/bnxt: support flow API item parsing") Signed-off-by: Shahaji Bhosle <sbhosle@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 605c29223c..d21c088d59 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -137,10 +137,10 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[], /* Parse all the items in the pattern */ while (item && item->type != RTE_FLOW_ITEM_TYPE_END) { - if (item->type >= (uint32_t) + if (item->type >= (typeof(item->type)) BNXT_RTE_FLOW_ITEM_TYPE_END) { if (item->type >= - (uint32_t)BNXT_RTE_FLOW_ITEM_TYPE_LAST) + (typeof(item->type))BNXT_RTE_FLOW_ITEM_TYPE_LAST) goto hdr_parser_error; /* get the header information */ hdr_info = &ulp_vendor_hdr_info[item->type - @@ -186,9 +186,9 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[], /* Parse all the items in the pattern */ while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) { if (action_item->type >= - (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_END) { + (typeof(action_item->type))BNXT_RTE_FLOW_ACTION_TYPE_END) { if (action_item->type >= - (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_LAST) + (typeof(action_item->type))BNXT_RTE_FLOW_ACTION_TYPE_LAST) goto act_parser_error; /* get the header information from bnxt actinfo table */ hdr_info = &ulp_vendor_act_info[action_item->type - -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 12/20] net/bnxt: updated the log messages 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (10 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 11/20] net/bnxt: fix clang compiler warnings Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 13/20] net/bnxt: add support for socket direct feature Venkat Duvvuru ` (8 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Some of the error level log messages are made debug level messages. When Truflow is not enabled then Truflow init error messages are moved to debug level instead. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 24 ++++++++++++------------ drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 7deacd1f3e..21f71d6445 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1396,16 +1396,16 @@ bnxt_ulp_port_init(struct bnxt *bp) uint32_t ulp_flags; int32_t rc = 0; - if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { - BNXT_TF_DBG(ERR, - "Skip ulp init for port: %d, not a TVF or PF\n", + if (!BNXT_TRUFLOW_EN(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ulp init for port: %d, TF is not enabled\n", bp->eth_dev->data->port_id); return rc; } - if (!BNXT_TRUFLOW_EN(bp)) { - BNXT_TF_DBG(ERR, - "Skip ulp init for port: %d, truflow is not enabled\n", + if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ulp init for port: %d, not a TVF or PF\n", bp->eth_dev->data->port_id); return rc; } @@ -1520,16 +1520,16 @@ bnxt_ulp_port_deinit(struct bnxt *bp) struct rte_pci_device *pci_dev; struct rte_pci_addr *pci_addr; - if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { - BNXT_TF_DBG(ERR, - "Skip ULP deinit port:%d, not a TVF or PF\n", + if (!BNXT_TRUFLOW_EN(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ULP deinit for port:%d, TF is not enabled\n", bp->eth_dev->data->port_id); return; } - if (!BNXT_TRUFLOW_EN(bp)) { - BNXT_TF_DBG(ERR, - "Skip ULP deinit for port:%d, truflow is not enabled\n", + if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ULP deinit port:%d, not a TVF or PF\n", bp->eth_dev->data->port_id); return; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index 01233c0f5e..8790d7ac0d 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -323,7 +323,7 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev, ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); if (!ulp_ctx) { BNXT_TF_DBG(ERR, - "ULP context is not initialized. Failed to create dflt flow.\n"); + "ULP is not init'ed. Fail to create dflt flow.\n"); return -EINVAL; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c index 79dc869e64..9968311c44 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c @@ -470,7 +470,7 @@ ulp_flow_db_init(struct bnxt_ulp_context *ulp_ctxt) } /* All good so return. */ - BNXT_TF_DBG(INFO, "FlowDB initialized with %d flows.\n", + BNXT_TF_DBG(DEBUG, "FlowDB initialized with %d flows.\n", flow_tbl->num_flows); return 0; error_free: diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c index 271520e1d3..9dffaef73b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c @@ -116,7 +116,7 @@ ulp_mark_db_init(struct bnxt_ulp_context *ctxt) mark_tbl->gfid_mask = (mark_tbl->gfid_num_entries / 2) - 1; mark_tbl->gfid_type_bit = (mark_tbl->gfid_num_entries / 2); - BNXT_TF_DBG(DEBUG, "GFID Max = 0x%08x\nGFID MASK = 0x%08x\n", + BNXT_TF_DBG(DEBUG, "GFID Max = 0x%08x GFID MASK = 0x%08x\n", mark_tbl->gfid_num_entries - 1, mark_tbl->gfid_mask); -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 13/20] net/bnxt: add support for socket direct feature 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (11 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 12/20] net/bnxt: updated the log messages Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 14/20] net/bnxt: delete the VF pair before VF representor alloc Venkat Duvvuru ` (7 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Added support for socket direct feature. This feature allows to ignore the incoming interface and use other fields in the packet to identify the flow and forward. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 2 + drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 23 +- .../generic_templates/ulp_template_db_enum.h | 71 +- .../generic_templates/ulp_template_db_tbl.c | 3917 +++++++++++++---- .../ulp_template_db_thor_act.c | 150 +- .../ulp_template_db_thor_class.c | 660 +-- .../ulp_template_db_wh_plus_act.c | 242 +- .../ulp_template_db_wh_plus_class.c | 222 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 5 + 9 files changed, 3699 insertions(+), 1593 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 21f71d6445..14be079eaa 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -340,6 +340,8 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, if (BNXT_MULTIROOT_EN(bp)) ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_APP_SOCKET_DIRECT; + BNXT_TF_DBG(DEBUG, + "Socket Direct feature is enabled"); } } if (!found) { diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 272195f6a2..55885d1b8c 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -133,8 +133,27 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, } /* Update the socket direct flag */ - if (ULP_SOCKET_DIRECT_IS_ENABLED(ulp_flags)) - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT, 1); + if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_SVIF_IGNORE)) { + uint32_t ifindex; + uint16_t vport; + + /* Get the port db ifindex */ + if (ulp_port_db_dev_port_to_ulp_index(params->ulp_ctx, + params->port_id, + &ifindex)) { + BNXT_TF_DBG(ERR, "Invalid port id %u\n", + params->port_id); + return; + } + /* Update the phy port of the other interface */ + if (ulp_port_db_vport_get(params->ulp_ctx, ifindex, &vport)) { + BNXT_TF_DBG(ERR, "Invalid port if index %u\n", ifindex); + return; + } + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT_VPORT, + (vport == 1) ? 2 : 1); + } } /* Function to create the rte flow. */ diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index 8706e45f28..c01ae1601d 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,15 +3,15 @@ * All rights reserved. */ -/* date: Thu Sep 9 12:11:08 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ -#define BNXT_ULP_REGFILE_MAX_SZ 42 +#define BNXT_ULP_REGFILE_MAX_SZ 46 #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 -#define BNXT_ULP_GEN_TBL_MAX_SZ 16 +#define BNXT_ULP_GEN_TBL_MAX_SZ 18 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 65536 #define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 993 #define BNXT_ULP_CLASS_HID_LOW_PRIME 6701 @@ -26,11 +26,11 @@ #define BNXT_ULP_ACT_HID_SHFTR 27 #define BNXT_ULP_ACT_HID_SHFTL 26 #define BNXT_ULP_ACT_HID_MASK 2047 -#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8 -#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110 -#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50 -#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 277 -#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8 +#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 16 +#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 132 +#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 140 +#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 409 +#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 12 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 @@ -114,7 +114,8 @@ enum bnxt_ulp_hdr_bit { BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000, BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000, BNXT_ULP_HDR_BIT_F2 = 0x0000000000080000, - BNXT_ULP_HDR_BIT_LAST = 0x0000000000100000 + BNXT_ULP_HDR_BIT_SVIF_IGNORE = 0x0000000000100000, + BNXT_ULP_HDR_BIT_LAST = 0x0000000000200000 }; enum bnxt_ulp_accept_opc { @@ -212,7 +213,8 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72, BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73, BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74, - BNXT_ULP_CF_IDX_LAST = 75 + BNXT_ULP_CF_IDX_SOCKET_DIRECT_VPORT = 75, + BNXT_ULP_CF_IDX_LAST = 76 }; enum bnxt_ulp_cond_list_opc { @@ -427,21 +429,31 @@ enum bnxt_ulp_glb_rf_idx { BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 37, BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 38, BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 39, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 40, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 41, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 42, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 43, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 44, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 45, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 46, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 47, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 48, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 49, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 50, - BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 51, - BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 52, - BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 53, - BNXT_ULP_GLB_RF_IDX_LAST = 54 + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3 = 40, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 41, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 42, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 43, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 44, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 45, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 46, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 47, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3 = 48, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4 = 49, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5 = 50, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6 = 51, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7 = 52, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8 = 53, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9 = 54, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10 = 55, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 56, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 57, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 58, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 59, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2 = 60, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 61, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 62, + BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 63, + BNXT_ULP_GLB_RF_IDX_LAST = 64 }; enum bnxt_ulp_hdr_type { @@ -555,7 +567,11 @@ enum bnxt_ulp_rf_idx { BNXT_ULP_RF_IDX_PHY_PORT = 39, BNXT_ULP_RF_IDX_METADATA_PROF = 40, BNXT_ULP_RF_IDX_MODIFY_PTR = 41, - BNXT_ULP_RF_IDX_LAST = 42 + BNXT_ULP_RF_IDX_SOCK_DIR_SVIF = 42, + BNXT_ULP_RF_IDX_SOCK_DIR_PARIF = 43, + BNXT_ULP_RF_IDX_SOCK_DIR_ACT_PTR = 44, + BNXT_ULP_RF_IDX_SOCK_DIR_PARENT_MAC = 45, + BNXT_ULP_RF_IDX_LAST = 46 }; enum bnxt_ulp_shared_session { @@ -627,7 +643,8 @@ enum bnxt_ulp_resource_sub_type { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE = 6, - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7 + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE = 8 }; enum bnxt_ulp_act_prop_sz { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index e43e341927..d5aea4d456 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 16 11:49:55 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -171,6 +171,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { .num_buckets = 8, .hash_tbl_entries = 16384, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GEN_TABLE_SOCKET_DIRECT_CACHE", + .result_num_entries = 16, + .result_num_bytes = 14, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GEN_TABLE_SOCKET_DIRECT_CACHE", + .result_num_entries = 16, + .result_num_bytes = 14, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; @@ -371,6 +391,33 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY | + BNXT_ULP_APP_CAP_SOCKET_DIRECT + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY } }; @@ -439,6 +486,70 @@ struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 1024 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 128 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 1024 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 128 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 1024 } }; @@ -472,6 +583,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -560,6 +679,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -624,14 +751,6 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, - .direction = TF_DIR_RX - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX @@ -672,6 +791,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -760,6 +887,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -824,14 +959,6 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, - .direction = TF_DIR_RX - }, - { - .app_id = 2, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX @@ -843,509 +970,717 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, .direction = TF_DIR_RX - } -}; - -/* List of global tf resources required to be reserved per app/device */ -struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { + }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX + }, + { + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_METADATA, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0, - .direction = TF_DIR_TX + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, .direction = TF_DIR_RX }, { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, + .direction = TF_DIR_RX + }, + { + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, + .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX + } +}; + +/* List of global tf resources required to be reserved per app/device */ +struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { + { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1353,7 +1688,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1361,7 +1696,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, @@ -1369,7 +1704,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1377,7 +1712,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1385,7 +1720,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1393,7 +1728,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1401,7 +1736,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1409,7 +1744,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, @@ -1417,7 +1752,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1425,7 +1760,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1433,7 +1768,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1441,7 +1776,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, @@ -1449,7 +1784,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1457,7 +1792,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1465,7 +1800,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1473,7 +1808,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1481,7 +1816,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1489,7 +1824,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1497,7 +1832,15 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1505,7 +1848,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1513,7 +1856,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1521,7 +1864,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1529,7 +1872,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1537,7 +1880,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1545,23 +1888,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6, - .direction = TF_DIR_RX - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7, - .direction = TF_DIR_RX - }, - { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1569,7 +1896,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1577,7 +1904,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1585,7 +1912,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1593,7 +1920,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1601,7 +1928,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1609,7 +1936,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1617,7 +1944,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1625,7 +1952,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1633,427 +1960,2171 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .direction = TF_DIR_TX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_METADATA, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0, + .direction = TF_DIR_TX + }, + { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + } +}; + +/* List of tf resources required to be reserved per app/device */ +struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 422 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 191 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 6912 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 1023 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 511 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 15 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, + .count = 255 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 422 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 960 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 88 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 13168 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 292 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 148 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 191 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 6912 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 1023 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 511 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 223 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 255 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 488 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, + .count = 511 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 292 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 144 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 960 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 928 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 15232 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 5 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 31 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 2048 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 64 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 128 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4096 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 16384 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 5 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 2048 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 100 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 128 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4096 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 16384 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_METADATA, + .count = 1 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 16 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 528 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 256 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 512 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 256 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1, - .direction = TF_DIR_RX + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 }, { - .app_id = 3, + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2, - .direction = TF_DIR_RX + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 }, { - .app_id = 3, + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3, - .direction = TF_DIR_RX - } -}; - -/* List of tf resources required to be reserved per app/device */ -struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 6912 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 511 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 15 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, - .count = 255 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 88 + .count = 64 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 13168 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 148 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 6912 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 511 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 223 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 255 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 488 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .count = 511 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 144 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 928 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 15232 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 272 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2061,15 +4132,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 32 + .count = 16 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2077,759 +4148,815 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 528 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 8192 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 5 + .count = 256 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 31 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 2048 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 64 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 272 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4096 + .count = 512 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 16384 + .count = 1024 }, { - .app_id = 0, + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 272 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 512 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 8192 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 5 + .count = 256 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 2048 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 100 + .count = 4 }, { - .app_id = 0, + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 272 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4096 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 16384 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_METADATA, - .count = 1 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 422 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 4 + .count = 191 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 4 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 4 + .count = 192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 128 + .count = 8192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 128 + .count = 7168 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 4 + .count = 1023 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 4 + .count = 511 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 4 + .count = 15 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, - .count = 4 + .count = 255 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 422 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 960 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 88 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 13168 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 292 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 148 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 4 + .count = 191 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 4 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 4 + .count = 192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 128 + .count = 8192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 128 + .count = 7168 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 4 + .count = 1023 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 4 + .count = 511 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 4 + .count = 223 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 4 + .count = 255 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 4 + .count = 488 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .count = 4 + .count = 511 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 292 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 144 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 960 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 928 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 15232 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 16 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 528 + .count = 4096 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 256 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, + .count = 1024 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 2048 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 6144 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 4 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 4 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 4 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 512 + .count = 4096 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 256 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, + .count = 1024 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 2048 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 6144 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2837,7 +4964,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2845,7 +4972,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2853,7 +4980,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2861,7 +4988,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2869,7 +4996,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2877,7 +5004,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2885,7 +5012,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2893,7 +5020,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2901,7 +5028,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2909,7 +5036,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2917,7 +5044,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -2925,7 +5052,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -2933,7 +5060,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -2941,15 +5068,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 64 + .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -2957,7 +5084,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2965,7 +5092,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2973,7 +5100,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2981,7 +5108,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2989,7 +5116,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2997,7 +5124,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3005,7 +5132,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3013,7 +5140,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3021,7 +5148,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3029,7 +5156,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3037,7 +5164,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3045,7 +5172,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3053,7 +5180,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3061,7 +5188,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3069,7 +5196,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3077,7 +5204,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3085,7 +5212,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3093,7 +5220,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -3101,7 +5228,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3109,7 +5236,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3117,7 +5244,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3125,7 +5252,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3133,7 +5260,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 16 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3141,7 +5268,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3149,7 +5276,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 528 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3157,7 +5284,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 256 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3165,7 +5292,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3173,7 +5300,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3181,7 +5308,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3189,7 +5316,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3197,7 +5324,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3205,7 +5332,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3213,15 +5340,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 512 + .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -3229,7 +5356,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3237,7 +5364,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3245,7 +5372,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3253,7 +5380,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3261,7 +5388,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3269,7 +5396,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3277,7 +5404,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 512 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3285,7 +5412,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 256 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3293,7 +5420,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3301,7 +5428,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3309,7 +5436,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3317,7 +5444,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3325,7 +5452,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3333,7 +5460,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3341,7 +5468,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3349,7 +5476,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -3357,596 +5484,532 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 7168 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 511 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 15 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, - .count = 255 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 88 + .count = 64 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 13168 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 148 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 7168 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 511 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 223 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 255 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 488 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .count = 511 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 144 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 928 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 15232 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 16 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 4096 + .count = 528 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 256 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 2048 + .count = 512 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 6144 + .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 128 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 128 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 4096 + .count = 512 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 256 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 2048 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 6144 + .count = 1024 } }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c index e49c1151d3..8869ab1c33 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Aug 17 12:16:42 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -1575,8 +1575,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}, + (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1607,7 +1607,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, + ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_DECAP_FUNC_NONE} @@ -1666,8 +1666,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1692,7 +1692,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, + ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1747,7 +1747,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, + ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_DECAP_FUNC_NONE} @@ -1806,8 +1806,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1832,7 +1832,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, + ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2149,7 +2149,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2168,7 +2168,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2187,7 +2187,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2206,7 +2206,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2373,8 +2373,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2393,8 +2393,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2413,8 +2413,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2433,8 +2433,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 3, , table: mod_record.ing_no_ttl */ @@ -2526,7 +2526,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2545,7 +2545,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2564,7 +2564,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2583,7 +2583,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2737,8 +2737,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2757,8 +2757,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2777,8 +2777,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2797,8 +2797,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 3, , table: int_full_act_record.0 */ @@ -3593,7 +3593,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3612,7 +3612,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3631,7 +3631,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3650,7 +3650,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3817,8 +3817,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -3837,8 +3837,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -3857,8 +3857,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -3877,8 +3877,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 5, , table: mod_record.ing_no_ttl */ @@ -3970,7 +3970,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3989,7 +3989,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4008,7 +4008,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4027,7 +4027,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4181,8 +4181,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4201,8 +4201,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4221,8 +4221,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4241,8 +4241,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 5, , table: int_full_act_record.0 */ @@ -4526,8 +4526,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4546,8 +4546,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4566,8 +4566,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4586,8 +4586,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4833,8 +4833,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4853,8 +4853,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4873,8 +4873,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4893,8 +4893,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 54bc032b0c..2d464fb7c4 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 12:11:08 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -3232,8 +3232,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -3302,7 +3302,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -3492,7 +3492,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -3871,8 +3871,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -3987,8 +3987,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -4821,8 +4821,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -4835,8 +4835,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -4959,8 +4959,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -4973,8 +4973,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5037,8 +5037,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -5051,8 +5051,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5091,8 +5091,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -5105,8 +5105,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5153,8 +5153,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5358,8 +5358,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5383,8 +5383,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5542,8 +5542,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -5612,7 +5612,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -5659,7 +5659,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_VALID_YES}, + ULP_THOR_SYM_L4_HDR_VALID_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_VALID_IGNORE} @@ -5749,7 +5749,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L3_HDR_TYPE_IPV6} @@ -5830,7 +5830,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -6209,8 +6209,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -6734,7 +6734,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L3_HDR_TYPE_IPV6} @@ -6815,7 +6815,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_TL2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_TL2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_TL2_VTAG_PRESENT_NO} @@ -6900,8 +6900,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -7018,8 +7018,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -7852,8 +7852,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -7866,8 +7866,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7990,8 +7990,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8004,8 +8004,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8056,8 +8056,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8070,8 +8070,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8110,8 +8110,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8124,8 +8124,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8187,8 +8187,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8383,8 +8383,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8397,8 +8397,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8413,8 +8413,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8427,8 +8427,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9359,8 +9359,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9373,8 +9373,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9497,8 +9497,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9511,8 +9511,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9575,8 +9575,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9589,8 +9589,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9629,8 +9629,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9643,8 +9643,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9694,8 +9694,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9901,8 +9901,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9928,8 +9928,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10860,8 +10860,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -10874,8 +10874,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10998,8 +10998,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -11012,8 +11012,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -11064,8 +11064,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -11078,8 +11078,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -11118,8 +11118,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -11132,8 +11132,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -11195,8 +11195,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12335,8 +12335,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12349,8 +12349,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12473,8 +12473,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12487,8 +12487,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12551,8 +12551,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12565,8 +12565,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12605,8 +12605,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12619,8 +12619,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12670,8 +12670,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -13810,8 +13810,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -13824,8 +13824,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -13948,8 +13948,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -13962,8 +13962,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14712,8 +14712,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -14726,8 +14726,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14778,8 +14778,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -14792,8 +14792,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14832,8 +14832,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -14846,8 +14846,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14909,8 +14909,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -15093,8 +15093,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -15107,8 +15107,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -15123,8 +15123,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -15137,8 +15137,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -15345,8 +15345,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -15359,8 +15359,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16219,8 +16219,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16233,8 +16233,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16297,8 +16297,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16311,8 +16311,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16351,8 +16351,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16365,8 +16365,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16416,8 +16416,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16600,8 +16600,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16614,8 +16614,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16630,8 +16630,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16644,8 +16644,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16852,8 +16852,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16866,8 +16866,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -18434,7 +18434,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_I_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -19848,8 +19848,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -19862,8 +19862,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -19970,8 +19970,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -19984,8 +19984,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20168,8 +20168,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -20182,8 +20182,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20222,8 +20222,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -20236,8 +20236,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20284,8 +20284,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20489,8 +20489,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20514,8 +20514,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -22120,8 +22120,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22134,8 +22134,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22242,8 +22242,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22256,8 +22256,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22428,8 +22428,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22442,8 +22442,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22482,8 +22482,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22496,8 +22496,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22559,8 +22559,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22755,8 +22755,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22769,8 +22769,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22785,8 +22785,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22799,8 +22799,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -23041,7 +23041,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -23231,7 +23231,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -24532,8 +24532,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24546,8 +24546,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24562,8 +24562,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24576,8 +24576,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24700,8 +24700,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24714,8 +24714,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24778,8 +24778,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24792,8 +24792,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24832,8 +24832,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24846,8 +24846,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24894,8 +24894,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -25099,8 +25099,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -25124,8 +25124,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -25345,7 +25345,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -25469,7 +25469,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L3_HDR_TYPE_IPV6} @@ -25548,7 +25548,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -26210,7 +26210,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -27511,8 +27511,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -27525,8 +27525,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -27541,8 +27541,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -27555,8 +27555,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -27679,8 +27679,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -27693,8 +27693,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -27856,8 +27856,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -28052,8 +28052,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -28066,8 +28066,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -28082,8 +28082,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -28096,8 +28096,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29016,8 +29016,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -29030,8 +29030,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29046,8 +29046,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -29060,8 +29060,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29184,8 +29184,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -29198,8 +29198,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29361,8 +29361,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -30489,8 +30489,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -30503,8 +30503,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -30519,8 +30519,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -30533,8 +30533,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -30657,8 +30657,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -30671,8 +30671,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -34679,8 +34679,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -35206,8 +35206,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -36920,8 +36920,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}, + (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, @@ -36991,8 +36991,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff}, + (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff, @@ -38986,8 +38986,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}, + (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff, @@ -39570,8 +39570,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c index 4a2d201c2d..16a921e6c8 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Aug 25 14:37:06 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -1210,8 +1210,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1239,8 +1239,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1295,7 +1295,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_NONE} @@ -1346,8 +1346,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1481,8 +1481,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1510,8 +1510,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1566,7 +1566,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_NONE} @@ -1893,7 +1893,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1} + 1} }, { .description = "drop", @@ -2088,7 +2088,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1} + 1} }, { .description = "drop", @@ -2222,8 +2222,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2_POST, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - (1 >> 8) & 0xff, - 1 & 0xff} + (1 >> 8) & 0xff, + 1 & 0xff} }, /* act_tid: 3, , table: int_flow_counter_tbl.0 */ { @@ -2418,8 +2418,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2447,8 +2447,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2503,7 +2503,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -2662,8 +2662,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2691,8 +2691,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2747,7 +2747,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -3853,8 +3853,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3882,8 +3882,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3938,7 +3938,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -4097,8 +4097,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4126,8 +4126,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4182,7 +4182,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -4415,8 +4415,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4435,8 +4435,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4455,8 +4455,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4475,8 +4475,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4495,8 +4495,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4515,8 +4515,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4535,8 +4535,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4555,8 +4555,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4575,8 +4575,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4595,8 +4595,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4615,8 +4615,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4635,8 +4635,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4672,8 +4672,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4692,8 +4692,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4712,8 +4712,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4732,8 +4732,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4752,8 +4752,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4772,8 +4772,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4792,8 +4792,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4812,8 +4812,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4832,8 +4832,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 6, , table: int_full_act_record.0 */ @@ -5264,8 +5264,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5284,8 +5284,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5304,8 +5304,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5324,8 +5324,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5344,8 +5344,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5364,8 +5364,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5384,8 +5384,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5404,8 +5404,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5424,8 +5424,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5444,8 +5444,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5464,8 +5464,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5484,8 +5484,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5521,8 +5521,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5541,8 +5541,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5561,8 +5561,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5581,8 +5581,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5601,8 +5601,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5621,8 +5621,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5641,8 +5641,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5661,8 +5661,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5681,8 +5681,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c index 4b9cb7fd5b..d1c3ebe065 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Aug 11 16:00:16 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -2198,8 +2198,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -2218,8 +2218,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2261,8 +2261,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -2281,8 +2281,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2550,8 +2550,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -2570,8 +2570,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2631,8 +2631,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -2701,7 +2701,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -3258,8 +3258,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -3383,7 +3383,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -3942,8 +3942,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -4702,8 +4702,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -4778,8 +4778,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4803,8 +4803,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4827,8 +4827,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4980,8 +4980,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5005,8 +5005,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5029,8 +5029,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5182,8 +5182,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5207,8 +5207,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5231,8 +5231,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5398,8 +5398,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5423,8 +5423,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5447,8 +5447,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6746,7 +6746,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L3_HDR_TYPE_IPV4}, + ULP_WP_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L3_HDR_TYPE_IPV6} @@ -7714,8 +7714,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -7734,8 +7734,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7777,8 +7777,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -7797,8 +7797,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8066,8 +8066,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8086,8 +8086,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8147,8 +8147,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -8217,7 +8217,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -8774,8 +8774,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -8899,7 +8899,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -9458,8 +9458,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -9576,8 +9576,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -9652,8 +9652,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9677,8 +9677,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9701,8 +9701,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9854,8 +9854,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9879,8 +9879,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9903,8 +9903,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10056,8 +10056,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10081,8 +10081,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10105,8 +10105,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10272,8 +10272,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10297,8 +10297,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10321,8 +10321,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12392,8 +12392,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -12409,8 +12409,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, @@ -12544,8 +12544,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -12561,8 +12561,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, @@ -13715,7 +13715,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_LOOPBACK_PARIF}, + ULP_WP_SYM_LOOPBACK_PARIF}, .field_src3 = BNXT_ULP_FIELD_SRC_CF, .field_opr3 = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, @@ -13887,8 +13887,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -13904,8 +13904,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, @@ -14039,8 +14039,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -14056,8 +14056,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index d21c088d59..2ec3279239 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -685,6 +685,11 @@ ulp_rte_phy_port_hdr_handler(const struct rte_flow_item *item, hdr_field->size = sizeof(svif); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SVIF_FLAG, rte_be_to_cpu_16(svif)); + if (!mask) { + ULP_BITMAP_SET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_SVIF_IGNORE); + memset(hdr_field->mask, 0xFF, sizeof(mask)); + } return BNXT_TF_RC_SUCCESS; } -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 14/20] net/bnxt: delete the VF pair before VF representor alloc 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (12 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 13/20] net/bnxt: add support for socket direct feature Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 15/20] net/bnxt: add new API TruFlow get SRAM resources Venkat Duvvuru ` (6 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> When the VF representor interface is created, the VF pair relationship is established between the VF and it is representor. If the pair already exists then the pair needs to be deleted before allocation. This could happen if the application is abruptly killed and restarted. If the deletion of an existing VF rep is not done then hw pipeline is not cleaned and a new allocation shall leave the hw in inconsistent state. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com> --- drivers/net/bnxt/bnxt_hwrm.c | 28 ++++++++++++++++++++++++++++ drivers/net/bnxt/bnxt_hwrm.h | 1 + drivers/net/bnxt/bnxt_reps.c | 6 ++++++ 3 files changed, 35 insertions(+) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index c7041143a3..f8c27fe316 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -6025,6 +6025,34 @@ int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid, return rc; } +int bnxt_hwrm_cfa_pair_exists(struct bnxt *bp, struct bnxt_representor *rep_bp) +{ + struct hwrm_cfa_pair_info_output *resp = bp->hwrm_cmd_resp_addr; + struct hwrm_cfa_pair_info_input req = {0}; + int rc = 0; + + if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) { + PMD_DRV_LOG(DEBUG, + "Not a PF or trusted VF. Command not supported\n"); + return 0; + } + + HWRM_PREP(&req, HWRM_CFA_PAIR_INFO, BNXT_USE_CHIMP_MB); + snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d", + bp->eth_dev->data->name, rep_bp->vf_id); + req.flags = + rte_cpu_to_le_32(HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE); + + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); + HWRM_CHECK_RESULT(); + if (rc == HWRM_ERR_CODE_SUCCESS && strlen(resp->pair_name)) { + HWRM_UNLOCK(); + return !rc; + } + HWRM_UNLOCK(); + return rc; +} + int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp) { struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr; diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h index 6dc23b93ac..33e6ba99d5 100644 --- a/drivers/net/bnxt/bnxt_hwrm.h +++ b/drivers/net/bnxt/bnxt_hwrm.h @@ -294,6 +294,7 @@ int bnxt_clear_one_vnic_filter(struct bnxt *bp, void bnxt_free_vf_info(struct bnxt *bp); int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid, uint16_t *first_vf_id); +int bnxt_hwrm_cfa_pair_exists(struct bnxt *bp, struct bnxt_representor *rep_bp); int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep); int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep); int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp); diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c index 988f5a33a7..111d226a59 100644 --- a/drivers/net/bnxt/bnxt_reps.c +++ b/drivers/net/bnxt/bnxt_reps.c @@ -315,6 +315,12 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev) BNXT_TF_DBG(ERR, "Invalid arguments\n"); return 0; } + /* update the port id so you can backtrack to ethdev */ + vfr->dpdk_port_id = vfr_ethdev->data->port_id; + + /* If pair is present, then delete the pair */ + if (bnxt_hwrm_cfa_pair_exists(parent_bp, vfr)) + (void)bnxt_hwrm_cfa_pair_free(parent_bp, vfr); /* Update the ULP portdata base with the new VFR interface */ rc = ulp_port_db_dev_port_intf_update(parent_bp->ulp_ctx, vfr_ethdev); -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 15/20] net/bnxt: add new API TruFlow get SRAM resources 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (13 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 14/20] net/bnxt: delete the VF pair before VF representor alloc Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 16/20] net/bnxt: add TruFlow and AFM SRAM partitioning support Venkat Duvvuru ` (5 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru From: Jay Ding <jay.ding@broadcom.com> Implement tf_get_sram_resources to return SRAM partition information, including bank count and SRAM profile number. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 11 ++- drivers/net/bnxt/tf_core/tf_core.c | 86 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_core.h | 63 +++++++++++++++++ drivers/net/bnxt/tf_core/tf_device.h | 20 ++++++ drivers/net/bnxt/tf_core/tf_device_p4.c | 6 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 53 ++++++++++++++- drivers/net/bnxt/tf_core/tf_msg.c | 28 ++------ drivers/net/bnxt/tf_core/tf_msg.h | 6 +- drivers/net/bnxt/tf_core/tf_rm.c | 3 +- drivers/net/bnxt/tf_core/tf_sram_mgr.h | 10 --- 10 files changed, 245 insertions(+), 41 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 6d04e39e48..1a46f34249 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1058,8 +1058,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 58 -#define HWRM_VERSION_STR "1.10.2.58" +#define HWRM_VERSION_RSVD 64 +#define HWRM_VERSION_STR "1.10.2.64" /**************** * hwrm_ver_get * @@ -45817,8 +45817,13 @@ struct hwrm_tf_session_resc_qcaps_output { * qcaps_size. */ uint16_t size; + /* + * SRAM profile number that sets the partition of SRAM memory + * between TF and AFM within the 4 internal memory banks (Thor). + */ + uint8_t sram_profile; /* unused. */ - uint16_t unused0; + uint8_t unused0; /* unused. */ uint8_t unused1[7]; /* diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 86dfec0eb4..346d220c87 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1831,3 +1831,89 @@ int tf_get_version(struct tf *tfp, return 0; } + +int tf_query_sram_resources(struct tf *tfp, + struct tf_query_sram_resources_parms *parms) +{ + int rc; + struct tf_dev_info dev; + uint16_t max_types; + struct tfp_calloc_parms cparms; + struct tf_rm_resc_req_entry *query; + enum tf_rm_resc_resv_strategy resv_strategy; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_THOR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + if (dev.ops->tf_dev_get_max_types == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return -EOPNOTSUPP; + } + + /* Need device max number of elements for the RM QCAPS */ + rc = dev.ops->tf_dev_get_max_types(tfp, &max_types); + if (rc) { + TFP_DRV_LOG(ERR, + "Get SRAM resc info failed, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Allocate memory for RM QCAPS request */ + cparms.nitems = max_types; + cparms.size = sizeof(struct tf_rm_resc_req_entry); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) + return rc; + + query = (struct tf_rm_resc_req_entry *)cparms.mem_va; + tfp->bp = parms->bp; + + /* Get Firmware Capabilities */ + rc = tf_msg_session_resc_qcaps(tfp, + &dev, + parms->dir, + max_types, + query, + &resv_strategy, + &parms->sram_profile); + if (rc) + return rc; + + if (dev.ops->tf_dev_get_sram_resources == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return -EOPNOTSUPP; + } + + rc = dev.ops->tf_dev_get_sram_resources((void *)query, + parms->bank_resc_count, + &parms->dynamic_sram_capable); + if (rc) { + TFP_DRV_LOG(ERR, + "Get SRAM resc info failed, rc:%s\n", + strerror(-rc)); + return rc; + } + + return 0; +} diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index ba9881c69d..078fd278a1 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -75,6 +75,17 @@ enum tf_wc_num_slice { TF_WC_TCAM_8_SLICE_PER_ROW = 8, }; +/** + * Bank identifier + */ +enum tf_sram_bank_id { + TF_SRAM_BANK_ID_0, /**< SRAM Bank 0 id */ + TF_SRAM_BANK_ID_1, /**< SRAM Bank 1 id */ + TF_SRAM_BANK_ID_2, /**< SRAM Bank 2 id */ + TF_SRAM_BANK_ID_3, /**< SRAM Bank 3 id */ + TF_SRAM_BANK_ID_MAX /**< SRAM Bank index limit */ +}; + /** * EEM record AR helper * @@ -2438,4 +2449,56 @@ struct tf_get_version_parms { */ int tf_get_version(struct tf *tfp, struct tf_get_version_parms *parms); + +/** + * tf_query_sram_resources parameter definition + */ +struct tf_query_sram_resources_parms { + /** + * [in] device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] bp + * The pointer to the parent bp struct. This is only used for HWRM + * message passing within the portability layer. The type is struct + * bnxt. + */ + void *bp; + + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + + /** + * [out] Bank resource count in 8 bytes entry + */ + + uint32_t bank_resc_count[TF_SRAM_BANK_ID_MAX]; + + /** + * [out] Dynamic SRAM Enable + */ + bool dynamic_sram_capable; + + /** + * [out] SRAM profile + */ + uint8_t sram_profile; +}; + +/** + * Get SRAM resources information + * + * Used to retrieve sram bank partition information + * + * Returns success or failure code. + */ +int tf_query_sram_resources(struct tf *tfp, + struct tf_query_sram_resources_parms *parms); + #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 88bd4515ff..9360eb1358 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1081,6 +1081,26 @@ struct tf_dev_ops { uint32_t *tcam_caps, uint32_t *tbl_caps, uint32_t *em_caps); + + /** + * Device specific function that retrieve the sram resource + * + * [in] query + * Point to resources query result + * + * [out] sram_bank_caps + * Pointer to SRAM bank capabilities + * + * [out] dynamic_sram_capable + * Pointer to dynamic sram capable + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_sram_resources)(void *query, + uint32_t *sram_bank_caps, + bool *dynamic_sram_capable); }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 8089785b82..cf0e919f9f 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -382,7 +382,8 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = NULL, - .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, + .tf_dev_get_sram_resources = NULL }; /** @@ -445,5 +446,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = tf_dev_p4_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, - .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, + .tf_dev_get_sram_resources = NULL }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 03e72b90f5..4687fa65dd 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -397,6 +397,53 @@ static int tf_dev_p58_map_hcapi_caps(uint64_t hcapi_caps, return 0; } +/** + * Device specific function that retrieve the sram resource + * + * [in] query + * Point to resources query result + * + * [out] sram_bank_caps + * Pointer to SRAM bank capabilities + * + * [out] dynamic_sram_capable + * Pointer to dynamic sram capable + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_get_sram_resources(void *q, + uint32_t *sram_bank_caps, + bool *dynamic_sram_capable) +{ + uint32_t i; + struct tf_rm_resc_req_entry *query = q; + + for (i = 0; i < CFA_RESOURCE_TYPE_P58_LAST + 1; i++) { + switch (query[i].type) { + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_0: + sram_bank_caps[0] = query[i].max; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_1: + sram_bank_caps[1] = query[i].max; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_2: + sram_bank_caps[2] = query[i].max; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_3: + sram_bank_caps[3] = query[i].max; + break; + default: + break; + } + } + + *dynamic_sram_capable = false; + + return 0; +} + /** * Truflow P58 device specific functions */ @@ -447,7 +494,8 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = NULL, - .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources }; /** @@ -511,5 +559,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = tf_dev_p58_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, - .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources }; diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 25bf026658..fbc96d374c 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -380,39 +380,20 @@ tf_msg_session_resc_qcaps(struct tf *tfp, enum tf_dir dir, uint16_t size, struct tf_rm_resc_req_entry *query, - enum tf_rm_resc_resv_strategy *resv_strategy) + enum tf_rm_resc_resv_strategy *resv_strategy, + uint8_t *sram_profile) { int rc; int i; struct tfp_send_msg_parms parms = { 0 }; struct hwrm_tf_session_resc_qcaps_input req = { 0 }; struct hwrm_tf_session_resc_qcaps_output resp = { 0 }; - uint8_t fw_session_id; struct tf_msg_dma_buf qcaps_buf = { 0 }; struct tf_rm_resc_req_entry *data; int dma_size; - struct tf_session *tfs; - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to lookup session, rc:%s\n", - strerror(-rc)); - return rc; - } TF_CHECK_PARMS3(tfp, query, resv_strategy); - rc = tf_session_get_fw_session_id(tfp, &fw_session_id); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Unable to lookup FW id, rc:%s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - /* Prepare DMA buffer */ dma_size = size * sizeof(struct tf_rm_resc_req_entry); rc = tf_msg_alloc_dma_buf(&qcaps_buf, dma_size); @@ -420,7 +401,7 @@ tf_msg_session_resc_qcaps(struct tf *tfp, return rc; /* Populate the request */ - req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); + req.fw_session_id = 0; req.flags = tfp_cpu_to_le_16(dir); req.qcaps_size = size; req.qcaps_addr = tfp_cpu_to_le_64(qcaps_buf.pa_addr); @@ -460,6 +441,9 @@ tf_msg_session_resc_qcaps(struct tf *tfp, *resv_strategy = resp.flags & HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK; + if (sram_profile != NULL) + *sram_profile = resp.sram_profile; + cleanup: tf_msg_free_dma_buf(&qcaps_buf); diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 08d20cdd7a..188b361d71 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -158,6 +158,9 @@ int tf_msg_session_qcfg(struct tf *tfp); * [out] resv_strategy * Pointer to the reservation strategy * + * [out] sram_profile + * Pointer to the sram profile + * * Returns: * 0 on Success else internal Truflow error */ @@ -166,7 +169,8 @@ int tf_msg_session_resc_qcaps(struct tf *tfp, enum tf_dir dir, uint16_t size, struct tf_rm_resc_req_entry *query, - enum tf_rm_resc_resv_strategy *resv_strategy); + enum tf_rm_resc_resv_strategy *resv_strategy, + uint8_t *sram_profile); /** * Sends session HW resource allocation request to TF Firmware diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index dd537aaece..d2045921b9 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -551,7 +551,8 @@ tf_rm_create_db(struct tf *tfp, parms->dir, max_types, query, - &resv_strategy); + &resv_strategy, + NULL); if (rc) return rc; diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h index 4abe3fb468..eb2156456a 100644 --- a/drivers/net/bnxt/tf_core/tf_sram_mgr.h +++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h @@ -28,16 +28,6 @@ #define TF_SRAM_MGR_BLOCK_SZ_BYTES 64 #define TF_SRAM_MGR_MIN_SLICE_BYTES 8 -/** - * Bank identifier - */ -enum tf_sram_bank_id { - TF_SRAM_BANK_ID_0, /**< SRAM Bank 0 id */ - TF_SRAM_BANK_ID_1, /**< SRAM Bank 1 id */ - TF_SRAM_BANK_ID_2, /**< SRAM Bank 2 id */ - TF_SRAM_BANK_ID_3, /**< SRAM Bank 3 id */ - TF_SRAM_BANK_ID_MAX /**< SRAM Bank index limit */ -}; /** * TF slice size. -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 16/20] net/bnxt: add TruFlow and AFM SRAM partitioning support 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (14 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 15/20] net/bnxt: add new API TruFlow get SRAM resources Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 17/20] net/bnxt: add Tx TruFlow table config for p4 device Venkat Duvvuru ` (4 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru From: Jay Ding <jay.ding@broadcom.com> Implement set/get_sram_policy which support both rx/tx direction truflow type the specific SRAM bank. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> --- drivers/net/bnxt/tf_core/tf_core.c | 82 ++++++ drivers/net/bnxt/tf_core/tf_core.h | 66 ++++- drivers/net/bnxt/tf_core/tf_device.c | 7 +- drivers/net/bnxt/tf_core/tf_device.h | 34 ++- drivers/net/bnxt/tf_core/tf_device_p4.c | 8 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 311 ++++++++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p58.h | 118 +-------- drivers/net/bnxt/tf_core/tf_tbl.c | 2 +- 8 files changed, 503 insertions(+), 125 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 346d220c87..90ff93946b 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1917,3 +1917,85 @@ int tf_query_sram_resources(struct tf *tfp, return 0; } + +int tf_set_sram_policy(struct tf *tfp, + struct tf_set_sram_policy_parms *parms) +{ + int rc = 0; + struct tf_dev_info dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_THOR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + if (dev.ops->tf_dev_set_sram_policy == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + rc = dev.ops->tf_dev_set_sram_policy(parms->dir, parms->bank_id); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: SRAM policy set failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + return rc; +} + +int tf_get_sram_policy(struct tf *tfp, + struct tf_get_sram_policy_parms *parms) +{ + int rc = 0; + struct tf_dev_info dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_THOR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + if (dev.ops->tf_dev_get_sram_policy == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + rc = dev.ops->tf_dev_get_sram_policy(parms->dir, parms->bank_id); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: SRAM policy get failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 078fd278a1..b2886355fa 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2455,7 +2455,7 @@ int tf_get_version(struct tf *tfp, */ struct tf_query_sram_resources_parms { /** - * [in] device type + * [in] Device type * * Device type for the session. */ @@ -2501,4 +2501,68 @@ struct tf_query_sram_resources_parms { int tf_query_sram_resources(struct tf *tfp, struct tf_query_sram_resources_parms *parms); +/** + * tf_set_sram_policy parameter definition + */ +struct tf_set_sram_policy_parms { + /** + * [in] Device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + + /** + * [in] Array of Bank id for each truflow tbl type + */ + uint8_t *bank_id; +}; + +/** + * Set SRAM policy + * + * Used to assign SRAM bank index to all truflow table type. + * + * Returns success or failure code. + */ +int tf_set_sram_policy(struct tf *tfp, + struct tf_set_sram_policy_parms *parms); + +/** + * tf_get_sram_policy parameter definition + */ +struct tf_get_sram_policy_parms { + /** + * [in] Device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + + /** + * [out] Array of Bank id for each truflow tbl type + */ + uint8_t bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1]; +}; + +/** + * Get SRAM policy + * + * Used to get the assigned bank of table types. + * + * Returns success or failure code. + */ +int tf_get_sram_policy(struct tf *tfp, + struct tf_get_sram_policy_parms *parms); + #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 25a7166bbb..40db546604 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -415,11 +415,14 @@ tf_dev_bind_p58(struct tf *tfp, } rsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX, - tf_tbl_p58, + tf_tbl_p58[TF_DIR_RX], + (uint16_t *)resources->tbl_cnt); + rsv_cnt += tf_dev_reservation_check(TF_TBL_TYPE_MAX, + tf_tbl_p58[TF_DIR_TX], (uint16_t *)resources->tbl_cnt); if (rsv_cnt) { tbl_cfg.num_elements = TF_TBL_TYPE_MAX; - tbl_cfg.cfg = tf_tbl_p58; + tbl_cfg.cfg = tf_tbl_p58[TF_DIR_RX]; tbl_cfg.resources = resources; rc = tf_tbl_bind(tfp, &tbl_cfg); if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 9360eb1358..3d5de988c4 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1083,7 +1083,7 @@ struct tf_dev_ops { uint32_t *em_caps); /** - * Device specific function that retrieve the sram resource + * Device specific function that retrieves the sram resource * * [in] query * Point to resources query result @@ -1101,6 +1101,38 @@ struct tf_dev_ops { int (*tf_dev_get_sram_resources)(void *query, uint32_t *sram_bank_caps, bool *dynamic_sram_capable); + + /** + * Device specific function that sets the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [in] band_id + * SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_set_sram_policy)(enum tf_dir dir, + uint8_t *bank_id); + + /** + * Device specific function that gets the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [in] band_id + * pointer to SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_sram_policy)(enum tf_dir dir, + uint8_t *bank_id); }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index cf0e919f9f..244bd08914 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -383,7 +383,9 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = NULL, .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, - .tf_dev_get_sram_resources = NULL + .tf_dev_get_sram_resources = NULL, + .tf_dev_set_sram_policy = NULL, + .tf_dev_get_sram_policy = NULL, }; /** @@ -447,5 +449,7 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_word_align = tf_dev_p4_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, - .tf_dev_get_sram_resources = NULL + .tf_dev_get_sram_resources = NULL, + .tf_dev_set_sram_policy = NULL, + .tf_dev_get_sram_policy = NULL, }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 4687fa65dd..3c1c3a2de1 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -48,6 +48,235 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = "meter_dc", }; +struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { + [TF_DIR_RX][TF_TBL_TYPE_EM_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_WC_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_DROP_CNT] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METADATA] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, + 0, 0 + }, + /* Policy - ARs in bank 1 */ + [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 8, + }, + /* Policy - Encaps in bank 2 */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - Modify in bank 2 with Encaps */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - SP in bank 0 */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 8, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 2, + }, + /* Policy - Stats in bank 3 */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_EM_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_WC_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_DROP_CNT] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METADATA] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, + 0, 0 + }, + /* Policy - ARs in bank 1 */ + [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 8, + }, + /* Policy - Encaps in bank 2 */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - Modify in bank 2 with Encaps */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - SP in bank 0 */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 2, + }, + /* Policy - Stats in bank 3 */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, + .slices = 8, + }, +}; + /** * Device specific function that retrieves the MAX number of HCAPI * types the device supports. @@ -444,6 +673,80 @@ static int tf_dev_p58_get_sram_resources(void *q, return 0; } +int sram_bank_hcapi_type[] = { + CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + CFA_RESOURCE_TYPE_P58_SRAM_BANK_3 +}; + +/** + * Device specific function that set the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [in] band_id + * SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_set_sram_policy(enum tf_dir dir, + uint8_t *bank_id) +{ + struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; + uint8_t type; + uint8_t parent[TF_SRAM_BANK_ID_MAX] = { 0xFF, 0xFF, 0xFF, 0xFF }; + + for (type = TF_TBL_TYPE_FULL_ACT_RECORD; + type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++) { + if (bank_id[type] > 3) + return -EINVAL; + + rm_cfg[type].hcapi_type = sram_bank_hcapi_type[bank_id[type]]; + if (parent[bank_id[type]] == 0xFF) { + parent[bank_id[type]] = type; + rm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT; + rm_cfg[type].parent_subtype = 0; + if (rm_cfg[type].slices == 0) + rm_cfg[type].slices = 1; + } else { + rm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD; + rm_cfg[type].parent_subtype = parent[bank_id[type]]; + } + } + + return 0; +} + +/** + * Device specific function that get the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [out] band_id + * pointer to SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_get_sram_policy(enum tf_dir dir, + uint8_t *bank_id) +{ + struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; + uint8_t type; + + for (type = TF_TBL_TYPE_FULL_ACT_RECORD; + type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++) + bank_id[type] = rm_cfg[type].hcapi_type - CFA_RESOURCE_TYPE_P58_SRAM_BANK_0; + + return 0; +} + /** * Truflow P58 device specific functions */ @@ -495,7 +798,9 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = NULL, .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, - .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources, + .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy, + .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy, }; /** @@ -560,5 +865,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_word_align = tf_dev_p58_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, - .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources, + .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy, + .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy, }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index f6e66936f3..61c856b767 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -12,6 +12,8 @@ #include "tf_if_tbl.h" #include "tf_global_cfg.h" +extern struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX]; + struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = { [TF_IDENT_TYPE_L2_CTXT_HIGH] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH, @@ -58,122 +60,6 @@ struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = { }, }; -struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { - [TF_TBL_TYPE_EM_FKB] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, - 0, 0 - }, - [TF_TBL_TYPE_WC_FKB] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, - 0, 0 - }, - [TF_TBL_TYPE_METER_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, - 0, 0 - }, - [TF_TBL_TYPE_METER_INST] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, - 0, 0 - }, - [TF_TBL_TYPE_METER_DROP_CNT] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, - 0, 0 - }, - [TF_TBL_TYPE_MIRROR_CONFIG] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, - 0, 0 - }, - [TF_TBL_TYPE_METADATA] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, - 0, 0 - }, - /* Policy - ARs in bank 1 */ - [TF_TBL_TYPE_FULL_ACT_RECORD] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 4, - }, - [TF_TBL_TYPE_COMPACT_ACT_RECORD] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 8, - }, - /* Policy - Encaps in bank 2 */ - [TF_TBL_TYPE_ACT_ENCAP_8B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 8, - }, - [TF_TBL_TYPE_ACT_ENCAP_16B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 4, - }, - [TF_TBL_TYPE_ACT_ENCAP_32B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 2, - }, - [TF_TBL_TYPE_ACT_ENCAP_64B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, - }, - /* Policy - Modify in bank 2 with Encaps */ - [TF_TBL_TYPE_ACT_MODIFY_8B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 8, - }, - [TF_TBL_TYPE_ACT_MODIFY_16B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 4, - }, - [TF_TBL_TYPE_ACT_MODIFY_32B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 2, - }, - [TF_TBL_TYPE_ACT_MODIFY_64B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, - }, - /* Policy - SP in bank 0 */ - [TF_TBL_TYPE_ACT_SP_SMAC] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 8, - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 4, - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 2, - }, - /* Policy - Stats in bank 3 */ - [TF_TBL_TYPE_ACT_STATS_64] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, - .slices = 8, - }, -}; - struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_EM_RECORD] = { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC, diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 12eca36491..3fb22b52ac 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -58,10 +58,10 @@ tf_tbl_bind(struct tf *tfp, db_cfg.num_elements = parms->num_elements; db_cfg.module = TF_MODULE_TYPE_TABLE; db_cfg.num_elements = parms->num_elements; - db_cfg.cfg = parms->cfg; for (d = 0; d < TF_DIR_MAX; d++) { db_cfg.dir = d; + db_cfg.cfg = &parms->cfg[d ? TF_TBL_TYPE_MAX : 0]; db_cfg.alloc_cnt = parms->resources->tbl_cnt[d].cnt; db_cfg.rm_db = (void *)&tbl_db->tbl_db[d]; if (tf_session_is_shared_session(tfs) && -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 17/20] net/bnxt: add Tx TruFlow table config for p4 device 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (15 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 16/20] net/bnxt: add TruFlow and AFM SRAM partitioning support Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 18/20] net/bnxt: remove 2-slice WC entries for scale Venkat Duvvuru ` (3 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru From: Jay Ding <jay.ding@broadcom.com> Add TX direction TruFlow table type config to be compatible with other devices. For P4 device, the TX cfg is duplicated from RX. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/tf_core/tf_device.c | 4 +- drivers/net/bnxt/tf_core/tf_device_p4.c | 107 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p4.h | 58 +------------ 3 files changed, 111 insertions(+), 58 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 40db546604..4c416270b6 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -131,11 +131,11 @@ tf_dev_bind_p4(struct tf *tfp, } rsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX, - tf_tbl_p4, + tf_tbl_p4[TF_DIR_RX], (uint16_t *)resources->tbl_cnt); if (rsv_cnt) { tbl_cfg.num_elements = TF_TBL_TYPE_MAX; - tbl_cfg.cfg = tf_tbl_p4; + tbl_cfg.cfg = tf_tbl_p4[TF_DIR_RX]; tbl_cfg.resources = resources; rc = tf_tbl_bind(tfp, &tbl_cfg); if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 244bd08914..a6a59b8a07 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -59,6 +59,113 @@ const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = "tb_scope", }; +struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { + [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_MCAST_GROUPS] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_MCAST_GROUPS] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, + 0, 0 + }, +}; + /** * Device specific function that retrieves the MAX number of HCAPI * types the device supports. diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index e84c0f9e83..86de525995 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -12,6 +12,8 @@ #include "tf_if_tbl.h" #include "tf_global_cfg.h" +extern struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX]; + struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = { [TF_IDENT_TYPE_L2_CTXT_HIGH] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH, @@ -58,62 +60,6 @@ struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = { }, }; -struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = { - [TF_TBL_TYPE_FULL_ACT_RECORD] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, - 0, 0 - }, - [TF_TBL_TYPE_MCAST_GROUPS] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_8B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_16B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_64B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, - 0, 0 - }, - [TF_TBL_TYPE_ACT_STATS_64] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_MODIFY_IPV4] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, - 0, 0 - }, - [TF_TBL_TYPE_METER_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, - 0, 0 - }, - [TF_TBL_TYPE_METER_INST] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, - 0, 0 - }, - [TF_TBL_TYPE_MIRROR_CONFIG] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, - 0, 0 - }, - -}; - struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_TBL_SCOPE] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE, -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 18/20] net/bnxt: remove 2-slice WC entries for scale 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (16 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 17/20] net/bnxt: add Tx TruFlow table config for p4 device Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 19/20] net/bnxt: check for mismatch of control and physical port Venkat Duvvuru ` (2 subsequent siblings) 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Mike Baucom, Venkat Duvvuru From: Mike Baucom <michael.baucom@broadcom.com> The type-5 WC IPv6 flows were removed in order to increase the scale for app-id=3. The app no longer supports 2-slice WC entries. Signed-off-by: Mike Baucom <michael.baucom@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 14be079eaa..d40d726c58 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -461,7 +461,7 @@ ulp_ctx_shared_session_open(struct bnxt *bp, parms.shadow_copy = true; parms.bp = bp; - if (app_id == 0 || app_id == 3) + if (app_id == 0) parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW; else parms.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW; @@ -583,7 +583,7 @@ ulp_ctx_session_open(struct bnxt *bp, return rc; params.bp = bp; - if (app_id == 0 || app_id == 3) + if (app_id == 0) params.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW; else params.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW; -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 19/20] net/bnxt: check for mismatch of control and physical port 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (17 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 18/20] net/bnxt: remove 2-slice WC entries for scale Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 20/20] net/bnxt: use enum for bank ID Venkat Duvvuru 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> During the parsing of the ingress port ignore for a flow, added check to match the control port and the physical port that is configured to be ignored. If they do not match then the configuration to setup the svif ignore shall fail. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_port_db.c | 23 +++++++++++++++++++++++ drivers/net/bnxt/tf_ulp/ulp_port_db.h | 13 +++++++++++++ drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 12 ++++++++++++ 3 files changed, 48 insertions(+) diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c index 5e7c1d1c17..f8ffb567b5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c @@ -679,3 +679,26 @@ ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt, } return -EINVAL; } + +/* + * Api to get the phy port for a given port id. + * + * ulp_ctxt [in] Ptr to ulp context + * port_id [in] device port id + * phy_port [out] phy_port of the dpdk port_id + * + * Returns 0 on success or negative number on failure. + */ +int32_t +ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id, uint16_t *phy_port) +{ + struct ulp_func_if_info *info; + + info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id); + if (info) { + *phy_port = info->phy_port_id; + return 0; + } + return -EINVAL; +} diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h index 740c186e12..b112f1a216 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h @@ -314,4 +314,17 @@ int32_t ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt, uint32_t port_id, uint8_t **vnic); +/* + * Api to get the phy port for a given port id. + * + * ulp_ctxt [in] Ptr to ulp context + * port_id [in] device port id + * phy_port [out] phy_port of the dpdk port_id + * + * Returns 0 on success or negative number on failure. + */ +int32_t +ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id, uint16_t *phy_port); + #endif /* _ULP_PORT_DB_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 2ec3279239..f4274dd634 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -686,6 +686,18 @@ ulp_rte_phy_port_hdr_handler(const struct rte_flow_item *item, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SVIF_FLAG, rte_be_to_cpu_16(svif)); if (!mask) { + uint32_t port_id = 0; + uint16_t phy_port = 0; + + /* Validate the control port */ + port_id = ULP_COMP_FLD_IDX_RD(params, + BNXT_ULP_CF_IDX_DEV_PORT_ID); + if (ulp_port_db_phy_port_get(params->ulp_ctx, + port_id, &phy_port) || + (uint16_t)port_spec->index != phy_port) { + BNXT_TF_DBG(ERR, "Mismatch of control and phy_port\n"); + return BNXT_TF_RC_PARSE_ERR; + } ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF_IGNORE); memset(hdr_field->mask, 0xFF, sizeof(mask)); -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v3 20/20] net/bnxt: use enum for bank ID 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (18 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 19/20] net/bnxt: check for mismatch of control and physical port Venkat Duvvuru @ 2021-11-02 4:05 ` Venkat Duvvuru 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde 20 siblings, 0 replies; 118+ messages in thread From: Venkat Duvvuru @ 2021-11-02 4:05 UTC (permalink / raw) To: dev; +Cc: Jay Ding From: Jay Ding <jay.ding@broadcom.com> Instead of integer, using enum tf_sram_bank_id for bank id in tf_set_sram_policy_parms. Add index check against the allocation of the meter instance for meter drop count because there is no reason to access it if the corresponding meter entry is not allocated. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Reviewed-by: Steve Rempe <steve.rempe@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> --- drivers/net/bnxt/tf_core/tf_core.h | 4 +- drivers/net/bnxt/tf_core/tf_device.h | 4 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 10 ++-- drivers/net/bnxt/tf_core/tf_tbl.c | 75 ++++++++++++------------ 4 files changed, 47 insertions(+), 46 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index b2886355fa..f891d7a48f 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2520,7 +2520,7 @@ struct tf_set_sram_policy_parms { /** * [in] Array of Bank id for each truflow tbl type */ - uint8_t *bank_id; + enum tf_sram_bank_id bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1]; }; /** @@ -2552,7 +2552,7 @@ struct tf_get_sram_policy_parms { /** * [out] Array of Bank id for each truflow tbl type */ - uint8_t bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1]; + enum tf_sram_bank_id bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1]; }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 3d5de988c4..bfb5de4370 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1116,7 +1116,7 @@ struct tf_dev_ops { * - (-EINVAL) on failure. */ int (*tf_dev_set_sram_policy)(enum tf_dir dir, - uint8_t *bank_id); + enum tf_sram_bank_id *bank_id); /** * Device specific function that gets the sram policy @@ -1132,7 +1132,7 @@ struct tf_dev_ops { * - (-EINVAL) on failure. */ int (*tf_dev_get_sram_policy)(enum tf_dir dir, - uint8_t *bank_id); + enum tf_sram_bank_id *bank_id); }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 3c1c3a2de1..30c0af7eef 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -673,7 +673,7 @@ static int tf_dev_p58_get_sram_resources(void *q, return 0; } -int sram_bank_hcapi_type[] = { +static int sram_bank_hcapi_type[] = { CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, @@ -694,15 +694,15 @@ int sram_bank_hcapi_type[] = { * - (-EINVAL) on failure. */ static int tf_dev_p58_set_sram_policy(enum tf_dir dir, - uint8_t *bank_id) + enum tf_sram_bank_id *bank_id) { struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; uint8_t type; uint8_t parent[TF_SRAM_BANK_ID_MAX] = { 0xFF, 0xFF, 0xFF, 0xFF }; for (type = TF_TBL_TYPE_FULL_ACT_RECORD; - type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++) { - if (bank_id[type] > 3) + type <= TF_TBL_TYPE_ACT_MODIFY_64B; type++) { + if (bank_id[type] >= TF_SRAM_BANK_ID_MAX) return -EINVAL; rm_cfg[type].hcapi_type = sram_bank_hcapi_type[bank_id[type]]; @@ -735,7 +735,7 @@ static int tf_dev_p58_set_sram_policy(enum tf_dir dir, * - (-EINVAL) on failure. */ static int tf_dev_p58_get_sram_policy(enum tf_dir dir, - uint8_t *bank_id) + enum tf_sram_bank_id *bank_id) { struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; uint8_t type; diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 3fb22b52ac..f18e4ba346 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -307,28 +307,28 @@ tf_tbl_set(struct tf *tfp, } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; - - /* Do not check meter drop counter because it is not allocated - * resources + /* Verify that the entry has been previously allocated. + * for meter drop counter, check the corresponding meter + * entry */ - if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) { - /* Verify that the entry has been previously allocated */ - aparms.rm_db = tbl_db->tbl_db[parms->dir]; + aparms.rm_db = tbl_db->tbl_db[parms->dir]; + if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) aparms.subtype = parms->type; - aparms.allocated = &allocated; - aparms.index = parms->idx; - rc = tf_rm_is_allocated(&aparms); - if (rc) - return rc; + else + aparms.subtype = TF_TBL_TYPE_METER_INST; + aparms.allocated = &allocated; + aparms.index = parms->idx; + rc = tf_rm_is_allocated(&aparms); + if (rc) + return rc; - if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { - TFP_DRV_LOG(ERR, - "%s, Invalid or not allocated, type:%s, idx:%d\n", - tf_dir_2_str(parms->dir), - tf_tbl_type_2_str(parms->type), - parms->idx); - return -EINVAL; - } + if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { + TFP_DRV_LOG(ERR, + "%s, Invalid or not allocated, type:%s, idx:%d\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + parms->idx); + return -EINVAL; } /* Set the entry */ @@ -398,27 +398,28 @@ tf_tbl_get(struct tf *tfp, } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; - /* Do not check meter drop counter because it is not allocated - * resources. + /* Verify that the entry has been previously allocated. + * for meter drop counter, check the corresponding meter + * entry */ - if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) { - /* Verify that the entry has been previously allocated */ - aparms.rm_db = tbl_db->tbl_db[parms->dir]; + aparms.rm_db = tbl_db->tbl_db[parms->dir]; + if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) aparms.subtype = parms->type; - aparms.index = parms->idx; - aparms.allocated = &allocated; - rc = tf_rm_is_allocated(&aparms); - if (rc) - return rc; + else + aparms.subtype = TF_TBL_TYPE_METER_INST; + aparms.index = parms->idx; + aparms.allocated = &allocated; + rc = tf_rm_is_allocated(&aparms); + if (rc) + return rc; - if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { - TFP_DRV_LOG(ERR, - "%s, Invalid or not allocated index, type:%s, idx:%d\n", - tf_dir_2_str(parms->dir), - tf_tbl_type_2_str(parms->type), - parms->idx); - return -EINVAL; - } + if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { + TFP_DRV_LOG(ERR, + "%s, Invalid or not allocated index, type:%s, idx:%d\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + parms->idx); + return -EINVAL; } /* Set the entry */ -- 2.17.1 ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru ` (19 preceding siblings ...) 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 20/20] net/bnxt: use enum for bank ID Venkat Duvvuru @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 01/20] net/bnxt: add NAT support for dest IP and port combination Ajit Khaparde ` (21 more replies) 20 siblings, 22 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev [-- Attachment #1: Type: text/plain, Size: 4364 bytes --] Enhancements include: * Scaling numbers on Thor * Inner IP header support for GRE tunnel flows * Enable wildcard match for ingress flows * Add clear on read for flow stats on Thor * Add nat support for dest IP and port combination * Remove 2-slice WC support * Add support for socket redirect feature * Add new API TruFlow get SRAM resources * Remove accumulation of stats devargs argument * Add TruFlow and AFM SRAM partitioning support V2: * Compilation fixes * Remove 2-slice WC support * Add support for socket redirect feature * Add new API TruFlow get SRAM resources * Remove accumulation of stats devargs argument * Add TruFlow and AFM SRAM partitioning support V3: * Added one more patch (use enum for bank ID) V4: * Fixed typos in patch 2/20 * Fix checkpatch warnings * Updated commit logs * Rebased the patches to latest dpdk-next-net Farah Smith (1): net/bnxt: add clear on read support Jay Ding (5): net/bnxt: get TruFlow version net/bnxt: add new TruFlow API to get SRAM resources net/bnxt: add TruFlow and AFM SRAM partitioning support net/bnxt: add Tx TruFlow table config for P4 device net/bnxt: use enum for bank ID Kishore Padmanabha (11): net/bnxt: add NAT support for dest IP and port combination net/bnxt: add support for multi root capability net/bnxt: fix out of bounds issue in hash list net/bnxt: add capability option for socket redirect net/bnxt: enable wildcard match for ingress flows net/bnxt: support inner IP header for GRE tunnel flows net/bnxt: remove devargs for stats accumulation net/bnxt: update log messages in TruFlow path net/bnxt: add support for socket direct feature net/bnxt: modify VF representor alloc sequence net/bnxt: check mismatch of control and physical port Mike Baucom (1): net/bnxt: remove 2 slice WC entries Shahaji Bhosle (2): net/bnxt: increase flow scale for Thor net/bnxt: fix clang compiler warnings drivers/net/bnxt/bnxt.h | 25 +- drivers/net/bnxt/bnxt_cpr.c | 2 +- drivers/net/bnxt/bnxt_ethdev.c | 274 +- drivers/net/bnxt/bnxt_hwrm.c | 36 + drivers/net/bnxt/bnxt_hwrm.h | 1 + drivers/net/bnxt/bnxt_reps.c | 9 +- drivers/net/bnxt/hsi_struct_def_dpdk.h | 4007 ++++++++++++++--- drivers/net/bnxt/tf_core/tf_core.c | 197 + drivers/net/bnxt/tf_core/tf_core.h | 202 + drivers/net/bnxt/tf_core/tf_device.c | 11 +- drivers/net/bnxt/tf_core/tf_device.h | 102 + drivers/net/bnxt/tf_core/tf_device_p4.c | 178 +- drivers/net/bnxt/tf_core/tf_device_p4.h | 137 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 421 +- drivers/net/bnxt/tf_core/tf_device_p58.h | 205 +- drivers/net/bnxt/tf_core/tf_msg.c | 87 +- drivers/net/bnxt/tf_core/tf_msg.h | 31 +- drivers/net/bnxt/tf_core/tf_rm.c | 3 +- drivers/net/bnxt/tf_core/tf_sram_mgr.h | 10 - drivers/net/bnxt/tf_core/tf_tbl.c | 83 +- drivers/net/bnxt/tf_core/tf_tbl_sram.c | 13 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 59 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 9 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 29 +- .../generic_templates/ulp_template_db_act.c | 376 +- .../generic_templates/ulp_template_db_class.c | 1986 ++++---- .../generic_templates/ulp_template_db_enum.h | 91 +- .../generic_templates/ulp_template_db_tbl.c | 3946 ++++++++++++---- .../ulp_template_db_thor_act.c | 150 +- .../ulp_template_db_thor_class.c | 909 ++-- .../ulp_template_db_wh_plus_act.c | 336 +- .../ulp_template_db_wh_plus_class.c | 222 +- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 8 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 12 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 20 +- drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_port_db.c | 23 + drivers/net/bnxt/tf_ulp/ulp_port_db.h | 13 + drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 32 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +- 41 files changed, 10223 insertions(+), 4038 deletions(-) -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 01/20] net/bnxt: add NAT support for dest IP and port combination 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 02/20] net/bnxt: add support for multi root capability Ajit Khaparde ` (20 subsequent siblings) 21 siblings, 1 reply; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev Cc: Kishore Padmanabha, Venkat Duvvuru, Shahaji Bhosle, Mike Baucom, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 40793 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> * Added support for NAT action for the destination IP and port combination for the Thor platform. This is not supported for Whitney platform. * Consolidated the encapsulation and NAT entries for scaling flows with NAT actions. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- .../generic_templates/ulp_template_db_act.c | 376 +++++++++++------- .../generic_templates/ulp_template_db_enum.h | 18 +- .../generic_templates/ulp_template_db_tbl.c | 14 +- .../ulp_template_db_thor_class.c | 2 +- .../ulp_template_db_wh_plus_act.c | 96 +++-- 5 files changed, 317 insertions(+), 189 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c index 0da6070d7d..ce878d8e02 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon May 17 15:30:41 2021 */ +/* date: Wed Aug 25 14:37:06 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -47,59 +47,67 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { [BNXT_ULP_ACT_HID_04bc] = 30, [BNXT_ULP_ACT_HID_00a9] = 31, [BNXT_ULP_ACT_HID_020f] = 32, - [BNXT_ULP_ACT_HID_04a9] = 33, - [BNXT_ULP_ACT_HID_01fc] = 34, - [BNXT_ULP_ACT_HID_04be] = 35, - [BNXT_ULP_ACT_HID_00ab] = 36, - [BNXT_ULP_ACT_HID_0211] = 37, - [BNXT_ULP_ACT_HID_04ab] = 38, - [BNXT_ULP_ACT_HID_01fe] = 39, - [BNXT_ULP_ACT_HID_0667] = 40, - [BNXT_ULP_ACT_HID_0254] = 41, - [BNXT_ULP_ACT_HID_03ba] = 42, - [BNXT_ULP_ACT_HID_0654] = 43, - [BNXT_ULP_ACT_HID_03a7] = 44, - [BNXT_ULP_ACT_HID_0669] = 45, - [BNXT_ULP_ACT_HID_0256] = 46, - [BNXT_ULP_ACT_HID_03bc] = 47, - [BNXT_ULP_ACT_HID_0656] = 48, - [BNXT_ULP_ACT_HID_03a9] = 49, - [BNXT_ULP_ACT_HID_021b] = 50, - [BNXT_ULP_ACT_HID_021c] = 51, - [BNXT_ULP_ACT_HID_021e] = 52, - [BNXT_ULP_ACT_HID_063f] = 53, - [BNXT_ULP_ACT_HID_0510] = 54, - [BNXT_ULP_ACT_HID_03c6] = 55, - [BNXT_ULP_ACT_HID_0082] = 56, - [BNXT_ULP_ACT_HID_06bb] = 57, - [BNXT_ULP_ACT_HID_021d] = 58, - [BNXT_ULP_ACT_HID_0641] = 59, - [BNXT_ULP_ACT_HID_0512] = 60, - [BNXT_ULP_ACT_HID_03c8] = 61, - [BNXT_ULP_ACT_HID_0084] = 62, - [BNXT_ULP_ACT_HID_06bd] = 63, - [BNXT_ULP_ACT_HID_06d7] = 64, - [BNXT_ULP_ACT_HID_02c4] = 65, - [BNXT_ULP_ACT_HID_042a] = 66, - [BNXT_ULP_ACT_HID_06c4] = 67, - [BNXT_ULP_ACT_HID_0417] = 68, - [BNXT_ULP_ACT_HID_06d9] = 69, - [BNXT_ULP_ACT_HID_02c6] = 70, - [BNXT_ULP_ACT_HID_042c] = 71, - [BNXT_ULP_ACT_HID_06c6] = 72, - [BNXT_ULP_ACT_HID_0419] = 73, - [BNXT_ULP_ACT_HID_0119] = 74, - [BNXT_ULP_ACT_HID_046f] = 75, - [BNXT_ULP_ACT_HID_05d5] = 76, - [BNXT_ULP_ACT_HID_0106] = 77, - [BNXT_ULP_ACT_HID_05c2] = 78, - [BNXT_ULP_ACT_HID_011b] = 79, - [BNXT_ULP_ACT_HID_0471] = 80, - [BNXT_ULP_ACT_HID_05d7] = 81, - [BNXT_ULP_ACT_HID_0108] = 82, - [BNXT_ULP_ACT_HID_05c4] = 83, - [BNXT_ULP_ACT_HID_00a2] = 84, - [BNXT_ULP_ACT_HID_00a4] = 85 + [BNXT_ULP_ACT_HID_0153] = 33, + [BNXT_ULP_ACT_HID_04a9] = 34, + [BNXT_ULP_ACT_HID_01fc] = 35, + [BNXT_ULP_ACT_HID_04be] = 36, + [BNXT_ULP_ACT_HID_00ab] = 37, + [BNXT_ULP_ACT_HID_0211] = 38, + [BNXT_ULP_ACT_HID_0155] = 39, + [BNXT_ULP_ACT_HID_04ab] = 40, + [BNXT_ULP_ACT_HID_01fe] = 41, + [BNXT_ULP_ACT_HID_0667] = 42, + [BNXT_ULP_ACT_HID_0254] = 43, + [BNXT_ULP_ACT_HID_03ba] = 44, + [BNXT_ULP_ACT_HID_02fe] = 45, + [BNXT_ULP_ACT_HID_0654] = 46, + [BNXT_ULP_ACT_HID_03a7] = 47, + [BNXT_ULP_ACT_HID_0669] = 48, + [BNXT_ULP_ACT_HID_0256] = 49, + [BNXT_ULP_ACT_HID_03bc] = 50, + [BNXT_ULP_ACT_HID_0300] = 51, + [BNXT_ULP_ACT_HID_0656] = 52, + [BNXT_ULP_ACT_HID_03a9] = 53, + [BNXT_ULP_ACT_HID_021b] = 54, + [BNXT_ULP_ACT_HID_021c] = 55, + [BNXT_ULP_ACT_HID_021e] = 56, + [BNXT_ULP_ACT_HID_063f] = 57, + [BNXT_ULP_ACT_HID_0510] = 58, + [BNXT_ULP_ACT_HID_03c6] = 59, + [BNXT_ULP_ACT_HID_0082] = 60, + [BNXT_ULP_ACT_HID_06bb] = 61, + [BNXT_ULP_ACT_HID_021d] = 62, + [BNXT_ULP_ACT_HID_0641] = 63, + [BNXT_ULP_ACT_HID_0512] = 64, + [BNXT_ULP_ACT_HID_03c8] = 65, + [BNXT_ULP_ACT_HID_0084] = 66, + [BNXT_ULP_ACT_HID_06bd] = 67, + [BNXT_ULP_ACT_HID_06d7] = 68, + [BNXT_ULP_ACT_HID_02c4] = 69, + [BNXT_ULP_ACT_HID_042a] = 70, + [BNXT_ULP_ACT_HID_036e] = 71, + [BNXT_ULP_ACT_HID_06c4] = 72, + [BNXT_ULP_ACT_HID_0417] = 73, + [BNXT_ULP_ACT_HID_06d9] = 74, + [BNXT_ULP_ACT_HID_02c6] = 75, + [BNXT_ULP_ACT_HID_042c] = 76, + [BNXT_ULP_ACT_HID_0370] = 77, + [BNXT_ULP_ACT_HID_06c6] = 78, + [BNXT_ULP_ACT_HID_0419] = 79, + [BNXT_ULP_ACT_HID_0119] = 80, + [BNXT_ULP_ACT_HID_046f] = 81, + [BNXT_ULP_ACT_HID_05d5] = 82, + [BNXT_ULP_ACT_HID_0519] = 83, + [BNXT_ULP_ACT_HID_0106] = 84, + [BNXT_ULP_ACT_HID_05c2] = 85, + [BNXT_ULP_ACT_HID_011b] = 86, + [BNXT_ULP_ACT_HID_0471] = 87, + [BNXT_ULP_ACT_HID_05d7] = 88, + [BNXT_ULP_ACT_HID_051b] = 89, + [BNXT_ULP_ACT_HID_0108] = 90, + [BNXT_ULP_ACT_HID_05c4] = 91, + [BNXT_ULP_ACT_HID_00a2] = 92, + [BNXT_ULP_ACT_HID_00a4] = 93 }; /* Array for the act matcher list */ @@ -429,22 +437,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 3 }, [33] = { - .act_hid = BNXT_ULP_ACT_HID_04a9, + .act_hid = BNXT_ULP_ACT_HID_0153, .act_pattern_id = 3, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [34] = { - .act_hid = BNXT_ULP_ACT_HID_01fc, + .act_hid = BNXT_ULP_ACT_HID_04a9, .act_pattern_id = 4, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | @@ -452,40 +458,63 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 3 }, [35] = { - .act_hid = BNXT_ULP_ACT_HID_04be, + .act_hid = BNXT_ULP_ACT_HID_01fc, .act_pattern_id = 5, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [36] = { - .act_hid = BNXT_ULP_ACT_HID_00ab, + .act_hid = BNXT_ULP_ACT_HID_04be, .act_pattern_id = 6, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [37] = { - .act_hid = BNXT_ULP_ACT_HID_0211, + .act_hid = BNXT_ULP_ACT_HID_00ab, .act_pattern_id = 7, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [38] = { - .act_hid = BNXT_ULP_ACT_HID_04ab, + .act_hid = BNXT_ULP_ACT_HID_0211, .act_pattern_id = 8, .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [39] = { + .act_hid = BNXT_ULP_ACT_HID_0155, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [40] = { + .act_hid = BNXT_ULP_ACT_HID_04ab, + .act_pattern_id = 10, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -494,9 +523,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [39] = { + [41] = { .act_hid = BNXT_ULP_ACT_HID_01fe, - .act_pattern_id = 9, + .act_pattern_id = 11, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -507,9 +536,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [40] = { + [42] = { .act_hid = BNXT_ULP_ACT_HID_0667, - .act_pattern_id = 10, + .act_pattern_id = 12, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -517,9 +546,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [41] = { + [43] = { .act_hid = BNXT_ULP_ACT_HID_0254, - .act_pattern_id = 11, + .act_pattern_id = 13, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -528,9 +557,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [42] = { + [44] = { .act_hid = BNXT_ULP_ACT_HID_03ba, - .act_pattern_id = 12, + .act_pattern_id = 14, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -538,9 +567,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [43] = { + [45] = { + .act_hid = BNXT_ULP_ACT_HID_02fe, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [46] = { .act_hid = BNXT_ULP_ACT_HID_0654, - .act_pattern_id = 13, + .act_pattern_id = 16, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -550,9 +590,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [44] = { + [47] = { .act_hid = BNXT_ULP_ACT_HID_03a7, - .act_pattern_id = 14, + .act_pattern_id = 17, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -563,9 +603,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [45] = { + [48] = { .act_hid = BNXT_ULP_ACT_HID_0669, - .act_pattern_id = 15, + .act_pattern_id = 18, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -574,9 +614,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [46] = { + [49] = { .act_hid = BNXT_ULP_ACT_HID_0256, - .act_pattern_id = 16, + .act_pattern_id = 19, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -586,9 +626,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [47] = { + [50] = { .act_hid = BNXT_ULP_ACT_HID_03bc, - .act_pattern_id = 17, + .act_pattern_id = 20, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -597,9 +637,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [48] = { + [51] = { + .act_hid = BNXT_ULP_ACT_HID_0300, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [52] = { .act_hid = BNXT_ULP_ACT_HID_0656, - .act_pattern_id = 18, + .act_pattern_id = 22, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -610,9 +662,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [49] = { + [53] = { .act_hid = BNXT_ULP_ACT_HID_03a9, - .act_pattern_id = 19, + .act_pattern_id = 23, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -624,7 +676,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [50] = { + [54] = { .act_hid = BNXT_ULP_ACT_HID_021b, .act_pattern_id = 0, .app_sig = 0, @@ -632,7 +684,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [51] = { + [55] = { .act_hid = BNXT_ULP_ACT_HID_021c, .act_pattern_id = 1, .app_sig = 0, @@ -641,7 +693,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [52] = { + [56] = { .act_hid = BNXT_ULP_ACT_HID_021e, .act_pattern_id = 2, .app_sig = 0, @@ -651,7 +703,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [53] = { + [57] = { .act_hid = BNXT_ULP_ACT_HID_063f, .act_pattern_id = 3, .app_sig = 0, @@ -662,7 +714,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [54] = { + [58] = { .act_hid = BNXT_ULP_ACT_HID_0510, .act_pattern_id = 4, .app_sig = 0, @@ -672,7 +724,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [55] = { + [59] = { .act_hid = BNXT_ULP_ACT_HID_03c6, .act_pattern_id = 5, .app_sig = 0, @@ -681,7 +733,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [56] = { + [60] = { .act_hid = BNXT_ULP_ACT_HID_0082, .act_pattern_id = 6, .app_sig = 0, @@ -693,7 +745,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [57] = { + [61] = { .act_hid = BNXT_ULP_ACT_HID_06bb, .act_pattern_id = 7, .app_sig = 0, @@ -704,7 +756,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [58] = { + [62] = { .act_hid = BNXT_ULP_ACT_HID_021d, .act_pattern_id = 8, .app_sig = 0, @@ -713,7 +765,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [59] = { + [63] = { .act_hid = BNXT_ULP_ACT_HID_0641, .act_pattern_id = 9, .app_sig = 0, @@ -725,7 +777,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [60] = { + [64] = { .act_hid = BNXT_ULP_ACT_HID_0512, .act_pattern_id = 10, .app_sig = 0, @@ -736,7 +788,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [61] = { + [65] = { .act_hid = BNXT_ULP_ACT_HID_03c8, .act_pattern_id = 11, .app_sig = 0, @@ -746,7 +798,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [62] = { + [66] = { .act_hid = BNXT_ULP_ACT_HID_0084, .act_pattern_id = 12, .app_sig = 0, @@ -759,7 +811,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [63] = { + [67] = { .act_hid = BNXT_ULP_ACT_HID_06bd, .act_pattern_id = 13, .app_sig = 0, @@ -771,7 +823,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [64] = { + [68] = { .act_hid = BNXT_ULP_ACT_HID_06d7, .act_pattern_id = 0, .app_sig = 0, @@ -780,7 +832,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [65] = { + [69] = { .act_hid = BNXT_ULP_ACT_HID_02c4, .act_pattern_id = 1, .app_sig = 0, @@ -790,7 +842,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [66] = { + [70] = { .act_hid = BNXT_ULP_ACT_HID_042a, .act_pattern_id = 2, .app_sig = 0, @@ -799,10 +851,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [67] = { - .act_hid = BNXT_ULP_ACT_HID_06c4, + [71] = { + .act_hid = BNXT_ULP_ACT_HID_036e, .act_pattern_id = 3, .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [72] = { + .act_hid = BNXT_ULP_ACT_HID_06c4, + .act_pattern_id = 4, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | @@ -810,9 +872,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [68] = { + [73] = { .act_hid = BNXT_ULP_ACT_HID_0417, - .act_pattern_id = 4, + .act_pattern_id = 5, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -822,9 +884,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [69] = { + [74] = { .act_hid = BNXT_ULP_ACT_HID_06d9, - .act_pattern_id = 5, + .act_pattern_id = 6, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -832,9 +894,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [70] = { + [75] = { .act_hid = BNXT_ULP_ACT_HID_02c6, - .act_pattern_id = 6, + .act_pattern_id = 7, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -843,9 +905,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [71] = { + [76] = { .act_hid = BNXT_ULP_ACT_HID_042c, - .act_pattern_id = 7, + .act_pattern_id = 8, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -853,9 +915,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [72] = { + [77] = { + .act_hid = BNXT_ULP_ACT_HID_0370, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [78] = { .act_hid = BNXT_ULP_ACT_HID_06c6, - .act_pattern_id = 8, + .act_pattern_id = 10, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -865,9 +938,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [73] = { + [79] = { .act_hid = BNXT_ULP_ACT_HID_0419, - .act_pattern_id = 9, + .act_pattern_id = 11, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -878,9 +951,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [74] = { + [80] = { .act_hid = BNXT_ULP_ACT_HID_0119, - .act_pattern_id = 10, + .act_pattern_id = 12, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -888,9 +961,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [75] = { + [81] = { .act_hid = BNXT_ULP_ACT_HID_046f, - .act_pattern_id = 11, + .act_pattern_id = 13, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -899,9 +972,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [76] = { + [82] = { .act_hid = BNXT_ULP_ACT_HID_05d5, - .act_pattern_id = 12, + .act_pattern_id = 14, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -909,9 +982,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [77] = { + [83] = { + .act_hid = BNXT_ULP_ACT_HID_0519, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [84] = { .act_hid = BNXT_ULP_ACT_HID_0106, - .act_pattern_id = 13, + .act_pattern_id = 16, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -921,9 +1005,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [78] = { + [85] = { .act_hid = BNXT_ULP_ACT_HID_05c2, - .act_pattern_id = 14, + .act_pattern_id = 17, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -934,9 +1018,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [79] = { + [86] = { .act_hid = BNXT_ULP_ACT_HID_011b, - .act_pattern_id = 15, + .act_pattern_id = 18, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -945,9 +1029,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [80] = { + [87] = { .act_hid = BNXT_ULP_ACT_HID_0471, - .act_pattern_id = 16, + .act_pattern_id = 19, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -957,9 +1041,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [81] = { + [88] = { .act_hid = BNXT_ULP_ACT_HID_05d7, - .act_pattern_id = 17, + .act_pattern_id = 20, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -968,9 +1052,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [82] = { + [89] = { + .act_hid = BNXT_ULP_ACT_HID_051b, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [90] = { .act_hid = BNXT_ULP_ACT_HID_0108, - .act_pattern_id = 18, + .act_pattern_id = 22, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -981,9 +1077,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [83] = { + [91] = { .act_hid = BNXT_ULP_ACT_HID_05c4, - .act_pattern_id = 19, + .act_pattern_id = 23, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -995,7 +1091,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [84] = { + [92] = { .act_hid = BNXT_ULP_ACT_HID_00a2, .act_pattern_id = 0, .app_sig = 0, @@ -1004,7 +1100,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [85] = { + [93] = { .act_hid = BNXT_ULP_ACT_HID_00a4, .act_pattern_id = 1, .app_sig = 0, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index c016e1940a..fcd460e707 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 20 17:59:14 2021 */ +/* date: Thu Aug 26 17:43:36 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -20,7 +20,7 @@ #define BNXT_ULP_CLASS_HID_SHFTL 28 #define BNXT_ULP_CLASS_HID_MASK 65535 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 -#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86 +#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 94 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 #define BNXT_ULP_ACT_HID_HIGH_PRIME 3793 #define BNXT_ULP_ACT_HID_SHFTR 27 @@ -29,7 +29,7 @@ #define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110 #define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50 -#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278 +#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 277 #define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 @@ -50,11 +50,11 @@ #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313 #define ULP_THOR_CLASS_COND_LIST_SIZE 55 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 -#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35 +#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1 #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536 -#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39 +#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 41 #define ULP_THOR_ACT_TMPL_LIST_SIZE 7 #define ULP_THOR_ACT_TBL_LIST_SIZE 36 #define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16 @@ -2224,21 +2224,25 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_04bc = 0x04bc, BNXT_ULP_ACT_HID_00a9 = 0x00a9, BNXT_ULP_ACT_HID_020f = 0x020f, + BNXT_ULP_ACT_HID_0153 = 0x0153, BNXT_ULP_ACT_HID_04a9 = 0x04a9, BNXT_ULP_ACT_HID_01fc = 0x01fc, BNXT_ULP_ACT_HID_04be = 0x04be, BNXT_ULP_ACT_HID_00ab = 0x00ab, BNXT_ULP_ACT_HID_0211 = 0x0211, + BNXT_ULP_ACT_HID_0155 = 0x0155, BNXT_ULP_ACT_HID_04ab = 0x04ab, BNXT_ULP_ACT_HID_01fe = 0x01fe, BNXT_ULP_ACT_HID_0667 = 0x0667, BNXT_ULP_ACT_HID_0254 = 0x0254, BNXT_ULP_ACT_HID_03ba = 0x03ba, + BNXT_ULP_ACT_HID_02fe = 0x02fe, BNXT_ULP_ACT_HID_0654 = 0x0654, BNXT_ULP_ACT_HID_03a7 = 0x03a7, BNXT_ULP_ACT_HID_0669 = 0x0669, BNXT_ULP_ACT_HID_0256 = 0x0256, BNXT_ULP_ACT_HID_03bc = 0x03bc, + BNXT_ULP_ACT_HID_0300 = 0x0300, BNXT_ULP_ACT_HID_0656 = 0x0656, BNXT_ULP_ACT_HID_03a9 = 0x03a9, BNXT_ULP_ACT_HID_021b = 0x021b, @@ -2258,21 +2262,25 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_06d7 = 0x06d7, BNXT_ULP_ACT_HID_02c4 = 0x02c4, BNXT_ULP_ACT_HID_042a = 0x042a, + BNXT_ULP_ACT_HID_036e = 0x036e, BNXT_ULP_ACT_HID_06c4 = 0x06c4, BNXT_ULP_ACT_HID_0417 = 0x0417, BNXT_ULP_ACT_HID_06d9 = 0x06d9, BNXT_ULP_ACT_HID_02c6 = 0x02c6, BNXT_ULP_ACT_HID_042c = 0x042c, + BNXT_ULP_ACT_HID_0370 = 0x0370, BNXT_ULP_ACT_HID_06c6 = 0x06c6, BNXT_ULP_ACT_HID_0419 = 0x0419, BNXT_ULP_ACT_HID_0119 = 0x0119, BNXT_ULP_ACT_HID_046f = 0x046f, BNXT_ULP_ACT_HID_05d5 = 0x05d5, + BNXT_ULP_ACT_HID_0519 = 0x0519, BNXT_ULP_ACT_HID_0106 = 0x0106, BNXT_ULP_ACT_HID_05c2 = 0x05c2, BNXT_ULP_ACT_HID_011b = 0x011b, BNXT_ULP_ACT_HID_0471 = 0x0471, BNXT_ULP_ACT_HID_05d7 = 0x05d7, + BNXT_ULP_ACT_HID_051b = 0x051b, BNXT_ULP_ACT_HID_0108 = 0x0108, BNXT_ULP_ACT_HID_05c4 = 0x05c4, BNXT_ULP_ACT_HID_00a2 = 0x00a2, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 684fa66f48..84be09b368 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Aug 17 12:16:42 2021 */ +/* date: Thu Aug 26 17:43:36 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -2121,7 +2121,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 2048 }, { .app_id = 0, @@ -2249,7 +2249,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 2048 }, { .app_id = 0, @@ -2263,14 +2263,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, - .count = 32 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 272 diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 68c1e292b2..95205a2421 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 20 18:05:25 2021 */ +/* date: Wed Aug 25 16:41:37 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c index 578ede8bba..4a2d201c2d 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Jun 1 16:05:30 2021 */ +/* date: Wed Aug 25 14:37:06 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -35,7 +35,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { /* act_tid: 3, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, + .num_tbls = 7, .start_tbl_idx = 12, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, @@ -46,30 +46,30 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, - .start_tbl_idx = 18, + .start_tbl_idx = 19, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 20, + .cond_start_idx = 21, .cond_nums = 0 } }, /* act_tid: 5, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 23, + .num_tbls = 7, + .start_tbl_idx = 24, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 28, + .cond_start_idx = 29, .cond_nums = 0 } }, /* act_tid: 6, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, - .start_tbl_idx = 29, + .start_tbl_idx = 31, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 0 } } }; @@ -322,6 +322,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 34, .result_num_fields = 2 }, + { /* act_tid: 3, , table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 15, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, { /* act_tid: 3, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, @@ -332,7 +343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 15, + .cond_start_idx = 16, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -351,7 +362,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 16, + .cond_start_idx = 17, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, @@ -370,7 +381,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, + .cond_start_idx = 18, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, @@ -389,7 +400,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, @@ -410,7 +421,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 18, + .cond_start_idx = 19, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -429,7 +440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 19, + .cond_start_idx = 20, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -449,7 +460,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 21, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -468,7 +479,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 21, + .cond_start_idx = 22, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -489,7 +500,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 23, + .cond_start_idx = 24, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -508,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 25, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -528,7 +539,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 26, + .cond_start_idx = 27, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -538,6 +549,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 11 }, + { /* act_tid: 5, , table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 29, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, { /* act_tid: 5, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, @@ -548,7 +570,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 28, + .cond_start_idx = 30, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -567,7 +589,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, + .cond_start_idx = 31, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, @@ -586,7 +608,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 32, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, @@ -605,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 33, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, @@ -626,7 +648,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, + .cond_start_idx = 33, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -645,7 +667,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, + .cond_start_idx = 34, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -665,7 +687,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -684,7 +706,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 36, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, @@ -705,7 +727,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 37, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, @@ -726,7 +748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 38, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -747,7 +769,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 39, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -766,7 +788,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, + .cond_start_idx = 40, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -844,6 +866,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, + /* cond_execute: act_tid: 3, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, @@ -900,6 +927,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN }, + /* cond_execute: act_tid: 5, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH v4 01/20] net/bnxt: add NAT support for dest IP and port combination 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 01/20] net/bnxt: add NAT support for dest IP and port combination Ajit Khaparde @ 2021-11-03 13:24 ` Ferruh Yigit 0 siblings, 0 replies; 118+ messages in thread From: Ferruh Yigit @ 2021-11-03 13:24 UTC (permalink / raw) To: Ajit Khaparde, dev Cc: Kishore Padmanabha, Venkat Duvvuru, Shahaji Bhosle, Mike Baucom, Randy Schacher On 11/3/2021 12:52 AM, Ajit Khaparde wrote: > From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> > > * Added support for NAT action for the destination IP and port > combination for the Thor platform. This is not supported for > Whitney platform. I know a Whitley platform but I guess this is something else, still want to highlight if it is a typo. And if it matters can you please describe what that platform is, since there is not documentation etc for the limitation, can be good to have some information at least in the commit log. > * Consolidated the encapsulation and NAT entries for scaling flows > with NAT actions. > > Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> > Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> > Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com> > Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> > Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> > Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> <...> ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 02/20] net/bnxt: add support for multi root capability 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 01/20] net/bnxt: add NAT support for dest IP and port combination Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 03/20] net/bnxt: fix out of bounds issue in hash list Ajit Khaparde ` (19 subsequent siblings) 21 siblings, 1 reply; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Mike Baucom, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 185940 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Update driver to read the multi root capability and ignore pci address check while creating ulp session when multi root capability is enabled in the hardware. DPDK HSI version updated from 1.10.1.70 to 1.10.2.68. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/bnxt.h | 3 + drivers/net/bnxt/bnxt_hwrm.c | 8 + drivers/net/bnxt/hsi_struct_def_dpdk.h | 4007 ++++++++++++++++++++---- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 10 +- 4 files changed, 3496 insertions(+), 532 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 39bd739c7b..97e281a2fc 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -723,6 +723,9 @@ struct bnxt { uint16_t chip_num; #define CHIP_NUM_58818 0xd818 #define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818) +#define BNXT_FLAGS2_MULTIROOT_EN BIT(4) +#define BNXT_MULTIROOT_EN(bp) \ + ((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN) uint32_t fw_cap; #define BNXT_FW_CAP_HOT_RESET BIT(0) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 55dcb1dd6a..37640abcbe 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -3363,6 +3363,7 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp) { struct hwrm_func_qcfg_input req = {0}; struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; + uint16_t flags; int rc; if (!BNXT_VF_IS_TRUSTED(bp)) @@ -3386,6 +3387,13 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp) bp->parent->fid = rte_le_to_cpu_16(resp->fid); bp->parent->port_id = rte_le_to_cpu_16(resp->port_id); + flags = rte_le_to_cpu_16(resp->flags); + /* check for the multi-root support */ + if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) { + bp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN; + PMD_DRV_LOG(DEBUG, "PF enabled with multi root capability\n"); + } + HWRM_UNLOCK(); return 0; diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 4d7efb19f4..01ee14645c 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -657,6 +657,12 @@ struct cmd_nums { #define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0) /* PTP - Query extended PTP configuration. */ #define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1) + /* The command is used to allocate KTLS crypto key contexts. */ + #define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2) + /* The is the new API to configure backing stores. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2 UINT32_C(0x1a3) + /* The is the new API to query backing store configurations. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2 UINT32_C(0x1a4) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -714,6 +720,18 @@ struct cmd_nums { * calculated during firmware boot. */ #define HWRM_MFG_GET_NVM_MEASUREMENT UINT32_C(0x214) + /* Retrieves the PSOC status and provisioning information. */ + #define HWRM_MFG_PSOC_QSTATUS UINT32_C(0x215) + /* + * This command allows manufacturing tool to determine which selftests + * are available to be run. + */ + #define HWRM_MFG_SELFTEST_QLIST UINT32_C(0x216) + /* + * This command allows manufacturing tool to request which selftests + * to run. + */ + #define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217) /* Experimental */ #define HWRM_TF UINT32_C(0x2bc) /* Experimental */ @@ -1056,8 +1074,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 44 -#define HWRM_VERSION_STR "1.10.2.44" +#define HWRM_VERSION_RSVD 68 +#define HWRM_VERSION_STR "1.10.2.68" /**************** * hwrm_ver_get * @@ -1357,6 +1375,12 @@ struct hwrm_ver_get_output { */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \ UINT32_C(0x4000) + /* + * If set to 1, then firmware supports secure boot. + * If set to 0, then firmware doesn't support secure boot. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE \ + UINT32_C(0x8000) /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. @@ -8283,8 +8307,14 @@ struct hwrm_async_event_cmpl_reset_notify { /* Fast reset */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \ (UINT32_C(0x4) << 8) + /* + * Reset was a result of a firmware activation. That is, the + * fw_activation flag was set in a FW_RESET operation. + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION \ + (UINT32_C(0x5) << 8) #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION /* * Minimum time before driver should attempt access - units 100ms ticks. * Range 0-65535 @@ -10244,8 +10274,21 @@ struct hwrm_async_event_cmpl_error_report_base { */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \ UINT32_C(0x2) + /* + * There was a low level error with an NVM write or erase. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM \ + UINT32_C(0x3) + /* + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD } __rte_packed; /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ @@ -10386,6 +10429,162 @@ struct hwrm_async_event_cmpl_error_report_invalid_signal { HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL } __rte_packed; +/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_nvm { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Indicates the address where error was detected */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK \ + UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT \ + 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * There was a low level error with an NVM operation. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR + /* The specific type of NVM error */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT \ + 8 + /* + * There was a low level error with an NVM write operation. + * Verification of written data did not match. + * event_data2 will be the failing address. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE \ + (UINT32_C(0x1) << 8) + /* + * There was a low level error with an NVM erase operation. + * All the bits were not erased. + * event_data2 will be the failing address. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE \ + (UINT32_C(0x2) << 8) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT \ + 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD +} __rte_packed; + /* metadata_base_msg (size:64b/8B) */ struct metadata_base_msg { uint16_t md_type_link; @@ -11204,6 +11403,18 @@ struct hwrm_func_vf_cfg_input { */ #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ UINT32_C(0x800) + /* + * This bit must be '1' for the num_tx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the num_rx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS \ + UINT32_C(0x2000) /* * The maximum transmission unit requested on the function. * The HWRM should make sure that the mtu of @@ -11353,7 +11564,10 @@ struct hwrm_func_vf_cfg_input { uint16_t num_stat_ctxs; /* The number of HW ring groups requested for the VF. */ uint16_t num_hw_ring_grps; - uint8_t unused_0[4]; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; } __rte_packed; /* hwrm_func_vf_cfg_output (size:128b/16B) */ @@ -11423,7 +11637,7 @@ struct hwrm_func_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcaps_output (size:704b/88B) */ +/* hwrm_func_qcaps_output (size:768b/96B) */ struct hwrm_func_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -11787,7 +12001,13 @@ struct hwrm_func_qcaps_output { * (max_tx_rings) to the function. */ uint16_t max_sp_tx_rings; - uint8_t unused_0[2]; + /* + * The maximum number of MSI-X vectors that may be allocated across + * all VFs for the function. This is valid only on the PF with SR-IOV + * enabled. Returns zero if this command is called on a PF with + * SR-IOV disabled or on a VF. + */ + uint16_t max_msix_vfs; uint32_t flags_ext; /* * If 1, the device can be configured to set the ECN bits in the @@ -11911,7 +12131,9 @@ struct hwrm_func_qcaps_output { UINT32_C(0x80000) /* * When this bit is '1', the NIC supports configuration of - * partition_min_bw and partition_max_bw. + * partition_min_bw and partition_max_bw. Configuration of a + * minimum guaranteed bandwidth is only supported if the + * min_bw_supported flag is also set. */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PARTITION_BW_SUPPORTED \ UINT32_C(0x100000) @@ -11928,10 +12150,39 @@ struct hwrm_func_qcaps_output { * When this bit is '1', the firmware supports HWRM_PORT_EP_TX_CFG * and HWRM_PORT_EP_TX_QCFG for endpoint rate control, and additions * to HWRM_QUEUE_GLOBAL_CFG and HWRM_QUEUE_GLOBAL_QCFG for receive - * rate control. + * rate control. Configuration of a minimum guaranteed bandwidth + * is only supported if the min_bw_supported flag is also set. */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EP_RATE_CONTROL \ UINT32_C(0x800000) + /* + * When this bit is '1', the firmware supports enforcement of + * minimum guaranteed bandwidth. A minimum guaranteed bandwidth + * could be configured for a partition or for an endpoint. Firmware + * only sets this flag if one or both of the ep_rate_control and + * partition_bw_supported flags are set. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_MIN_BW_SUPPORTED \ + UINT32_C(0x1000000) + /* + * When this bit is '1', HW supports TX coalesced completion + * records. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_COAL_CMPL_CAP \ + UINT32_C(0x2000000) + /* + * When this bit is '1', it indicates the FW has full support + * for all backing store types with the BACKING_STORE_CFG/QCFG + * V2 APIs. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_SUPPORTED \ + UINT32_C(0x4000000) + /* + * When this bit is '1', it indicates the FW forces to use the + * BACKING_STORE_CFG/QCFG V2 APIs. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_REQUIRED \ + UINT32_C(0x8000000) /* The maximum number of SCHQs supported by this device. */ uint8_t max_schqs; uint8_t mpc_chnls_cap; @@ -11965,7 +12216,12 @@ struct hwrm_func_qcaps_output { * to the primate processor block. */ #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10) - uint8_t unused_1; + /* + * Maximum number of Key Contexts supported per HWRM + * function call for allocating Key Contexts. + */ + uint16_t max_key_ctxs_alloc; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12023,7 +12279,7 @@ struct hwrm_func_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcfg_output (size:832b/104B) */ +/* hwrm_func_qcfg_output (size:896b/112B) */ struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -12614,7 +12870,11 @@ struct hwrm_func_qcfg_output { * value is used if ring MTU is not specified. */ uint16_t host_mtu; - uint8_t unused_3; + /* Number of Tx Key Contexts allocated. */ + uint16_t alloc_tx_key_ctxs; + /* Number of Rx Key Contexts allocated. */ + uint16_t alloc_rx_key_ctxs; + uint8_t unused_3[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12630,7 +12890,7 @@ struct hwrm_func_qcfg_output { *****************/ -/* hwrm_func_cfg_input (size:832b/104B) */ +/* hwrm_func_cfg_input (size:896b/112B) */ struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -13076,6 +13336,18 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \ UINT32_C(0x20000000) + /* + * This bit must be '1' for the number of Tx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS \ + UINT32_C(0x40000000) + /* + * This bit must be '1' for the number of Rx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS \ + UINT32_C(0x80000000) /* * This field can be used by the admin PF to configure * mtu of foster PFs. @@ -13527,6 +13799,11 @@ struct hwrm_func_cfg_input { * ring that is assigned to a function has a valid mtu. */ uint16_t host_mtu; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; + uint8_t unused_0[4]; } __rte_packed; /* hwrm_func_cfg_output (size:128b/16B) */ @@ -13550,6 +13827,33 @@ struct hwrm_func_cfg_output { uint8_t valid; } __rte_packed; +/* hwrm_func_cfg_cmd_err (size:64b/8B) */ +struct hwrm_func_cfg_cmd_err { + /* command specific error codes for the cmd_err field in hwrm_err_output */ + uint8_t code; + /* Unknown error. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* The partition minimum bandwidth is out of range. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE \ + UINT32_C(0x1) + /* The minimum bandwidth is more than the maximum bandwidth. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX \ + UINT32_C(0x2) + /* + * The NIC does not support enforcement of a minimum guaranteed + * bandwidth for a partition. + */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED \ + UINT32_C(0x3) + /* Partition bandwidths must be specified as a percentage. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT \ + UINT32_C(0x4) + #define HWRM_FUNC_CFG_CMD_ERR_CODE_LAST \ + HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT + uint8_t unused_0[7]; +} __rte_packed; + /******************** * hwrm_func_qstats * ********************/ @@ -14103,6 +14407,13 @@ struct hwrm_func_drv_rgtr_input { */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \ UINT32_C(0x100) + /* + * When this bit is 1, the function's driver is indicating the + * support of handling the NPAR 1.2 feature where the s-tag may be + * a value other than 0x8100 or 0x88a8. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \ + UINT32_C(0x200) uint32_t enables; /* * This bit must be '1' for the os_type field to be @@ -14664,7 +14975,7 @@ struct hwrm_func_resource_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_resource_qcaps_output (size:448b/56B) */ +/* hwrm_func_resource_qcaps_output (size:512b/64B) */ struct hwrm_func_resource_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -14739,6 +15050,14 @@ struct hwrm_func_resource_qcaps_output { */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output @@ -14755,7 +15074,7 @@ struct hwrm_func_resource_qcaps_output { *****************************/ -/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ +/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ struct hwrm_func_vf_resource_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -14829,6 +15148,14 @@ struct hwrm_func_vf_resource_cfg_input { */ #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; uint8_t unused_0[2]; } __rte_packed; @@ -14858,7 +15185,11 @@ struct hwrm_func_vf_resource_cfg_output { uint16_t reserved_stat_ctx; /* Reserved number of ring groups */ uint16_t reserved_hw_ring_grps; - uint8_t unused_0[7]; + /* Actual number of Tx Key Contexts reserved */ + uint16_t reserved_tx_key_ctxs; + /* Actual number of Rx Key Contexts reserved */ + uint16_t reserved_rx_key_ctxs; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -14924,7 +15255,10 @@ struct hwrm_func_backing_store_qcaps_output { * this many QP context entries, even if RoCE will not be used. */ uint16_t qp_min_qp1_entries; - /* Maximum number of QP context entries that can be used for L2. */ + /* + * Maximum number of QP context entries that can be used for L2 and + * mid-path. + */ uint16_t qp_max_l2_entries; /* Number of bytes that must be allocated for each context entry. */ uint16_t qp_entry_size; @@ -15141,8 +15475,13 @@ struct hwrm_func_backing_store_qcaps_output { * function. */ uint32_t rkc_max_entries; + /* + * Number of mid-path TQM rings to be used for allocating + * backing stores. + */ + uint8_t mp_tqm_rings_count; /* Reserved for future. */ - uint8_t rsvd[7]; + uint8_t rsvd1[6]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18132,7 +18471,7 @@ struct hwrm_error_recovery_qcfg_output { /*************************** * hwrm_func_echo_response * - ****************************/ + ***************************/ /* hwrm_func_echo_response_input (size:192b/24B) */ @@ -18152,10 +18491,10 @@ struct hwrm_func_echo_response_input { uint16_t seq_id; /* * The target ID of the command: - * 0x0-0xFFF8 - The function ID - * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * 0xFFFD - Reserved for user-space HWRM interface - * 0xFFFF - HWRM + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ uint16_t target_id; /* @@ -18190,104 +18529,1400 @@ struct hwrm_func_echo_response_output { uint8_t valid; } __rte_packed; -/*********************** - * hwrm_func_vlan_qcfg * - ***********************/ - - -/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ -struct hwrm_func_vlan_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[6]; -} __rte_packed; - -/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ -struct hwrm_func_vlan_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint64_t unused_0; - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; - /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. - */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; - /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. - */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd2; - /* Future use. */ - uint32_t rsvd3; - uint8_t unused_3[3]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/********************** - * hwrm_func_vlan_cfg * - **********************/ +/************************** + * hwrm_func_ptp_pin_qcfg * + **************************/ -/* hwrm_func_vlan_cfg_input (size:384b/48B) */ -struct hwrm_func_vlan_cfg_input { +/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_pin_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * The number of TSIO pins that are configured on this board + * Up to 4 pins can be returned in the response. + */ + uint8_t num_pins; + /* Pin state */ + uint8_t state; + /* + * When this bit is '1', TSIO pin 0 is enabled. + * When this bit is '0', TSIO pin 0 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED \ + UINT32_C(0x1) + /* + * When this bit is '1', TSIO pin 1 is enabled. + * When this bit is '0', TSIO pin 1 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED \ + UINT32_C(0x2) + /* + * When this bit is '1', TSIO pin 2 is enabled. + * When this bit is '0', TSIO pin 2 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED \ + UINT32_C(0x4) + /* + * When this bit is '1', TSIO pin 3 is enabled. + * When this bit is '0', TSIO pin 3 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED \ + UINT32_C(0x8) + /* Type of function for Pin #0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT + /* Type of function for Pin #1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT + /* Type of function for Pin #2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT + /* Type of function for Pin #3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_func_ptp_pin_cfg * + *************************/ + + +/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_pin_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the pin0_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE \ + UINT32_C(0x1) + /* + * This bit must be '1' for the pin0_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the pin1_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the pin1_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE \ + UINT32_C(0x8) + /* + * This bit must be '1' for the pin2_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE \ + UINT32_C(0x10) + /* + * This bit must be '1' for the pin2_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE \ + UINT32_C(0x20) + /* + * This bit must be '1' for the pin3_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE \ + UINT32_C(0x40) + /* + * This bit must be '1' for the pin3_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE \ + UINT32_C(0x80) + /* Enable or disable functionality of Pin #0. */ + uint8_t pin0_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED + /* Configure function for TSIO pin#0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #1. */ + uint8_t pin1_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED + /* Configure function for TSIO pin#1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #2. */ + uint8_t pin2_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED + /* Configure function for TSIO pin#2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #3. */ + uint8_t pin3_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED + /* Configure function for TSIO pin#3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_func_ptp_cfg * + *********************/ + + +/* hwrm_func_ptp_cfg_input (size:320b/40B) */ +struct hwrm_func_ptp_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the ptp_pps_event field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT \ + UINT32_C(0x1) + /* + * This bit must be '1' for the ptp_freq_adj_dll_source field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the ptp_freq_adj_dll_phase field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the ptp_freq_adj_ext_period field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD \ + UINT32_C(0x8) + /* + * This bit must be '1' for the ptp_freq_adj_ext_up field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP \ + UINT32_C(0x10) + /* + * This bit must be '1' for the ptp_freq_adj_ext_phase field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE \ + UINT32_C(0x20) + /* This field is used to enable interrupt for a specific PPS event. */ + uint8_t ptp_pps_event; + /* + * When this bit is set to '1', interrupt is enabled for internal + * PPS event. Latches timestamp on PPS_OUT TSIO Pin. If user does + * not configure PPS_OUT on a TSIO pin, then firmware will allocate + * PPS_OUT to an unallocated pin. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL \ + UINT32_C(0x1) + /* + * When this bit is set to '1', interrupt is enabled for external + * PPS event. Latches timestamp on PPS_IN TSIO pin. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL \ + UINT32_C(0x2) + /* + * This field is used to set the source signal used to discipline + * PHC (PTP Hardware Clock) + */ + uint8_t ptp_freq_adj_dll_source; + /* No source is selected. Use servo to discipline PHC */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE \ + UINT32_C(0x0) + /* TSIO Pin #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 \ + UINT32_C(0x1) + /* TSIO Pin #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 \ + UINT32_C(0x2) + /* TSIO Pin #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 \ + UINT32_C(0x3) + /* TSIO Pin #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 \ + UINT32_C(0x4) + /* Port #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 \ + UINT32_C(0x5) + /* Port #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 \ + UINT32_C(0x6) + /* Port #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 \ + UINT32_C(0x7) + /* Port #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 \ + UINT32_C(0x8) + /* Invalid signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID \ + UINT32_C(0xff) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID + /* + * This field is used to provide phase adjustment for DLL + * used to discipline PHC (PTP Hardware clock) + */ + uint8_t ptp_freq_adj_dll_phase; + /* No Phase adjustment. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE \ + UINT32_C(0x0) + /* 4Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K \ + UINT32_C(0x1) + /* 8Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K \ + UINT32_C(0x2) + /* 10Mhz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M \ + UINT32_C(0x3) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M + uint8_t unused_0[3]; + /* + * Period in nanoseconds (ns) for external signal + * input. + */ + uint32_t ptp_freq_adj_ext_period; + /* + * Up time in nanoseconds (ns) of the duty cycle + * of the external signal. This value should be + * less than ptp_freq_adj_ext_period. + */ + uint32_t ptp_freq_adj_ext_up; + /* + * Phase value is provided. This field provides the + * least significant 32 bits of the phase input. The + * most significant 16 bits come from + * ptp_freq_adj_ext_phase_upper field. Setting this + * field requires setting ptp_freq_adj_ext_period + * field as well to identify the external signal + * pin. + */ + uint32_t ptp_freq_adj_ext_phase_lower; + /* + * Phase value is provided. The lower 16 bits of this field is used + * with the 32 bit value from ptp_freq_adj_ext_phase_lower + * to provide a 48 bit value input for Phase. + */ + uint32_t ptp_freq_adj_ext_phase_upper; +} __rte_packed; + +/* hwrm_func_ptp_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ts_query * + **************************/ + + +/* hwrm_func_ptp_ts_query_input (size:192b/24B) */ +struct hwrm_func_ptp_ts_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* If set, the response includes PPS event timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1) + /* If set, the response includes PTM timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_ptp_ts_query_output (size:320b/40B) */ +struct hwrm_func_ptp_ts_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Timestamp value of last PPS event latched. */ + uint64_t pps_event_ts; + /* PTM local timestamp value. */ + uint64_t ptm_res_local_ts; + /* PTM Master timestamp value. */ + uint64_t ptm_pmstr_ts; + /* PTM Master propagation delay */ + uint32_t ptm_mstr_prop_dly; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_func_ptp_ext_cfg * + *************************/ + + +/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_ext_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the phc_master_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the phc_sec_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the phc_sec_mode field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the failover_timer field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER \ + UINT32_C(0x8) + /* + * This field is used to configure the Master function. Only this + * function can modify or condition the PHC. Only driver calls from + * this function are allowed to adjust frequency of PHC or configure + * PPS functionality. + * If driver does not specify this FID, then firmware will auto select + * the first function that makes the call to modify PHC as the Master. + */ + uint16_t phc_master_fid; + /* + * This field is used to configure the secondary function. This + * function becomes the Master function in case of failover from + * Master function. + * If driver does not specify this FID, firmware will auto select + * the last non-master function to make a call to condition PHC as + * secondary. + */ + uint16_t phc_sec_fid; + /* + * This field is used to configure conditions under which a function + * can become a secondary function. + */ + uint8_t phc_sec_mode; + /* + * Immediately failover to the current secondary function. If there + * is no secondary function available, failover does not happen. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0) + /* + * All functions (PF and VF) can be used during auto selection + * of a secondary function. This is not used in case of admin + * configured secondary function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1) + /* + * Only PF's can be selected as a secondary function during auto + * selection. This is not used in case of admin configured secondary + * function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2) + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_LAST \ + HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY + uint8_t unused_0; + /* + * This field indicates the failover time is milliseconds. If the + * timeout expires, firmware will failover PTP configurability from + * current master to secondary fid. + * 0 - Failover timer is automatically selected based on the last + * adjFreq() call. If adjFreq() is not called for 3 * (last interval) + * the failover kicks in. For example, if last interval between + * adjFreq() calls was 2 seconds and the next adjFreq() is not made for + * at least 6 seconds, then secondary takes over as master to condition + * PHC. Firmware rounds up the failover timer to be a multiple of 250 + * ms. Firmware checks every 250 ms to see if timer expired. + * 0xFFFFFFFF - If driver specifies this value, then failover never + * happens. Admin or auto selected Master will always be used for + * conditioning PHC. + * X - If driver specifies any other value, this is admin indicated + * failover timeout. If no adjFreq() call is made within this timeout + * value, then failover happens. This value should be a multiple of + * 250 ms. Firmware checks every 250 ms to see if timer expired. + */ + uint32_t failover_timer; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_ext_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ext_qcfg * + **************************/ + + +/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_ext_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ +struct hwrm_func_ptp_ext_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Firmware returns the current PHC master function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_master_fid; + /* + * Firmware returns the current PHC secondary function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_sec_fid; + /* + * Firmware returns the last non-master/non-secondary function to + * make a call to condition PHC. + */ + uint16_t phc_active_fid0; + /* + * Firmware returns the second last non-master/non-secondary function + * to make a call to condition PHC. + */ + uint16_t phc_active_fid1; + /* + * Timestamp indicating the last time a failover happened. The master + * and secondary functions in the failover event is indicated in the + * next two fields. + */ + uint32_t last_failover_event; + /* + * Last failover happened from this function. This was the master + * function at the time of failover. + */ + uint16_t from_fid; + /* + * Last failover happened to this function. This was the secondary + * function at the time of failover. + */ + uint16_t to_fid; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_func_key_ctx_alloc * + ***************************/ + + +/* hwrm_func_key_ctx_alloc_input (size:320b/40B) */ +struct hwrm_func_key_ctx_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Function ID. */ + uint16_t fid; + /* Number of Key Contexts to be allocated. */ + uint16_t num_key_ctxs; + /* DMA buffer size in bytes. */ + uint32_t dma_bufr_size_bytes; + /* Key Context type. */ + uint8_t key_ctx_type; + /* Tx Key Context. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0) + /* Rx KTLS Context. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1) + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST \ + HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX + uint8_t unused_0[7]; + /* Host DMA address to send back KTLS context IDs. */ + uint64_t host_dma_addr; +} __rte_packed; + +/* hwrm_func_key_ctx_alloc_output (size:128b/16B) */ +struct hwrm_func_key_ctx_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Actual number of Key Contexts allocated. */ + uint16_t num_key_ctxs_allocated; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************** + * hwrm_func_backing_store_cfg_v2 * + **********************************/ + + +/* hwrm_func_backing_store_cfg_v2_input (size:320b/40B) */ +struct hwrm_func_backing_store_cfg_v2_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Type of backing store to be configured. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP \ + UINT32_C(0x0) + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ \ + UINT32_C(0x1) + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ \ + UINT32_C(0x2) + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* MRAV. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM \ + UINT32_C(0xf) + /* Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC \ + UINT32_C(0x13) + /* Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING + /* + * Instance of the backing store type. It is zero-based, + * which means "0" indicates the first instance. For backing + * stores with single instance only, leave this field to 0. + */ + uint16_t instance; + /* Control flags. */ + uint32_t flags; + /* + * When set, the firmware only uses on-chip resources and + * does not expect any backing store to be provided by the + * host driver. This mode provides minimal L2 functionality + * (e.g. limited L2 resources, no RoCE). + */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE \ + UINT32_C(0x1) + /* Page directory. */ + uint64_t page_dir; + /* Number of entries */ + uint32_t num_entries; + /* Number of bytes allocated for each entry */ + uint16_t entry_size; + /* Page size and pbl level. */ + uint8_t page_size_pbl_level; + /* PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2 + /* Page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G + uint8_t rsvd; +} __rte_packed; + +/* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */ +struct hwrm_func_backing_store_cfg_v2_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t rsvd0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been completely + * written. When writing a command completion or response to + * an internal processor, the order of writes has to be such + * that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************************** + * hwrm_func_backing_store_qcfg_v2 * + ***********************************/ + + +/* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */ +struct hwrm_func_backing_store_qcfg_v2_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Type of backing store to be configured. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QP \ + UINT32_C(0x0) + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ \ + UINT32_C(0x1) + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ \ + UINT32_C(0x2) + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* MRAV. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM \ + UINT32_C(0xf) + /* Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TKC \ + UINT32_C(0x13) + /* Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING + /* + * Instance of the backing store type. It is zero-based, + * which means "0" indicates the first instance. For backing + * stores with single instance only, leave this field to 0. + */ + uint16_t instance; + uint8_t rsvd[4]; +} __rte_packed; + +/* hwrm_func_backing_store_qcfg_v2_output (size:256b/32B) */ +struct hwrm_func_backing_store_qcfg_v2_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Type of backing store to be configured. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QP \ + UINT32_C(0x0) + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRQ \ + UINT32_C(0x1) + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CQ \ + UINT32_C(0x2) + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* MRAV. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM \ + UINT32_C(0xf) + /* Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TKC \ + UINT32_C(0x13) + /* Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING + /* + * Instance of the backing store type. It is zero-based, + * which means "0" indicates the first instance. For backing + * stores with single instance only, leave this field to 0. + */ + uint16_t instance; + /* Control flags. */ + uint32_t flags; + /* Page directory. */ + uint64_t page_dir; + /* Number of entries */ + uint32_t num_entries; + /* Page size and pbl level. */ + uint8_t page_size_pbl_level; + /* PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2 + /* Page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G + uint8_t rsvd[2]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been completely + * written. When writing a command completion or response to + * an internal processor, the order of writes has to be such + * that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_func_vlan_qcfg * + ***********************/ + + +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ +struct hwrm_func_vlan_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ +struct hwrm_func_vlan_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint64_t unused_0; + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd2; + /* Future use. */ + uint32_t rsvd3; + uint8_t unused_3[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_vlan_cfg * + **********************/ + + +/* hwrm_func_vlan_cfg_input (size:384b/48B) */ +struct hwrm_func_vlan_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -20690,20 +22325,44 @@ struct hwrm_port_phy_qcfg_output { /* 1G_baseCX */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \ UINT32_C(0x1b) - /* 100G_BASECR4 */ + /* 200G_BASECR4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \ UINT32_C(0x1c) - /* 100G_BASESR4 */ + /* 200G_BASESR4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \ UINT32_C(0x1d) - /* 100G_BASELR4 */ + /* 200G_BASELR4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \ UINT32_C(0x1e) - /* 100G_BASEER4 */ + /* 200G_BASEER4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \ UINT32_C(0x1f) + /* 50G_BASECR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASECR \ + UINT32_C(0x20) + /* 50G_BASESR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASESR \ + UINT32_C(0x21) + /* 50G_BASELR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASELR \ + UINT32_C(0x22) + /* 50G_BASEER */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASEER \ + UINT32_C(0x23) + /* 100G_BASECR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR2 \ + UINT32_C(0x24) + /* 100G_BASESR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR2 \ + UINT32_C(0x25) + /* 100G_BASELR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR2 \ + UINT32_C(0x26) + /* 100G_BASEER2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 \ + UINT32_C(0x27) #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 + HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 /* This value represents a media type. */ uint8_t media_type; /* Unknown */ @@ -21398,6 +23057,12 @@ struct hwrm_port_mac_cfg_input { */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \ UINT32_C(0x200) + /* + * This bit must be '1' for the ptp_adj_phase field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE \ + UINT32_C(0x400) /* Port ID of port that is to be configured. */ uint16_t port_id; /* @@ -21590,7 +23255,12 @@ struct hwrm_port_mac_cfg_input { * of sync timer updates (measured in parts per billion). */ int32_t ptp_freq_adj_ppb; - uint8_t unused_1[4]; + /* + * This unsigned field specifies the phase offset to be applied + * to the PHC (PTP Hardware Clock). This field is specified in + * nanoseconds. + */ + uint32_t ptp_adj_phase; } __rte_packed; /* hwrm_port_mac_cfg_output (size:128b/16B) */ @@ -21991,7 +23661,7 @@ struct hwrm_port_mac_ptp_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ +/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ struct hwrm_port_mac_ptp_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -22024,10 +23694,23 @@ struct hwrm_port_mac_ptp_qcfg_output { */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ UINT32_C(0x8) + /* + * When this bit is set to '1', two specific registers for current + * time (ts_ref_clock_reg_lower and ts_ref_clock_reg_upper) are + * directly accessible by the host. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK \ + UINT32_C(0x10) uint8_t unused_0[3]; - /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for RX. */ uint32_t rx_ts_reg_off_seq_id; @@ -22045,9 +23728,15 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t rx_ts_reg_off_fifo_adv; /* PTP timestamp granularity for RX. */ uint32_t rx_ts_reg_off_granularity; - /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for TX. */ uint32_t tx_ts_reg_off_seq_id; @@ -22055,6 +23744,10 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t tx_ts_reg_off_fifo; /* PTP timestamp granularity for TX. */ uint32_t tx_ts_reg_off_granularity; + /* Offset of register to get lower 32 bits of current time. */ + uint32_t ts_ref_clock_reg_lower; + /* Offset of register to get upper 32 bits of current time. */ + uint32_t ts_ref_clock_reg_upper; uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output @@ -22578,7 +24271,7 @@ struct tx_port_stats_ext { } __rte_packed; /* Port Rx Statistics extended Format */ -/* rx_port_stats_ext (size:3648b/456B) */ +/* rx_port_stats_ext (size:3776b/472B) */ struct rx_port_stats_ext { /* Number of times link state changed to down */ uint64_t link_down_events; @@ -22697,6 +24390,13 @@ struct rx_port_stats_ext { uint64_t rx_discard_packets_cos6; /* Total number of rx discard packets count on cos queue 7 */ uint64_t rx_discard_packets_cos7; + /* Total number of FEC blocks corrected by the FEC function in the PHY */ + uint64_t rx_fec_corrected_blocks; + /* + * Total number of FEC blocks determined to be uncorrectable by the + * FEC function in the PHY + */ + uint64_t rx_fec_uncorrectable_blocks; } __rte_packed; /* @@ -23718,8 +25418,10 @@ struct hwrm_port_phy_qcaps_output { #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3) /* 4-port device */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4) + /* 12-port device */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12 UINT32_C(0xc) #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \ - HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 + HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12 /* * This is a bit mask to indicate what speeds are supported * as forced speeds on this link. @@ -23901,7 +25603,28 @@ struct hwrm_port_phy_qcaps_output { UINT32_C(0x2) #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G \ UINT32_C(0x4) - uint8_t unused_0[3]; + /* More PHY capability flags */ + uint16_t flags2; + /* + * If set to 1, then this field indicates that + * 802.3x flow control is not supported. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED \ + UINT32_C(0x1) + /* + * If set to 1, then this field indicates that + * priority-based flow control is not supported. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED \ + UINT32_C(0x2) + /* + * Number of internal ports for this device. This field allows the FW + * to advertise how many internal ports are present. Manufacturing + * tools uses this to determine how many internal ports should have + * the PRBS test run on them. This field always return 0 unless NVM + * option "HPTN_MODE" is set to 1. + */ + uint8_t internal_port_cnt; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -25190,7 +26913,13 @@ struct hwrm_port_prbs_test_input { * use this entire buffer or less than the entire buffer, but never more. */ uint16_t data_len; - uint16_t unused_0; + uint16_t flags; + /* + * If set, the port_id field should be interpreted as an internal + * port. The internal port id range is returned in port_phy_qcaps + * response internal_port_cnt field. + */ + #define HWRM_PORT_PRBS_TEST_INPUT_FLAGS_INTERNAL UINT32_C(0x1) uint32_t unused_1; /* Port ID of port where PRBS test to be run. */ uint16_t port_id; @@ -25981,6 +27710,315 @@ struct hwrm_port_tx_fir_qcfg_output { uint8_t valid; } __rte_packed; +/*********************** + * hwrm_port_ep_tx_cfg * + ***********************/ + + +/* hwrm_port_ep_tx_cfg_input (size:256b/32B) */ +struct hwrm_port_ep_tx_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* When this bit is '1', the value in the ep0_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1) + /* When this bit is '1', the value in the ep0_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2) + /* When this bit is '1', the value in the ep1_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4) + /* When this bit is '1', the value in the ep1_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8) + /* When this bit is '1', the value in the ep2_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10) + /* When this bit is '1', the value in the ep2_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20) + /* When this bit is '1', the value in the ep3_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40) + /* When this bit is '1', the value in the ep3_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80) + /* A port index, from 0 to the number of front panel ports, minus 1. */ + uint8_t port_id; + uint8_t unused; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set of + * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of + * the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_output (size:128b/16B) */ +struct hwrm_port_ep_tx_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_cmd_err (size:64b/8B) */ +struct hwrm_port_ep_tx_cfg_cmd_err { + /* + * command specific error codes for the cmd_err field in + * hwrm_err_output + */ + uint8_t code; + /* Unknown error. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* The port ID is invalid */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID \ + UINT32_C(0x1) + /* One of the PCIe endpoints configured is not active. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE \ + UINT32_C(0x2) + /* A minimum bandwidth is out of range. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE \ + UINT32_C(0x3) + /* + * One endpoint's minimum bandwidth is more than its maximum + * bandwidth. + */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX \ + UINT32_C(0x4) + /* The sum of the minimum bandwidths on the port is more than 100%. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM \ + UINT32_C(0x5) + /* + * The NIC does not support enforcement of a minimum guaranteed + * bandwidth for an endpoint. + */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED \ + UINT32_C(0x6) + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_LAST \ + HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED + uint8_t unused_0[7]; +} __rte_packed; + +/************************ + * hwrm_port_ep_tx_qcfg * + ************************/ + + +/* hwrm_port_ep_tx_qcfg_input (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The port whose endpoint rate limits are queried. */ + uint8_t port_id; + uint8_t unused[7]; +} __rte_packed; + +/* hwrm_port_ep_tx_qcfg_output (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /*********************** * hwrm_queue_qportcfg * ***********************/ @@ -26097,6 +28135,13 @@ struct hwrm_queue_qportcfg_output { */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ UINT32_C(0x1) + /* + * If this flag is set to '1', then service_profile will carry + * either lossy/lossless type and the new service_profile_type + * field will be used to determine if the queue is for L2/ROCE/CNP. + */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE \ + UINT32_C(0x2) /* * Bitmask indicating which queues can be configured by the * hwrm_queue_pfcenable_cfg command. @@ -30198,17 +32243,409 @@ struct hwrm_queue_vlanpri2pri_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure VLAN priority to user priority mapping on this port. - */ - uint8_t port_id; - uint8_t unused_0[7]; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure VLAN priority to user priority mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ +struct hwrm_queue_vlanpri2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * User priority assigned to VLAN priority 0. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri0_user_pri_id; + /* + * User priority assigned to VLAN priority 1. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri1_user_pri_id; + /* + * User priority assigned to VLAN priority 2. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri2_user_pri_id; + /* + * User priority assigned to VLAN priority 3. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri3_user_pri_id; + /* + * User priority assigned to VLAN priority 4. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri4_user_pri_id; + /* + * User priority assigned to VLAN priority 5. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri5_user_pri_id; + /* + * User priority assigned to VLAN priority 6. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri6_user_pri_id; + /* + * User priority assigned to VLAN priority 7. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri7_user_pri_id; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_queue_vlanpri2pri_cfg * + ******************************/ + + +/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ +struct hwrm_queue_vlanpri2pri_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vlanpri0_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the vlanpri1_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the vlanpri2_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vlanpri3_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the vlanpri4_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the vlanpri5_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the vlanpri6_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the vlanpri7_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ + UINT32_C(0x80) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure VLAN priority to user priority mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[3]; + /* + * User priority assigned to VLAN priority 0. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri0_user_pri_id; + /* + * User priority assigned to VLAN priority 1. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri1_user_pri_id; + /* + * User priority assigned to VLAN priority 2. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri2_user_pri_id; + /* + * User priority assigned to VLAN priority 3. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri3_user_pri_id; + /* + * User priority assigned to VLAN priority 4. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri4_user_pri_id; + /* + * User priority assigned to VLAN priority 5. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri5_user_pri_id; + /* + * User priority assigned to VLAN priority 6. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri6_user_pri_id; + /* + * User priority assigned to VLAN priority 7. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri7_user_pri_id; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_vlanpri2pri_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_queue_global_cfg * + *************************/ + + +/* hwrm_queue_global_cfg_input (size:192b/24B) */ +struct hwrm_queue_global_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. + */ + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0) + /* + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT + uint8_t unused_0; + uint16_t enables; + /* This bit must be '1' when the mode field is configured. */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1) + /* + * This bit must be '1' when the maximum bandwidth for queue group 0 + * (g0_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2) + /* + * This bit must be '1' when the maximum bandwidth for queue group 1 + * (g1_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4) + /* + * This bit must be '1' when the maximum bandwidth for queue group 2 + * (g2_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8) + /* + * This bit must be '1' when the maximum bandwidth for queue group 3 + * (g3_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW \ + UINT32_C(0x10) + /* + * Specifies the maximum receive rate, as a percentage of total link + * bandwidth, of the receive traffic through queue group 0. A value + * of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. + */ + uint8_t g0_max_bw; + /* + * Specifies the maximum rate of the traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. + */ + uint8_t g1_max_bw; + /* + * Specifies the maximum rate of the traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. + */ + uint8_t g2_max_bw; + /* + * Specifies the maximum receive rate, in Mbps, of the receive traffic + * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0 + * indicates no rate limit. + */ + uint8_t g3_max_bw; +} __rte_packed; + +/* hwrm_queue_global_cfg_output (size:128b/16B) */ +struct hwrm_queue_global_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_queue_global_qcfg * + **************************/ + + +/* hwrm_queue_global_qcfg_input (size:128b/16B) */ +struct hwrm_queue_global_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; } __rte_packed; -/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ -struct hwrm_queue_vlanpri2pri_qcfg_output { +/* hwrm_queue_global_qcfg_output (size:320b/40B) */ +struct hwrm_queue_global_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30217,209 +32654,95 @@ struct hwrm_queue_vlanpri2pri_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Port or PCIe endpoint id to be mapped for buffer pool 0. */ + uint8_t buffer_pool_id0_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 1. */ + uint8_t buffer_pool_id1_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 2. */ + uint8_t buffer_pool_id2_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 3. */ + uint8_t buffer_pool_id3_map; + /* Size of buffer pool 0 (KBytes). */ + uint32_t buffer_pool_id0_size; + /* Size of buffer pool 1 (KBytes). */ + uint32_t buffer_pool_id1_size; + /* Size of buffer pool 2 (KBytes). */ + uint32_t buffer_pool_id2_size; + /* Size of buffer pool 3 (KBytes). */ + uint32_t buffer_pool_id3_size; + uint16_t flags; /* - * User priority assigned to VLAN priority 0. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri0_user_pri_id; - /* - * User priority assigned to VLAN priority 1. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri1_user_pri_id; - /* - * User priority assigned to VLAN priority 2. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri2_user_pri_id; - /* - * User priority assigned to VLAN priority 3. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri3_user_pri_id; - /* - * User priority assigned to VLAN priority 4. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri4_user_pri_id; - /* - * User priority assigned to VLAN priority 5. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri5_user_pri_id; - /* - * User priority assigned to VLAN priority 6. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri6_user_pri_id; - /* - * User priority assigned to VLAN priority 7. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri7_user_pri_id; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/****************************** - * hwrm_queue_vlanpri2pri_cfg * - ******************************/ - - -/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ -struct hwrm_queue_vlanpri2pri_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Enumeration denoting whether the rx buffer pool mapping is + * per port or per PCIe endpoint */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the vlanpri0_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING \ UINT32_C(0x1) /* - * This bit must be '1' for the vlanpri1_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ - UINT32_C(0x2) - /* - * This bit must be '1' for the vlanpri2_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ - UINT32_C(0x4) - /* - * This bit must be '1' for the vlanpri3_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ - UINT32_C(0x8) - /* - * This bit must be '1' for the vlanpri4_user_pri_id field to be - * configured. + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a port. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ - UINT32_C(0x10) - /* - * This bit must be '1' for the vlanpri5_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ - UINT32_C(0x20) - /* - * This bit must be '1' for the vlanpri6_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ - UINT32_C(0x40) - /* - * This bit must be '1' for the vlanpri7_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ - UINT32_C(0x80) - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure VLAN priority to user priority mapping on this port. - */ - uint8_t port_id; - uint8_t unused_0[3]; - /* - * User priority assigned to VLAN priority 0. This value can only - * be changed before traffic has started. - */ - uint8_t vlanpri0_user_pri_id; + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT \ + UINT32_C(0x0) /* - * User priority assigned to VLAN priority 1. This value can only - * be changed before traffic has started. + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a PCIe endpoint. */ - uint8_t vlanpri1_user_pri_id; + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT \ + UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT /* - * User priority assigned to VLAN priority 2. This value can only - * be changed before traffic has started. + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. */ - uint8_t vlanpri2_user_pri_id; + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0) /* - * User priority assigned to VLAN priority 3. This value can only - * be changed before traffic has started. + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues */ - uint8_t vlanpri3_user_pri_id; + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT + uint8_t unused_0; /* - * User priority assigned to VLAN priority 4. This value can only - * be changed before traffic has started. + * Reports the rate limit applied to traffic through receive CoS queue + * group 0. The rate limit is a percentage of total link bandwidth. A + * value of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. */ - uint8_t vlanpri4_user_pri_id; + uint8_t g0_max_bw; /* - * User priority assigned to VLAN priority 5. This value can only - * be changed before traffic has started. + * Reports the rate limit applied to traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. */ - uint8_t vlanpri5_user_pri_id; + uint8_t g1_max_bw; /* - * User priority assigned to VLAN priority 6. This value can only - * be changed before traffic has started. + * Reports the rate limit applied to traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. */ - uint8_t vlanpri6_user_pri_id; + uint8_t g2_max_bw; /* - * User priority assigned to VLAN priority 7. This value can only - * be changed before traffic has started. + * Reports the rate limit applied to traffic through receive CoS queue + * group 3 (for port 3 or PCIe endpoint 3). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. */ - uint8_t vlanpri7_user_pri_id; -} __rte_packed; - -/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_vlanpri2pri_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint8_t g3_max_bw; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -30567,6 +32890,12 @@ struct hwrm_vnic_update_input { */ #define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID \ UINT32_C(0x4) + /* + * This bit must be '1' for the rss_hash_function field to be + * configured. + */ + #define HWRM_VNIC_UPDATE_INPUT_ENABLES_RSS_HASH_FUNCTION_VALID \ + UINT32_C(0x8) /* * This will update the context variable with the same name if * the corresponding enable is set. @@ -30612,7 +32941,32 @@ struct hwrm_vnic_update_input { * the mru of the port the function is associated with. */ uint16_t mru; - uint8_t unused_1[4]; + /* + * Used to choose the RSS hash algorithm based on which HW + * can select the destination ring + */ + uint8_t rss_hash_function; + /* + * NIC calculates the RSS hash using the Toeplitz algorithm on L3/L4 + * headers and uses the hash to select the ring. + */ + #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_TOEPLITZ UINT32_C(0x0) + /* + * NIC calculates the RSS hash using the XOR algorithm on L3/L4 + * headers and uses the hash to select the ring. + */ + #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_XOR UINT32_C(0x1) + /* + * In this mode, RSS hash is calculated with Toeplitz and reported + * in the RX completion. However, the ring selection algorithm is + * based on the checksum. In this mode, only the innermost L3/L4 + * packet checksums are used. So this hash function mode will not + * be exposed/valid when the outer RSS mode is enabled. + */ + #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_CHECKSUM UINT32_C(0x2) + #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_LAST \ + HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_CHECKSUM + uint8_t unused_1[3]; } __rte_packed; /* hwrm_vnic_update_output (size:128b/16B) */ @@ -31324,6 +33678,48 @@ struct hwrm_vnic_qcaps_output { */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \ UINT32_C(0x1000) + /* + * When this bit is set '1', it indicates that firmware returns + * INVALID_PARAM error, if host drivers choose invalid hash type + * bit combinations in vnic_rss_cfg. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP \ + UINT32_C(0x2000) + /* + * When this bit is set '1', it indicates that firmware supports + * the hash_type include and exclude flags in hwrm_vnic_rss_cfg. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_TYPE_DELTA_CAP \ + UINT32_C(0x4000) + /* + * When this bit is '1', it indicates that HW is capable + * of calculating the RSS hash using Toeplitz algorithm. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_FUNCTION_TOEPLITZ_CAP \ + UINT32_C(0x8000) + /* + * When this bit is '1', it indicates that HW is capable + * of calculating the RSS hash using XOR algorithm. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_FUNCTION_XOR_CAP \ + UINT32_C(0x10000) + /* + * When this bit is '1', it indicates that HW is capable + * of using checksum algorithm. + * In this mode, RSS hash is calculated with Toeplitz and reported + * in the RX completion. However, the ring selection algorithm is + * based on the checksum. In this mode, only the innermost L3/L4 + * packet checksums are used. So this hash function mode will not + * be exposed/valid when the outer RSS mode is enabled. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_FUNCTION_CHKSM_CAP \ + UINT32_C(0x20000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPV6 flow labels. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPV6_FLOW_LABEL_CAP \ + UINT32_C(0x40000) /* * This field advertises the maximum concurrent TPA aggregations * supported by the VNIC on new devices that support TPA v2. @@ -31603,7 +33999,7 @@ struct hwrm_vnic_rss_cfg_input { #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) /* * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 + * over source and destination IPv6 addresses of IPv6 * packets. */ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) @@ -31674,7 +34070,62 @@ struct hwrm_vnic_rss_cfg_input { uint64_t hash_key_tbl_addr; /* Index to the rss indirection table. */ uint16_t rss_ctx_idx; - uint8_t unused_1[6]; + uint8_t flags; + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to add to the current + * hash. Zeroes designate the hash_type state bits that should remain + * unchanged, if possible. If this constraint on the existing state + * cannot be satisfied, then the implementation should preference + * adding other headers so as to honor the request to add the + * specified headers. It is an error to set this flag concurrently + * with hash_type_exclude. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to remove from the + * current hash. Zeroes designate the hash_type state bits that + * should remain unchanged, if possible. If this constraint on the + * existing state cannot be satisfied, then the implementation should + * preference removing other headers so as to honor the request to + * remove the specified headers. It is an error to set this flag + * concurrently with hash_type_include. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE \ + UINT32_C(0x2) + /* + * Used to choose the RSS hash algorithm based on which HW + * can select the destination ring + */ + uint8_t rss_hash_function; + /* + * NIC calculates the RSS hash using the Toeplitz algorithm on L3/L4 + * headers and uses the hash to select the ring. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_TOEPLITZ \ + UINT32_C(0x0) + /* + * NIC calculates the RSS hash using the XOR algorithm on L3/L4 + * headers and uses the hash to select the ring. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_XOR \ + UINT32_C(0x1) + /* + * In this mode, RSS hash is calculated with Toeplitz and reported + * in the RX completion. However, the ring selection algorithm is + * based on the checksum. In this mode, only the innermost L3/L4 + * packet checksums are used. So this hash function mode will not + * be exposed/valid when the outer RSS mode is enabled. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_CHECKSUM \ + UINT32_C(0x2) + #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_LAST \ + HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_CHECKSUM + uint8_t unused_1[4]; } __rte_packed; /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ @@ -31790,7 +34241,7 @@ struct hwrm_vnic_rss_qcfg_output { #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) /* * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 + * over source and destination IPv6 addresses of IPv6 * packets. */ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) @@ -31851,7 +34302,35 @@ struct hwrm_vnic_rss_qcfg_output { */ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ UINT32_C(0x10) - uint8_t unused_1[6]; + /* + * Used to choose the RSS hash algorithm based on which HW + * can select the destination ring + */ + uint8_t rss_hash_function; + /* + * NIC calculates the RSS hash using the Toeplitz algorithm on L3/L4 + * headers and uses the hash to select the ring. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_TOEPLITZ \ + UINT32_C(0x0) + /* + * NIC calculates the RSS hash using the XOR algorithm on L3/L4 + * headers and uses the hash to select the ring. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_XOR \ + UINT32_C(0x1) + /* + * In this mode, RSS hash is calculated with Toeplitz and reported + * in the RX completion. However, the ring selection algorithm is + * based on the checksum. In this mode, only the innermost L3/L4 + * packet checksums are used. So this hash function mode will not + * be exposed/valid when the outer RSS mode is enabled. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_CHECKSUM \ + UINT32_C(0x2) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_LAST \ + HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_CHECKSUM + uint8_t unused_1[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -32426,7 +34905,47 @@ struct hwrm_ring_alloc_input { #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5) #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \ HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ - uint8_t unused_0; + /* + * This field controls the number of packets transmitted before a TX + * completion is generated. Non-zero values for the field are only + * valid if HWRM_FUNC_QCAPS indicates that the TX coalesced completion + * records capability is supported. + */ + uint8_t cmpl_coal_cnt; + /* Generates a legacy TX completion on every packet. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF UINT32_C(0x0) + /* Generates a TX coalesced completion for up to 4 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_4 UINT32_C(0x1) + /* Generates a TX coalesced completion for up to 8 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_8 UINT32_C(0x2) + /* Generates a TX coalesced completion for up to 12 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_12 UINT32_C(0x3) + /* Generates a TX coalesced completion for up to 16 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_16 UINT32_C(0x4) + /* Generates a TX coalesced completion for up to 24 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_24 UINT32_C(0x5) + /* Generates a TX coalesced completion for up to 32 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_32 UINT32_C(0x6) + /* Generates a TX coalesced completion for up to 48 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_48 UINT32_C(0x7) + /* Generates a TX coalesced completion for up to 64 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_64 UINT32_C(0x8) + /* Generates a TX coalesced completion for up to 96 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_96 UINT32_C(0x9) + /* Generates a TX coalesced completion for up to 128 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_128 UINT32_C(0xa) + /* Generates a TX coalesced completion for up to 192 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_192 UINT32_C(0xb) + /* Generates a TX coalesced completion for up to 256 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_256 UINT32_C(0xc) + /* Generates a TX coalesced completion for up to 320 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_320 UINT32_C(0xd) + /* Generates a TX coalesced completion for up to 384 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_384 UINT32_C(0xe) + /* Generates a TX coalesced completion up to the last packet. (Maximum coalescing). */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX UINT32_C(0xf) + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_LAST \ + HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX /* Ring allocation flags. */ uint16_t flags; /* @@ -36754,6 +39273,14 @@ struct hwrm_cfa_ntuple_filter_alloc_input { */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \ UINT32_C(0x20) + /* + * Setting of this flag indicates that when the ntuple filter is + * created, the L2 context should not be used in the filter. This + * allows packet from different L2 contexts to match and be directed + * to the same destination. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_NO_L2_CONTEXT \ + UINT32_C(0x40) uint32_t enables; /* * This bit must be '1' for the l2_filter_id field to be @@ -37276,6 +39803,14 @@ struct hwrm_cfa_ntuple_filter_cfg_input { */ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \ UINT32_C(0x2) + /* + * Setting of this flag indicates that when the ntuple filter is + * created, the L2 context should not be used in the filter. This + * allows packet from different L2 contexts to match and be directed + * to the same destination. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_NO_L2_CONTEXT \ + UINT32_C(0x4) /* This value is an opaque id into CFA data structures. */ uint64_t ntuple_filter_id; /* @@ -42974,6 +45509,12 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_LAG_SUPPORTED \ UINT32_C(0x20000) + /* + * If set to 1, firmware is capable installing ntuple rules without + * additional classification on the L2 Context. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED \ + UINT32_C(0x40000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -43062,6 +45603,161 @@ struct hwrm_cfa_tflib_output { uint8_t valid; } __rte_packed; +/********************************** + * hwrm_cfa_lag_group_member_rgtr * + **********************************/ + + +/* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t mode; + /* + * Transmit only on the active port. Automatically failover + * to backup port. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP \ + UINT32_C(0x1) + /* + * Transmit based on packet header ntuple hash. Packet with only + * layer 2 headers will hash using the destination MAC, source MAC + * and Ethertype fields. Packets with layer 3 (IP) headers will + * hash using the destination MAC, source MAC, IP protocol/next + * header, source IP address and destination IP address. Packets + * with layer 4 (TCP/UDP) headers will hash using the destination + * MAC, source MAC, IP protocol/next header, source IP address, + * destination IP address, source port and destination port fields. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR \ + UINT32_C(0x2) + /* Transmit packets on all specified ports. */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST \ + UINT32_C(0x3) + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST \ + HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST + /* + * Supports up to 5 ports. bit0 = port 0, bit1 = port 1, + * bit2 = port 2, bit3 = port 4, bit4 = loopback port + */ + uint8_t port_bitmap; + /* Specify the active port when active-backup mode is specified */ + uint8_t active_port; + uint8_t unused_0[5]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************************ + * hwrm_cfa_lag_group_member_unrgtr * + ************************************/ + + +/* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /*********** * hwrm_tf * ***********/ @@ -43175,7 +45871,7 @@ struct hwrm_tf_version_get_input { uint64_t resp_addr; } __rte_packed; -/* hwrm_tf_version_get_output (size:128b/16B) */ +/* hwrm_tf_version_get_output (size:256b/32B) */ struct hwrm_tf_version_get_output { /* The specific error status for the command. */ uint16_t error_code; @@ -43192,7 +45888,14 @@ struct hwrm_tf_version_get_output { /* Version Update number. */ uint8_t update; /* unused. */ - uint8_t unused0[4]; + uint8_t unused0[5]; + /* + * This field is used to indicate device's capabilities and + * configurations. + */ + uint64_t dev_caps_cfg; + /* unused. */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -43263,8 +45966,13 @@ struct hwrm_tf_session_open_output { * the newly created session. */ uint32_t fw_session_client_id; + /* This field is used to return the status of fw session to host. */ uint32_t flags; - /* Indicates if the shared session has been created. */ + /* + * Indicates if the shared session has been created. Shared seesion + * should be the first session created ever. Its fw_rm_client_id + * should be 1. The AFM session's fw_rm_client_id is 0. + */ #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \ UINT32_C(0x1) /* @@ -43745,7 +46453,7 @@ struct hwrm_tf_session_resc_qcaps_input { #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX @@ -43802,8 +46510,13 @@ struct hwrm_tf_session_resc_qcaps_output { * qcaps_size. */ uint16_t size; + /* + * SRAM profile number that sets the partition of SRAM memory + * between TF and AFM within the 4 internal memory banks (Thor). + */ + uint8_t sram_profile; /* unused. */ - uint16_t unused0; + uint8_t unused0; /* unused. */ uint8_t unused1[7]; /* @@ -43860,7 +46573,7 @@ struct hwrm_tf_session_resc_alloc_input { #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX @@ -43959,7 +46672,7 @@ struct hwrm_tf_session_resc_free_input { #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX @@ -44043,7 +46756,7 @@ struct hwrm_tf_session_resc_flush_input { #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX @@ -44124,134 +46837,143 @@ struct hwrm_tf_session_resc_info_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX + /* + * Defines the array size of the provided req_addr and + * resv_addr array buffers. Should be set to the number of + * request entries. + */ + uint16_t req_size; + /* + * This is the DMA address for the request input data array + * buffer. Array is of tf_rm_resc_req_entry type. Size of the + * array buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t req_addr; + /* + * This is the DMA address for the resc output data array + * buffer. Array is of tf_rm_resc_entry type. Size of the array + * buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t resc_addr; +} __rte_packed; + +/* hwrm_tf_session_resc_info_output (size:128b/16B) */ +struct hwrm_tf_session_resc_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Size of the returned tf_rm_resc_entry data array. The value + * cannot exceed the req_size defined by the input msg. The data + * array is returned using the resv_addr specified DMA + * address also provided by the input msg. + */ + uint16_t size; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/* TruFlow RM capability of a resource. */ +/* tf_rm_resc_req_entry (size:64b/8B) */ +struct tf_rm_resc_req_entry { + /* Type of the resource, defined globally in HCAPI RM. */ + uint32_t type; + /* Minimum value. */ + uint16_t min; + /* Maximum value. */ + uint16_t max; +} __rte_packed; + +/* TruFlow RM reservation information. */ +/* tf_rm_resc_entry (size:64b/8B) */ +struct tf_rm_resc_entry { + /* Type of the resource, defined globally in HCAPI RM. */ + uint32_t type; + /* Start offset. */ + uint16_t start; + /* Number of resources. */ + uint16_t stride; +} __rte_packed; + +/************************ + * hwrm_tf_tbl_type_get * + ************************/ + + +/* hwrm_tf_tbl_type_get_input (size:256b/32B) */ +struct hwrm_tf_tbl_type_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX - /* - * Defines the array size of the provided req_addr and - * resv_addr array buffers. Should be set to the number of - * request entries. - */ - uint16_t req_size; - /* - * This is the DMA address for the request input data array - * buffer. Array is of tf_rm_resc_req_entry type. Size of the - * array buffer is provided by the 'req_size' field in this - * message. - */ - uint64_t req_addr; - /* - * This is the DMA address for the resc output data array - * buffer. Array is of tf_rm_resc_entry type. Size of the array - * buffer is provided by the 'req_size' field in this - * message. - */ - uint64_t resc_addr; -} __rte_packed; - -/* hwrm_tf_session_resc_info_output (size:128b/16B) */ -struct hwrm_tf_session_resc_info_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* - * Size of the returned tf_rm_resc_entry data array. The value - * cannot exceed the req_size defined by the input msg. The data - * array is returned using the resv_addr specified DMA - * address also provided by the input msg. - */ - uint16_t size; - /* unused. */ - uint8_t unused0[5]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. - */ - uint8_t valid; -} __rte_packed; - -/* TruFlow RM capability of a resource. */ -/* tf_rm_resc_req_entry (size:64b/8B) */ -struct tf_rm_resc_req_entry { - /* Type of the resource, defined globally in HCAPI RM. */ - uint32_t type; - /* Minimum value. */ - uint16_t min; - /* Maximum value. */ - uint16_t max; -} __rte_packed; - -/* TruFlow RM reservation information. */ -/* tf_rm_resc_entry (size:64b/8B) */ -struct tf_rm_resc_entry { - /* Type of the resource, defined globally in HCAPI RM. */ - uint32_t type; - /* Start offset. */ - uint16_t start; - /* Number of resources. */ - uint16_t stride; -} __rte_packed; - -/************************ - * hwrm_tf_tbl_type_get * - ************************/ - - -/* hwrm_tf_tbl_type_get_input (size:256b/32B) */ -struct hwrm_tf_tbl_type_get_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Control flags. */ - uint16_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entry on read. + */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* @@ -44337,7 +47059,7 @@ struct hwrm_tf_tbl_type_set_input { #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX @@ -44819,7 +47541,7 @@ struct hwrm_tf_ext_em_qcaps_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \ @@ -44997,7 +47719,7 @@ struct hwrm_tf_ext_em_op_input { #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX @@ -45104,7 +47826,7 @@ struct hwrm_tf_ext_em_cfg_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \ @@ -45309,7 +48031,7 @@ struct hwrm_tf_ext_em_qcfg_input { #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX @@ -45335,7 +48057,7 @@ struct hwrm_tf_ext_em_qcfg_output { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ @@ -45475,7 +48197,7 @@ struct hwrm_tf_em_insert_input { #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX @@ -45556,7 +48278,7 @@ struct hwrm_tf_em_hash_insert_input { #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX @@ -45637,13 +48359,13 @@ struct hwrm_tf_em_delete_input { #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX /* Unused0 */ uint16_t unused0; - /* EM internal flow hanndle. */ + /* EM internal flow handle. */ uint64_t flow_handle; /* EM Key value */ uint64_t em_key[8]; @@ -45785,7 +48507,7 @@ struct hwrm_tf_tcam_set_input { #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX @@ -45887,7 +48609,7 @@ struct hwrm_tf_tcam_get_input { #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX @@ -45983,7 +48705,7 @@ struct hwrm_tf_tcam_move_input { #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX @@ -46066,7 +48788,7 @@ struct hwrm_tf_tcam_free_input { #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX @@ -46149,7 +48871,7 @@ struct hwrm_tf_global_cfg_set_input { #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX @@ -46233,7 +48955,7 @@ struct hwrm_tf_global_cfg_get_input { #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX @@ -46308,7 +49030,7 @@ struct hwrm_tf_if_tbl_get_input { #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX @@ -46397,7 +49119,7 @@ struct hwrm_tf_if_tbl_set_input { #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX @@ -46481,13 +49203,22 @@ struct hwrm_tf_tbl_type_bulk_get_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entries on read. + */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* @@ -48261,7 +50992,7 @@ struct hwrm_nvm_get_dir_info_output { ******************/ -/* hwrm_nvm_write_input (size:384b/48B) */ +/* hwrm_nvm_write_input (size:448b/56B) */ struct hwrm_nvm_write_input { /* The HWRM command request type. */ uint16_t req_type; @@ -48306,13 +51037,19 @@ struct hwrm_nvm_write_input { * The 0-based instance of the combined Directory Entry Type and Extension. */ uint16_t dir_ordinal; - /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */ + /* + * The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file + * bnxnvm_defs.h). + */ uint16_t dir_ext; - /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ + /* + * Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file + * bnxnvm_defs.h). + */ uint16_t dir_attr; /* - * Length of data to write, in bytes.May be - * less than or equal to the allocated size for the directory entry. + * Length of data to write, in bytes. May be less than or equal to the + * allocated size for the directory entry. * The data length stored in the directory entry will be updated to * reflect this value once the write is complete. */ @@ -48326,18 +51063,47 @@ struct hwrm_nvm_write_input { */ #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ UINT32_C(0x1) + /* + * This flag indicates the sender wants to modify a continuous + * NVRAM area using a batch of this HWRM requests. The + * offset of a request must be continuous to the end of previous + * request's. Firmware does not update the directory entry until + * receiving the last request, which is indicated by the batch_last + * flag. This flag is set usually when a sender does not have a + * block of memory that is big enough to hold the entire NVRAM + * data for send at one time. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE \ + UINT32_C(0x2) + /* + * This flag can be used only when the batch_mode flag is set. It + * indicates this request is the last of batch requests. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST \ + UINT32_C(0x4) /* * The requested length of the allocated NVM for the item, in bytes. - * This value may be greater than or equal to the specified data length (dir_data_length). + * This value may be greater than or equal to the specified data + * length (dir_data_length). * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, which may - * be greater than the requested item length. - * The purpose for allocating more than the required number of bytes for - * an item's data is to pre-allocate extra storage (padding) to accommodate - * the potential future growth of an item (e.g. upgraded firmware with - * a size increase, log growth, expanded configuration data). + * The response will contain the actual allocated item length, + * which may be greater than the requested item length. + * The purpose for allocating more than the required number of bytes + * for an item's data is to pre-allocate extra storage (padding) to + * accommodate the potential future growth of an item (e.g. upgraded + * firmware with a size increase, log growth, expanded configuration data). */ uint32_t dir_item_length; + /* + * 32-bit offset of data blob from where data is being written. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t offset; + /* + * Length of data to be written.Should be non-zero. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t len; uint32_t unused_0; } __rte_packed; @@ -48353,7 +51119,8 @@ struct hwrm_nvm_write_output { uint16_t resp_len; /* * Length of the allocated NVM for the item, in bytes. The value may be - * greater than or equal to the specified data length or the requested item length. + * greater than or equal to the specified data length or the requested + * item length. * The actual item length used when creating a new directory entry will * be a multiple of an NVM block size. */ @@ -48564,7 +51331,8 @@ struct hwrm_nvm_find_dir_entry_output { uint32_t dir_data_length; /* * Firmware version. - * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format. + * Only valid if the directory entry is for embedded firmware stored + * in APE_BIN Format. */ uint32_t fw_ver; /* Directory ordinal. */ @@ -48849,7 +51617,10 @@ struct hwrm_nvm_mod_dir_entry_input { * extension flag definitions). */ uint16_t dir_ext; - /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */ + /* + * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute + * flag definitions). + */ uint16_t dir_attr; /* * If valid, then this field updates the checksum @@ -48924,8 +51695,10 @@ struct hwrm_nvm_verify_update_input { /* * The Directory Entry Extension flags. * The "UPDATE" extension flag must be set in this value. - * A corresponding directory entry with the same type and ordinal values but *without* - * the "UPDATE" extension flag must also exist. The other flags of the extension must + * A corresponding directory entry with the same type and ordinal + * values but *without* + * the "UPDATE" extension flag must also exist. The other flags of + * the extension must * be identical between the active and update entries. */ uint16_t dir_ext; @@ -49012,20 +51785,25 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \ HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL uint16_t flags; - /* If set to 1, then securely erase all unused locations in persistent storage. */ + /* + * If set to 1, then securely erase all unused locations in + * persistent storage. + */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \ UINT32_C(0x1) /* - * If set to 1, then unspecified images, images not in the package file, - * will be safely deleted. - * When combined with erase_unused_space then unspecified images will be - * securely erased. + * If set to 1, then unspecified images, images not in the package + * file, will be safely deleted. + * When combined with erase_unused_space then unspecified images will + * be securely erased. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ UINT32_C(0x2) /* - * If set to 1, FW will defragment the NVM if defragmentation is required for the update. - * Allow additional time for this command to complete if this bit is set to 1. + * If set to 1, FW will defragment the NVM if defragmentation is + * required for the update. + * Allow additional time for this command to complete if this bit is + * set to 1. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \ UINT32_C(0x4) @@ -49055,12 +51833,94 @@ struct hwrm_nvm_install_update_output { * A value of 0 indicates that no items were successfully installed. */ uint64_t installed_items; - /* result is 8 b */ + /* result is 8 b corresponding to BCMRETVAL error codes */ uint8_t result; /* There was no problem with the package installation. */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0) + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS \ + UINT32_C(0x0) + /* Generic failure */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_FAILURE \ + UINT32_C(0xff) + /* Allocation error malloc failure */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_MALLOC_FAILURE \ + UINT32_C(0xfd) + /* NVM install error due to invalid index */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_INDEX_PARAMETER \ + UINT32_C(0xfb) + /* NVM install error due to invalid type */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TYPE_PARAMETER \ + UINT32_C(0xf3) + /* Invalid package due to invalid prerequisite */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PREREQUISITE \ + UINT32_C(0xf2) + /* Invalid package due to invalid file header */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_FILE_HEADER \ + UINT32_C(0xec) + /* Invalid package due to invalid format */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_SIGNATURE \ + UINT32_C(0xeb) + /* Invalid package due to invalid property stream */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_STREAM \ + UINT32_C(0xea) + /* Invalid package due to invalid property length */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_LENGTH \ + UINT32_C(0xe9) + /* Invalid package due to invalid manifest */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_MANIFEST \ + UINT32_C(0xe8) + /* Invalid package due to invalid trailer */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TRAILER \ + UINT32_C(0xe7) + /* Invalid package due to invalid checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_CHECKSUM \ + UINT32_C(0xe6) + /* Invalid package due to invalid item checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_ITEM_CHECKSUM \ + UINT32_C(0xe5) + /* Invalid package due to invalid length */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DATA_LENGTH \ + UINT32_C(0xe4) + /* Invalid package due to invalid directive */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DIRECTIVE \ + UINT32_C(0xe1) + /* Invalid device due to unsupported chip revision */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_CHIP_REV \ + UINT32_C(0xce) + /* Invalid device due to unsupported device ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_DEVICE_ID \ + UINT32_C(0xcd) + /* Invalid device due to unsupported subsystem vendor */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_VENDOR \ + UINT32_C(0xcc) + /* Invalid device due to unsupported subsystem ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_ID \ + UINT32_C(0xcb) + /* Invalid device due to unsupported product ID or customer ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_PLATFORM \ + UINT32_C(0xc5) + /* Invalid package due to duplicate item */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_DUPLICATE_ITEM \ + UINT32_C(0xc4) + /* Invalid package due to zero length item */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ZERO_LENGTH_ITEM \ + UINT32_C(0xc3) + /* NVM integrity error checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_CHECKSUM_ERROR \ + UINT32_C(0xb9) + /* NVM integrity error */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_DATA_ERROR \ + UINT32_C(0xb8) + /* Authentication error */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_AUTHENTICATION_ERROR \ + UINT32_C(0xb7) + /* NVM install error item not found */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_NOT_FOUND \ + UINT32_C(0xb0) + /* NVM install error item locked */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED \ + UINT32_C(0xa7) #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \ - HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS + HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED /* problem_item is 8 b */ uint8_t problem_item; /* There was no problem with any packaged items. */ @@ -49116,13 +51976,19 @@ struct hwrm_nvm_install_update_cmd_err { */ uint8_t code; /* Unknown error */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) /* Unable to complete operation due to fragmentation */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR \ + UINT32_C(0x1) /* nvm is completely full. */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE \ + UINT32_C(0x2) + /* Firmware update failed due to Anti-rollback. */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \ + UINT32_C(0x3) #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \ - HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE + HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK uint8_t unused_0[7]; } __rte_packed; @@ -49290,12 +52156,13 @@ struct hwrm_nvm_get_variable_output { /* size of data of the actual variable retrieved in bits */ uint16_t data_len; /* - * option_num is the option number for the data retrieved. It is possible in the - * future that the option number returned would be different than requested. This - * condition could occur if an option is deprecated and a new option id is defined - * with similar characteristics, but has a slightly different definition. This - * also makes it convenient for the caller to identify the variable result with - * the option id from the response. + * option_num is the option number for the data retrieved. It is + * possible in the future that the option number returned would be + * different than requested. This condition could occur if an option is + * deprecated and a new option id is defined with similar + * characteristics, but has a slightly different definition. This + * also makes it convenient for the caller to identify the variable + * result with the option id from the response. */ uint16_t option_num; /* reserved. */ @@ -49405,8 +52272,8 @@ struct hwrm_nvm_set_variable_input { uint16_t index_3; uint8_t flags; /* - * When this bit is 1, flush internal cache after this write operation - * (see hwrm_nvm_flush command.) + * When this bit is 1, flush internal cache after this write + * operation (see hwrm_nvm_flush command.) */ #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \ UINT32_C(0x1) @@ -49558,9 +52425,15 @@ struct hwrm_nvm_validate_option_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; uint8_t result; - /* indicates that the value provided for the option is not matching with the saved data. */ + /* + * indicates that the value provided for the option is not matching + * with the saved data. + */ #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0) - /* indicates that the value provided for the option is matching the saved data. */ + /* + * indicates that the value provided for the option is matching the + * saved data. + */ #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1) #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \ HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH @@ -49589,6 +52462,84 @@ struct hwrm_nvm_validate_option_cmd_err { uint8_t unused_0[7]; } __rte_packed; +/******************* + * hwrm_nvm_defrag * + *******************/ + + +/* hwrm_nvm_defrag_input (size:192b/24B) */ +struct hwrm_nvm_defrag_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* This bit must be '1' to perform NVM defragmentation. */ + #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_nvm_defrag_output (size:128b/16B) */ +struct hwrm_nvm_defrag_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_nvm_defrag_cmd_err (size:64b/8B) */ +struct hwrm_nvm_defrag_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* NVM defragmentation could not be performed */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1) + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST \ + HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL + uint8_t unused_0[7]; +} __rte_packed; + /**************** * hwrm_oem_cmd * ****************/ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index bd57229968..dbc8a3c5bb 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1010,13 +1010,15 @@ ulp_context_initialized(struct bnxt_ulp_session_state *session, bool *init) * pointer, otherwise allocate a new session. */ static struct bnxt_ulp_session_state * -ulp_get_session(struct rte_pci_addr *pci_addr) +ulp_get_session(struct bnxt *bp, struct rte_pci_addr *pci_addr) { struct bnxt_ulp_session_state *session; + /* if multi root capability is enabled, then ignore the pci bus id */ STAILQ_FOREACH(session, &bnxt_ulp_session_list, next) { if (session->pci_info.domain == pci_addr->domain && - session->pci_info.bus == pci_addr->bus) { + (BNXT_MULTIROOT_EN(bp) || + session->pci_info.bus == pci_addr->bus)) { return session; } } @@ -1044,7 +1046,7 @@ ulp_session_init(struct bnxt *bp, pthread_mutex_lock(&bnxt_ulp_global_mutex); - session = ulp_get_session(pci_addr); + session = ulp_get_session(bp, pci_addr); if (!session) { /* Not Found the session Allocate a new one */ session = rte_zmalloc("bnxt_ulp_session", @@ -1547,7 +1549,7 @@ bnxt_ulp_port_deinit(struct bnxt *bp) pci_dev = RTE_DEV_TO_PCI(bp->eth_dev->device); pci_addr = &pci_dev->addr; pthread_mutex_lock(&bnxt_ulp_global_mutex); - session = ulp_get_session(pci_addr); + session = ulp_get_session(bp, pci_addr); pthread_mutex_unlock(&bnxt_ulp_global_mutex); /* session not found then just exit */ -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH v4 02/20] net/bnxt: add support for multi root capability 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 02/20] net/bnxt: add support for multi root capability Ajit Khaparde @ 2021-11-03 13:24 ` Ferruh Yigit 0 siblings, 0 replies; 118+ messages in thread From: Ferruh Yigit @ 2021-11-03 13:24 UTC (permalink / raw) To: Ajit Khaparde, dev Cc: Kishore Padmanabha, Venkat Duvvuru, Mike Baucom, Randy Schacher On 11/3/2021 12:52 AM, Ajit Khaparde wrote: > From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> > > Update driver to read the multi root capability and ignore > pci address check while creating ulp session when multi root > capability is enabled in the hardware. DPDK HSI version updated > from 1.10.1.70 to 1.10.2.68. According code it is updated from '1.10.2.44', not sure if it matters. > > Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> > Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> > Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> > Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> > Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> <...> > @@ -43263,8 +45966,13 @@ struct hwrm_tf_session_open_output { > * the newly created session. > */ > uint32_t fw_session_client_id; > + /* This field is used to return the status of fw session to host. */ > uint32_t flags; > - /* Indicates if the shared session has been created. */ > + /* > + * Indicates if the shared session has been created. Shared seesion typo, s/seesion/session/ ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 03/20] net/bnxt: fix out of bounds issue in hash list 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 01/20] net/bnxt: add NAT support for dest IP and port combination Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 02/20] net/bnxt: add support for multi root capability Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 04/20] net/bnxt: add clear on read support Ajit Khaparde ` (18 subsequent siblings) 21 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev Cc: Kishore Padmanabha, stable, Venkat Duvvuru, Mike Baucom, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 3050 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> The number of hash bucket list calculation is fixed. Added check to avoid the out of bounds condition. Fixes: 0001cc58d362 ("net/bnxt: support generic hash table") Cc: stable@dpdk.org Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c index 3c6e7fe924..84c83de35c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c @@ -16,20 +16,21 @@ int32_t ulp_bit_alloc_list_alloc(struct bit_alloc_list *blist, { uint64_t bentry; uint32_t idx = 0, jdx = 0; + uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES; /* Iterate all numbers that have all 1's */ do { bentry = blist->bdata[idx++]; - } while (bentry == -1UL && idx < blist->bsize); + } while (bentry == -1UL && idx <= bsize_64); - if (idx < blist->bsize) { + if (idx <= bsize_64) { if (bentry) jdx = __builtin_clzl(~bentry); *index = ((idx - 1) * ULP_INDEX_BITMAP_SIZE) + jdx; ULP_INDEX_BITMAP_SET(blist->bdata[(idx - 1)], jdx); return 0; } - jdx = (uint32_t)(blist->bsize * ULP_INDEX_BITMAP_SIZE); + jdx = (uint32_t)(bsize_64 * ULP_INDEX_BITMAP_SIZE); BNXT_TF_DBG(ERR, "bit allocator is full reached max:%x\n", jdx); return -1; } @@ -39,9 +40,10 @@ int32_t ulp_bit_alloc_list_dealloc(struct bit_alloc_list *blist, uint32_t index) { uint32_t idx = 0, jdx; + uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES; idx = index / ULP_INDEX_BITMAP_SIZE; - if (idx >= blist->bsize) { + if (idx >= bsize_64) { BNXT_TF_DBG(ERR, "invalid bit index %x:%x\n", idx, blist->bsize); return -EINVAL; @@ -127,7 +129,8 @@ ulp_gen_hash_tbl_list_init(struct ulp_hash_create_params *cparams, hash_tbl->hash_mask = size - 1; /* allocate the memory for the bit allocator */ - size = (cparams->num_key_entries / sizeof(uint64_t)) + 1; + size = (cparams->num_key_entries / sizeof(uint64_t)); + size = ULP_BYTE_ROUND_OFF_8(size); hash_tbl->bit_list.bsize = size; hash_tbl->bit_list.bdata = rte_zmalloc("Generic hash bit alloc", size, ULP_BUFFER_ALIGN_64_BYTE); @@ -311,7 +314,12 @@ ulp_gen_hash_tbl_list_add(struct ulp_gen_hash_tbl *hash_tbl, BNXT_TF_DBG(ERR, "Error in bit list alloc\n"); return -ENOMEM; } - + if (key_index > hash_tbl->num_key_entries) { + BNXT_TF_DBG(ERR, "reached max size %u:%u\n", key_index, + hash_tbl->num_key_entries); + ulp_bit_alloc_list_dealloc(&hash_tbl->bit_list, key_index); + return -ENOMEM; + } /* Update the hash entry */ ULP_HASH_BUCKET_MARK_INUSE(bucket, (uint16_t)key_index); -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 04/20] net/bnxt: add clear on read support 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (2 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 03/20] net/bnxt: fix out of bounds issue in hash list Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 05/20] net/bnxt: add capability option for socket redirect Ajit Khaparde ` (17 subsequent siblings) 21 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev Cc: Farah Smith, Kishore Padmanabha, Venkat Duvvuru, Randy Schacher, Shahaji Bhosle [-- Attachment #1: Type: text/plain, Size: 7396 bytes --] From: Farah Smith <farah.smith@broadcom.com> Add clear on read stats support for Thor. Currently, the flow stats are not cleared after they are read from the FW. This patch adds support for clear on read. Since clear on read support is added for flow stats in Thor, the flow accumulation is enabled on Thor as well. Signed-off-by: Farah Smith <farah.smith@broadcom.com> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_core/tf_msg.c | 24 ++++++++++++++++++++---- drivers/net/bnxt/tf_core/tf_msg.h | 6 ++++-- drivers/net/bnxt/tf_core/tf_tbl.c | 6 ++++-- drivers/net/bnxt/tf_core/tf_tbl_sram.c | 13 +++++++++++-- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 3 ++- 5 files changed, 41 insertions(+), 11 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 0fbb2fe837..ea6e2af7ce 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -1851,7 +1851,8 @@ tf_msg_get_tbl_entry(struct tf *tfp, uint16_t hcapi_type, uint16_t size, uint8_t *data, - uint32_t index) + uint32_t index, + bool clear_on_read) { int rc; struct hwrm_tf_tbl_type_get_input req = { 0 }; @@ -1860,6 +1861,7 @@ tf_msg_get_tbl_entry(struct tf *tfp, uint8_t fw_session_id; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t flags = 0; /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); @@ -1889,10 +1891,16 @@ tf_msg_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } + flags = (dir == TF_DIR_TX ? + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX : + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX); + + if (clear_on_read) + flags |= HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ; /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); - req.flags = tfp_cpu_to_le_16(dir); + req.flags = tfp_cpu_to_le_16(flags); req.type = tfp_cpu_to_le_32(hcapi_type); req.index = tfp_cpu_to_le_32(index); @@ -2105,7 +2113,8 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint32_t starting_idx, uint16_t num_entries, uint16_t entry_sz_in_bytes, - uint64_t physical_mem_addr) + uint64_t physical_mem_addr, + bool clear_on_read) { int rc; struct tfp_send_msg_parms parms = { 0 }; @@ -2115,6 +2124,7 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint8_t fw_session_id; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t flags = 0; /* Retrieve the session information */ rc = tf_session_get_session(tfp, &tfs); @@ -2144,10 +2154,16 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } + flags = (dir == TF_DIR_TX ? + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX : + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX); + + if (clear_on_read) + flags |= HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ; /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); - req.flags = tfp_cpu_to_le_16(dir); + req.flags = tfp_cpu_to_le_16(flags); req.type = tfp_cpu_to_le_32(hcapi_type); req.start_index = tfp_cpu_to_le_32(starting_idx); req.num_entries = tfp_cpu_to_le_32(num_entries); diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index b26b15bfa3..718bc2f3b2 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -652,7 +652,8 @@ int tf_msg_get_tbl_entry(struct tf *tfp, uint16_t hcapi_type, uint16_t size, uint8_t *data, - uint32_t index); + uint32_t index, + bool clear_on_read); /* HWRM Tunneled messages */ @@ -704,7 +705,8 @@ int tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint32_t starting_idx, uint16_t num_entries, uint16_t entry_sz_in_bytes, - uint64_t physical_mem_addr); + uint64_t physical_mem_addr, + bool clear_on_read); /** * Sends Set message of a IF Table Type element to the firmware. diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 0a8720e7b6..12eca36491 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -441,7 +441,8 @@ tf_tbl_get(struct tf *tfp, hcapi_type, parms->data_sz_in_bytes, parms->data, - parms->idx); + parms->idx, + false); if (rc) { TFP_DRV_LOG(ERR, "%s, Get failed, type:%s, rc:%s\n", @@ -526,7 +527,8 @@ tf_tbl_bulk_get(struct tf *tfp, parms->starting_idx, parms->num_entries, parms->entry_sz_in_bytes, - parms->physical_mem_addr); + parms->physical_mem_addr, + false); if (rc) { TFP_DRV_LOG(ERR, "%s, Bulk get failed, type:%s, rc:%s\n", diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c index 636811bc2d..567f912dfa 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c +++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c @@ -539,6 +539,7 @@ tf_tbl_sram_get(struct tf *tfp, struct tf_tbl_sram_get_info_parms iparms = { 0 }; struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; void *sram_handle = NULL; + bool clear_on_read = false; TF_CHECK_PARMS3(tfp, parms, parms->data); @@ -608,6 +609,8 @@ tf_tbl_sram_get(struct tf *tfp, strerror(-rc)); return rc; } + if (parms->type == TF_TBL_TYPE_ACT_STATS_64) + clear_on_read = true; /* Get the entry */ rc = tf_msg_get_tbl_entry(tfp, @@ -615,7 +618,8 @@ tf_tbl_sram_get(struct tf *tfp, hcapi_type, parms->data_sz_in_bytes, parms->data, - parms->idx); + parms->idx, + clear_on_read); if (rc) { TFP_DRV_LOG(ERR, "%s, Get failed, type:%s, rc:%s\n", @@ -643,6 +647,7 @@ tf_tbl_sram_bulk_get(struct tf *tfp, struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; bool allocated = false; void *sram_handle = NULL; + bool clear_on_read = false; TF_CHECK_PARMS2(tfp, parms); @@ -728,6 +733,9 @@ tf_tbl_sram_bulk_get(struct tf *tfp, return rc; } + if (parms->type == TF_TBL_TYPE_ACT_STATS_64) + clear_on_read = true; + /* Get the entries */ rc = tf_msg_bulk_get_tbl_entry(tfp, parms->dir, @@ -735,7 +743,8 @@ tf_tbl_sram_bulk_get(struct tf *tfp, parms->starting_idx, parms->num_entries, parms->entry_sz_in_bytes, - parms->physical_mem_addr); + parms->physical_mem_addr, + clear_on_read); if (rc) { TFP_DRV_LOG(ERR, "%s, Bulk get failed, type:%s, rc:%s\n", diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index dbc8a3c5bb..f1763e2519 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1483,7 +1483,8 @@ bnxt_ulp_port_init(struct bnxt *bp) goto jump_to_error; } - if (devid != BNXT_ULP_DEVICE_ID_THOR && BNXT_ACCUM_STATS_EN(bp)) + /* set the accumulation of the stats */ + if (BNXT_ACCUM_STATS_EN(bp)) bp->ulp_ctx->cfg_data->accum_stats = true; BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init, accum_stats:%d\n", -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 05/20] net/bnxt: add capability option for socket redirect 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (3 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 04/20] net/bnxt: add clear on read support Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 06/20] net/bnxt: enable wildcard match for ingress flows Ajit Khaparde ` (16 subsequent siblings) 21 siblings, 1 reply; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Mike Baucom, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 13188 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Added support for socket redirect feature capability so applications can enable or disable this feature. This patch contains the template changes. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/bnxt.h | 13 -- drivers/net/bnxt/bnxt_ethdev.c | 203 ------------------ drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 11 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 6 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 10 +- .../generic_templates/ulp_template_db_enum.h | 8 +- .../generic_templates/ulp_template_db_tbl.c | 5 +- 7 files changed, 30 insertions(+), 226 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 97e281a2fc..4ab9ebd049 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -1054,19 +1054,6 @@ int32_t bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); int32_t bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); -void bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, - uint8_t *mac, uint8_t *parent_mac); -uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); -struct bnxt *bnxt_get_bp(uint16_t port); -uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, - enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_phy_port_id(uint16_t port); -uint16_t bnxt_get_vport(uint16_t port); -enum bnxt_ulp_intf_type -bnxt_get_interface_type(uint16_t port); int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev); void bnxt_cancel_fc_thread(struct bnxt *bp); diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 257e6b0d6a..2ab0cf3784 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -5047,209 +5047,6 @@ static void bnxt_config_vf_req_fwd(struct bnxt *bp) BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); } -struct bnxt * -bnxt_get_bp(uint16_t port) -{ - struct bnxt *bp; - struct rte_eth_dev *dev; - - if (!rte_eth_dev_is_valid_port(port)) { - PMD_DRV_LOG(ERR, "Invalid port %d\n", port); - return NULL; - } - - dev = &rte_eth_devices[port]; - if (!is_bnxt_supported(dev)) { - PMD_DRV_LOG(ERR, "Device %d not supported\n", port); - return NULL; - } - - bp = (struct bnxt *)dev->data->dev_private; - if (!BNXT_TRUFLOW_EN(bp)) { - PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); - return NULL; - } - - return bp; -} - -uint16_t -bnxt_get_svif(uint16_t port_id, bool func_svif, - enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->svif; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return func_svif ? bp->func_svif : bp->port_svif; -} - -void -bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, - uint8_t *mac, uint8_t *parent_mac) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF && - type != BNXT_ULP_INTF_TYPE_PF) - return; - - eth_dev = &rte_eth_devices[port]; - bp = eth_dev->data->dev_private; - memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN); - - if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF) - memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN); -} - -uint16_t -bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF) - return 0; - - eth_dev = &rte_eth_devices[port]; - bp = eth_dev->data->dev_private; - - return bp->parent->vnic; -} -uint16_t -bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt_vnic_info *vnic; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->dflt_vnic_id; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - vnic = BNXT_GET_DEFAULT_VNIC(bp); - - return vnic->fw_vnic_id; -} - -uint16_t -bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->fw_fid; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return bp->fw_fid; -} - -enum bnxt_ulp_intf_type -bnxt_get_interface_type(uint16_t port) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) - return BNXT_ULP_INTF_TYPE_VF_REP; - - bp = eth_dev->data->dev_private; - if (BNXT_PF(bp)) - return BNXT_ULP_INTF_TYPE_PF; - else if (BNXT_VF_IS_TRUSTED(bp)) - return BNXT_ULP_INTF_TYPE_TRUSTED_VF; - else if (BNXT_VF(bp)) - return BNXT_ULP_INTF_TYPE_VF; - - return BNXT_ULP_INTF_TYPE_INVALID; -} - -uint16_t -bnxt_get_phy_port_id(uint16_t port_id) -{ - struct bnxt_representor *vfr; - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; -} - -uint16_t -bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->fw_fid - 1; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; -} - -uint16_t -bnxt_get_vport(uint16_t port_id) -{ - return (1 << bnxt_get_phy_port_id(port_id)); -} - static void bnxt_alloc_error_recovery_info(struct bnxt *bp) { struct bnxt_error_recovery_info *info = bp->recovery_info; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index f1763e2519..2ac1a8625f 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -301,13 +301,14 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, } int32_t -bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, uint8_t app_id, uint32_t dev_id) { struct bnxt_ulp_app_capabilities_info *info; uint32_t num = 0; uint16_t i; bool found = false; + struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx; if (ULP_APP_DEV_UNSUPPORTED_ENABLED(ulp_ctx->cfg_data->ulp_flags)) { BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", @@ -334,6 +335,12 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, if (info[i].flags & BNXT_ULP_APP_CAP_UNICAST_ONLY) ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_APP_UNICAST_ONLY; + if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) { + /* Enable socket direction only if MR is enabled in fw*/ + if (BNXT_MULTIROOT_EN(bp)) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_SOCKET_DIRECT; + } } if (!found) { BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", @@ -832,7 +839,7 @@ ulp_ctx_init(struct bnxt *bp, } BNXT_TF_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id); - rc = bnxt_ulp_cntxt_app_caps_init(bp->ulp_ctx, bp->app_id, devid); + rc = bnxt_ulp_cntxt_app_caps_init(bp, bp->app_id, devid); if (rc) { BNXT_TF_DBG(ERR, "Unable to set caps for app(%x)/dev(%x)\n", bp->app_id, devid); diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 006df9cbc5..68f1470c61 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -13,6 +13,7 @@ #include "rte_version.h" #include "rte_ethdev.h" +#include "bnxt.h" #include "ulp_template_db_enum.h" #include "ulp_tun.h" #include "bnxt_tf_common.h" @@ -33,12 +34,15 @@ #define BNXT_ULP_APP_DEV_UNSUPPORTED 0x4 #define BNXT_ULP_HIGH_AVAIL_ENABLED 0x8 #define BNXT_ULP_APP_UNICAST_ONLY 0x10 +#define BNXT_ULP_APP_SOCKET_DIRECT 0x20 + #define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED) #define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\ BNXT_ULP_SHARED_SESSION_ENABLED) #define ULP_APP_DEV_UNSUPPORTED_ENABLED(flag) ((flag) &\ BNXT_ULP_APP_DEV_UNSUPPORTED) #define ULP_HIGH_AVAIL_IS_ENABLED(flag) ((flag) & BNXT_ULP_HIGH_AVAIL_ENABLED) +#define ULP_SOCKET_DIRECT_IS_ENABLED(flag) ((flag) & BNXT_ULP_APP_SOCKET_DIRECT) enum bnxt_ulp_flow_mem_type { BNXT_ULP_FLOW_MEM_TYPE_INT = 0, @@ -287,7 +291,7 @@ struct bnxt_ulp_app_capabilities_info * bnxt_ulp_app_cap_list_get(uint32_t *num_entries); int32_t -bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, uint8_t app_id, uint32_t dev_id); struct bnxt_ulp_resource_resv_info * diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 2fec79a388..272195f6a2 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -115,9 +115,11 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FLOW_SIG_ID, params->flow_sig_id); + if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags)) + return; + /* update the WC Priority flag */ - if (!bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags) && - ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) { + if (ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) { enum ulp_ha_mgr_region region = ULP_HA_REGION_LOW; int32_t rc; @@ -129,6 +131,10 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG, 1); } + + /* Update the socket direct flag */ + if (ULP_SOCKET_DIRECT_IS_ENABLED(ulp_flags)) + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT, 1); } /* Function to create the rte flow. */ diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index fcd460e707..31a94c14dc 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Aug 26 17:43:36 2021 */ +/* date: Thu Sep 9 11:11:05 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -211,7 +211,8 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 71, BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72, BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73, - BNXT_ULP_CF_IDX_LAST = 74 + BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74, + BNXT_ULP_CF_IDX_LAST = 75 }; enum bnxt_ulp_cond_list_opc { @@ -582,7 +583,8 @@ enum bnxt_ulp_template_type { enum bnxt_ulp_app_cap { BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001, BNXT_ULP_APP_CAP_HOT_UPGRADE_EN = 0x00000002, - BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004 + BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004, + BNXT_ULP_APP_CAP_SOCKET_DIRECT = 0x00000008 }; enum bnxt_ulp_fdb_resource_flags { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 84be09b368..5383e2cd70 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Aug 26 17:43:36 2021 */ +/* date: Thu Sep 9 11:11:05 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -347,7 +347,8 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { .device_id = BNXT_ULP_DEVICE_ID_THOR, .flags = BNXT_ULP_APP_CAP_SHARED_EN | BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | - BNXT_ULP_APP_CAP_UNICAST_ONLY + BNXT_ULP_APP_CAP_UNICAST_ONLY | + BNXT_ULP_APP_CAP_SOCKET_DIRECT }, { .app_id = 2, -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH v4 05/20] net/bnxt: add capability option for socket redirect 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 05/20] net/bnxt: add capability option for socket redirect Ajit Khaparde @ 2021-11-03 13:24 ` Ferruh Yigit 0 siblings, 0 replies; 118+ messages in thread From: Ferruh Yigit @ 2021-11-03 13:24 UTC (permalink / raw) To: Ajit Khaparde, dev Cc: Kishore Padmanabha, Venkat Duvvuru, Mike Baucom, Randy Schacher On 11/3/2021 12:52 AM, Ajit Khaparde wrote: > From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> > > Added support for socket redirect feature capability so applications > can enable or disable this feature. This patch contains the template > changes. > > Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> > Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> > Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> > Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> > Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> > --- > drivers/net/bnxt/bnxt.h | 13 -- > drivers/net/bnxt/bnxt_ethdev.c | 203 ------------------ > drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 11 +- > drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 6 +- > drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 10 +- > .../generic_templates/ulp_template_db_enum.h | 8 +- > .../generic_templates/ulp_template_db_tbl.c | 5 +- > 7 files changed, 30 insertions(+), 226 deletions(-) > > diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h > index 97e281a2fc..4ab9ebd049 100644 > --- a/drivers/net/bnxt/bnxt.h > +++ b/drivers/net/bnxt/bnxt.h > @@ -1054,19 +1054,6 @@ int32_t > bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); > int32_t > bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); > -void bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, > - uint8_t *mac, uint8_t *parent_mac); > -uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); > -uint16_t bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); > -struct bnxt *bnxt_get_bp(uint16_t port); > -uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, > - enum bnxt_ulp_intf_type type); > -uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); > -uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); > -uint16_t bnxt_get_phy_port_id(uint16_t port); > -uint16_t bnxt_get_vport(uint16_t port); > -enum bnxt_ulp_intf_type > -bnxt_get_interface_type(uint16_t port); Are these removed functions related to the socket redirect capability? ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 06/20] net/bnxt: enable wildcard match for ingress flows 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (4 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 05/20] net/bnxt: add capability option for socket redirect Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 07/20] net/bnxt: support inner IP header for GRE tunnel flows Ajit Khaparde ` (15 subsequent siblings) 21 siblings, 1 reply; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Michael Baucom, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 320314 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Enabled wildcard match support for ipv4 ingress flows. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- .../generic_templates/ulp_template_db_class.c | 1986 ++++++++--------- .../generic_templates/ulp_template_db_enum.h | 4 +- .../ulp_template_db_thor_class.c | 251 +-- 3 files changed, 1118 insertions(+), 1123 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c index ad3866243d..1d1e6463e0 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 6 11:15:47 2021 */ +/* date: Thu Sep 16 13:12:05 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -1016,7 +1016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55dd, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1031,7 +1031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1df1, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4104, + .flow_sig_id = 4104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1047,7 +1047,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e55, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1063,7 +1063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0649, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 6152, + .flow_sig_id = 6152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1080,7 +1080,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1011, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1095,7 +1095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40e9, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 16392, + .flow_sig_id = 16392UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1111,7 +1111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e99, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1127,7 +1127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06ad, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 24584, + .flow_sig_id = 24584UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1144,7 +1144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_38c7, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1160,7 +1160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00fb, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32776, + .flow_sig_id = 32776UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1177,7 +1177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_24d3, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1194,7 +1194,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_559b, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32840, + .flow_sig_id = 32840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1212,7 +1212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5003, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1229,7 +1229,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1837, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1247,7 +1247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bef, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1265,7 +1265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0403, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49224, + .flow_sig_id = 49224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1284,7 +1284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d3f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1300,7 +1300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0543, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131080, + .flow_sig_id = 131080UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1317,7 +1317,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_292b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1334,7 +1334,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59e3, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131144, + .flow_sig_id = 131144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1352,7 +1352,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d3b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1369,7 +1369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_254f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196616, + .flow_sig_id = 196616UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1387,7 +1387,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4917, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1405,7 +1405,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_113b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196680, + .flow_sig_id = 196680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1424,7 +1424,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55fd, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1440,7 +1440,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1dd1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 4104, + .flow_sig_id = 4104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1457,7 +1457,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e75, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1474,7 +1474,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0669, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 6152, + .flow_sig_id = 6152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1492,7 +1492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ba1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1509,7 +1509,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c69, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 12296, + .flow_sig_id = 12296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1527,7 +1527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0439, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1545,7 +1545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34e1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 14344, + .flow_sig_id = 14344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1564,7 +1564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0465, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1581,7 +1581,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_352d, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 20488, + .flow_sig_id = 20488UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1599,7 +1599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55b1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1617,7 +1617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1da5, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 22536, + .flow_sig_id = 22536UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1636,7 +1636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_32fd, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1654,7 +1654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_63a5, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 28680, + .flow_sig_id = 28680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1673,7 +1673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1b75, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1692,7 +1692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c3d, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 30728, + .flow_sig_id = 30728UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1712,7 +1712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1031, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1728,7 +1728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40c9, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 16392, + .flow_sig_id = 16392UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1745,7 +1745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3eb9, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1762,7 +1762,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_068d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24584, + .flow_sig_id = 24584UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1780,7 +1780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5039, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1797,7 +1797,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_180d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1815,7 +1815,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15fd, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1833,7 +1833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46b5, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 57352, + .flow_sig_id = 57352UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1852,7 +1852,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_303d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1869,7 +1869,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_60f5, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 81928, + .flow_sig_id = 81928UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1887,7 +1887,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ea5, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1905,7 +1905,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2689, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 90120, + .flow_sig_id = 90120UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1924,7 +1924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0771, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1942,7 +1942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3809, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1961,7 +1961,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35f9, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1980,7 +1980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66b1, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 122888, + .flow_sig_id = 122888UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2000,7 +2000,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_559d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2016,7 +2016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1db1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 4104, + .flow_sig_id = 4104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2033,7 +2033,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e15, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2050,7 +2050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0609, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 6152, + .flow_sig_id = 6152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2068,7 +2068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1bc1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2085,7 +2085,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c09, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 12296, + .flow_sig_id = 12296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2103,7 +2103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0459, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2121,7 +2121,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3481, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14344, + .flow_sig_id = 14344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2140,7 +2140,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0405, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2157,7 +2157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_354d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 20488, + .flow_sig_id = 20488UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2175,7 +2175,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55d1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2193,7 +2193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1dc5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 22536, + .flow_sig_id = 22536UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2212,7 +2212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_329d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2230,7 +2230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_63c5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 28680, + .flow_sig_id = 28680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2249,7 +2249,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1b15, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2268,7 +2268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c5d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 30728, + .flow_sig_id = 30728UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2288,7 +2288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1051, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2304,7 +2304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40a9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16392, + .flow_sig_id = 16392UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2321,7 +2321,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ed9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2338,7 +2338,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06ed, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 24584, + .flow_sig_id = 24584UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2356,7 +2356,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5059, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2373,7 +2373,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_186d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2391,7 +2391,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_159d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2409,7 +2409,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46d5, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 57352, + .flow_sig_id = 57352UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2428,7 +2428,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_305d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2445,7 +2445,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6095, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 81928, + .flow_sig_id = 81928UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2463,7 +2463,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ec5, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2481,7 +2481,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26e9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 90120, + .flow_sig_id = 90120UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2500,7 +2500,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0711, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2518,7 +2518,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3869, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2537,7 +2537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3599, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2556,7 +2556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66d1, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 122888, + .flow_sig_id = 122888UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2576,7 +2576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_38e7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2593,7 +2593,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00db, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32776, + .flow_sig_id = 32776UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2611,7 +2611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_24f3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2629,7 +2629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55bb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32840, + .flow_sig_id = 32840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2648,7 +2648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5023, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2666,7 +2666,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1817, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2685,7 +2685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bcf, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2704,7 +2704,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0423, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49224, + .flow_sig_id = 49224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2724,7 +2724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_58e3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2742,7 +2742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20d7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98312, + .flow_sig_id = 98312UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2761,7 +2761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_448f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2780,7 +2780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0ce3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98376, + .flow_sig_id = 98376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2800,7 +2800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_076b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2819,7 +2819,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3813, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2839,7 +2839,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5bcb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2859,7 +2859,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_243f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114760, + .flow_sig_id = 114760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2880,7 +2880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_144b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2898,7 +2898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4573, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163848, + .flow_sig_id = 163848UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2917,7 +2917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0057, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2936,7 +2936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_311f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163912, + .flow_sig_id = 163912UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2956,7 +2956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2b87, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2975,7 +2975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c4f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180232, + .flow_sig_id = 180232UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2995,7 +2995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1793, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3015,7 +3015,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_485b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180296, + .flow_sig_id = 180296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3036,7 +3036,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3447, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3055,7 +3055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_650f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229384, + .flow_sig_id = 229384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3075,7 +3075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2053, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3095,7 +3095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_511b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229448, + .flow_sig_id = 229448UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3116,7 +3116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4b83, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3136,7 +3136,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13f7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245768, + .flow_sig_id = 245768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3157,7 +3157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_37af, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3178,7 +3178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6857, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245832, + .flow_sig_id = 245832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3200,7 +3200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d1f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3217,7 +3217,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0563, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131080, + .flow_sig_id = 131080UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3235,7 +3235,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_290b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3253,7 +3253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59c3, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131144, + .flow_sig_id = 131144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3272,7 +3272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d1b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3290,7 +3290,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_256f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196616, + .flow_sig_id = 196616UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3309,7 +3309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4937, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3328,7 +3328,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_111b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196680, + .flow_sig_id = 196680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3348,7 +3348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f4b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3366,7 +3366,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_275f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393224, + .flow_sig_id = 393224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3385,7 +3385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4b67, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3404,7 +3404,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_134b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393288, + .flow_sig_id = 393288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3424,7 +3424,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1683, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3443,7 +3443,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_475b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458760, + .flow_sig_id = 458760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3463,7 +3463,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_02bf, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3483,7 +3483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3377, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458824, + .flow_sig_id = 458824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3504,7 +3504,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19db, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3522,7 +3522,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4a93, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655368, + .flow_sig_id = 655368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3541,7 +3541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_05f7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3560,7 +3560,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_368f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655432, + .flow_sig_id = 655432UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3580,7 +3580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39c7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3599,7 +3599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_022b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720904, + .flow_sig_id = 720904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3619,7 +3619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_25f3, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3639,7 +3639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_568b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720968, + .flow_sig_id = 720968UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3660,7 +3660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c37, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3679,7 +3679,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_041b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917512, + .flow_sig_id = 917512UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3699,7 +3699,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2823, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3719,7 +3719,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_58fb, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917576, + .flow_sig_id = 917576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3740,7 +3740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c33, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3760,7 +3760,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2407, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983048, + .flow_sig_id = 983048UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3781,7 +3781,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_482f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3802,7 +3802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1033, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983112, + .flow_sig_id = 983112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3824,7 +3824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3887, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3841,7 +3841,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00bb, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32776, + .flow_sig_id = 32776UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3859,7 +3859,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2493, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3877,7 +3877,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55db, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32840, + .flow_sig_id = 32840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3896,7 +3896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5043, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3914,7 +3914,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1877, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3933,7 +3933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3baf, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3952,7 +3952,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0443, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49224, + .flow_sig_id = 49224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3972,7 +3972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5883, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3990,7 +3990,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20b7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98312, + .flow_sig_id = 98312UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4009,7 +4009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_44ef, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4028,7 +4028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c83, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98376, + .flow_sig_id = 98376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4048,7 +4048,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_070b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4067,7 +4067,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3873, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4087,7 +4087,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5bab, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4107,7 +4107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_245f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114760, + .flow_sig_id = 114760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4128,7 +4128,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_142b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4146,7 +4146,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4513, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163848, + .flow_sig_id = 163848UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4165,7 +4165,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0037, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4184,7 +4184,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_317f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163912, + .flow_sig_id = 163912UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4204,7 +4204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2be7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4223,7 +4223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c2f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180232, + .flow_sig_id = 180232UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4243,7 +4243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_17f3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4263,7 +4263,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_483b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180296, + .flow_sig_id = 180296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4284,7 +4284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3427, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4303,7 +4303,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_656f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229384, + .flow_sig_id = 229384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4323,7 +4323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2033, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4343,7 +4343,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_517b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229448, + .flow_sig_id = 229448UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4364,7 +4364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4be3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4384,7 +4384,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1397, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245768, + .flow_sig_id = 245768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4405,7 +4405,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_37cf, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4426,7 +4426,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6837, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245832, + .flow_sig_id = 245832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4448,7 +4448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d7f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4465,7 +4465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0503, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131080, + .flow_sig_id = 131080UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4483,7 +4483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_296b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4501,7 +4501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59a3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131144, + .flow_sig_id = 131144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4520,7 +4520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d7b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4538,7 +4538,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_250f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196616, + .flow_sig_id = 196616UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4557,7 +4557,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4957, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4576,7 +4576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_117b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196680, + .flow_sig_id = 196680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4596,7 +4596,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f2b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4614,7 +4614,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_273f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393224, + .flow_sig_id = 393224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4633,7 +4633,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4b07, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4652,7 +4652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_132b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393288, + .flow_sig_id = 393288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4672,7 +4672,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_16e3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4691,7 +4691,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_473b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458760, + .flow_sig_id = 458760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4711,7 +4711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_02df, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4731,7 +4731,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3317, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458824, + .flow_sig_id = 458824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4752,7 +4752,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19bb, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4770,7 +4770,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4af3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655368, + .flow_sig_id = 655368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4789,7 +4789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0597, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4808,7 +4808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_36ef, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655432, + .flow_sig_id = 655432UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4828,7 +4828,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39a7, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4847,7 +4847,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_024b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720904, + .flow_sig_id = 720904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4867,7 +4867,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2593, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4887,7 +4887,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_56eb, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720968, + .flow_sig_id = 720968UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4908,7 +4908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c57, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4927,7 +4927,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_047b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917512, + .flow_sig_id = 917512UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4947,7 +4947,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2843, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4967,7 +4967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_589b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917576, + .flow_sig_id = 917576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4988,7 +4988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c53, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5008,7 +5008,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2467, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983048, + .flow_sig_id = 983048UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5029,7 +5029,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_484f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5050,7 +5050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1053, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983112, + .flow_sig_id = 983112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5072,7 +5072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ce1, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5086,7 +5086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4579, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5101,7 +5101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1735, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5115,7 +5115,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_45bd, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5130,7 +5130,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3feb, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5145,7 +5145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bf7, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5161,7 +5161,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5727, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5177,7 +5177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4333, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5194,7 +5194,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4453, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5209,7 +5209,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_304f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5225,7 +5225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_645f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5241,7 +5241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_504b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5258,7 +5258,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5cc1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5273,7 +5273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4559, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5289,7 +5289,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2285, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5305,7 +5305,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b1d, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5322,7 +5322,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b49, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5338,7 +5338,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c95, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5355,7 +5355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39c1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5372,7 +5372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2259, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5390,7 +5390,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1715, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5405,7 +5405,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_459d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5421,7 +5421,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_571d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5437,7 +5437,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cd1, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5454,7 +5454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3711, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5470,7 +5470,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6599, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5487,7 +5487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e55, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5504,7 +5504,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3cdd, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5522,7 +5522,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ca1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5537,7 +5537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4539, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5553,7 +5553,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_22e5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5569,7 +5569,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b7d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5586,7 +5586,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b29, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5602,7 +5602,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5cf5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5619,7 +5619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39a1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5636,7 +5636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2239, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5654,7 +5654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1775, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5669,7 +5669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_45fd, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5685,7 +5685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_577d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5701,7 +5701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cb1, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5718,7 +5718,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3771, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5734,7 +5734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_65f9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5751,7 +5751,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e35, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5768,7 +5768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3cbd, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5786,7 +5786,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3fcb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5802,7 +5802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bd7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5819,7 +5819,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5707, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5836,7 +5836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4313, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5854,7 +5854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5fc7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5871,7 +5871,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4bd3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5889,7 +5889,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e4f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5907,7 +5907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_632f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5926,7 +5926,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1baf, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5943,7 +5943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_07bb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5961,7 +5961,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_32eb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5979,7 +5979,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ef7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5998,7 +5998,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bab, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6016,7 +6016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_27b7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6035,7 +6035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52e7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6054,7 +6054,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ef3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6074,7 +6074,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4473, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6090,7 +6090,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_306f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6107,7 +6107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_647f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6124,7 +6124,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_506b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6142,7 +6142,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66af, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6159,7 +6159,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_525b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6177,7 +6177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1de7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6195,7 +6195,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0993, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6214,7 +6214,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_213f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6231,7 +6231,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d2b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6249,7 +6249,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_413b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6267,7 +6267,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2cd7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6286,7 +6286,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_436b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6304,7 +6304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2f07, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6323,7 +6323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6317, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6342,7 +6342,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4f03, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6362,7 +6362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3fab, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6378,7 +6378,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bb7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6395,7 +6395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5767, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6412,7 +6412,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4373, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6430,7 +6430,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5fa7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6447,7 +6447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4bb3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6465,7 +6465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e2f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6483,7 +6483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_634f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6502,7 +6502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1bcf, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6519,7 +6519,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_07db, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6537,7 +6537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_328b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6555,7 +6555,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1e97, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6574,7 +6574,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bcb, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6592,7 +6592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_27d7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6611,7 +6611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5287, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6630,7 +6630,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e93, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6650,7 +6650,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4413, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6666,7 +6666,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_300f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6683,7 +6683,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_641f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6700,7 +6700,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_500b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6718,7 +6718,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66cf, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6735,7 +6735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_523b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6753,7 +6753,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1d87, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6771,7 +6771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09f3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6790,7 +6790,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_215f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6807,7 +6807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d4b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6825,7 +6825,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_415b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6843,7 +6843,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2cb7, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6862,7 +6862,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_430b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6880,7 +6880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2f67, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6899,7 +6899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6377, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6918,7 +6918,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4f63, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6938,7 +6938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29b5, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -6953,7 +6953,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29ad, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -6968,7 +6968,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29b7, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -6984,7 +6984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1583, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7001,7 +7001,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29af, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7017,7 +7017,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_159b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7034,7 +7034,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2995, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7050,7 +7050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_298d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7066,7 +7066,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29f5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7082,7 +7082,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29ed, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7098,7 +7098,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2997, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7115,7 +7115,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15a3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7133,7 +7133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_298f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7150,7 +7150,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15bb, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7168,7 +7168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29f7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7185,7 +7185,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15c3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7203,7 +7203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29ef, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7220,7 +7220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15db, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7238,7 +7238,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1151, .class_tid = 1, .hdr_sig_id = 12, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 3, .app_sig = 0, .hdr_sig = { .bits = @@ -7255,7 +7255,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_315d, .class_tid = 1, .hdr_sig_id = 12, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 3, .app_sig = 0, .hdr_sig = { .bits = @@ -7273,7 +7273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3612, .class_tid = 2, .hdr_sig_id = 0, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -7292,7 +7292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66da, .class_tid = 2, .hdr_sig_id = 0, - .flow_sig_id = 81928, + .flow_sig_id = 81928UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -7312,7 +7312,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e082, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7332,7 +7332,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ab46, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7353,7 +7353,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c82a, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7374,7 +7374,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f9a2, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7396,7 +7396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d8ce, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 538184704, + .flow_sig_id = 538184704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7417,7 +7417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a2d2, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 538192896, + .flow_sig_id = 538192896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7439,7 +7439,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c076, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 540281856, + .flow_sig_id = 540281856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7461,7 +7461,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f1ee, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 540290048, + .flow_sig_id = 540290048UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7484,7 +7484,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a96e, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1075055616, + .flow_sig_id = 1075055616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7505,7 +7505,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dae6, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1075063808, + .flow_sig_id = 1075063808UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7527,7 +7527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c7aa, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1077152768, + .flow_sig_id = 1077152768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7549,7 +7549,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c26e, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1077160960, + .flow_sig_id = 1077160960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7572,7 +7572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a0fa, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1611926528, + .flow_sig_id = 1611926528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7594,7 +7594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d272, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1611934720, + .flow_sig_id = 1611934720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7617,7 +7617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fff6, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1614023680, + .flow_sig_id = 1614023680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7640,7 +7640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e16e, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1614031872, + .flow_sig_id = 1614031872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7664,7 +7664,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e165, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7684,7 +7684,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aaa1, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7705,7 +7705,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c9cd, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7726,7 +7726,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f845, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7748,7 +7748,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_90f9, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7769,7 +7769,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c371, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7791,7 +7791,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e19d, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7813,7 +7813,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d015, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7836,7 +7836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8c09, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7857,7 +7857,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_be89, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7879,7 +7879,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ddad, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7901,7 +7901,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cc2d, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7924,7 +7924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a4d9, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7946,7 +7946,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d759, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7969,7 +7969,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f27d, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7992,7 +7992,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e4fd, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8016,7 +8016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ecf6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8037,7 +8037,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a732, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8059,7 +8059,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c45e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8081,7 +8081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f5d6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8104,7 +8104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d4ba, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 538184704, + .flow_sig_id = 538184704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8126,7 +8126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aea6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 538192896, + .flow_sig_id = 538192896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8149,7 +8149,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cc02, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 540281856, + .flow_sig_id = 540281856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8172,7 +8172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fd9a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 540290048, + .flow_sig_id = 540290048UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8196,7 +8196,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a51a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1075055616, + .flow_sig_id = 1075055616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8218,7 +8218,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d692, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1075063808, + .flow_sig_id = 1075063808UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8241,7 +8241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cbde, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1077152768, + .flow_sig_id = 1077152768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8264,7 +8264,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce1a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1077160960, + .flow_sig_id = 1077160960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8288,7 +8288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ac8e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1611926528, + .flow_sig_id = 1611926528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8311,7 +8311,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_de06, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1611934720, + .flow_sig_id = 1611934720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8335,7 +8335,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f382, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1614023680, + .flow_sig_id = 1614023680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8359,7 +8359,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ed1a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1614031872, + .flow_sig_id = 1614031872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8384,7 +8384,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9d6a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8406,7 +8406,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cee2, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8429,7 +8429,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ec0e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8452,7 +8452,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dd86, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8476,7 +8476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_852e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2685668352, + .flow_sig_id = 2685668352UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8499,7 +8499,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b6a6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2685676544, + .flow_sig_id = 2685676544UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8523,7 +8523,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_eb82, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2687765504, + .flow_sig_id = 2687765504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8547,7 +8547,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c50a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2687773696, + .flow_sig_id = 2687773696UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8572,7 +8572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ccca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3222539264, + .flow_sig_id = 3222539264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8595,7 +8595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8706, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3222547456, + .flow_sig_id = 3222547456UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8619,7 +8619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d38e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3224636416, + .flow_sig_id = 3224636416UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8643,7 +8643,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d5ca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3224644608, + .flow_sig_id = 3224644608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8668,7 +8668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b48e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3759410176, + .flow_sig_id = 3759410176UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8692,7 +8692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8e8a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3759418368, + .flow_sig_id = 3759418368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8717,7 +8717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_db02, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3761507328, + .flow_sig_id = 3761507328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8742,7 +8742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dd8e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3761515520, + .flow_sig_id = 3761515520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8768,7 +8768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_819a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8790,7 +8790,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b31a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8813,7 +8813,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d03e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8836,7 +8836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c1be, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8860,7 +8860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_890e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4833152000, + .flow_sig_id = 4833152000UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8883,7 +8883,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ba8e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4833160192, + .flow_sig_id = 4833160192UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8907,7 +8907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dfaa, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4835249152, + .flow_sig_id = 4835249152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8931,7 +8931,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c93a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4835257344, + .flow_sig_id = 4835257344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8956,7 +8956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b11a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5370022912, + .flow_sig_id = 5370022912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8979,7 +8979,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8b4e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5370031104, + .flow_sig_id = 5370031104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9003,7 +9003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c79e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5372120064, + .flow_sig_id = 5372120064UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9027,7 +9027,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d9da, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5372128256, + .flow_sig_id = 5372128256UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9052,7 +9052,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b88e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5906893824, + .flow_sig_id = 5906893824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9076,7 +9076,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ea0e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5906902016, + .flow_sig_id = 5906902016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9101,7 +9101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cf0a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5908990976, + .flow_sig_id = 5908990976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9126,7 +9126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c18e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5908999168, + .flow_sig_id = 5908999168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9152,7 +9152,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a94a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9175,7 +9175,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_daca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9199,7 +9199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ffee, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9223,7 +9223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e96e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9248,7 +9248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_910e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6980635648, + .flow_sig_id = 6980635648UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9272,7 +9272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c28e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6980643840, + .flow_sig_id = 6980643840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9297,7 +9297,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e7aa, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6982732800, + .flow_sig_id = 6982732800UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9322,7 +9322,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d12a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6982740992, + .flow_sig_id = 6982740992UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9348,7 +9348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d8ca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7517506560, + .flow_sig_id = 7517506560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9372,7 +9372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_930e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7517514752, + .flow_sig_id = 7517514752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9397,7 +9397,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ef4e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7519603712, + .flow_sig_id = 7519603712UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9422,7 +9422,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e18a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7519611904, + .flow_sig_id = 7519611904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9448,7 +9448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c08e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8054377472, + .flow_sig_id = 8054377472UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9473,7 +9473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9a8a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8054385664, + .flow_sig_id = 8054385664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9499,7 +9499,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d70a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8056474624, + .flow_sig_id = 8056474624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9525,7 +9525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e90e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8056482816, + .flow_sig_id = 8056482816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9552,7 +9552,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_edd9, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9573,7 +9573,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a61d, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9595,7 +9595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c571, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9617,7 +9617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f4f9, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9640,7 +9640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9c45, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9662,7 +9662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cfcd, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9685,7 +9685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ed21, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9708,7 +9708,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dca9, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9732,7 +9732,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_80b5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9754,7 +9754,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b235, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9777,7 +9777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d111, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9800,7 +9800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c091, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9824,7 +9824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a865, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9847,7 +9847,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dbe5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9871,7 +9871,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fec1, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9895,7 +9895,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e841, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9920,7 +9920,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8e85, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8591248384, + .flow_sig_id = 8591248384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9942,7 +9942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b80d, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8591256576, + .flow_sig_id = 8591256576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9965,7 +9965,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_df65, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8593345536, + .flow_sig_id = 8593345536UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9988,7 +9988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ceed, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8593353728, + .flow_sig_id = 8593353728UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10012,7 +10012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9645, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10738732032, + .flow_sig_id = 10738732032UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10035,7 +10035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c1cd, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10738740224, + .flow_sig_id = 10738740224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10059,7 +10059,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e725, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10740829184, + .flow_sig_id = 10740829184UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10083,7 +10083,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d6ad, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10740837376, + .flow_sig_id = 10740837376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10108,7 +10108,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9aa5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12886215680, + .flow_sig_id = 12886215680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10131,7 +10131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b425, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12886223872, + .flow_sig_id = 12886223872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10155,7 +10155,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_eb05, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12888312832, + .flow_sig_id = 12888312832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10179,7 +10179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_da85, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12888321024, + .flow_sig_id = 12888321024UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10204,7 +10204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a265, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15033699328, + .flow_sig_id = 15033699328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10228,7 +10228,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dde5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15033707520, + .flow_sig_id = 15033707520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10253,7 +10253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f0c5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15035796480, + .flow_sig_id = 15035796480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10278,7 +10278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e245, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15035804672, + .flow_sig_id = 15035804672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10304,7 +10304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8b8f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17181182976, + .flow_sig_id = 17181182976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10326,7 +10326,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a517, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17181191168, + .flow_sig_id = 17181191168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10349,7 +10349,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d86b, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17183280128, + .flow_sig_id = 17183280128UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10372,7 +10372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cbf3, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17183288320, + .flow_sig_id = 17183288320UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10396,7 +10396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_934f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19328666624, + .flow_sig_id = 19328666624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10419,7 +10419,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c2c7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19328674816, + .flow_sig_id = 19328674816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10443,7 +10443,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e02b, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19330763776, + .flow_sig_id = 19330763776UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10467,7 +10467,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d3a3, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19330771968, + .flow_sig_id = 19330771968UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10492,7 +10492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_87a7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21476150272, + .flow_sig_id = 21476150272UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10515,7 +10515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b137, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21476158464, + .flow_sig_id = 21476158464UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10539,7 +10539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d403, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21478247424, + .flow_sig_id = 21478247424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10563,7 +10563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c793, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21478255616, + .flow_sig_id = 21478255616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10588,7 +10588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_af67, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23623633920, + .flow_sig_id = 23623633920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10612,7 +10612,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dee7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23623642112, + .flow_sig_id = 23623642112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10637,7 +10637,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fdc3, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23625731072, + .flow_sig_id = 23625731072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10662,7 +10662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ef43, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23625739264, + .flow_sig_id = 23625739264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10688,7 +10688,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8dbf, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25771117568, + .flow_sig_id = 25771117568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10711,7 +10711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_bf07, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25771125760, + .flow_sig_id = 25771125760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10735,7 +10735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d21f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25773214720, + .flow_sig_id = 25773214720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10759,7 +10759,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cde7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25773222912, + .flow_sig_id = 25773222912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10784,7 +10784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_956f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27918601216, + .flow_sig_id = 27918601216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10808,7 +10808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c4c7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27918609408, + .flow_sig_id = 27918609408UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10833,7 +10833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fbcf, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27920698368, + .flow_sig_id = 27920698368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10858,7 +10858,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d5a7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27920706560, + .flow_sig_id = 27920706560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10884,7 +10884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9957, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30066084864, + .flow_sig_id = 30066084864UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10908,7 +10908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cb27, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30066093056, + .flow_sig_id = 30066093056UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10933,7 +10933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ee37, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30068182016, + .flow_sig_id = 30068182016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10958,7 +10958,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d987, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30068190208, + .flow_sig_id = 30068190208UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10984,7 +10984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a107, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32213568512, + .flow_sig_id = 32213568512UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11009,7 +11009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d0e7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32213576704, + .flow_sig_id = 32213576704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11035,7 +11035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f7e7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32215665664, + .flow_sig_id = 32215665664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11061,7 +11061,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c827, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32215673856, + .flow_sig_id = 32215673856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11088,7 +11088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f76a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11109,7 +11109,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_bcae, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11131,7 +11131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dfc2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11153,7 +11153,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ee4a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11176,7 +11176,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cf26, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 538184704, + .flow_sig_id = 538184704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11198,7 +11198,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b53a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 538192896, + .flow_sig_id = 538192896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11221,7 +11221,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d79e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 540281856, + .flow_sig_id = 540281856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11244,7 +11244,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e606, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 540290048, + .flow_sig_id = 540290048UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11268,7 +11268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_be86, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1075055616, + .flow_sig_id = 1075055616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11290,7 +11290,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cd0e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1075063808, + .flow_sig_id = 1075063808UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11313,7 +11313,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d042, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1077152768, + .flow_sig_id = 1077152768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11336,7 +11336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d586, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1077160960, + .flow_sig_id = 1077160960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11360,7 +11360,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b712, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1611926528, + .flow_sig_id = 1611926528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11383,7 +11383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c59a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1611934720, + .flow_sig_id = 1611934720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11407,7 +11407,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e81e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1614023680, + .flow_sig_id = 1614023680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11431,7 +11431,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f686, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1614031872, + .flow_sig_id = 1614031872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11456,7 +11456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_86f6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11478,7 +11478,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d57e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11501,7 +11501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f792, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11524,7 +11524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c61a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11548,7 +11548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9eb2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2685668352, + .flow_sig_id = 2685668352UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11571,7 +11571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ad3a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2685676544, + .flow_sig_id = 2685676544UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11595,7 +11595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f01e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2687765504, + .flow_sig_id = 2687765504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11619,7 +11619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_de96, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2687773696, + .flow_sig_id = 2687773696UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11644,7 +11644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d756, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3222539264, + .flow_sig_id = 3222539264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11667,7 +11667,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9c9a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3222547456, + .flow_sig_id = 3222547456UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11691,7 +11691,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c812, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3224636416, + .flow_sig_id = 3224636416UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11715,7 +11715,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce56, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3224644608, + .flow_sig_id = 3224644608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11740,7 +11740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_af12, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3759410176, + .flow_sig_id = 3759410176UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11764,7 +11764,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9516, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3759418368, + .flow_sig_id = 3759418368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11789,7 +11789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c09e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3761507328, + .flow_sig_id = 3761507328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11814,7 +11814,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c612, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3761515520, + .flow_sig_id = 3761515520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11840,7 +11840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9a06, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11862,7 +11862,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a886, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11885,7 +11885,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cba2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11908,7 +11908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_da22, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11932,7 +11932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9292, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4833152000, + .flow_sig_id = 4833152000UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11955,7 +11955,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a112, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4833160192, + .flow_sig_id = 4833160192UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11979,7 +11979,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c436, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4835249152, + .flow_sig_id = 4835249152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12003,7 +12003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d2a6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4835257344, + .flow_sig_id = 4835257344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12028,7 +12028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aa86, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5370022912, + .flow_sig_id = 5370022912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12051,7 +12051,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_90d2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5370031104, + .flow_sig_id = 5370031104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12075,7 +12075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dc02, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5372120064, + .flow_sig_id = 5372120064UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12099,7 +12099,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c246, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5372128256, + .flow_sig_id = 5372128256UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12124,7 +12124,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a312, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5906893824, + .flow_sig_id = 5906893824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12148,7 +12148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f192, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5906902016, + .flow_sig_id = 5906902016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12173,7 +12173,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d496, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5908990976, + .flow_sig_id = 5908990976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12198,7 +12198,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_da12, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5908999168, + .flow_sig_id = 5908999168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12224,7 +12224,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b2d6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12247,7 +12247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c156, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12271,7 +12271,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e472, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12295,7 +12295,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f2f2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12320,7 +12320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8a92, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6980635648, + .flow_sig_id = 6980635648UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12344,7 +12344,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d912, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6980643840, + .flow_sig_id = 6980643840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12369,7 +12369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fc36, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6982732800, + .flow_sig_id = 6982732800UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12394,7 +12394,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cab6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6982740992, + .flow_sig_id = 6982740992UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12420,7 +12420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c356, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7517506560, + .flow_sig_id = 7517506560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12444,7 +12444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8892, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7517514752, + .flow_sig_id = 7517514752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12469,7 +12469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f4d2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7519603712, + .flow_sig_id = 7519603712UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12494,7 +12494,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fa16, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7519611904, + .flow_sig_id = 7519611904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12520,7 +12520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_db12, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8054377472, + .flow_sig_id = 8054377472UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12545,7 +12545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8116, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8054385664, + .flow_sig_id = 8054385664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12571,7 +12571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cc96, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8056474624, + .flow_sig_id = 8056474624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12597,7 +12597,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f292, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8056482816, + .flow_sig_id = 8056482816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12624,7 +12624,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e84d, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12645,7 +12645,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a389, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12667,7 +12667,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c0e5, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12689,7 +12689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f16d, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12712,7 +12712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_99d1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12734,7 +12734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ca59, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12757,7 +12757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e8b5, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12780,7 +12780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d93d, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12804,7 +12804,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8521, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12826,7 +12826,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b7a1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12849,7 +12849,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d485, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12872,7 +12872,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c505, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12896,7 +12896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_adf1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12919,7 +12919,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_de71, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12943,7 +12943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fb55, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12967,7 +12967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_edd5, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12992,7 +12992,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8b11, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8591248384, + .flow_sig_id = 8591248384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13014,7 +13014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_bd99, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8591256576, + .flow_sig_id = 8591256576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13037,7 +13037,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_daf1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8593345536, + .flow_sig_id = 8593345536UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13060,7 +13060,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cb79, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8593353728, + .flow_sig_id = 8593353728UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13084,7 +13084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_93d1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10738732032, + .flow_sig_id = 10738732032UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13107,7 +13107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c459, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10738740224, + .flow_sig_id = 10738740224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13131,7 +13131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e2b1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10740829184, + .flow_sig_id = 10740829184UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13155,7 +13155,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d339, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10740837376, + .flow_sig_id = 10740837376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13180,7 +13180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9f31, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12886215680, + .flow_sig_id = 12886215680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13203,7 +13203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b1b1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12886223872, + .flow_sig_id = 12886223872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13227,7 +13227,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ee91, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12888312832, + .flow_sig_id = 12888312832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13251,7 +13251,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_df11, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12888321024, + .flow_sig_id = 12888321024UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13276,7 +13276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a7f1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15033699328, + .flow_sig_id = 15033699328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13300,7 +13300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d871, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15033707520, + .flow_sig_id = 15033707520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13325,7 +13325,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f551, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15035796480, + .flow_sig_id = 15035796480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13350,7 +13350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e7d1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15035804672, + .flow_sig_id = 15035804672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13376,7 +13376,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8e1b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17181182976, + .flow_sig_id = 17181182976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13398,7 +13398,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a083, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17181191168, + .flow_sig_id = 17181191168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13421,7 +13421,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ddff, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17183280128, + .flow_sig_id = 17183280128UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13444,7 +13444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce67, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17183288320, + .flow_sig_id = 17183288320UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13468,7 +13468,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_96db, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19328666624, + .flow_sig_id = 19328666624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13491,7 +13491,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c753, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19328674816, + .flow_sig_id = 19328674816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13515,7 +13515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e5bf, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19330763776, + .flow_sig_id = 19330763776UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13539,7 +13539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d637, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19330771968, + .flow_sig_id = 19330771968UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13564,7 +13564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8233, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21476150272, + .flow_sig_id = 21476150272UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13587,7 +13587,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b4a3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21476158464, + .flow_sig_id = 21476158464UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13611,7 +13611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d197, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21478247424, + .flow_sig_id = 21478247424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13635,7 +13635,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c207, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21478255616, + .flow_sig_id = 21478255616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13660,7 +13660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aaf3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23623633920, + .flow_sig_id = 23623633920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13684,7 +13684,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_db73, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23623642112, + .flow_sig_id = 23623642112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13709,7 +13709,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f857, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23625731072, + .flow_sig_id = 23625731072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13734,7 +13734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ead7, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23625739264, + .flow_sig_id = 23625739264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13760,7 +13760,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_882b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25771117568, + .flow_sig_id = 25771117568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13783,7 +13783,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ba93, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25771125760, + .flow_sig_id = 25771125760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13807,7 +13807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d78b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25773214720, + .flow_sig_id = 25773214720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13831,7 +13831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c873, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25773222912, + .flow_sig_id = 25773222912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13856,7 +13856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_90fb, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27918601216, + .flow_sig_id = 27918601216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13880,7 +13880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c153, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27918609408, + .flow_sig_id = 27918609408UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13905,7 +13905,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fe5b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27920698368, + .flow_sig_id = 27920698368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13930,7 +13930,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d033, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27920706560, + .flow_sig_id = 27920706560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13956,7 +13956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9cc3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30066084864, + .flow_sig_id = 30066084864UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13980,7 +13980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ceb3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30066093056, + .flow_sig_id = 30066093056UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14005,7 +14005,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_eba3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30068182016, + .flow_sig_id = 30068182016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14030,7 +14030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dc13, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30068190208, + .flow_sig_id = 30068190208UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14056,7 +14056,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a493, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32213568512, + .flow_sig_id = 32213568512UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14081,7 +14081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d573, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32213576704, + .flow_sig_id = 32213576704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14107,7 +14107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f273, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32215665664, + .flow_sig_id = 32215665664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14133,7 +14133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cdb3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32215673856, + .flow_sig_id = 32215673856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14160,7 +14160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ff35, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14181,7 +14181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b4f1, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14203,7 +14203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d79d, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14225,7 +14225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e615, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14248,7 +14248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8ea9, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14270,7 +14270,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dd21, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14293,7 +14293,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ffcd, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14316,7 +14316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce45, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14340,7 +14340,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9259, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14362,7 +14362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a0d9, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14385,7 +14385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c3fd, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14408,7 +14408,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d27d, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14432,7 +14432,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ba89, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14455,7 +14455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c909, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14479,7 +14479,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ec2d, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14503,7 +14503,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_faad, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14528,7 +14528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34c6, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14543,7 +14543,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c22, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4100, + .flow_sig_id = 4100UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14559,7 +14559,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cbe, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14575,7 +14575,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_179a, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 6148, + .flow_sig_id = 6148UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14592,7 +14592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59be, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14607,7 +14607,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_515a, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 16388, + .flow_sig_id = 16388UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14623,7 +14623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c72, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14639,7 +14639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_171e, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 24580, + .flow_sig_id = 24580UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14656,7 +14656,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19c8, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14672,7 +14672,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_112c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32772, + .flow_sig_id = 32772UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14689,7 +14689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d68, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14706,7 +14706,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_444c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32836, + .flow_sig_id = 32836UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14724,7 +14724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e8c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14741,7 +14741,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09e0, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14759,7 +14759,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1af0, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14777,7 +14777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15d4, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49220, + .flow_sig_id = 49220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14796,7 +14796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1dd0, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14812,7 +14812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14f4, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131076, + .flow_sig_id = 131076UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14829,7 +14829,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_70b0, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14846,7 +14846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4854, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131140, + .flow_sig_id = 131140UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14864,7 +14864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3dd4, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14881,7 +14881,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34f8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196612, + .flow_sig_id = 196612UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14899,7 +14899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09e8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14917,7 +14917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_008c, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196676, + .flow_sig_id = 196676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14936,7 +14936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34e6, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14952,7 +14952,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c02, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4100, + .flow_sig_id = 4100UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14969,7 +14969,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c9e, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14986,7 +14986,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_17ba, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 6148, + .flow_sig_id = 6148UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15004,7 +15004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_429e, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15021,7 +15021,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5dba, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 12292, + .flow_sig_id = 12292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15039,7 +15039,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a16, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15057,7 +15057,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2532, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 14340, + .flow_sig_id = 14340UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15076,7 +15076,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2da2, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15093,7 +15093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_24fe, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 20484, + .flow_sig_id = 20484UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15111,7 +15111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_355a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15129,7 +15129,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c76, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 22532, + .flow_sig_id = 22532UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15148,7 +15148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13e6, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15166,7 +15166,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7276, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 28676, + .flow_sig_id = 28676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15185,7 +15185,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_42d2, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15204,7 +15204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5dee, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 30724, + .flow_sig_id = 30724UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15224,7 +15224,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59de, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15240,7 +15240,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_513a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 16388, + .flow_sig_id = 16388UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15257,7 +15257,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c12, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15274,7 +15274,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_177e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 24580, + .flow_sig_id = 24580UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15292,7 +15292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e92, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15309,7 +15309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09fe, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15327,7 +15327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c1a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15345,7 +15345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5746, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 57348, + .flow_sig_id = 57348UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15364,7 +15364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_79da, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15381,7 +15381,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7106, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 81924, + .flow_sig_id = 81924UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15399,7 +15399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c1e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15417,7 +15417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_377a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 90116, + .flow_sig_id = 90116UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15436,7 +15436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e9e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15454,7 +15454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29fa, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15473,7 +15473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14d2, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15492,7 +15492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7742, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 122884, + .flow_sig_id = 122884UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15512,7 +15512,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3706, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15528,7 +15528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0fe2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4100, + .flow_sig_id = 4100UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15545,7 +15545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1f7e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15562,7 +15562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_145a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 6148, + .flow_sig_id = 6148UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15580,7 +15580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_417e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15597,7 +15597,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e5a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 12292, + .flow_sig_id = 12292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15615,7 +15615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29f6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15633,7 +15633,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26d2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 14340, + .flow_sig_id = 14340UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15652,7 +15652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e42, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15669,7 +15669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_271e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 20484, + .flow_sig_id = 20484UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15687,7 +15687,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_36ba, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15705,7 +15705,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0f96, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 22532, + .flow_sig_id = 22532UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15724,7 +15724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1006, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15742,7 +15742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7196, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 28676, + .flow_sig_id = 28676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15761,7 +15761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4132, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15780,7 +15780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e0e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 30724, + .flow_sig_id = 30724UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15800,7 +15800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59fe, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15816,7 +15816,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_511a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 16388, + .flow_sig_id = 16388UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15833,7 +15833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c32, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15850,7 +15850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_175e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 24580, + .flow_sig_id = 24580UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15868,7 +15868,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0eb2, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15885,7 +15885,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09de, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15903,7 +15903,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c3a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15921,7 +15921,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5766, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 57348, + .flow_sig_id = 57348UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15940,7 +15940,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_79fa, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15957,7 +15957,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7126, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 81924, + .flow_sig_id = 81924UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15975,7 +15975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c3e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15993,7 +15993,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_375a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 90116, + .flow_sig_id = 90116UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16012,7 +16012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2ebe, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16030,7 +16030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29da, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16049,7 +16049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14f2, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16068,7 +16068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7762, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 122884, + .flow_sig_id = 122884UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16088,7 +16088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19e8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16105,7 +16105,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_110c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32772, + .flow_sig_id = 32772UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16123,7 +16123,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d48, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16141,7 +16141,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_446c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32836, + .flow_sig_id = 32836UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16160,7 +16160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0eac, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16178,7 +16178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09c0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16197,7 +16197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ad0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16216,7 +16216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15f4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49220, + .flow_sig_id = 49220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16236,7 +16236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39ec, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16254,7 +16254,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3100, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98308, + .flow_sig_id = 98308UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16273,7 +16273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0210, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16292,7 +16292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1d34, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98372, + .flow_sig_id = 98372UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16312,7 +16312,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2ea0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16331,7 +16331,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29c4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16351,7 +16351,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ad4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16371,7 +16371,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35e8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114756, + .flow_sig_id = 114756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16392,7 +16392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d80, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16410,7 +16410,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_54a4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163844, + .flow_sig_id = 163844UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16429,7 +16429,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29b4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16448,7 +16448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20c8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163908, + .flow_sig_id = 163908UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16468,7 +16468,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7244, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16487,7 +16487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d98, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180228, + .flow_sig_id = 180228UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16507,7 +16507,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e68, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16527,7 +16527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_598c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180292, + .flow_sig_id = 180292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16548,7 +16548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1248, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16567,7 +16567,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_74d8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229380, + .flow_sig_id = 229380UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16587,7 +16587,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_49a8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16607,7 +16607,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40cc, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229444, + .flow_sig_id = 229444UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16628,7 +16628,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b0c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16648,7 +16648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0220, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245764, + .flow_sig_id = 245764UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16669,7 +16669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1730, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16690,7 +16690,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7980, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245828, + .flow_sig_id = 245828UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16712,7 +16712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1db0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16729,7 +16729,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1494, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131076, + .flow_sig_id = 131076UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16747,7 +16747,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_70d0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16765,7 +16765,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4834, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131140, + .flow_sig_id = 131140UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16784,7 +16784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3db4, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16802,7 +16802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3498, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196612, + .flow_sig_id = 196612UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16821,7 +16821,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0988, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16840,7 +16840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00ec, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196676, + .flow_sig_id = 196676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16860,7 +16860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3f44, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16878,7 +16878,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_36a8, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393220, + .flow_sig_id = 393220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16897,7 +16897,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b58, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16916,7 +16916,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_02bc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393284, + .flow_sig_id = 393284UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16936,7 +16936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f48, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16955,7 +16955,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_56ac, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458756, + .flow_sig_id = 458756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16975,7 +16975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2b5c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16995,7 +16995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2280, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458820, + .flow_sig_id = 458820UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17016,7 +17016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4000, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17034,7 +17034,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5b64, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655364, + .flow_sig_id = 655364UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17053,7 +17053,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2c14, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17072,7 +17072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2778, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655428, + .flow_sig_id = 655428UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17092,7 +17092,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_18f8, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17111,7 +17111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13dc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720900, + .flow_sig_id = 720900UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17131,7 +17131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c18, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17151,7 +17151,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_477c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720964, + .flow_sig_id = 720964UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17172,7 +17172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1a88, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17191,7 +17191,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15ec, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917508, + .flow_sig_id = 917508UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17211,7 +17211,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e28, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17231,7 +17231,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_490c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917572, + .flow_sig_id = 917572UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17252,7 +17252,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a8c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17272,7 +17272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35f0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983044, + .flow_sig_id = 983044UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17293,7 +17293,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06e0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17314,7 +17314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01c4, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983108, + .flow_sig_id = 983108UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17336,7 +17336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1a08, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17353,7 +17353,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_12ec, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32772, + .flow_sig_id = 32772UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17371,7 +17371,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4ea8, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17389,7 +17389,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_478c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32836, + .flow_sig_id = 32836UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17408,7 +17408,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d4c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17426,7 +17426,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0a20, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17445,7 +17445,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1930, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17464,7 +17464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1614, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49220, + .flow_sig_id = 49220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17484,7 +17484,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a0c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17502,7 +17502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_32e0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98308, + .flow_sig_id = 98308UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17521,7 +17521,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01f0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17540,7 +17540,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ed4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98372, + .flow_sig_id = 98372UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17560,7 +17560,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2d40, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17579,7 +17579,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a24, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17599,7 +17599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3934, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17619,7 +17619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3608, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114756, + .flow_sig_id = 114756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17640,7 +17640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e60, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17658,7 +17658,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5744, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163844, + .flow_sig_id = 163844UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17677,7 +17677,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a54, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17696,7 +17696,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2328, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163908, + .flow_sig_id = 163908UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17716,7 +17716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_71a4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17735,7 +17735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e78, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180228, + .flow_sig_id = 180228UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17755,7 +17755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d88, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17775,7 +17775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5a6c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180292, + .flow_sig_id = 180292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17796,7 +17796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_11a8, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17815,7 +17815,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7738, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229380, + .flow_sig_id = 229380UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17835,7 +17835,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4a48, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17855,7 +17855,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_432c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229444, + .flow_sig_id = 229444UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17876,7 +17876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_08ec, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17896,7 +17896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01c0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245764, + .flow_sig_id = 245764UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17917,7 +17917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14d0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17938,7 +17938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7a60, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245828, + .flow_sig_id = 245828UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17960,7 +17960,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1d90, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17977,7 +17977,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14b4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131076, + .flow_sig_id = 131076UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17995,7 +17995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_70f0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18013,7 +18013,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4814, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131140, + .flow_sig_id = 131140UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18032,7 +18032,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d94, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18050,7 +18050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34b8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196612, + .flow_sig_id = 196612UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18069,7 +18069,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09a8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18088,7 +18088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00cc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196676, + .flow_sig_id = 196676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18108,7 +18108,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3f64, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18126,7 +18126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3688, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393220, + .flow_sig_id = 393220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18145,7 +18145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b78, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18164,7 +18164,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_029c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393284, + .flow_sig_id = 393284UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18184,7 +18184,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f68, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18203,7 +18203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_568c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458756, + .flow_sig_id = 458756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18223,7 +18223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2b7c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18243,7 +18243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_22a0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458820, + .flow_sig_id = 458820UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18264,7 +18264,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4020, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18282,7 +18282,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5b44, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655364, + .flow_sig_id = 655364UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18301,7 +18301,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2c34, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18320,7 +18320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2758, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655428, + .flow_sig_id = 655428UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18340,7 +18340,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_18d8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18359,7 +18359,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13fc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720900, + .flow_sig_id = 720900UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18379,7 +18379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c38, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18399,7 +18399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_475c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720964, + .flow_sig_id = 720964UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18420,7 +18420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1aa8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18439,7 +18439,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15cc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917508, + .flow_sig_id = 917508UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18459,7 +18459,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e08, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18479,7 +18479,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_492c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917572, + .flow_sig_id = 917572UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18500,7 +18500,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3aac, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18520,7 +18520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35d0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983044, + .flow_sig_id = 983044UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18541,7 +18541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06c0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18562,7 +18562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01e4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983108, + .flow_sig_id = 983108UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18584,7 +18584,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d32, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18598,7 +18598,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_54aa, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18613,7 +18613,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0686, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18627,7 +18627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_540e, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18642,7 +18642,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e3c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18657,7 +18657,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a20, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18673,7 +18673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46f0, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18689,7 +18689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52e4, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18706,7 +18706,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55e4, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18721,7 +18721,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_21f8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18737,7 +18737,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_75e8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18753,7 +18753,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_41fc, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18770,7 +18770,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d12, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18785,7 +18785,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_548a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18801,7 +18801,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3356, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18817,7 +18817,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ace, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18834,7 +18834,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1a9a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18850,7 +18850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d46, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18867,7 +18867,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2812, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18884,7 +18884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_338a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18902,7 +18902,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06e6, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18917,7 +18917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_546e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18933,7 +18933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46ee, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18949,7 +18949,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d22, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18966,7 +18966,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26e2, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18982,7 +18982,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_746a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18999,7 +18999,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1fa6, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19016,7 +19016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2d2e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19034,7 +19034,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4ef2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19049,7 +19049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_576a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19065,7 +19065,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_30b6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19081,7 +19081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_192e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19098,7 +19098,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_197a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19114,7 +19114,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4ea6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19131,7 +19131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bf2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19148,7 +19148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_306a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19166,7 +19166,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06c6, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19181,7 +19181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_544e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19197,7 +19197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46ce, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19213,7 +19213,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d02, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19230,7 +19230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26c2, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19246,7 +19246,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_744a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19263,7 +19263,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1f86, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19280,7 +19280,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2d0e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19298,7 +19298,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e1c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19314,7 +19314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a00, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19331,7 +19331,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46d0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19348,7 +19348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52c4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19366,7 +19366,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e10, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19383,7 +19383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5a04, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19401,7 +19401,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1f98, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19419,7 +19419,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_72f8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19438,7 +19438,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0a78, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19455,7 +19455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_166c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19473,7 +19473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_233c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19491,7 +19491,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0f20, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19510,7 +19510,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a7c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19528,7 +19528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3660, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19547,7 +19547,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4330, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19566,7 +19566,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2f24, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19586,7 +19586,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5584, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19602,7 +19602,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2198, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19619,7 +19619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7588, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19636,7 +19636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_419c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19654,7 +19654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7758, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19671,7 +19671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_43ac, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19689,7 +19689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c10, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19707,7 +19707,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1864, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19726,7 +19726,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_30c8, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19743,7 +19743,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cdc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19761,7 +19761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_50cc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19779,7 +19779,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d20, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19798,7 +19798,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_529c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19816,7 +19816,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ef0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19835,7 +19835,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_72e0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19854,7 +19854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ef4, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19874,7 +19874,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2dfc, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19890,7 +19890,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39e0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19907,7 +19907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4530, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19924,7 +19924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5124, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19942,7 +19942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4df0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19959,7 +19959,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59e4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19977,7 +19977,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c78, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19995,7 +19995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7118, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20014,7 +20014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0998, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20031,7 +20031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_158c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20049,7 +20049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20dc, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20067,7 +20067,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0cc0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20086,7 +20086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_299c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20104,7 +20104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3580, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20123,7 +20123,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40d0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20142,7 +20142,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2cc4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20162,7 +20162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55a4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20178,7 +20178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_21b8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20195,7 +20195,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_75a8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20212,7 +20212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_41bc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20230,7 +20230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7778, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20247,7 +20247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_438c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20265,7 +20265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c30, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20283,7 +20283,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1844, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20302,7 +20302,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_30e8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20319,7 +20319,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cfc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20337,7 +20337,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_50ec, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20355,7 +20355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d00, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20374,7 +20374,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52bc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20392,7 +20392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ed0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20411,7 +20411,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_72c0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20430,7 +20430,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ed4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20450,7 +20450,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3866, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20465,7 +20465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_381e, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20480,7 +20480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3860, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20496,7 +20496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0454, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20513,7 +20513,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3818, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20529,7 +20529,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_042c, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20546,7 +20546,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3846, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20562,7 +20562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_387e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20578,7 +20578,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ba6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20594,7 +20594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_385e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20610,7 +20610,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3840, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20627,7 +20627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0474, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20645,7 +20645,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3878, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20662,7 +20662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_044c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20680,7 +20680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ba0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20697,7 +20697,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0794, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20715,7 +20715,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3858, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20732,7 +20732,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_046c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index 31a94c14dc..8706e45f28 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 11:11:05 2021 */ +/* date: Thu Sep 9 12:11:08 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -48,7 +48,7 @@ #define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2323 #define ULP_THOR_CLASS_IDENT_LIST_SIZE 38 #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313 -#define ULP_THOR_CLASS_COND_LIST_SIZE 55 +#define ULP_THOR_CLASS_COND_LIST_SIZE 54 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 95205a2421..54bc032b0c 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Aug 25 16:41:37 2021 */ +/* date: Thu Sep 9 12:11:08 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -18,9 +18,9 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .num_tbls = 28, .start_tbl_idx = 0, .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 0, - .cond_nums = 1 } + .cond_nums = 0 } }, /* class_tid: 2, ingress */ [2] = { @@ -29,7 +29,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 28, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 } }, /* class_tid: 3, egress */ @@ -39,7 +39,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 52, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 0 } }, /* class_tid: 4, ingress */ @@ -49,7 +49,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 70, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 } }, /* class_tid: 5, egress */ @@ -59,7 +59,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 91, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 } } }; @@ -74,7 +74,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -96,7 +96,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 5, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -117,7 +117,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -136,7 +136,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -149,7 +149,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -176,7 +176,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -196,7 +196,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -209,7 +209,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 4, + .cond_start_idx = 3, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -228,7 +228,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 5, + .cond_start_idx = 4, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -240,7 +240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 6, + .cond_start_idx = 5, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -259,7 +259,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 7, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -277,7 +277,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 7, + .cond_start_idx = 6, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -307,7 +307,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -328,7 +328,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -349,7 +349,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -368,7 +368,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 6, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -381,7 +381,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 9, + .cond_start_idx = 8, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, @@ -398,7 +398,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 10, + .cond_start_idx = 9, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, @@ -415,7 +415,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 11, + .cond_start_idx = 10, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -443,7 +443,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 13, + .cond_start_idx = 12, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -473,7 +473,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -494,7 +494,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 14, + .cond_start_idx = 13, .cond_nums = 3 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -519,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, + .cond_start_idx = 16, .cond_nums = 3 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -544,7 +544,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 19, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -569,7 +569,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 22, + .cond_start_idx = 21, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -594,7 +594,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 23, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -619,7 +619,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 25, + .cond_start_idx = 24, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -644,7 +644,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 27, + .cond_start_idx = 26, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -670,7 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -691,7 +691,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -710,7 +710,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -723,7 +723,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -750,7 +750,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -770,7 +770,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -783,7 +783,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 30, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -802,7 +802,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, + .cond_start_idx = 30, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -815,7 +815,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -842,7 +842,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -862,7 +862,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -875,7 +875,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, + .cond_start_idx = 32, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -894,7 +894,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 33, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -906,7 +906,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 34, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -925,7 +925,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -943,7 +943,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -973,7 +973,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -994,7 +994,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -1016,7 +1016,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1035,7 +1035,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1048,7 +1048,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 36, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, @@ -1065,7 +1065,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1093,7 +1093,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1114,7 +1114,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1140,7 +1140,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1159,7 +1159,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -1172,7 +1172,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 40, + .cond_start_idx = 39, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1191,7 +1191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 41, + .cond_start_idx = 40, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1203,7 +1203,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 42, + .cond_start_idx = 41, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -1222,7 +1222,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -1240,7 +1240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1270,7 +1270,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1291,7 +1291,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -1312,7 +1312,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1331,7 +1331,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1344,7 +1344,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 44, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, @@ -1361,7 +1361,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 44, + .cond_start_idx = 43, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1389,7 +1389,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1419,7 +1419,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1440,7 +1440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1465,7 +1465,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 47, + .cond_start_idx = 46, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1490,7 +1490,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1517,7 +1517,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, @@ -1536,7 +1536,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1558,7 +1558,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1577,7 +1577,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1590,7 +1590,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1619,7 +1619,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1640,7 +1640,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -1657,7 +1657,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -1676,7 +1676,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -1696,7 +1696,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1716,7 +1716,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -1729,7 +1729,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 50, + .cond_start_idx = 49, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1748,7 +1748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 50, + .cond_start_idx = 49, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1761,7 +1761,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, @@ -1780,7 +1780,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1802,7 +1802,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1821,7 +1821,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1834,7 +1834,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1861,7 +1861,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1882,7 +1882,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1899,7 +1899,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1918,7 +1918,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, @@ -1938,7 +1938,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1960,7 +1960,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1979,7 +1979,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1992,7 +1992,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -2019,7 +2019,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2040,7 +2040,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, @@ -2057,7 +2057,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, @@ -2076,7 +2076,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2095,7 +2095,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF, @@ -2114,7 +2114,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2133,7 +2133,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -2146,7 +2146,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, @@ -2165,7 +2165,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2188,7 +2188,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0, @@ -2207,7 +2207,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, @@ -2227,7 +2227,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2246,7 +2246,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2265,7 +2265,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -2278,7 +2278,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -2306,7 +2306,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, @@ -2323,7 +2323,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -2350,7 +2350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2373,7 +2373,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2391,7 +2391,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -2406,11 +2406,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { }; struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { - /* cond_reject: thor, class_tid: 1 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH - }, /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */ { .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH v4 06/20] net/bnxt: enable wildcard match for ingress flows 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 06/20] net/bnxt: enable wildcard match for ingress flows Ajit Khaparde @ 2021-11-03 13:24 ` Ferruh Yigit 0 siblings, 0 replies; 118+ messages in thread From: Ferruh Yigit @ 2021-11-03 13:24 UTC (permalink / raw) To: Ajit Khaparde, dev Cc: Kishore Padmanabha, Venkat Duvvuru, Michael Baucom, Randy Schacher On 11/3/2021 12:52 AM, Ajit Khaparde wrote: > From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> > > Enabled wildcard match support for ipv4 ingress flows. > > Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> > Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> > Reviewed-by: Michael Baucom <michael.baucom@broadcom.com> > Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> > Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> > --- > .../generic_templates/ulp_template_db_class.c | 1986 ++++++++--------- > .../generic_templates/ulp_template_db_enum.h | 4 +- > .../ulp_template_db_thor_class.c | 251 +-- > 3 files changed, 1118 insertions(+), 1123 deletions(-) > > diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c > index ad3866243d..1d1e6463e0 100644 > --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c > +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c > @@ -3,7 +3,7 @@ > * All rights reserved. > */ > > -/* date: Fri Aug 6 11:15:47 2021 */ > +/* date: Thu Sep 16 13:12:05 2021 */ > > #include "ulp_template_db_enum.h" > #include "ulp_template_db_field.h" > @@ -1016,7 +1016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { > .class_hid = BNXT_ULP_CLASS_HID_55dd, > .class_tid = 1, > .hdr_sig_id = 0, > - .flow_sig_id = 4096, > + .flow_sig_id = 4096UL, Is these changes related? The 90+% of the patch is adding 'UL' to 'flow_sig_id' & '.cond_start_idx' values changed, not sure how much they are related to the IPv4. Should they moved to separate patch? ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 07/20] net/bnxt: support inner IP header for GRE tunnel flows 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (5 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 06/20] net/bnxt: enable wildcard match for ingress flows Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 08/20] net/bnxt: get TruFlow version Ajit Khaparde ` (14 subsequent siblings) 21 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Mike Baucom, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 2945 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> This change allows adding IP header matches for GRE flows that does not specify outer IP header in the flow match pattern. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 7 ++++--- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 40da953f06..605c29223c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -1119,7 +1119,8 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, /* Set the ipv4 header bitmap and computed l3 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) { + ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6) || + ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV4); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1); inner_flag = 1; @@ -1245,7 +1246,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, /* Set the ipv6 header bitmap and computed l3 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) { + ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6) || + ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV6); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1); inner_flag = 1; @@ -2127,7 +2129,6 @@ ulp_rte_vxlan_decap_act_handler(const struct rte_flow_action *action_item BNXT_ULP_ACT_BIT_VXLAN_DECAP); /* Update computational field with tunnel decap info */ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN_DECAP, 1); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1); return BNXT_TF_RC_SUCCESS; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index d3bfb8c12d..7d1bc06a3e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -27,7 +27,7 @@ #define BNXT_ULP_PROTO_HDR_UDP_NUM 4 #define BNXT_ULP_PROTO_HDR_TCP_NUM 9 #define BNXT_ULP_PROTO_HDR_VXLAN_NUM 4 -#define BNXT_ULP_PROTO_HDR_GRE_NUM 6 +#define BNXT_ULP_PROTO_HDR_GRE_NUM 2 #define BNXT_ULP_PROTO_HDR_ICMP_NUM 5 #define BNXT_ULP_PROTO_HDR_MAX 128 #define BNXT_ULP_PROTO_HDR_ENCAP_MAX 64 -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 08/20] net/bnxt: get TruFlow version 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (6 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 07/20] net/bnxt: support inner IP header for GRE tunnel flows Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 09/20] net/bnxt: increase flow scale for Thor Ajit Khaparde ` (13 subsequent siblings) 21 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev Cc: Jay Ding, Venkat Duvvuru, Farah Smith, Randy Schacher, Peter Spreadborough [-- Attachment #1: Type: text/plain, Size: 18919 bytes --] From: Jay Ding <jay.ding@broadcom.com> Implement tf_get_version that returns TruFlow version numbers and CFA resources capbilities. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_core/tf_core.c | 29 ++++++++ drivers/net/bnxt/tf_core/tf_core.h | 75 ++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device.h | 50 ++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p4.c | 65 +++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p4.h | 79 +++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p58.c | 65 +++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p58.h | 87 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_msg.c | 35 ++++++++++ drivers/net/bnxt/tf_core/tf_msg.h | 19 ++++++ 9 files changed, 502 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 936102c804..86dfec0eb4 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1802,3 +1802,32 @@ int tf_get_session_info(struct tf *tfp, return 0; } + +int tf_get_version(struct tf *tfp, + struct tf_get_version_parms *parms) +{ + int rc; + struct tf_dev_info dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_WH && + parms->device_type != TF_DEVICE_TYPE_THOR && + parms->device_type != TF_DEVICE_TYPE_SR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + rc = tf_msg_get_version(parms->bp, &dev, parms); + if (rc) + return rc; + + return 0; +} diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index fb02c2b161..ba9881c69d 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2363,4 +2363,79 @@ struct tf_get_if_tbl_entry_parms { int tf_get_if_tbl_entry(struct tf *tfp, struct tf_get_if_tbl_entry_parms *parms); +/** + * tf_get_version parameters definition. + */ +struct tf_get_version_parms { + /** + * [in] device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] bp + * The pointer to the parent bp struct. This is only used for HWRM + * message passing within the portability layer. The type is struct + * bnxt. + */ + void *bp; + + /* [out] major + * + * Version Major number. + */ + uint8_t major; + + /* [out] minor + * + * Version Minor number. + */ + uint8_t minor; + + /* [out] update + * + * Version Update number. + */ + uint8_t update; + + /** + * [out] dev_ident_caps + * + * fw available identifier resource list + */ + uint32_t dev_ident_caps; + + /** + * [out] dev_tbl_caps + * + * fw available table resource list + */ + uint32_t dev_tbl_caps; + + /** + * [out] dev_tcam_caps + * + * fw available tcam resource list + */ + uint32_t dev_tcam_caps; + + /** + * [out] dev_em_caps + * + * fw available em resource list + */ + uint32_t dev_em_caps; +}; + +/** + * Get tf fw version + * + * Used to retrieve Truflow fw version information. + * + * Returns success or failure code. + */ +int tf_get_version(struct tf *tfp, + struct tf_get_version_parms *parms); #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 9b0c037db0..88bd4515ff 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -6,6 +6,7 @@ #ifndef _TF_DEVICE_H_ #define _TF_DEVICE_H_ +#include "cfa_resource_types.h" #include "tf_core.h" #include "tf_identifier.h" #include "tf_tbl.h" @@ -36,6 +37,21 @@ struct tf_dev_info { const struct tf_dev_ops *ops; }; +/** + * This structure can be used to translate the CFA resource type to TF type. + */ +struct tf_hcapi_resource_map { + /** + * Truflow module type associated with this resource type. + */ + enum tf_module_type module_type; + + /** + * Bitmap of TF sub-type for the element. + */ + uint32_t type_caps; +}; + /** * @page device Device * @@ -1037,6 +1053,34 @@ struct tf_dev_ops { */ uint64_t (*tf_dev_cfa_key_hash)(uint64_t *key_data, uint16_t bitlen); + + /** + * Translate the CFA resource type to Truflow type + * + * [in] hcapi_types + * CFA resource type bitmap + * + * [out] ident_types + * Pointer to identifier type bitmap + * + * [out] tcam_types + * Pointer to tcam type bitmap + * + * [out] tbl_types + * Pointer to table type bitmap + * + * [out] em_types + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_map_hcapi_caps)(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps); }; /** @@ -1047,4 +1091,10 @@ extern const struct tf_dev_ops tf_dev_ops_p4; extern const struct tf_dev_ops tf_dev_ops_p58_init; extern const struct tf_dev_ops tf_dev_ops_p58; +/** + * Supported device resource type mapping structures + */ +extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1]; +extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1]; + #endif /* _TF_DEVICE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 826cd0cdbc..8089785b82 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -271,6 +271,67 @@ static bool tf_dev_p4_is_sram_managed(struct tf *tfp __rte_unused, { return false; } + +/** + * Device specific function that maps the hcapi resource types + * to Truflow type. + * + * [in] hcapi_caps + * CFA resource type bitmap + * + * [out] ident_caps + * Pointer to identifier type bitmap + * + * [out] tcam_caps + * Pointer to tcam type bitmap + * + * [out] tbl_caps + * Pointer to table type bitmap + * + * [out] em_caps + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p4_map_hcapi_caps(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps) +{ + uint32_t i; + + *ident_caps = 0; + *tcam_caps = 0; + *tbl_caps = 0; + *em_caps = 0; + + for (i = 0; i <= CFA_RESOURCE_TYPE_P4_LAST; i++) { + if (hcapi_caps & 1ULL << i) { + switch (tf_hcapi_res_map_p4[i].module_type) { + case TF_MODULE_TYPE_IDENTIFIER: + *ident_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_TABLE: + *tbl_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_TCAM: + *tcam_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_EM: + *em_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + default: + return -EINVAL; + } + } + } + + return 0; +} + /** * Truflow P4 device specific functions */ @@ -321,6 +382,7 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = NULL, + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps }; /** @@ -382,5 +444,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = tf_dev_p4_word_align, - .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash + .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index c1357913f1..e84c0f9e83 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -157,4 +157,83 @@ struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = { TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK }, }; + +const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { + [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW + }, + [CFA_RESOURCE_TYPE_P4_PROF_FUNC] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC + }, + [CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF + }, + [CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW + }, + [CFA_RESOURCE_TYPE_P4_PROF_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM + }, + [CFA_RESOURCE_TYPE_P4_WC_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM + }, + [CFA_RESOURCE_TYPE_P4_SP_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_SP_TCAM + }, + [CFA_RESOURCE_TYPE_P4_NAT_IPV4] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_MODIFY_IPV4 + }, + [CFA_RESOURCE_TYPE_P4_METER_PROF] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF + }, + [CFA_RESOURCE_TYPE_P4_METER] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST + }, + [CFA_RESOURCE_TYPE_P4_MIRROR] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG + }, + [CFA_RESOURCE_TYPE_P4_FULL_ACTION] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_FULL_ACT_RECORD + }, + [CFA_RESOURCE_TYPE_P4_MCG] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MCAST_GROUPS + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_8B + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_16B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_16B + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_64B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_64B + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4 + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6 + }, + [CFA_RESOURCE_TYPE_P4_COUNTER_64B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64 + }, + [CFA_RESOURCE_TYPE_P4_EM_REC] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD + }, + [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_TBL_SCOPE + }, +}; + #endif /* _TF_DEVICE_P4_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 47d7836a58..03e72b90f5 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -45,6 +45,7 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { [CFA_RESOURCE_TYPE_P58_WC_FKB] = "wc_fkb ", [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = "veb ", [CFA_RESOURCE_TYPE_P58_METADATA] = "metadata", + [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = "meter_dc", }; /** @@ -336,6 +337,66 @@ static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused, return 0; } +/** + * Device specific function that maps the hcapi resource types + * to Truflow type. + * + * [in] hcapi_caps + * CFA resource type bitmap + * + * [out] ident_caps + * Pointer to identifier type bitmap + * + * [out] tcam_caps + * Pointer to tcam type bitmap + * + * [out] tbl_caps + * Pointer to table type bitmap + * + * [out] em_caps + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_map_hcapi_caps(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps) +{ + uint32_t i; + + *ident_caps = 0; + *tcam_caps = 0; + *tbl_caps = 0; + *em_caps = 0; + + for (i = 0; i <= CFA_RESOURCE_TYPE_P58_LAST; i++) { + if (hcapi_caps & 1ULL << i) { + switch (tf_hcapi_res_map_p58[i].module_type) { + case TF_MODULE_TYPE_IDENTIFIER: + *ident_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_TABLE: + *tbl_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_TCAM: + *tcam_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_EM: + *em_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + default: + return -EINVAL; + } + } + } + + return 0; +} + /** * Truflow P58 device specific functions */ @@ -386,6 +447,7 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = NULL, + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps }; /** @@ -448,5 +510,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = tf_dev_p58_word_align, - .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash + .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index 3e8759f2df..f6e66936f3 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -209,4 +209,91 @@ struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = { TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_INTERVAL_CFG }, }; + +const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { + [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW + }, + [CFA_RESOURCE_TYPE_P58_PROF_FUNC] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC + }, + [CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF + }, + [CFA_RESOURCE_TYPE_P58_EM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW + }, + [CFA_RESOURCE_TYPE_P58_PROF_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM + }, + [CFA_RESOURCE_TYPE_P58_WC_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM + }, + [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_VEB_TCAM + }, + [CFA_RESOURCE_TYPE_P58_EM_FKB] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_EM_FKB + }, + [CFA_RESOURCE_TYPE_P58_WC_FKB] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_WC_FKB + }, + [CFA_RESOURCE_TYPE_P58_METER_PROF] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF + }, + [CFA_RESOURCE_TYPE_P58_METER] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST + }, + [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_DROP_CNT + }, + [CFA_RESOURCE_TYPE_P58_MIRROR] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG + }, + [CFA_RESOURCE_TYPE_P58_METADATA] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METADATA + }, + /* Resources in bank 1 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_FULL_ACT_RECORD + | 1 << TF_TBL_TYPE_COMPACT_ACT_RECORD + }, + /* Resources in bank 2 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_ACT_ENCAP_8B | + 1 << TF_TBL_TYPE_ACT_ENCAP_16B | + 1 << TF_TBL_TYPE_ACT_ENCAP_32B | + 1 << TF_TBL_TYPE_ACT_ENCAP_64B | + 1 << TF_TBL_TYPE_ACT_MODIFY_8B | + 1 << TF_TBL_TYPE_ACT_MODIFY_16B | + 1 << TF_TBL_TYPE_ACT_MODIFY_32B | + 1 << TF_TBL_TYPE_ACT_MODIFY_64B + + }, + /* Resources in bank 0 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_ACT_SP_SMAC | + 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4 | + 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6 + }, + /* Resources in bank 3 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64 + }, + [CFA_RESOURCE_TYPE_P58_EM_REC] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD + }, +}; #endif /* _TF_DEVICE_P58_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index ea6e2af7ce..25bf026658 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -2306,3 +2306,38 @@ tf_msg_set_if_tbl_entry(struct tf *tfp, return 0; } + +int +tf_msg_get_version(struct bnxt *bp, + struct tf_dev_info *dev, + struct tf_get_version_parms *params) + +{ + int rc; + struct hwrm_tf_version_get_input req = { 0 }; + struct hwrm_tf_version_get_output resp = { 0 }; + struct tfp_send_msg_parms parms = { 0 }; + + /* Populate the request */ + parms.tf_type = HWRM_TF_VERSION_GET, + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(bp, + &parms); + + params->major = resp.major; + params->minor = resp.minor; + params->update = resp.update; + + dev->ops->tf_dev_map_hcapi_caps(resp.dev_caps_cfg, + ¶ms->dev_ident_caps, + ¶ms->dev_tcam_caps, + ¶ms->dev_tbl_caps, + ¶ms->dev_em_caps); + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 718bc2f3b2..08d20cdd7a 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -738,4 +738,23 @@ int tf_msg_set_if_tbl_entry(struct tf *tfp, int tf_msg_get_if_tbl_entry(struct tf *tfp, struct tf_if_tbl_get_parms *params); +/** + * Send get version request to the firmware. + * + * [in] bp + * Pointer to bnxt handle + * + * [in] dev + * Pointer to the associated device + * + * [in/out] parms + * Pointer to the version info parameter + * + * Returns: + * 0 on Success else internal Truflow error + */ +int +tf_msg_get_version(struct bnxt *bp, + struct tf_dev_info *dev, + struct tf_get_version_parms *parms); #endif /* _TF_MSG_H_ */ -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 09/20] net/bnxt: increase flow scale for Thor 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (7 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 08/20] net/bnxt: get TruFlow version Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 10/20] net/bnxt: remove devargs for stats accumulation Ajit Khaparde ` (12 subsequent siblings) 21 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Shahaji Bhosle, Kishore Padmanabha, Venkat Duvvuru, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 8091 bytes --] From: Shahaji Bhosle <sbhosle@broadcom.com> * Updated defines and data types to allow 256 VFRs. * Increased the encap record cache to support 256 to 4K entries. So VxLAN connections can be scaled to 4K entries. Signed-off-by: Shahaji Bhosle <sbhosle@broadcom.com> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/bnxt.h | 6 +++++- drivers/net/bnxt/bnxt_cpr.c | 2 +- drivers/net/bnxt/bnxt_ethdev.c | 18 +++++++++--------- drivers/net/bnxt/bnxt_reps.c | 3 +-- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 2 +- .../generic_templates/ulp_template_db_tbl.c | 8 ++++---- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 6 +++--- 7 files changed, 24 insertions(+), 21 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 4ab9ebd049..54039ba1a9 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -240,7 +240,11 @@ struct bnxt_parent_info { struct bnxt_pf_info { #define BNXT_FIRST_PF_FID 1 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) -#define BNXT_MAX_VF_REPS 64 +#define BNXT_MAX_VF_REPS_WH 64 +#define BNXT_MAX_VF_REPS_TH 256 +#define BNXT_MAX_VF_REPS(bp) \ + (BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_TH : \ + BNXT_MAX_VF_REPS_WH) #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) #define BNXT_FIRST_VF_FID 128 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) diff --git a/drivers/net/bnxt/bnxt_cpr.c b/drivers/net/bnxt/bnxt_cpr.c index 63ff02a198..6bb70d516e 100644 --- a/drivers/net/bnxt/bnxt_cpr.c +++ b/drivers/net/bnxt/bnxt_cpr.c @@ -74,7 +74,7 @@ bnxt_process_default_vnic_change(struct bnxt *bp, BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT; PMD_DRV_LOG(INFO, "async event received vf_id 0x%x\n", vf_fid); - for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) { + for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS(bp); vf_id++) { eth_dev = bp->rep_info[vf_id].vfr_eth_dev; if (!eth_dev) continue; diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 2ab0cf3784..90836401b7 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1172,7 +1172,7 @@ void bnxt_print_link_info(struct rte_eth_dev *eth_dev) struct rte_eth_link *link = ð_dev->data->dev_link; if (link->link_status) - PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", + PMD_DRV_LOG(DEBUG, "Port %d Link Up - speed %u Mbps - %s\n", eth_dev->data->port_id, (uint32_t)link->link_speed, (link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ? @@ -6025,7 +6025,7 @@ static int bnxt_init_rep_info(struct bnxt *bp) return 0; bp->rep_info = rte_zmalloc("bnxt_rep_info", - sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, + sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS(bp), 0); if (!bp->rep_info) { PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); @@ -6067,7 +6067,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, { struct rte_eth_dev *vf_rep_eth_dev; char name[RTE_ETH_NAME_MAX_LEN]; - struct bnxt *backing_bp; + struct bnxt *backing_bp = backing_eth_dev->data->dev_private; + uint16_t max_vf_reps = BNXT_MAX_VF_REPS(backing_bp); + uint16_t num_rep; int i, ret = 0; struct rte_kvargs *kvlist = NULL; @@ -6080,9 +6082,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, return -ENOTSUP; } num_rep = eth_da->nb_representor_ports; - if (num_rep > BNXT_MAX_VF_REPS) { + if (num_rep > max_vf_reps) { PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", - num_rep, BNXT_MAX_VF_REPS); + num_rep, max_vf_reps); return -EINVAL; } @@ -6093,8 +6095,6 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, return -EINVAL; } - backing_bp = backing_eth_dev->data->dev_private; - if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { PMD_DRV_LOG(ERR, "Not a PF or trusted VF. No Representor support\n"); @@ -6114,9 +6114,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, .parent_dev = backing_eth_dev }; - if (representor.vf_id >= BNXT_MAX_VF_REPS) { + if (representor.vf_id >= max_vf_reps) { PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", - representor.vf_id, BNXT_MAX_VF_REPS); + representor.vf_id, max_vf_reps); continue; } diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c index 19da24b41d..60aaa56299 100644 --- a/drivers/net/bnxt/bnxt_reps.c +++ b/drivers/net/bnxt/bnxt_reps.c @@ -210,7 +210,6 @@ int bnxt_representor_init(struct rte_eth_dev *eth_dev, void *params) eth_dev->data->dev_link.link_status = link->link_status; eth_dev->data->dev_link.link_autoneg = link->link_autoneg; - PMD_DRV_LOG(INFO, "calling bnxt_print_link_info\n"); bnxt_print_link_info(eth_dev); PMD_DRV_LOG(INFO, @@ -842,7 +841,7 @@ int bnxt_rep_stop_all(struct bnxt *bp) if (!bp->rep_info) return 0; - for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) { + for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS(bp); vf_id++) { rep_eth_dev = bp->rep_info[vf_id].vfr_eth_dev; if (!rep_eth_dev) continue; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 68f1470c61..960a5a0c93 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -262,7 +262,7 @@ bnxt_ulp_cntxt_ptr2_ulp_flags_get(struct bnxt_ulp_context *ulp_ctx, uint32_t *flags); int32_t -bnxt_ulp_get_df_rule_info(uint8_t port_id, struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_get_df_rule_info(uint16_t port_id, struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_df_rule_info *info); struct bnxt_ulp_vfr_rule_info* diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 5383e2cd70..e43e341927 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 11:11:05 2021 */ +/* date: Thu Sep 16 11:49:55 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -164,12 +164,12 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE", - .result_num_entries = 256, + .name = "EGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE", + .result_num_entries = 4096, .result_num_bytes = 6, .key_num_bytes = 17, .num_buckets = 8, - .hash_tbl_entries = 1024, + .hash_tbl_entries = 16384, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index d8336d164e..01233c0f5e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -441,7 +441,7 @@ void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global) { struct bnxt_ulp_df_rule_info *info; - uint8_t port_id; + uint16_t port_id; if (!BNXT_TRUFLOW_EN(bp) || BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev)) @@ -505,7 +505,7 @@ int32_t bnxt_ulp_create_df_rules(struct bnxt *bp) { struct bnxt_ulp_df_rule_info *info; - uint8_t port_id; + uint16_t port_id; int rc = 0; if (!BNXT_TRUFLOW_EN(bp) || @@ -562,7 +562,7 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev) struct rte_eth_dev *parent_dev = vfr->parent_dev; struct bnxt *bp = parent_dev->data->dev_private; uint16_t vfr_port_id = vfr_ethdev->data->port_id; - uint8_t port_id; + uint16_t port_id; int rc; if (!bp || !BNXT_TRUFLOW_EN(bp)) -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 10/20] net/bnxt: remove devargs for stats accumulation 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (8 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 09/20] net/bnxt: increase flow scale for Thor Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 11/20] net/bnxt: fix clang compiler warnings Ajit Khaparde ` (11 subsequent siblings) 21 siblings, 1 reply; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Mike Baucom [-- Attachment #1: Type: text/plain, Size: 6867 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> The accumulation of flow counters is not determined by the application device arguments anymore. Instead it is now dictated by the platform capabilities whether to do software based accumulation or not. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/bnxt.h | 3 -- drivers/net/bnxt/bnxt_ethdev.c | 53 ---------------------------- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 8 ----- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 1 - drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 12 +++---- 5 files changed, 4 insertions(+), 73 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 54039ba1a9..04b994e5ec 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -718,11 +718,8 @@ struct bnxt { uint32_t flags2; #define BNXT_FLAGS2_PTP_TIMESYNC_ENABLED BIT(0) #define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1) -#define BNXT_FLAGS2_ACCUM_STATS_EN BIT(2) #define BNXT_P5_PTP_TIMESYNC_ENABLED(bp) \ ((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED) -#define BNXT_ACCUM_STATS_EN(bp) \ - ((bp)->flags2 & BNXT_FLAGS2_ACCUM_STATS_EN) uint16_t chip_num; #define CHIP_NUM_58818 0xd818 diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 90836401b7..4413b5d72e 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -87,7 +87,6 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { { .vendor_id = 0, /* sentinel */ }, }; -#define BNXT_DEVARG_ACCUM_STATS "accum-stats" #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" #define BNXT_DEVARG_REPRESENTOR "representor" @@ -101,7 +100,6 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { static const char *const bnxt_dev_args[] = { BNXT_DEVARG_REPRESENTOR, - BNXT_DEVARG_ACCUM_STATS, BNXT_DEVARG_FLOW_XSTAT, BNXT_DEVARG_MAX_NUM_KFLOWS, BNXT_DEVARG_REP_BASED_PF, @@ -114,12 +112,6 @@ static const char *const bnxt_dev_args[] = { NULL }; -/* - * accum-stats == false to disable flow counter accumulation - * accum-stats == true to enable flow counter accumulation - */ -#define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1) - /* * app-id = an non-negative 8-bit number */ @@ -5290,45 +5282,6 @@ static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) return 0; } -static int -bnxt_parse_devarg_accum_stats(__rte_unused const char *key, - const char *value, void *opaque_arg) -{ - struct bnxt *bp = opaque_arg; - unsigned long accum_stats; - char *end = NULL; - - if (!value || !opaque_arg) { - PMD_DRV_LOG(ERR, - "Invalid parameter passed to accum-stats devargs.\n"); - return -EINVAL; - } - - accum_stats = strtoul(value, &end, 10); - if (end == NULL || *end != '\0' || - (accum_stats == ULONG_MAX && errno == ERANGE)) { - PMD_DRV_LOG(ERR, - "Invalid parameter passed to accum-stats devargs.\n"); - return -EINVAL; - } - - if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) { - PMD_DRV_LOG(ERR, - "Invalid value passed to accum-stats devargs.\n"); - return -EINVAL; - } - - if (accum_stats) { - bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN; - PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n"); - } else { - bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN; - PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n"); - } - - return 0; -} - static int bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, const char *value, void *opaque_arg) @@ -5681,12 +5634,6 @@ bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) if (ret) goto err; - /* - * Handler for "accum-stats" devarg. - * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1" - */ - rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS, - bnxt_parse_devarg_accum_stats, bp); /* * Handler for "max_num_kflows" devarg. * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 2ac1a8625f..7deacd1f3e 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1490,14 +1490,6 @@ bnxt_ulp_port_init(struct bnxt *bp) goto jump_to_error; } - /* set the accumulation of the stats */ - if (BNXT_ACCUM_STATS_EN(bp)) - bp->ulp_ctx->cfg_data->accum_stats = true; - - BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init, accum_stats:%d\n", - bp->eth_dev->data->port_id, - bp->ulp_ctx->cfg_data->accum_stats); - /* set the unicast mode */ if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(bp->ulp_ctx, &ulp_flags)) { BNXT_TF_DBG(ERR, "Error in getting ULP context flags\n"); diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 960a5a0c93..17c6898196 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -92,7 +92,6 @@ struct bnxt_ulp_data { #define BNXT_ULP_TUN_ENTRY_INVALID -1 #define BNXT_ULP_MAX_TUN_CACHE_ENTRIES 16 struct bnxt_tun_cache_entry tun_tbl[BNXT_ULP_MAX_TUN_CACHE_ENTRIES]; - bool accum_stats; uint8_t app_id; uint8_t num_shared_clients; struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES]; diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c index d6b4f93d31..92243083b5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c @@ -396,21 +396,17 @@ static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt, return rc; } - /* TBD - Get PKT/BYTE COUNT SHIFT/MASK from Template */ + /* PKT/BYTE COUNT SHIFT/MASK are device specific */ sw_cntr_indx = hw_cntr_id - fc_info->shadow_hw_tbl[dir].start_idx; sw_acc_tbl_entry = &fc_info->sw_acc_tbl[dir][sw_cntr_indx]; + /* Some dpdk applications may accumulate the flow counters while some * may not. In cases where the application is accumulating the counters * the PMD need not do the accumulation itself and viceversa to report * the correct flow counters. */ - if (ctxt->cfg_data->accum_stats) { - sw_acc_tbl_entry->pkt_count += FLOW_CNTR_PKTS(stats, dparms); - sw_acc_tbl_entry->byte_count += FLOW_CNTR_BYTES(stats, dparms); - } else { - sw_acc_tbl_entry->pkt_count = FLOW_CNTR_PKTS(stats, dparms); - sw_acc_tbl_entry->byte_count = FLOW_CNTR_BYTES(stats, dparms); - } + sw_acc_tbl_entry->pkt_count += FLOW_CNTR_PKTS(stats, dparms); + sw_acc_tbl_entry->byte_count += FLOW_CNTR_BYTES(stats, dparms); /* Update the parent counters if it is child flow */ if (sw_acc_tbl_entry->pc_flow_idx & FLOW_CNTR_PC_FLOW_VALID) { -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH v4 10/20] net/bnxt: remove devargs for stats accumulation 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 10/20] net/bnxt: remove devargs for stats accumulation Ajit Khaparde @ 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 13:35 ` Ajit Khaparde 0 siblings, 1 reply; 118+ messages in thread From: Ferruh Yigit @ 2021-11-03 13:24 UTC (permalink / raw) To: Ajit Khaparde, dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Mike Baucom On 11/3/2021 12:52 AM, Ajit Khaparde wrote: > From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> > > The accumulation of flow counters is not determined by the > application device arguments anymore. Instead it is now dictated by > the platform capabilities whether to do software based accumulation or not. > > Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> > Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> > Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> > Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> <...> > @@ -87,7 +87,6 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { > { .vendor_id = 0, /* sentinel */ }, > }; > > -#define BNXT_DEVARG_ACCUM_STATS "accum-stats" > #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" > #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" > #define BNXT_DEVARG_REPRESENTOR "representor" Hi Ajit, Not for this patch, but I recognized that runtime devargs for the driver is not documented at all. Can you please have a separate patch to document them in bnxt.rst? ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH v4 10/20] net/bnxt: remove devargs for stats accumulation 2021-11-03 13:24 ` Ferruh Yigit @ 2021-11-03 13:35 ` Ajit Khaparde 0 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 13:35 UTC (permalink / raw) To: Ferruh Yigit; +Cc: dpdk-dev, Kishore Padmanabha, Venkat Duvvuru, Mike Baucom On Wed, Nov 3, 2021 at 6:24 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote: > > On 11/3/2021 12:52 AM, Ajit Khaparde wrote: > > From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> > > > > The accumulation of flow counters is not determined by the > > application device arguments anymore. Instead it is now dictated by > > the platform capabilities whether to do software based accumulation or not. > > > > Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> > > Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> > > Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> > > Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> > > <...> > > > @@ -87,7 +87,6 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { > > { .vendor_id = 0, /* sentinel */ }, > > }; > > > > -#define BNXT_DEVARG_ACCUM_STATS "accum-stats" > > #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" > > #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" > > #define BNXT_DEVARG_REPRESENTOR "representor" > > Hi Ajit, > > Not for this patch, but I recognized that runtime devargs for the driver > is not documented at all. > > Can you please have a separate patch to document them in bnxt.rst? Hi Freeuh, Yes. I am working on that. ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 11/20] net/bnxt: fix clang compiler warnings 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (9 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 10/20] net/bnxt: remove devargs for stats accumulation Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 12/20] net/bnxt: update log messages in TruFlow path Ajit Khaparde ` (10 subsequent siblings) 21 siblings, 1 reply; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Shahaji Bhosle, stable, Venkat Duvvuru [-- Attachment #1: Type: text/plain, Size: 1959 bytes --] From: Shahaji Bhosle <sbhosle@broadcom.com> Typecast flow_item type, action_item type and the ENUMs to uint32_t before comparing. Fixes: 53a0d4f7663 ("net/bnxt: support flow API item parsing") Cc: stable@dpdk.org Bugzilla ID: 821 Signed-off-by: Shahaji Bhosle <sbhosle@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 605c29223c..d21c088d59 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -137,10 +137,10 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[], /* Parse all the items in the pattern */ while (item && item->type != RTE_FLOW_ITEM_TYPE_END) { - if (item->type >= (uint32_t) + if (item->type >= (typeof(item->type)) BNXT_RTE_FLOW_ITEM_TYPE_END) { if (item->type >= - (uint32_t)BNXT_RTE_FLOW_ITEM_TYPE_LAST) + (typeof(item->type))BNXT_RTE_FLOW_ITEM_TYPE_LAST) goto hdr_parser_error; /* get the header information */ hdr_info = &ulp_vendor_hdr_info[item->type - @@ -186,9 +186,9 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[], /* Parse all the items in the pattern */ while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) { if (action_item->type >= - (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_END) { + (typeof(action_item->type))BNXT_RTE_FLOW_ACTION_TYPE_END) { if (action_item->type >= - (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_LAST) + (typeof(action_item->type))BNXT_RTE_FLOW_ACTION_TYPE_LAST) goto act_parser_error; /* get the header information from bnxt actinfo table */ hdr_info = &ulp_vendor_act_info[action_item->type - -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH v4 11/20] net/bnxt: fix clang compiler warnings 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 11/20] net/bnxt: fix clang compiler warnings Ajit Khaparde @ 2021-11-03 13:24 ` Ferruh Yigit 0 siblings, 0 replies; 118+ messages in thread From: Ferruh Yigit @ 2021-11-03 13:24 UTC (permalink / raw) To: Ajit Khaparde, dev; +Cc: Shahaji Bhosle, stable, Venkat Duvvuru On 11/3/2021 12:52 AM, Ajit Khaparde wrote: > From: Shahaji Bhosle <sbhosle@broadcom.com> > > Typecast flow_item type, action_item type and the ENUMs to uint32_t > before comparing. > > Fixes: 53a0d4f7663 ("net/bnxt: support flow API item parsing") > Cc: stable@dpdk.org Hi Ajit, Is above Fixes commit correct? It is from v20.05. As far as I can see the error comes from: Fixes: bdf4a3c6316b ("net/bnxt: support tunnel offload") if that is correct, stable tag is not needed. > > Bugzilla ID: 821 Can you please move the tag above 'Fixes' line? > Signed-off-by: Shahaji Bhosle <sbhosle@broadcom.com> > Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> > Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> <...> ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 12/20] net/bnxt: update log messages in TruFlow path 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (10 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 11/20] net/bnxt: fix clang compiler warnings Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 13/20] net/bnxt: add support for socket direct feature Ajit Khaparde ` (9 subsequent siblings) 21 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Shahaji Bhosle, Mike Baucom [-- Attachment #1: Type: text/plain, Size: 4081 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Some of the error level log messages are made debug level messages. When Truflow is not enabled then Truflow init error messages are moved to debug level instead. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 24 ++++++++++++------------ drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 7deacd1f3e..21f71d6445 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1396,16 +1396,16 @@ bnxt_ulp_port_init(struct bnxt *bp) uint32_t ulp_flags; int32_t rc = 0; - if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { - BNXT_TF_DBG(ERR, - "Skip ulp init for port: %d, not a TVF or PF\n", + if (!BNXT_TRUFLOW_EN(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ulp init for port: %d, TF is not enabled\n", bp->eth_dev->data->port_id); return rc; } - if (!BNXT_TRUFLOW_EN(bp)) { - BNXT_TF_DBG(ERR, - "Skip ulp init for port: %d, truflow is not enabled\n", + if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ulp init for port: %d, not a TVF or PF\n", bp->eth_dev->data->port_id); return rc; } @@ -1520,16 +1520,16 @@ bnxt_ulp_port_deinit(struct bnxt *bp) struct rte_pci_device *pci_dev; struct rte_pci_addr *pci_addr; - if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { - BNXT_TF_DBG(ERR, - "Skip ULP deinit port:%d, not a TVF or PF\n", + if (!BNXT_TRUFLOW_EN(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ULP deinit for port:%d, TF is not enabled\n", bp->eth_dev->data->port_id); return; } - if (!BNXT_TRUFLOW_EN(bp)) { - BNXT_TF_DBG(ERR, - "Skip ULP deinit for port:%d, truflow is not enabled\n", + if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ULP deinit port:%d, not a TVF or PF\n", bp->eth_dev->data->port_id); return; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index 01233c0f5e..8790d7ac0d 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -323,7 +323,7 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev, ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); if (!ulp_ctx) { BNXT_TF_DBG(ERR, - "ULP context is not initialized. Failed to create dflt flow.\n"); + "ULP is not init'ed. Fail to create dflt flow.\n"); return -EINVAL; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c index 79dc869e64..9968311c44 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c @@ -470,7 +470,7 @@ ulp_flow_db_init(struct bnxt_ulp_context *ulp_ctxt) } /* All good so return. */ - BNXT_TF_DBG(INFO, "FlowDB initialized with %d flows.\n", + BNXT_TF_DBG(DEBUG, "FlowDB initialized with %d flows.\n", flow_tbl->num_flows); return 0; error_free: diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c index 271520e1d3..9dffaef73b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c @@ -116,7 +116,7 @@ ulp_mark_db_init(struct bnxt_ulp_context *ctxt) mark_tbl->gfid_mask = (mark_tbl->gfid_num_entries / 2) - 1; mark_tbl->gfid_type_bit = (mark_tbl->gfid_num_entries / 2); - BNXT_TF_DBG(DEBUG, "GFID Max = 0x%08x\nGFID MASK = 0x%08x\n", + BNXT_TF_DBG(DEBUG, "GFID Max = 0x%08x GFID MASK = 0x%08x\n", mark_tbl->gfid_num_entries - 1, mark_tbl->gfid_mask); -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 13/20] net/bnxt: add support for socket direct feature 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (11 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 12/20] net/bnxt: update log messages in TruFlow path Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 14/20] net/bnxt: modify VF representor alloc sequence Ajit Khaparde ` (8 subsequent siblings) 21 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Mike Baucom, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 394315 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Added support for socket direct feature. This feature allows to ignore the incoming interface and use other fields in the packet to identify the flow and forward. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 5 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 23 +- .../generic_templates/ulp_template_db_enum.h | 71 +- .../generic_templates/ulp_template_db_tbl.c | 3917 +++++++++++++---- .../ulp_template_db_thor_act.c | 150 +- .../ulp_template_db_thor_class.c | 660 +-- .../ulp_template_db_wh_plus_act.c | 242 +- .../ulp_template_db_wh_plus_class.c | 222 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 5 + 9 files changed, 3701 insertions(+), 1594 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 21f71d6445..b64279710b 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -337,9 +337,12 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, BNXT_ULP_APP_UNICAST_ONLY; if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) { /* Enable socket direction only if MR is enabled in fw*/ - if (BNXT_MULTIROOT_EN(bp)) + if (BNXT_MULTIROOT_EN(bp)) { ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_APP_SOCKET_DIRECT; + BNXT_TF_DBG(DEBUG, + "Socket Direct feature is enabled"); + } } } if (!found) { diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 272195f6a2..55885d1b8c 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -133,8 +133,27 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, } /* Update the socket direct flag */ - if (ULP_SOCKET_DIRECT_IS_ENABLED(ulp_flags)) - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT, 1); + if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_SVIF_IGNORE)) { + uint32_t ifindex; + uint16_t vport; + + /* Get the port db ifindex */ + if (ulp_port_db_dev_port_to_ulp_index(params->ulp_ctx, + params->port_id, + &ifindex)) { + BNXT_TF_DBG(ERR, "Invalid port id %u\n", + params->port_id); + return; + } + /* Update the phy port of the other interface */ + if (ulp_port_db_vport_get(params->ulp_ctx, ifindex, &vport)) { + BNXT_TF_DBG(ERR, "Invalid port if index %u\n", ifindex); + return; + } + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT_VPORT, + (vport == 1) ? 2 : 1); + } } /* Function to create the rte flow. */ diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index 8706e45f28..c01ae1601d 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,15 +3,15 @@ * All rights reserved. */ -/* date: Thu Sep 9 12:11:08 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ -#define BNXT_ULP_REGFILE_MAX_SZ 42 +#define BNXT_ULP_REGFILE_MAX_SZ 46 #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 -#define BNXT_ULP_GEN_TBL_MAX_SZ 16 +#define BNXT_ULP_GEN_TBL_MAX_SZ 18 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 65536 #define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 993 #define BNXT_ULP_CLASS_HID_LOW_PRIME 6701 @@ -26,11 +26,11 @@ #define BNXT_ULP_ACT_HID_SHFTR 27 #define BNXT_ULP_ACT_HID_SHFTL 26 #define BNXT_ULP_ACT_HID_MASK 2047 -#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8 -#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110 -#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50 -#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 277 -#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8 +#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 16 +#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 132 +#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 140 +#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 409 +#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 12 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 @@ -114,7 +114,8 @@ enum bnxt_ulp_hdr_bit { BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000, BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000, BNXT_ULP_HDR_BIT_F2 = 0x0000000000080000, - BNXT_ULP_HDR_BIT_LAST = 0x0000000000100000 + BNXT_ULP_HDR_BIT_SVIF_IGNORE = 0x0000000000100000, + BNXT_ULP_HDR_BIT_LAST = 0x0000000000200000 }; enum bnxt_ulp_accept_opc { @@ -212,7 +213,8 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72, BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73, BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74, - BNXT_ULP_CF_IDX_LAST = 75 + BNXT_ULP_CF_IDX_SOCKET_DIRECT_VPORT = 75, + BNXT_ULP_CF_IDX_LAST = 76 }; enum bnxt_ulp_cond_list_opc { @@ -427,21 +429,31 @@ enum bnxt_ulp_glb_rf_idx { BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 37, BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 38, BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 39, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 40, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 41, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 42, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 43, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 44, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 45, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 46, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 47, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 48, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 49, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 50, - BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 51, - BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 52, - BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 53, - BNXT_ULP_GLB_RF_IDX_LAST = 54 + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3 = 40, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 41, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 42, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 43, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 44, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 45, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 46, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 47, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3 = 48, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4 = 49, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5 = 50, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6 = 51, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7 = 52, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8 = 53, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9 = 54, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10 = 55, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 56, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 57, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 58, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 59, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2 = 60, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 61, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 62, + BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 63, + BNXT_ULP_GLB_RF_IDX_LAST = 64 }; enum bnxt_ulp_hdr_type { @@ -555,7 +567,11 @@ enum bnxt_ulp_rf_idx { BNXT_ULP_RF_IDX_PHY_PORT = 39, BNXT_ULP_RF_IDX_METADATA_PROF = 40, BNXT_ULP_RF_IDX_MODIFY_PTR = 41, - BNXT_ULP_RF_IDX_LAST = 42 + BNXT_ULP_RF_IDX_SOCK_DIR_SVIF = 42, + BNXT_ULP_RF_IDX_SOCK_DIR_PARIF = 43, + BNXT_ULP_RF_IDX_SOCK_DIR_ACT_PTR = 44, + BNXT_ULP_RF_IDX_SOCK_DIR_PARENT_MAC = 45, + BNXT_ULP_RF_IDX_LAST = 46 }; enum bnxt_ulp_shared_session { @@ -627,7 +643,8 @@ enum bnxt_ulp_resource_sub_type { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE = 6, - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7 + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE = 8 }; enum bnxt_ulp_act_prop_sz { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index e43e341927..d5aea4d456 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 16 11:49:55 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -171,6 +171,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { .num_buckets = 8, .hash_tbl_entries = 16384, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GEN_TABLE_SOCKET_DIRECT_CACHE", + .result_num_entries = 16, + .result_num_bytes = 14, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GEN_TABLE_SOCKET_DIRECT_CACHE", + .result_num_entries = 16, + .result_num_bytes = 14, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; @@ -371,6 +391,33 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY | + BNXT_ULP_APP_CAP_SOCKET_DIRECT + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY } }; @@ -439,6 +486,70 @@ struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 1024 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 128 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 1024 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 128 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 1024 } }; @@ -472,6 +583,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -560,6 +679,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -624,14 +751,6 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, - .direction = TF_DIR_RX - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX @@ -672,6 +791,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -760,6 +887,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -824,14 +959,6 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, - .direction = TF_DIR_RX - }, - { - .app_id = 2, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX @@ -843,509 +970,717 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, .direction = TF_DIR_RX - } -}; - -/* List of global tf resources required to be reserved per app/device */ -struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { + }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX + }, + { + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_METADATA, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0, - .direction = TF_DIR_TX + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, .direction = TF_DIR_RX }, { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, + .direction = TF_DIR_RX + }, + { + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, + .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX + } +}; + +/* List of global tf resources required to be reserved per app/device */ +struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { + { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1353,7 +1688,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1361,7 +1696,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, @@ -1369,7 +1704,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1377,7 +1712,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1385,7 +1720,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1393,7 +1728,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1401,7 +1736,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1409,7 +1744,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, @@ -1417,7 +1752,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1425,7 +1760,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1433,7 +1768,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1441,7 +1776,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, @@ -1449,7 +1784,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1457,7 +1792,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1465,7 +1800,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1473,7 +1808,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1481,7 +1816,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1489,7 +1824,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1497,7 +1832,15 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1505,7 +1848,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1513,7 +1856,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1521,7 +1864,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1529,7 +1872,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1537,7 +1880,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1545,23 +1888,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6, - .direction = TF_DIR_RX - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7, - .direction = TF_DIR_RX - }, - { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1569,7 +1896,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1577,7 +1904,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1585,7 +1912,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1593,7 +1920,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1601,7 +1928,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1609,7 +1936,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1617,7 +1944,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1625,7 +1952,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1633,427 +1960,2171 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .direction = TF_DIR_TX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_METADATA, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0, + .direction = TF_DIR_TX + }, + { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + } +}; + +/* List of tf resources required to be reserved per app/device */ +struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 422 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 191 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 6912 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 1023 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 511 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 15 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, + .count = 255 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 422 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 960 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 88 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 13168 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 292 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 148 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 191 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 6912 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 1023 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 511 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 223 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 255 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 488 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, + .count = 511 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 292 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 144 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 960 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 928 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 15232 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 5 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 31 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 2048 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 64 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 128 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4096 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 16384 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 5 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 2048 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 100 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 128 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4096 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 16384 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_METADATA, + .count = 1 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 16 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 528 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 256 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 512 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 256 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1, - .direction = TF_DIR_RX + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 }, { - .app_id = 3, + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2, - .direction = TF_DIR_RX + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 }, { - .app_id = 3, + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3, - .direction = TF_DIR_RX - } -}; - -/* List of tf resources required to be reserved per app/device */ -struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 6912 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 511 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 15 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, - .count = 255 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 88 + .count = 64 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 13168 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 148 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 6912 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 511 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 223 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 255 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 488 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .count = 511 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 144 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 928 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 15232 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 272 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2061,15 +4132,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 32 + .count = 16 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2077,759 +4148,815 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 528 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 8192 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 5 + .count = 256 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 31 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 2048 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 64 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 272 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4096 + .count = 512 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 16384 + .count = 1024 }, { - .app_id = 0, + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 272 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 512 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 8192 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 5 + .count = 256 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 2048 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 100 + .count = 4 }, { - .app_id = 0, + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 272 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4096 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 16384 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_METADATA, - .count = 1 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 422 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 4 + .count = 191 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 4 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 4 + .count = 192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 128 + .count = 8192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 128 + .count = 7168 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 4 + .count = 1023 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 4 + .count = 511 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 4 + .count = 15 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, - .count = 4 + .count = 255 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 422 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 960 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 88 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 13168 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 292 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 148 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 4 + .count = 191 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 4 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 4 + .count = 192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 128 + .count = 8192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 128 + .count = 7168 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 4 + .count = 1023 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 4 + .count = 511 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 4 + .count = 223 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 4 + .count = 255 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 4 + .count = 488 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .count = 4 + .count = 511 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 292 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 144 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 960 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 928 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 15232 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 16 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 528 + .count = 4096 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 256 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, + .count = 1024 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 2048 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 6144 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 4 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 4 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 4 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 512 + .count = 4096 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 256 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, + .count = 1024 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 2048 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 6144 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2837,7 +4964,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2845,7 +4972,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2853,7 +4980,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2861,7 +4988,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2869,7 +4996,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2877,7 +5004,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2885,7 +5012,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2893,7 +5020,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2901,7 +5028,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2909,7 +5036,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2917,7 +5044,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -2925,7 +5052,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -2933,7 +5060,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -2941,15 +5068,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 64 + .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -2957,7 +5084,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2965,7 +5092,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2973,7 +5100,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2981,7 +5108,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2989,7 +5116,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2997,7 +5124,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3005,7 +5132,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3013,7 +5140,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3021,7 +5148,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3029,7 +5156,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3037,7 +5164,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3045,7 +5172,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3053,7 +5180,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3061,7 +5188,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3069,7 +5196,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3077,7 +5204,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3085,7 +5212,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3093,7 +5220,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -3101,7 +5228,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3109,7 +5236,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3117,7 +5244,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3125,7 +5252,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3133,7 +5260,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 16 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3141,7 +5268,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3149,7 +5276,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 528 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3157,7 +5284,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 256 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3165,7 +5292,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3173,7 +5300,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3181,7 +5308,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3189,7 +5316,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3197,7 +5324,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3205,7 +5332,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3213,15 +5340,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 512 + .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -3229,7 +5356,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3237,7 +5364,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3245,7 +5372,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3253,7 +5380,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3261,7 +5388,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3269,7 +5396,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3277,7 +5404,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 512 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3285,7 +5412,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 256 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3293,7 +5420,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3301,7 +5428,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3309,7 +5436,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3317,7 +5444,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3325,7 +5452,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3333,7 +5460,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3341,7 +5468,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3349,7 +5476,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -3357,596 +5484,532 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 7168 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 511 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 15 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, - .count = 255 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 88 + .count = 64 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 13168 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 148 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 7168 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 511 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 223 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 255 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 488 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .count = 511 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 144 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 928 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 15232 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 16 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 4096 + .count = 528 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 256 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 2048 + .count = 512 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 6144 + .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 128 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 128 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 4096 + .count = 512 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 256 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 2048 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 6144 + .count = 1024 } }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c index e49c1151d3..8869ab1c33 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Aug 17 12:16:42 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -1575,8 +1575,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}, + (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1607,7 +1607,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, + ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_DECAP_FUNC_NONE} @@ -1666,8 +1666,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1692,7 +1692,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, + ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1747,7 +1747,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, + ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_DECAP_FUNC_NONE} @@ -1806,8 +1806,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1832,7 +1832,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, + ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2149,7 +2149,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2168,7 +2168,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2187,7 +2187,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2206,7 +2206,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2373,8 +2373,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2393,8 +2393,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2413,8 +2413,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2433,8 +2433,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 3, , table: mod_record.ing_no_ttl */ @@ -2526,7 +2526,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2545,7 +2545,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2564,7 +2564,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2583,7 +2583,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2737,8 +2737,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2757,8 +2757,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2777,8 +2777,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2797,8 +2797,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 3, , table: int_full_act_record.0 */ @@ -3593,7 +3593,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3612,7 +3612,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3631,7 +3631,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3650,7 +3650,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3817,8 +3817,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -3837,8 +3837,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -3857,8 +3857,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -3877,8 +3877,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 5, , table: mod_record.ing_no_ttl */ @@ -3970,7 +3970,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3989,7 +3989,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4008,7 +4008,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4027,7 +4027,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4181,8 +4181,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4201,8 +4201,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4221,8 +4221,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4241,8 +4241,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 5, , table: int_full_act_record.0 */ @@ -4526,8 +4526,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4546,8 +4546,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4566,8 +4566,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4586,8 +4586,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4833,8 +4833,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4853,8 +4853,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4873,8 +4873,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4893,8 +4893,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 54bc032b0c..2d464fb7c4 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 12:11:08 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -3232,8 +3232,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -3302,7 +3302,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -3492,7 +3492,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -3871,8 +3871,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -3987,8 +3987,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -4821,8 +4821,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -4835,8 +4835,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -4959,8 +4959,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -4973,8 +4973,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5037,8 +5037,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -5051,8 +5051,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5091,8 +5091,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -5105,8 +5105,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5153,8 +5153,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5358,8 +5358,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5383,8 +5383,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5542,8 +5542,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -5612,7 +5612,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -5659,7 +5659,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_VALID_YES}, + ULP_THOR_SYM_L4_HDR_VALID_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_VALID_IGNORE} @@ -5749,7 +5749,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L3_HDR_TYPE_IPV6} @@ -5830,7 +5830,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -6209,8 +6209,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -6734,7 +6734,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L3_HDR_TYPE_IPV6} @@ -6815,7 +6815,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_TL2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_TL2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_TL2_VTAG_PRESENT_NO} @@ -6900,8 +6900,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -7018,8 +7018,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -7852,8 +7852,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -7866,8 +7866,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7990,8 +7990,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8004,8 +8004,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8056,8 +8056,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8070,8 +8070,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8110,8 +8110,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8124,8 +8124,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8187,8 +8187,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8383,8 +8383,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8397,8 +8397,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8413,8 +8413,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8427,8 +8427,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9359,8 +9359,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9373,8 +9373,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9497,8 +9497,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9511,8 +9511,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9575,8 +9575,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9589,8 +9589,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9629,8 +9629,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9643,8 +9643,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9694,8 +9694,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9901,8 +9901,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9928,8 +9928,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10860,8 +10860,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -10874,8 +10874,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10998,8 +10998,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -11012,8 +11012,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -11064,8 +11064,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -11078,8 +11078,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -11118,8 +11118,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -11132,8 +11132,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -11195,8 +11195,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12335,8 +12335,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12349,8 +12349,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12473,8 +12473,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12487,8 +12487,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12551,8 +12551,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12565,8 +12565,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12605,8 +12605,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12619,8 +12619,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12670,8 +12670,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -13810,8 +13810,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -13824,8 +13824,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -13948,8 +13948,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -13962,8 +13962,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14712,8 +14712,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -14726,8 +14726,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14778,8 +14778,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -14792,8 +14792,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14832,8 +14832,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -14846,8 +14846,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14909,8 +14909,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -15093,8 +15093,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -15107,8 +15107,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -15123,8 +15123,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -15137,8 +15137,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -15345,8 +15345,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -15359,8 +15359,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16219,8 +16219,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16233,8 +16233,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16297,8 +16297,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16311,8 +16311,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16351,8 +16351,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16365,8 +16365,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16416,8 +16416,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16600,8 +16600,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16614,8 +16614,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16630,8 +16630,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16644,8 +16644,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16852,8 +16852,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16866,8 +16866,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -18434,7 +18434,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_I_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -19848,8 +19848,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -19862,8 +19862,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -19970,8 +19970,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -19984,8 +19984,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20168,8 +20168,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -20182,8 +20182,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20222,8 +20222,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -20236,8 +20236,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20284,8 +20284,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20489,8 +20489,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20514,8 +20514,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -22120,8 +22120,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22134,8 +22134,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22242,8 +22242,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22256,8 +22256,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22428,8 +22428,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22442,8 +22442,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22482,8 +22482,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22496,8 +22496,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22559,8 +22559,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22755,8 +22755,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22769,8 +22769,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22785,8 +22785,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22799,8 +22799,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -23041,7 +23041,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -23231,7 +23231,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -24532,8 +24532,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24546,8 +24546,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24562,8 +24562,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24576,8 +24576,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24700,8 +24700,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24714,8 +24714,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24778,8 +24778,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24792,8 +24792,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24832,8 +24832,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24846,8 +24846,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24894,8 +24894,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -25099,8 +25099,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -25124,8 +25124,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -25345,7 +25345,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -25469,7 +25469,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L3_HDR_TYPE_IPV6} @@ -25548,7 +25548,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -26210,7 +26210,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -27511,8 +27511,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -27525,8 +27525,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -27541,8 +27541,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -27555,8 +27555,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -27679,8 +27679,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -27693,8 +27693,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -27856,8 +27856,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -28052,8 +28052,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -28066,8 +28066,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -28082,8 +28082,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -28096,8 +28096,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29016,8 +29016,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -29030,8 +29030,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29046,8 +29046,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -29060,8 +29060,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29184,8 +29184,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -29198,8 +29198,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29361,8 +29361,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -30489,8 +30489,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -30503,8 +30503,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -30519,8 +30519,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -30533,8 +30533,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -30657,8 +30657,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -30671,8 +30671,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -34679,8 +34679,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -35206,8 +35206,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -36920,8 +36920,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}, + (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, @@ -36991,8 +36991,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff}, + (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff, @@ -38986,8 +38986,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}, + (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff, @@ -39570,8 +39570,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c index 4a2d201c2d..16a921e6c8 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Aug 25 14:37:06 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -1210,8 +1210,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1239,8 +1239,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1295,7 +1295,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_NONE} @@ -1346,8 +1346,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1481,8 +1481,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1510,8 +1510,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1566,7 +1566,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_NONE} @@ -1893,7 +1893,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1} + 1} }, { .description = "drop", @@ -2088,7 +2088,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1} + 1} }, { .description = "drop", @@ -2222,8 +2222,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2_POST, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - (1 >> 8) & 0xff, - 1 & 0xff} + (1 >> 8) & 0xff, + 1 & 0xff} }, /* act_tid: 3, , table: int_flow_counter_tbl.0 */ { @@ -2418,8 +2418,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2447,8 +2447,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2503,7 +2503,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -2662,8 +2662,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2691,8 +2691,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2747,7 +2747,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -3853,8 +3853,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3882,8 +3882,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3938,7 +3938,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -4097,8 +4097,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4126,8 +4126,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4182,7 +4182,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -4415,8 +4415,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4435,8 +4435,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4455,8 +4455,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4475,8 +4475,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4495,8 +4495,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4515,8 +4515,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4535,8 +4535,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4555,8 +4555,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4575,8 +4575,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4595,8 +4595,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4615,8 +4615,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4635,8 +4635,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4672,8 +4672,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4692,8 +4692,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4712,8 +4712,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4732,8 +4732,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4752,8 +4752,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4772,8 +4772,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4792,8 +4792,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4812,8 +4812,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4832,8 +4832,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 6, , table: int_full_act_record.0 */ @@ -5264,8 +5264,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5284,8 +5284,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5304,8 +5304,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5324,8 +5324,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5344,8 +5344,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5364,8 +5364,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5384,8 +5384,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5404,8 +5404,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5424,8 +5424,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5444,8 +5444,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5464,8 +5464,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5484,8 +5484,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5521,8 +5521,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5541,8 +5541,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5561,8 +5561,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5581,8 +5581,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5601,8 +5601,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5621,8 +5621,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5641,8 +5641,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5661,8 +5661,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5681,8 +5681,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c index 4b9cb7fd5b..d1c3ebe065 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Aug 11 16:00:16 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -2198,8 +2198,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -2218,8 +2218,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2261,8 +2261,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -2281,8 +2281,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2550,8 +2550,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -2570,8 +2570,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2631,8 +2631,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -2701,7 +2701,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -3258,8 +3258,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -3383,7 +3383,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -3942,8 +3942,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -4702,8 +4702,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -4778,8 +4778,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4803,8 +4803,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4827,8 +4827,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4980,8 +4980,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5005,8 +5005,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5029,8 +5029,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5182,8 +5182,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5207,8 +5207,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5231,8 +5231,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5398,8 +5398,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5423,8 +5423,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5447,8 +5447,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6746,7 +6746,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L3_HDR_TYPE_IPV4}, + ULP_WP_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L3_HDR_TYPE_IPV6} @@ -7714,8 +7714,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -7734,8 +7734,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7777,8 +7777,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -7797,8 +7797,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8066,8 +8066,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8086,8 +8086,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8147,8 +8147,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -8217,7 +8217,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -8774,8 +8774,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -8899,7 +8899,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -9458,8 +9458,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -9576,8 +9576,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -9652,8 +9652,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9677,8 +9677,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9701,8 +9701,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9854,8 +9854,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9879,8 +9879,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9903,8 +9903,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10056,8 +10056,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10081,8 +10081,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10105,8 +10105,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10272,8 +10272,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10297,8 +10297,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10321,8 +10321,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12392,8 +12392,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -12409,8 +12409,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, @@ -12544,8 +12544,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -12561,8 +12561,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, @@ -13715,7 +13715,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_LOOPBACK_PARIF}, + ULP_WP_SYM_LOOPBACK_PARIF}, .field_src3 = BNXT_ULP_FIELD_SRC_CF, .field_opr3 = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, @@ -13887,8 +13887,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -13904,8 +13904,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, @@ -14039,8 +14039,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -14056,8 +14056,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index d21c088d59..2ec3279239 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -685,6 +685,11 @@ ulp_rte_phy_port_hdr_handler(const struct rte_flow_item *item, hdr_field->size = sizeof(svif); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SVIF_FLAG, rte_be_to_cpu_16(svif)); + if (!mask) { + ULP_BITMAP_SET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_SVIF_IGNORE); + memset(hdr_field->mask, 0xFF, sizeof(mask)); + } return BNXT_TF_RC_SUCCESS; } -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 14/20] net/bnxt: modify VF representor alloc sequence 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (12 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 13/20] net/bnxt: add support for socket direct feature Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 15/20] net/bnxt: add new TruFlow API to get SRAM resources Ajit Khaparde ` (7 subsequent siblings) 21 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Shahaji Bhosle [-- Attachment #1: Type: text/plain, Size: 3599 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> When the VF representor interface is created, the VF pair relationship is established between the VF and it is representor. If the pair already exists then the pair needs to be deleted before allocation. This could happen if the application is abruptly killed and restarted. If the deletion of an existing VF rep is not done then hw pipeline is not cleaned and a new allocation shall leave the hw in inconsistent state. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/bnxt_hwrm.c | 28 ++++++++++++++++++++++++++++ drivers/net/bnxt/bnxt_hwrm.h | 1 + drivers/net/bnxt/bnxt_reps.c | 6 ++++++ 3 files changed, 35 insertions(+) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 37640abcbe..1ad39c1445 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -5994,6 +5994,34 @@ int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid, return rc; } +int bnxt_hwrm_cfa_pair_exists(struct bnxt *bp, struct bnxt_representor *rep_bp) +{ + struct hwrm_cfa_pair_info_output *resp = bp->hwrm_cmd_resp_addr; + struct hwrm_cfa_pair_info_input req = {0}; + int rc = 0; + + if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) { + PMD_DRV_LOG(DEBUG, + "Not a PF or trusted VF. Command not supported\n"); + return 0; + } + + HWRM_PREP(&req, HWRM_CFA_PAIR_INFO, BNXT_USE_CHIMP_MB); + snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d", + bp->eth_dev->data->name, rep_bp->vf_id); + req.flags = + rte_cpu_to_le_32(HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE); + + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); + HWRM_CHECK_RESULT(); + if (rc == HWRM_ERR_CODE_SUCCESS && strlen(resp->pair_name)) { + HWRM_UNLOCK(); + return !rc; + } + HWRM_UNLOCK(); + return rc; +} + int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp) { struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr; diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h index 72d486468c..f8f0556201 100644 --- a/drivers/net/bnxt/bnxt_hwrm.h +++ b/drivers/net/bnxt/bnxt_hwrm.h @@ -293,6 +293,7 @@ int bnxt_clear_one_vnic_filter(struct bnxt *bp, void bnxt_free_vf_info(struct bnxt *bp); int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid, uint16_t *first_vf_id); +int bnxt_hwrm_cfa_pair_exists(struct bnxt *bp, struct bnxt_representor *rep_bp); int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep); int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep); int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp); diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c index 60aaa56299..22b76b72b9 100644 --- a/drivers/net/bnxt/bnxt_reps.c +++ b/drivers/net/bnxt/bnxt_reps.c @@ -315,6 +315,12 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev) BNXT_TF_DBG(ERR, "Invalid arguments\n"); return 0; } + /* update the port id so you can backtrack to ethdev */ + vfr->dpdk_port_id = vfr_ethdev->data->port_id; + + /* If pair is present, then delete the pair */ + if (bnxt_hwrm_cfa_pair_exists(parent_bp, vfr)) + (void)bnxt_hwrm_cfa_pair_free(parent_bp, vfr); /* Update the ULP portdata base with the new VFR interface */ rc = ulp_port_db_dev_port_intf_update(parent_bp->ulp_ctx, vfr_ethdev); -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 15/20] net/bnxt: add new TruFlow API to get SRAM resources 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (13 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 14/20] net/bnxt: modify VF representor alloc sequence Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 16/20] net/bnxt: add TruFlow and AFM SRAM partitioning support Ajit Khaparde ` (6 subsequent siblings) 21 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru, Farah Smith, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 12976 bytes --] From: Jay Ding <jay.ding@broadcom.com> Implement tf_get_sram_resources to return SRAM partition information, including bank count and SRAM profile number. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_core/tf_core.c | 86 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_core.h | 63 +++++++++++++++++ drivers/net/bnxt/tf_core/tf_device.h | 20 ++++++ drivers/net/bnxt/tf_core/tf_device_p4.c | 6 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 53 ++++++++++++++- drivers/net/bnxt/tf_core/tf_msg.c | 28 ++------ drivers/net/bnxt/tf_core/tf_msg.h | 6 +- drivers/net/bnxt/tf_core/tf_rm.c | 3 +- drivers/net/bnxt/tf_core/tf_sram_mgr.h | 10 --- 9 files changed, 237 insertions(+), 38 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 86dfec0eb4..346d220c87 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1831,3 +1831,89 @@ int tf_get_version(struct tf *tfp, return 0; } + +int tf_query_sram_resources(struct tf *tfp, + struct tf_query_sram_resources_parms *parms) +{ + int rc; + struct tf_dev_info dev; + uint16_t max_types; + struct tfp_calloc_parms cparms; + struct tf_rm_resc_req_entry *query; + enum tf_rm_resc_resv_strategy resv_strategy; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_THOR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + if (dev.ops->tf_dev_get_max_types == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return -EOPNOTSUPP; + } + + /* Need device max number of elements for the RM QCAPS */ + rc = dev.ops->tf_dev_get_max_types(tfp, &max_types); + if (rc) { + TFP_DRV_LOG(ERR, + "Get SRAM resc info failed, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Allocate memory for RM QCAPS request */ + cparms.nitems = max_types; + cparms.size = sizeof(struct tf_rm_resc_req_entry); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) + return rc; + + query = (struct tf_rm_resc_req_entry *)cparms.mem_va; + tfp->bp = parms->bp; + + /* Get Firmware Capabilities */ + rc = tf_msg_session_resc_qcaps(tfp, + &dev, + parms->dir, + max_types, + query, + &resv_strategy, + &parms->sram_profile); + if (rc) + return rc; + + if (dev.ops->tf_dev_get_sram_resources == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return -EOPNOTSUPP; + } + + rc = dev.ops->tf_dev_get_sram_resources((void *)query, + parms->bank_resc_count, + &parms->dynamic_sram_capable); + if (rc) { + TFP_DRV_LOG(ERR, + "Get SRAM resc info failed, rc:%s\n", + strerror(-rc)); + return rc; + } + + return 0; +} diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index ba9881c69d..078fd278a1 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -75,6 +75,17 @@ enum tf_wc_num_slice { TF_WC_TCAM_8_SLICE_PER_ROW = 8, }; +/** + * Bank identifier + */ +enum tf_sram_bank_id { + TF_SRAM_BANK_ID_0, /**< SRAM Bank 0 id */ + TF_SRAM_BANK_ID_1, /**< SRAM Bank 1 id */ + TF_SRAM_BANK_ID_2, /**< SRAM Bank 2 id */ + TF_SRAM_BANK_ID_3, /**< SRAM Bank 3 id */ + TF_SRAM_BANK_ID_MAX /**< SRAM Bank index limit */ +}; + /** * EEM record AR helper * @@ -2438,4 +2449,56 @@ struct tf_get_version_parms { */ int tf_get_version(struct tf *tfp, struct tf_get_version_parms *parms); + +/** + * tf_query_sram_resources parameter definition + */ +struct tf_query_sram_resources_parms { + /** + * [in] device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] bp + * The pointer to the parent bp struct. This is only used for HWRM + * message passing within the portability layer. The type is struct + * bnxt. + */ + void *bp; + + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + + /** + * [out] Bank resource count in 8 bytes entry + */ + + uint32_t bank_resc_count[TF_SRAM_BANK_ID_MAX]; + + /** + * [out] Dynamic SRAM Enable + */ + bool dynamic_sram_capable; + + /** + * [out] SRAM profile + */ + uint8_t sram_profile; +}; + +/** + * Get SRAM resources information + * + * Used to retrieve sram bank partition information + * + * Returns success or failure code. + */ +int tf_query_sram_resources(struct tf *tfp, + struct tf_query_sram_resources_parms *parms); + #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 88bd4515ff..9360eb1358 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1081,6 +1081,26 @@ struct tf_dev_ops { uint32_t *tcam_caps, uint32_t *tbl_caps, uint32_t *em_caps); + + /** + * Device specific function that retrieve the sram resource + * + * [in] query + * Point to resources query result + * + * [out] sram_bank_caps + * Pointer to SRAM bank capabilities + * + * [out] dynamic_sram_capable + * Pointer to dynamic sram capable + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_sram_resources)(void *query, + uint32_t *sram_bank_caps, + bool *dynamic_sram_capable); }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 8089785b82..cf0e919f9f 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -382,7 +382,8 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = NULL, - .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, + .tf_dev_get_sram_resources = NULL }; /** @@ -445,5 +446,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = tf_dev_p4_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, - .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, + .tf_dev_get_sram_resources = NULL }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 03e72b90f5..4687fa65dd 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -397,6 +397,53 @@ static int tf_dev_p58_map_hcapi_caps(uint64_t hcapi_caps, return 0; } +/** + * Device specific function that retrieve the sram resource + * + * [in] query + * Point to resources query result + * + * [out] sram_bank_caps + * Pointer to SRAM bank capabilities + * + * [out] dynamic_sram_capable + * Pointer to dynamic sram capable + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_get_sram_resources(void *q, + uint32_t *sram_bank_caps, + bool *dynamic_sram_capable) +{ + uint32_t i; + struct tf_rm_resc_req_entry *query = q; + + for (i = 0; i < CFA_RESOURCE_TYPE_P58_LAST + 1; i++) { + switch (query[i].type) { + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_0: + sram_bank_caps[0] = query[i].max; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_1: + sram_bank_caps[1] = query[i].max; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_2: + sram_bank_caps[2] = query[i].max; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_3: + sram_bank_caps[3] = query[i].max; + break; + default: + break; + } + } + + *dynamic_sram_capable = false; + + return 0; +} + /** * Truflow P58 device specific functions */ @@ -447,7 +494,8 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = NULL, - .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources }; /** @@ -511,5 +559,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = tf_dev_p58_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, - .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources }; diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 25bf026658..fbc96d374c 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -380,39 +380,20 @@ tf_msg_session_resc_qcaps(struct tf *tfp, enum tf_dir dir, uint16_t size, struct tf_rm_resc_req_entry *query, - enum tf_rm_resc_resv_strategy *resv_strategy) + enum tf_rm_resc_resv_strategy *resv_strategy, + uint8_t *sram_profile) { int rc; int i; struct tfp_send_msg_parms parms = { 0 }; struct hwrm_tf_session_resc_qcaps_input req = { 0 }; struct hwrm_tf_session_resc_qcaps_output resp = { 0 }; - uint8_t fw_session_id; struct tf_msg_dma_buf qcaps_buf = { 0 }; struct tf_rm_resc_req_entry *data; int dma_size; - struct tf_session *tfs; - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to lookup session, rc:%s\n", - strerror(-rc)); - return rc; - } TF_CHECK_PARMS3(tfp, query, resv_strategy); - rc = tf_session_get_fw_session_id(tfp, &fw_session_id); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Unable to lookup FW id, rc:%s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - /* Prepare DMA buffer */ dma_size = size * sizeof(struct tf_rm_resc_req_entry); rc = tf_msg_alloc_dma_buf(&qcaps_buf, dma_size); @@ -420,7 +401,7 @@ tf_msg_session_resc_qcaps(struct tf *tfp, return rc; /* Populate the request */ - req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); + req.fw_session_id = 0; req.flags = tfp_cpu_to_le_16(dir); req.qcaps_size = size; req.qcaps_addr = tfp_cpu_to_le_64(qcaps_buf.pa_addr); @@ -460,6 +441,9 @@ tf_msg_session_resc_qcaps(struct tf *tfp, *resv_strategy = resp.flags & HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK; + if (sram_profile != NULL) + *sram_profile = resp.sram_profile; + cleanup: tf_msg_free_dma_buf(&qcaps_buf); diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 08d20cdd7a..188b361d71 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -158,6 +158,9 @@ int tf_msg_session_qcfg(struct tf *tfp); * [out] resv_strategy * Pointer to the reservation strategy * + * [out] sram_profile + * Pointer to the sram profile + * * Returns: * 0 on Success else internal Truflow error */ @@ -166,7 +169,8 @@ int tf_msg_session_resc_qcaps(struct tf *tfp, enum tf_dir dir, uint16_t size, struct tf_rm_resc_req_entry *query, - enum tf_rm_resc_resv_strategy *resv_strategy); + enum tf_rm_resc_resv_strategy *resv_strategy, + uint8_t *sram_profile); /** * Sends session HW resource allocation request to TF Firmware diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index dd537aaece..d2045921b9 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -551,7 +551,8 @@ tf_rm_create_db(struct tf *tfp, parms->dir, max_types, query, - &resv_strategy); + &resv_strategy, + NULL); if (rc) return rc; diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h index 4abe3fb468..eb2156456a 100644 --- a/drivers/net/bnxt/tf_core/tf_sram_mgr.h +++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h @@ -28,16 +28,6 @@ #define TF_SRAM_MGR_BLOCK_SZ_BYTES 64 #define TF_SRAM_MGR_MIN_SLICE_BYTES 8 -/** - * Bank identifier - */ -enum tf_sram_bank_id { - TF_SRAM_BANK_ID_0, /**< SRAM Bank 0 id */ - TF_SRAM_BANK_ID_1, /**< SRAM Bank 1 id */ - TF_SRAM_BANK_ID_2, /**< SRAM Bank 2 id */ - TF_SRAM_BANK_ID_3, /**< SRAM Bank 3 id */ - TF_SRAM_BANK_ID_MAX /**< SRAM Bank index limit */ -}; /** * TF slice size. -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 16/20] net/bnxt: add TruFlow and AFM SRAM partitioning support 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (14 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 15/20] net/bnxt: add new TruFlow API to get SRAM resources Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 17/20] net/bnxt: add Tx TruFlow table config for P4 device Ajit Khaparde ` (5 subsequent siblings) 21 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru, Randy Schacher, Farah Smith [-- Attachment #1: Type: text/plain, Size: 24863 bytes --] From: Jay Ding <jay.ding@broadcom.com> Implement set/get_sram_policy which support both rx/tx direction truflow type the specific SRAM bank. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_core/tf_core.c | 82 ++++++ drivers/net/bnxt/tf_core/tf_core.h | 66 ++++- drivers/net/bnxt/tf_core/tf_device.c | 7 +- drivers/net/bnxt/tf_core/tf_device.h | 34 ++- drivers/net/bnxt/tf_core/tf_device_p4.c | 8 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 311 ++++++++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p58.h | 118 +-------- drivers/net/bnxt/tf_core/tf_tbl.c | 2 +- 8 files changed, 503 insertions(+), 125 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 346d220c87..90ff93946b 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1917,3 +1917,85 @@ int tf_query_sram_resources(struct tf *tfp, return 0; } + +int tf_set_sram_policy(struct tf *tfp, + struct tf_set_sram_policy_parms *parms) +{ + int rc = 0; + struct tf_dev_info dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_THOR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + if (dev.ops->tf_dev_set_sram_policy == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + rc = dev.ops->tf_dev_set_sram_policy(parms->dir, parms->bank_id); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: SRAM policy set failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + return rc; +} + +int tf_get_sram_policy(struct tf *tfp, + struct tf_get_sram_policy_parms *parms) +{ + int rc = 0; + struct tf_dev_info dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_THOR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + if (dev.ops->tf_dev_get_sram_policy == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + rc = dev.ops->tf_dev_get_sram_policy(parms->dir, parms->bank_id); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: SRAM policy get failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 078fd278a1..b2886355fa 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2455,7 +2455,7 @@ int tf_get_version(struct tf *tfp, */ struct tf_query_sram_resources_parms { /** - * [in] device type + * [in] Device type * * Device type for the session. */ @@ -2501,4 +2501,68 @@ struct tf_query_sram_resources_parms { int tf_query_sram_resources(struct tf *tfp, struct tf_query_sram_resources_parms *parms); +/** + * tf_set_sram_policy parameter definition + */ +struct tf_set_sram_policy_parms { + /** + * [in] Device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + + /** + * [in] Array of Bank id for each truflow tbl type + */ + uint8_t *bank_id; +}; + +/** + * Set SRAM policy + * + * Used to assign SRAM bank index to all truflow table type. + * + * Returns success or failure code. + */ +int tf_set_sram_policy(struct tf *tfp, + struct tf_set_sram_policy_parms *parms); + +/** + * tf_get_sram_policy parameter definition + */ +struct tf_get_sram_policy_parms { + /** + * [in] Device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + + /** + * [out] Array of Bank id for each truflow tbl type + */ + uint8_t bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1]; +}; + +/** + * Get SRAM policy + * + * Used to get the assigned bank of table types. + * + * Returns success or failure code. + */ +int tf_get_sram_policy(struct tf *tfp, + struct tf_get_sram_policy_parms *parms); + #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 25a7166bbb..40db546604 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -415,11 +415,14 @@ tf_dev_bind_p58(struct tf *tfp, } rsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX, - tf_tbl_p58, + tf_tbl_p58[TF_DIR_RX], + (uint16_t *)resources->tbl_cnt); + rsv_cnt += tf_dev_reservation_check(TF_TBL_TYPE_MAX, + tf_tbl_p58[TF_DIR_TX], (uint16_t *)resources->tbl_cnt); if (rsv_cnt) { tbl_cfg.num_elements = TF_TBL_TYPE_MAX; - tbl_cfg.cfg = tf_tbl_p58; + tbl_cfg.cfg = tf_tbl_p58[TF_DIR_RX]; tbl_cfg.resources = resources; rc = tf_tbl_bind(tfp, &tbl_cfg); if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 9360eb1358..3d5de988c4 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1083,7 +1083,7 @@ struct tf_dev_ops { uint32_t *em_caps); /** - * Device specific function that retrieve the sram resource + * Device specific function that retrieves the sram resource * * [in] query * Point to resources query result @@ -1101,6 +1101,38 @@ struct tf_dev_ops { int (*tf_dev_get_sram_resources)(void *query, uint32_t *sram_bank_caps, bool *dynamic_sram_capable); + + /** + * Device specific function that sets the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [in] band_id + * SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_set_sram_policy)(enum tf_dir dir, + uint8_t *bank_id); + + /** + * Device specific function that gets the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [in] band_id + * pointer to SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_sram_policy)(enum tf_dir dir, + uint8_t *bank_id); }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index cf0e919f9f..244bd08914 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -383,7 +383,9 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = NULL, .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, - .tf_dev_get_sram_resources = NULL + .tf_dev_get_sram_resources = NULL, + .tf_dev_set_sram_policy = NULL, + .tf_dev_get_sram_policy = NULL, }; /** @@ -447,5 +449,7 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_word_align = tf_dev_p4_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, - .tf_dev_get_sram_resources = NULL + .tf_dev_get_sram_resources = NULL, + .tf_dev_set_sram_policy = NULL, + .tf_dev_get_sram_policy = NULL, }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 4687fa65dd..3c1c3a2de1 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -48,6 +48,235 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = "meter_dc", }; +struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { + [TF_DIR_RX][TF_TBL_TYPE_EM_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_WC_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_DROP_CNT] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METADATA] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, + 0, 0 + }, + /* Policy - ARs in bank 1 */ + [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 8, + }, + /* Policy - Encaps in bank 2 */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - Modify in bank 2 with Encaps */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - SP in bank 0 */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 8, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 2, + }, + /* Policy - Stats in bank 3 */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_EM_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_WC_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_DROP_CNT] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METADATA] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, + 0, 0 + }, + /* Policy - ARs in bank 1 */ + [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 8, + }, + /* Policy - Encaps in bank 2 */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - Modify in bank 2 with Encaps */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - SP in bank 0 */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 2, + }, + /* Policy - Stats in bank 3 */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, + .slices = 8, + }, +}; + /** * Device specific function that retrieves the MAX number of HCAPI * types the device supports. @@ -444,6 +673,80 @@ static int tf_dev_p58_get_sram_resources(void *q, return 0; } +int sram_bank_hcapi_type[] = { + CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + CFA_RESOURCE_TYPE_P58_SRAM_BANK_3 +}; + +/** + * Device specific function that set the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [in] band_id + * SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_set_sram_policy(enum tf_dir dir, + uint8_t *bank_id) +{ + struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; + uint8_t type; + uint8_t parent[TF_SRAM_BANK_ID_MAX] = { 0xFF, 0xFF, 0xFF, 0xFF }; + + for (type = TF_TBL_TYPE_FULL_ACT_RECORD; + type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++) { + if (bank_id[type] > 3) + return -EINVAL; + + rm_cfg[type].hcapi_type = sram_bank_hcapi_type[bank_id[type]]; + if (parent[bank_id[type]] == 0xFF) { + parent[bank_id[type]] = type; + rm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT; + rm_cfg[type].parent_subtype = 0; + if (rm_cfg[type].slices == 0) + rm_cfg[type].slices = 1; + } else { + rm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD; + rm_cfg[type].parent_subtype = parent[bank_id[type]]; + } + } + + return 0; +} + +/** + * Device specific function that get the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [out] band_id + * pointer to SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_get_sram_policy(enum tf_dir dir, + uint8_t *bank_id) +{ + struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; + uint8_t type; + + for (type = TF_TBL_TYPE_FULL_ACT_RECORD; + type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++) + bank_id[type] = rm_cfg[type].hcapi_type - CFA_RESOURCE_TYPE_P58_SRAM_BANK_0; + + return 0; +} + /** * Truflow P58 device specific functions */ @@ -495,7 +798,9 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = NULL, .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, - .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources, + .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy, + .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy, }; /** @@ -560,5 +865,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_word_align = tf_dev_p58_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, - .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources, + .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy, + .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy, }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index f6e66936f3..61c856b767 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -12,6 +12,8 @@ #include "tf_if_tbl.h" #include "tf_global_cfg.h" +extern struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX]; + struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = { [TF_IDENT_TYPE_L2_CTXT_HIGH] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH, @@ -58,122 +60,6 @@ struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = { }, }; -struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { - [TF_TBL_TYPE_EM_FKB] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, - 0, 0 - }, - [TF_TBL_TYPE_WC_FKB] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, - 0, 0 - }, - [TF_TBL_TYPE_METER_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, - 0, 0 - }, - [TF_TBL_TYPE_METER_INST] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, - 0, 0 - }, - [TF_TBL_TYPE_METER_DROP_CNT] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, - 0, 0 - }, - [TF_TBL_TYPE_MIRROR_CONFIG] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, - 0, 0 - }, - [TF_TBL_TYPE_METADATA] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, - 0, 0 - }, - /* Policy - ARs in bank 1 */ - [TF_TBL_TYPE_FULL_ACT_RECORD] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 4, - }, - [TF_TBL_TYPE_COMPACT_ACT_RECORD] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 8, - }, - /* Policy - Encaps in bank 2 */ - [TF_TBL_TYPE_ACT_ENCAP_8B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 8, - }, - [TF_TBL_TYPE_ACT_ENCAP_16B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 4, - }, - [TF_TBL_TYPE_ACT_ENCAP_32B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 2, - }, - [TF_TBL_TYPE_ACT_ENCAP_64B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, - }, - /* Policy - Modify in bank 2 with Encaps */ - [TF_TBL_TYPE_ACT_MODIFY_8B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 8, - }, - [TF_TBL_TYPE_ACT_MODIFY_16B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 4, - }, - [TF_TBL_TYPE_ACT_MODIFY_32B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 2, - }, - [TF_TBL_TYPE_ACT_MODIFY_64B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, - }, - /* Policy - SP in bank 0 */ - [TF_TBL_TYPE_ACT_SP_SMAC] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 8, - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 4, - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 2, - }, - /* Policy - Stats in bank 3 */ - [TF_TBL_TYPE_ACT_STATS_64] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, - .slices = 8, - }, -}; - struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_EM_RECORD] = { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC, diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 12eca36491..3fb22b52ac 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -58,10 +58,10 @@ tf_tbl_bind(struct tf *tfp, db_cfg.num_elements = parms->num_elements; db_cfg.module = TF_MODULE_TYPE_TABLE; db_cfg.num_elements = parms->num_elements; - db_cfg.cfg = parms->cfg; for (d = 0; d < TF_DIR_MAX; d++) { db_cfg.dir = d; + db_cfg.cfg = &parms->cfg[d ? TF_TBL_TYPE_MAX : 0]; db_cfg.alloc_cnt = parms->resources->tbl_cnt[d].cnt; db_cfg.rm_db = (void *)&tbl_db->tbl_db[d]; if (tf_session_is_shared_session(tfs) && -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 17/20] net/bnxt: add Tx TruFlow table config for P4 device 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (15 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 16/20] net/bnxt: add TruFlow and AFM SRAM partitioning support Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 18/20] net/bnxt: remove 2 slice WC entries Ajit Khaparde ` (4 subsequent siblings) 21 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru, Farah Smith, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 7163 bytes --] From: Jay Ding <jay.ding@broadcom.com> Add TX direction TruFlow table type config to be compatible with other devices. For P4 device, the TX cfg is duplicated from RX. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_core/tf_device.c | 4 +- drivers/net/bnxt/tf_core/tf_device_p4.c | 107 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p4.h | 58 +------------ 3 files changed, 111 insertions(+), 58 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 40db546604..4c416270b6 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -131,11 +131,11 @@ tf_dev_bind_p4(struct tf *tfp, } rsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX, - tf_tbl_p4, + tf_tbl_p4[TF_DIR_RX], (uint16_t *)resources->tbl_cnt); if (rsv_cnt) { tbl_cfg.num_elements = TF_TBL_TYPE_MAX; - tbl_cfg.cfg = tf_tbl_p4; + tbl_cfg.cfg = tf_tbl_p4[TF_DIR_RX]; tbl_cfg.resources = resources; rc = tf_tbl_bind(tfp, &tbl_cfg); if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 244bd08914..a6a59b8a07 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -59,6 +59,113 @@ const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = "tb_scope", }; +struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { + [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_MCAST_GROUPS] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_MCAST_GROUPS] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, + 0, 0 + }, +}; + /** * Device specific function that retrieves the MAX number of HCAPI * types the device supports. diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index e84c0f9e83..86de525995 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -12,6 +12,8 @@ #include "tf_if_tbl.h" #include "tf_global_cfg.h" +extern struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX]; + struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = { [TF_IDENT_TYPE_L2_CTXT_HIGH] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH, @@ -58,62 +60,6 @@ struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = { }, }; -struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = { - [TF_TBL_TYPE_FULL_ACT_RECORD] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, - 0, 0 - }, - [TF_TBL_TYPE_MCAST_GROUPS] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_8B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_16B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_64B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, - 0, 0 - }, - [TF_TBL_TYPE_ACT_STATS_64] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_MODIFY_IPV4] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, - 0, 0 - }, - [TF_TBL_TYPE_METER_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, - 0, 0 - }, - [TF_TBL_TYPE_METER_INST] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, - 0, 0 - }, - [TF_TBL_TYPE_MIRROR_CONFIG] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, - 0, 0 - }, - -}; - struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_TBL_SCOPE] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE, -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 18/20] net/bnxt: remove 2 slice WC entries 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (16 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 17/20] net/bnxt: add Tx TruFlow table config for P4 device Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 19/20] net/bnxt: check mismatch of control and physical port Ajit Khaparde ` (3 subsequent siblings) 21 siblings, 1 reply; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Mike Baucom, Venkat Duvvuru, Kishore Padmanabha, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 1392 bytes --] From: Mike Baucom <michael.baucom@broadcom.com> Remove 2-slice Wild Card entries for scale. The type-5 WC IPv6 flows are removed in order to increase the scale for app-id=3. The app no longer supports 2-slice WC entries. Signed-off-by: Mike Baucom <michael.baucom@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index b64279710b..fd211bbc3f 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -462,7 +462,7 @@ ulp_ctx_shared_session_open(struct bnxt *bp, parms.shadow_copy = true; parms.bp = bp; - if (app_id == 0 || app_id == 3) + if (app_id == 0) parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW; else parms.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW; @@ -584,7 +584,7 @@ ulp_ctx_session_open(struct bnxt *bp, return rc; params.bp = bp; - if (app_id == 0 || app_id == 3) + if (app_id == 0) params.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW; else params.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW; -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH v4 18/20] net/bnxt: remove 2 slice WC entries 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 18/20] net/bnxt: remove 2 slice WC entries Ajit Khaparde @ 2021-11-03 13:24 ` Ferruh Yigit 0 siblings, 0 replies; 118+ messages in thread From: Ferruh Yigit @ 2021-11-03 13:24 UTC (permalink / raw) To: Ajit Khaparde, dev Cc: Mike Baucom, Venkat Duvvuru, Kishore Padmanabha, Randy Schacher On 11/3/2021 12:52 AM, Ajit Khaparde wrote: > From: Mike Baucom <michael.baucom@broadcom.com> > > Remove 2-slice Wild Card entries for scale. > The type-5 WC IPv6 flows are removed in order to increase the scale for > app-id=3. The app no longer supports 2-slice WC entries. > 'WC' is mostly used for "Write combining", didn't see before it is use for "wild card", can you please use long version of the abbreviation? > Signed-off-by: Mike Baucom <michael.baucom@broadcom.com> > Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> > Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> > Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> > Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> <...> ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 19/20] net/bnxt: check mismatch of control and physical port 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (17 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 18/20] net/bnxt: remove 2 slice WC entries Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 20/20] net/bnxt: use enum for bank ID Ajit Khaparde ` (2 subsequent siblings) 21 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Mike Baucom, Shahaji Bhosle [-- Attachment #1: Type: text/plain, Size: 3329 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> During the parsing of the ingress port ignore for a flow, added check to match the control port and the physical port that is configured to be ignored. If they do not match then the configuration to setup the svif ignore shall fail. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_port_db.c | 23 +++++++++++++++++++++++ drivers/net/bnxt/tf_ulp/ulp_port_db.h | 13 +++++++++++++ drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 12 ++++++++++++ 3 files changed, 48 insertions(+) diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c index 5e7c1d1c17..f8ffb567b5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c @@ -679,3 +679,26 @@ ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt, } return -EINVAL; } + +/* + * Api to get the phy port for a given port id. + * + * ulp_ctxt [in] Ptr to ulp context + * port_id [in] device port id + * phy_port [out] phy_port of the dpdk port_id + * + * Returns 0 on success or negative number on failure. + */ +int32_t +ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id, uint16_t *phy_port) +{ + struct ulp_func_if_info *info; + + info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id); + if (info) { + *phy_port = info->phy_port_id; + return 0; + } + return -EINVAL; +} diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h index 740c186e12..b112f1a216 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h @@ -314,4 +314,17 @@ int32_t ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt, uint32_t port_id, uint8_t **vnic); +/* + * Api to get the phy port for a given port id. + * + * ulp_ctxt [in] Ptr to ulp context + * port_id [in] device port id + * phy_port [out] phy_port of the dpdk port_id + * + * Returns 0 on success or negative number on failure. + */ +int32_t +ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id, uint16_t *phy_port); + #endif /* _ULP_PORT_DB_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 2ec3279239..f4274dd634 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -686,6 +686,18 @@ ulp_rte_phy_port_hdr_handler(const struct rte_flow_item *item, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SVIF_FLAG, rte_be_to_cpu_16(svif)); if (!mask) { + uint32_t port_id = 0; + uint16_t phy_port = 0; + + /* Validate the control port */ + port_id = ULP_COMP_FLD_IDX_RD(params, + BNXT_ULP_CF_IDX_DEV_PORT_ID); + if (ulp_port_db_phy_port_get(params->ulp_ctx, + port_id, &phy_port) || + (uint16_t)port_spec->index != phy_port) { + BNXT_TF_DBG(ERR, "Mismatch of control and phy_port\n"); + return BNXT_TF_RC_PARSE_ERR; + } ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF_IGNORE); memset(hdr_field->mask, 0xFF, sizeof(mask)); -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v4 20/20] net/bnxt: use enum for bank ID 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (18 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 19/20] net/bnxt: check mismatch of control and physical port Ajit Khaparde @ 2021-11-03 0:52 ` Ajit Khaparde 2021-11-03 3:40 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde 21 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 0:52 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Steve Rempe, Farah Smith [-- Attachment #1: Type: text/plain, Size: 6704 bytes --] From: Jay Ding <jay.ding@broadcom.com> Instead of integer, using enum tf_sram_bank_id for bank id in tf_set_sram_policy_parms. Add index check against the allocation of the meter instance for meter drop count because there is no reason to access it if the corresponding meter entry is not allocated. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Reviewed-by: Steve Rempe <steve.rempe@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_core/tf_core.h | 4 +- drivers/net/bnxt/tf_core/tf_device.h | 4 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 10 ++-- drivers/net/bnxt/tf_core/tf_tbl.c | 75 ++++++++++++------------ 4 files changed, 47 insertions(+), 46 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index b2886355fa..f891d7a48f 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2520,7 +2520,7 @@ struct tf_set_sram_policy_parms { /** * [in] Array of Bank id for each truflow tbl type */ - uint8_t *bank_id; + enum tf_sram_bank_id bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1]; }; /** @@ -2552,7 +2552,7 @@ struct tf_get_sram_policy_parms { /** * [out] Array of Bank id for each truflow tbl type */ - uint8_t bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1]; + enum tf_sram_bank_id bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1]; }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 3d5de988c4..bfb5de4370 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1116,7 +1116,7 @@ struct tf_dev_ops { * - (-EINVAL) on failure. */ int (*tf_dev_set_sram_policy)(enum tf_dir dir, - uint8_t *bank_id); + enum tf_sram_bank_id *bank_id); /** * Device specific function that gets the sram policy @@ -1132,7 +1132,7 @@ struct tf_dev_ops { * - (-EINVAL) on failure. */ int (*tf_dev_get_sram_policy)(enum tf_dir dir, - uint8_t *bank_id); + enum tf_sram_bank_id *bank_id); }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 3c1c3a2de1..30c0af7eef 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -673,7 +673,7 @@ static int tf_dev_p58_get_sram_resources(void *q, return 0; } -int sram_bank_hcapi_type[] = { +static int sram_bank_hcapi_type[] = { CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, @@ -694,15 +694,15 @@ int sram_bank_hcapi_type[] = { * - (-EINVAL) on failure. */ static int tf_dev_p58_set_sram_policy(enum tf_dir dir, - uint8_t *bank_id) + enum tf_sram_bank_id *bank_id) { struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; uint8_t type; uint8_t parent[TF_SRAM_BANK_ID_MAX] = { 0xFF, 0xFF, 0xFF, 0xFF }; for (type = TF_TBL_TYPE_FULL_ACT_RECORD; - type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++) { - if (bank_id[type] > 3) + type <= TF_TBL_TYPE_ACT_MODIFY_64B; type++) { + if (bank_id[type] >= TF_SRAM_BANK_ID_MAX) return -EINVAL; rm_cfg[type].hcapi_type = sram_bank_hcapi_type[bank_id[type]]; @@ -735,7 +735,7 @@ static int tf_dev_p58_set_sram_policy(enum tf_dir dir, * - (-EINVAL) on failure. */ static int tf_dev_p58_get_sram_policy(enum tf_dir dir, - uint8_t *bank_id) + enum tf_sram_bank_id *bank_id) { struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; uint8_t type; diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 3fb22b52ac..f18e4ba346 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -307,28 +307,28 @@ tf_tbl_set(struct tf *tfp, } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; - - /* Do not check meter drop counter because it is not allocated - * resources + /* Verify that the entry has been previously allocated. + * for meter drop counter, check the corresponding meter + * entry */ - if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) { - /* Verify that the entry has been previously allocated */ - aparms.rm_db = tbl_db->tbl_db[parms->dir]; + aparms.rm_db = tbl_db->tbl_db[parms->dir]; + if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) aparms.subtype = parms->type; - aparms.allocated = &allocated; - aparms.index = parms->idx; - rc = tf_rm_is_allocated(&aparms); - if (rc) - return rc; + else + aparms.subtype = TF_TBL_TYPE_METER_INST; + aparms.allocated = &allocated; + aparms.index = parms->idx; + rc = tf_rm_is_allocated(&aparms); + if (rc) + return rc; - if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { - TFP_DRV_LOG(ERR, - "%s, Invalid or not allocated, type:%s, idx:%d\n", - tf_dir_2_str(parms->dir), - tf_tbl_type_2_str(parms->type), - parms->idx); - return -EINVAL; - } + if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { + TFP_DRV_LOG(ERR, + "%s, Invalid or not allocated, type:%s, idx:%d\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + parms->idx); + return -EINVAL; } /* Set the entry */ @@ -398,27 +398,28 @@ tf_tbl_get(struct tf *tfp, } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; - /* Do not check meter drop counter because it is not allocated - * resources. + /* Verify that the entry has been previously allocated. + * for meter drop counter, check the corresponding meter + * entry */ - if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) { - /* Verify that the entry has been previously allocated */ - aparms.rm_db = tbl_db->tbl_db[parms->dir]; + aparms.rm_db = tbl_db->tbl_db[parms->dir]; + if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) aparms.subtype = parms->type; - aparms.index = parms->idx; - aparms.allocated = &allocated; - rc = tf_rm_is_allocated(&aparms); - if (rc) - return rc; + else + aparms.subtype = TF_TBL_TYPE_METER_INST; + aparms.index = parms->idx; + aparms.allocated = &allocated; + rc = tf_rm_is_allocated(&aparms); + if (rc) + return rc; - if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { - TFP_DRV_LOG(ERR, - "%s, Invalid or not allocated index, type:%s, idx:%d\n", - tf_dir_2_str(parms->dir), - tf_tbl_type_2_str(parms->type), - parms->idx); - return -EINVAL; - } + if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { + TFP_DRV_LOG(ERR, + "%s, Invalid or not allocated index, type:%s, idx:%d\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + parms->idx); + return -EINVAL; } /* Set the entry */ -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (19 preceding siblings ...) 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 20/20] net/bnxt: use enum for bank ID Ajit Khaparde @ 2021-11-03 3:40 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde 21 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-03 3:40 UTC (permalink / raw) To: dpdk-dev, Ferruh Yigit On Tue, Nov 2, 2021 at 5:52 PM Ajit Khaparde <ajit.khaparde@broadcom.com> wrote: > Enhancements include: > * Scaling numbers on Thor > * Inner IP header support for GRE tunnel flows > * Enable wildcard match for ingress flows > * Add clear on read for flow stats on Thor > * Add nat support for dest IP and port combination > * Remove 2-slice WC support > * Add support for socket redirect feature > * Add new API TruFlow get SRAM resources > * Remove accumulation of stats devargs argument > * Add TruFlow and AFM SRAM partitioning support > > V2: > * Compilation fixes > * Remove 2-slice WC support > * Add support for socket redirect feature > * Add new API TruFlow get SRAM resources > * Remove accumulation of stats devargs argument > * Add TruFlow and AFM SRAM partitioning support > > V3: > * Added one more patch (use enum for bank ID) > > V4: > * Fixed typos in patch 2/20 > * Fix checkpatch warnings > * Updated commit logs > * Rebased the patches to latest dpdk-next-net > Patchset applied to dpdk-next-net-brcm. Thanks > > Farah Smith (1): > net/bnxt: add clear on read support > > Jay Ding (5): > net/bnxt: get TruFlow version > net/bnxt: add new TruFlow API to get SRAM resources > net/bnxt: add TruFlow and AFM SRAM partitioning support > net/bnxt: add Tx TruFlow table config for P4 device > net/bnxt: use enum for bank ID > > Kishore Padmanabha (11): > net/bnxt: add NAT support for dest IP and port combination > net/bnxt: add support for multi root capability > net/bnxt: fix out of bounds issue in hash list > net/bnxt: add capability option for socket redirect > net/bnxt: enable wildcard match for ingress flows > net/bnxt: support inner IP header for GRE tunnel flows > net/bnxt: remove devargs for stats accumulation > net/bnxt: update log messages in TruFlow path > net/bnxt: add support for socket direct feature > net/bnxt: modify VF representor alloc sequence > net/bnxt: check mismatch of control and physical port > > Mike Baucom (1): > net/bnxt: remove 2 slice WC entries > > Shahaji Bhosle (2): > net/bnxt: increase flow scale for Thor > net/bnxt: fix clang compiler warnings > > drivers/net/bnxt/bnxt.h | 25 +- > drivers/net/bnxt/bnxt_cpr.c | 2 +- > drivers/net/bnxt/bnxt_ethdev.c | 274 +- > drivers/net/bnxt/bnxt_hwrm.c | 36 + > drivers/net/bnxt/bnxt_hwrm.h | 1 + > drivers/net/bnxt/bnxt_reps.c | 9 +- > drivers/net/bnxt/hsi_struct_def_dpdk.h | 4007 ++++++++++++++--- > drivers/net/bnxt/tf_core/tf_core.c | 197 + > drivers/net/bnxt/tf_core/tf_core.h | 202 + > drivers/net/bnxt/tf_core/tf_device.c | 11 +- > drivers/net/bnxt/tf_core/tf_device.h | 102 + > drivers/net/bnxt/tf_core/tf_device_p4.c | 178 +- > drivers/net/bnxt/tf_core/tf_device_p4.h | 137 +- > drivers/net/bnxt/tf_core/tf_device_p58.c | 421 +- > drivers/net/bnxt/tf_core/tf_device_p58.h | 205 +- > drivers/net/bnxt/tf_core/tf_msg.c | 87 +- > drivers/net/bnxt/tf_core/tf_msg.h | 31 +- > drivers/net/bnxt/tf_core/tf_rm.c | 3 +- > drivers/net/bnxt/tf_core/tf_sram_mgr.h | 10 - > drivers/net/bnxt/tf_core/tf_tbl.c | 83 +- > drivers/net/bnxt/tf_core/tf_tbl_sram.c | 13 +- > drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 59 +- > drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 9 +- > drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 29 +- > .../generic_templates/ulp_template_db_act.c | 376 +- > .../generic_templates/ulp_template_db_class.c | 1986 ++++---- > .../generic_templates/ulp_template_db_enum.h | 91 +- > .../generic_templates/ulp_template_db_tbl.c | 3946 ++++++++++++---- > .../ulp_template_db_thor_act.c | 150 +- > .../ulp_template_db_thor_class.c | 909 ++-- > .../ulp_template_db_wh_plus_act.c | 336 +- > .../ulp_template_db_wh_plus_class.c | 222 +- > drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 8 +- > drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 12 +- > drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 2 +- > drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 20 +- > drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +- > drivers/net/bnxt/tf_ulp/ulp_port_db.c | 23 + > drivers/net/bnxt/tf_ulp/ulp_port_db.h | 13 + > drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 32 +- > drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +- > 41 files changed, 10223 insertions(+), 4038 deletions(-) > > -- > 2.30.1 (Apple Git-130) > > ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde ` (20 preceding siblings ...) 2021-11-03 3:40 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 01/22] net/bnxt: add NAT support for dest IP and port combination Ajit Khaparde ` (23 more replies) 21 siblings, 24 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev [-- Attachment #1: Type: text/plain, Size: 4635 bytes --] Enhancements include: * Scaling numbers on Thor * Inner IP header support for GRE tunnel flows * Enable wildcard match for ingress flows * Add clear on read for flow stats on Thor * Add nat support for dest IP and port combination * Remove 2-slice WC support * Add support for socket redirect feature * Add new API TruFlow get SRAM resources * Remove accumulation of stats devargs argument * Add TruFlow and AFM SRAM partitioning support V2: * Compilation fixes * Remove 2-slice WC support * Add support for socket redirect feature * Add new API TruFlow get SRAM resources * Remove accumulation of stats devargs argument * Add TruFlow and AFM SRAM partitioning support V3: * Added one more patch (use enum for bank ID) V4: * Fixed typos in patch 2/20 * Fix checkpatch warnings * Updated commit logs * Rebased the patches to latest dpdk-next-net V5: * Split couple of patches into cleanup and code change patch * Fixed typo in some patches * Address review comments * Rebased patches to latest dpdk-next-net Ajit Khaparde (2): net/bnxt: remove unused functions net/bnxt: enable wildcard match for ingress flows Farah Smith (1): net/bnxt: add clear on read support Jay Ding (5): net/bnxt: get TruFlow version net/bnxt: add new TruFlow API to get SRAM resources net/bnxt: add TruFlow and AFM SRAM partitioning support net/bnxt: add Tx TruFlow table config for P4 device net/bnxt: use enum for bank ID Kishore Padmanabha (11): net/bnxt: add NAT support for dest IP and port combination net/bnxt: add support for multi root capability net/bnxt: fix out of bounds issue in hash list net/bnxt: add capability option for socket redirect net/bnxt: address ISO C90 compilation error net/bnxt: support inner IP header for GRE tunnel flows net/bnxt: remove devargs for stats accumulation net/bnxt: update log messages in TruFlow path net/bnxt: add support for socket direct feature net/bnxt: modify VF representor alloc sequence net/bnxt: check mismatch of control and physical port Mike Baucom (1): net/bnxt: remove 2 slice wildcard entries Shahaji Bhosle (2): net/bnxt: increase flow scale for Thor net/bnxt: fix clang compiler warnings drivers/net/bnxt/bnxt.h | 25 +- drivers/net/bnxt/bnxt_cpr.c | 2 +- drivers/net/bnxt/bnxt_ethdev.c | 274 +- drivers/net/bnxt/bnxt_hwrm.c | 36 + drivers/net/bnxt/bnxt_hwrm.h | 1 + drivers/net/bnxt/bnxt_reps.c | 9 +- drivers/net/bnxt/hsi_struct_def_dpdk.h | 4061 ++++++++++++++--- drivers/net/bnxt/tf_core/tf_core.c | 197 + drivers/net/bnxt/tf_core/tf_core.h | 202 + drivers/net/bnxt/tf_core/tf_device.c | 11 +- drivers/net/bnxt/tf_core/tf_device.h | 102 + drivers/net/bnxt/tf_core/tf_device_p4.c | 178 +- drivers/net/bnxt/tf_core/tf_device_p4.h | 137 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 421 +- drivers/net/bnxt/tf_core/tf_device_p58.h | 205 +- drivers/net/bnxt/tf_core/tf_msg.c | 87 +- drivers/net/bnxt/tf_core/tf_msg.h | 31 +- drivers/net/bnxt/tf_core/tf_rm.c | 3 +- drivers/net/bnxt/tf_core/tf_sram_mgr.h | 10 - drivers/net/bnxt/tf_core/tf_tbl.c | 83 +- drivers/net/bnxt/tf_core/tf_tbl_sram.c | 13 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 59 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 9 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 29 +- .../generic_templates/ulp_template_db_act.c | 376 +- .../generic_templates/ulp_template_db_class.c | 1986 ++++---- .../generic_templates/ulp_template_db_enum.h | 91 +- .../generic_templates/ulp_template_db_tbl.c | 3946 ++++++++++++---- .../ulp_template_db_thor_act.c | 150 +- .../ulp_template_db_thor_class.c | 909 ++-- .../ulp_template_db_wh_plus_act.c | 336 +- .../ulp_template_db_wh_plus_class.c | 222 +- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 8 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 12 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 20 +- drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_port_db.c | 23 + drivers/net/bnxt/tf_ulp/ulp_port_db.h | 13 + drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 32 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +- 41 files changed, 10250 insertions(+), 4065 deletions(-) -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 01/22] net/bnxt: add NAT support for dest IP and port combination 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 02/22] net/bnxt: add support for multi root capability Ajit Khaparde ` (22 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev Cc: Kishore Padmanabha, Venkat Duvvuru, Shahaji Bhosle, Mike Baucom, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 40738 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> * Added support for NAT action for destination IP and port combination for Thor devices. * Consolidated the encapsulation and NAT entries for scaling flows with NAT actions. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- .../generic_templates/ulp_template_db_act.c | 376 +++++++++++------- .../generic_templates/ulp_template_db_enum.h | 18 +- .../generic_templates/ulp_template_db_tbl.c | 14 +- .../ulp_template_db_thor_class.c | 2 +- .../ulp_template_db_wh_plus_act.c | 96 +++-- 5 files changed, 317 insertions(+), 189 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c index 0da6070d7d..ce878d8e02 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon May 17 15:30:41 2021 */ +/* date: Wed Aug 25 14:37:06 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -47,59 +47,67 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { [BNXT_ULP_ACT_HID_04bc] = 30, [BNXT_ULP_ACT_HID_00a9] = 31, [BNXT_ULP_ACT_HID_020f] = 32, - [BNXT_ULP_ACT_HID_04a9] = 33, - [BNXT_ULP_ACT_HID_01fc] = 34, - [BNXT_ULP_ACT_HID_04be] = 35, - [BNXT_ULP_ACT_HID_00ab] = 36, - [BNXT_ULP_ACT_HID_0211] = 37, - [BNXT_ULP_ACT_HID_04ab] = 38, - [BNXT_ULP_ACT_HID_01fe] = 39, - [BNXT_ULP_ACT_HID_0667] = 40, - [BNXT_ULP_ACT_HID_0254] = 41, - [BNXT_ULP_ACT_HID_03ba] = 42, - [BNXT_ULP_ACT_HID_0654] = 43, - [BNXT_ULP_ACT_HID_03a7] = 44, - [BNXT_ULP_ACT_HID_0669] = 45, - [BNXT_ULP_ACT_HID_0256] = 46, - [BNXT_ULP_ACT_HID_03bc] = 47, - [BNXT_ULP_ACT_HID_0656] = 48, - [BNXT_ULP_ACT_HID_03a9] = 49, - [BNXT_ULP_ACT_HID_021b] = 50, - [BNXT_ULP_ACT_HID_021c] = 51, - [BNXT_ULP_ACT_HID_021e] = 52, - [BNXT_ULP_ACT_HID_063f] = 53, - [BNXT_ULP_ACT_HID_0510] = 54, - [BNXT_ULP_ACT_HID_03c6] = 55, - [BNXT_ULP_ACT_HID_0082] = 56, - [BNXT_ULP_ACT_HID_06bb] = 57, - [BNXT_ULP_ACT_HID_021d] = 58, - [BNXT_ULP_ACT_HID_0641] = 59, - [BNXT_ULP_ACT_HID_0512] = 60, - [BNXT_ULP_ACT_HID_03c8] = 61, - [BNXT_ULP_ACT_HID_0084] = 62, - [BNXT_ULP_ACT_HID_06bd] = 63, - [BNXT_ULP_ACT_HID_06d7] = 64, - [BNXT_ULP_ACT_HID_02c4] = 65, - [BNXT_ULP_ACT_HID_042a] = 66, - [BNXT_ULP_ACT_HID_06c4] = 67, - [BNXT_ULP_ACT_HID_0417] = 68, - [BNXT_ULP_ACT_HID_06d9] = 69, - [BNXT_ULP_ACT_HID_02c6] = 70, - [BNXT_ULP_ACT_HID_042c] = 71, - [BNXT_ULP_ACT_HID_06c6] = 72, - [BNXT_ULP_ACT_HID_0419] = 73, - [BNXT_ULP_ACT_HID_0119] = 74, - [BNXT_ULP_ACT_HID_046f] = 75, - [BNXT_ULP_ACT_HID_05d5] = 76, - [BNXT_ULP_ACT_HID_0106] = 77, - [BNXT_ULP_ACT_HID_05c2] = 78, - [BNXT_ULP_ACT_HID_011b] = 79, - [BNXT_ULP_ACT_HID_0471] = 80, - [BNXT_ULP_ACT_HID_05d7] = 81, - [BNXT_ULP_ACT_HID_0108] = 82, - [BNXT_ULP_ACT_HID_05c4] = 83, - [BNXT_ULP_ACT_HID_00a2] = 84, - [BNXT_ULP_ACT_HID_00a4] = 85 + [BNXT_ULP_ACT_HID_0153] = 33, + [BNXT_ULP_ACT_HID_04a9] = 34, + [BNXT_ULP_ACT_HID_01fc] = 35, + [BNXT_ULP_ACT_HID_04be] = 36, + [BNXT_ULP_ACT_HID_00ab] = 37, + [BNXT_ULP_ACT_HID_0211] = 38, + [BNXT_ULP_ACT_HID_0155] = 39, + [BNXT_ULP_ACT_HID_04ab] = 40, + [BNXT_ULP_ACT_HID_01fe] = 41, + [BNXT_ULP_ACT_HID_0667] = 42, + [BNXT_ULP_ACT_HID_0254] = 43, + [BNXT_ULP_ACT_HID_03ba] = 44, + [BNXT_ULP_ACT_HID_02fe] = 45, + [BNXT_ULP_ACT_HID_0654] = 46, + [BNXT_ULP_ACT_HID_03a7] = 47, + [BNXT_ULP_ACT_HID_0669] = 48, + [BNXT_ULP_ACT_HID_0256] = 49, + [BNXT_ULP_ACT_HID_03bc] = 50, + [BNXT_ULP_ACT_HID_0300] = 51, + [BNXT_ULP_ACT_HID_0656] = 52, + [BNXT_ULP_ACT_HID_03a9] = 53, + [BNXT_ULP_ACT_HID_021b] = 54, + [BNXT_ULP_ACT_HID_021c] = 55, + [BNXT_ULP_ACT_HID_021e] = 56, + [BNXT_ULP_ACT_HID_063f] = 57, + [BNXT_ULP_ACT_HID_0510] = 58, + [BNXT_ULP_ACT_HID_03c6] = 59, + [BNXT_ULP_ACT_HID_0082] = 60, + [BNXT_ULP_ACT_HID_06bb] = 61, + [BNXT_ULP_ACT_HID_021d] = 62, + [BNXT_ULP_ACT_HID_0641] = 63, + [BNXT_ULP_ACT_HID_0512] = 64, + [BNXT_ULP_ACT_HID_03c8] = 65, + [BNXT_ULP_ACT_HID_0084] = 66, + [BNXT_ULP_ACT_HID_06bd] = 67, + [BNXT_ULP_ACT_HID_06d7] = 68, + [BNXT_ULP_ACT_HID_02c4] = 69, + [BNXT_ULP_ACT_HID_042a] = 70, + [BNXT_ULP_ACT_HID_036e] = 71, + [BNXT_ULP_ACT_HID_06c4] = 72, + [BNXT_ULP_ACT_HID_0417] = 73, + [BNXT_ULP_ACT_HID_06d9] = 74, + [BNXT_ULP_ACT_HID_02c6] = 75, + [BNXT_ULP_ACT_HID_042c] = 76, + [BNXT_ULP_ACT_HID_0370] = 77, + [BNXT_ULP_ACT_HID_06c6] = 78, + [BNXT_ULP_ACT_HID_0419] = 79, + [BNXT_ULP_ACT_HID_0119] = 80, + [BNXT_ULP_ACT_HID_046f] = 81, + [BNXT_ULP_ACT_HID_05d5] = 82, + [BNXT_ULP_ACT_HID_0519] = 83, + [BNXT_ULP_ACT_HID_0106] = 84, + [BNXT_ULP_ACT_HID_05c2] = 85, + [BNXT_ULP_ACT_HID_011b] = 86, + [BNXT_ULP_ACT_HID_0471] = 87, + [BNXT_ULP_ACT_HID_05d7] = 88, + [BNXT_ULP_ACT_HID_051b] = 89, + [BNXT_ULP_ACT_HID_0108] = 90, + [BNXT_ULP_ACT_HID_05c4] = 91, + [BNXT_ULP_ACT_HID_00a2] = 92, + [BNXT_ULP_ACT_HID_00a4] = 93 }; /* Array for the act matcher list */ @@ -429,22 +437,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 3 }, [33] = { - .act_hid = BNXT_ULP_ACT_HID_04a9, + .act_hid = BNXT_ULP_ACT_HID_0153, .act_pattern_id = 3, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [34] = { - .act_hid = BNXT_ULP_ACT_HID_01fc, + .act_hid = BNXT_ULP_ACT_HID_04a9, .act_pattern_id = 4, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | @@ -452,40 +458,63 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 3 }, [35] = { - .act_hid = BNXT_ULP_ACT_HID_04be, + .act_hid = BNXT_ULP_ACT_HID_01fc, .act_pattern_id = 5, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [36] = { - .act_hid = BNXT_ULP_ACT_HID_00ab, + .act_hid = BNXT_ULP_ACT_HID_04be, .act_pattern_id = 6, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [37] = { - .act_hid = BNXT_ULP_ACT_HID_0211, + .act_hid = BNXT_ULP_ACT_HID_00ab, .act_pattern_id = 7, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [38] = { - .act_hid = BNXT_ULP_ACT_HID_04ab, + .act_hid = BNXT_ULP_ACT_HID_0211, .act_pattern_id = 8, .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [39] = { + .act_hid = BNXT_ULP_ACT_HID_0155, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [40] = { + .act_hid = BNXT_ULP_ACT_HID_04ab, + .act_pattern_id = 10, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -494,9 +523,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [39] = { + [41] = { .act_hid = BNXT_ULP_ACT_HID_01fe, - .act_pattern_id = 9, + .act_pattern_id = 11, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -507,9 +536,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [40] = { + [42] = { .act_hid = BNXT_ULP_ACT_HID_0667, - .act_pattern_id = 10, + .act_pattern_id = 12, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -517,9 +546,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [41] = { + [43] = { .act_hid = BNXT_ULP_ACT_HID_0254, - .act_pattern_id = 11, + .act_pattern_id = 13, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -528,9 +557,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [42] = { + [44] = { .act_hid = BNXT_ULP_ACT_HID_03ba, - .act_pattern_id = 12, + .act_pattern_id = 14, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -538,9 +567,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [43] = { + [45] = { + .act_hid = BNXT_ULP_ACT_HID_02fe, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [46] = { .act_hid = BNXT_ULP_ACT_HID_0654, - .act_pattern_id = 13, + .act_pattern_id = 16, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -550,9 +590,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [44] = { + [47] = { .act_hid = BNXT_ULP_ACT_HID_03a7, - .act_pattern_id = 14, + .act_pattern_id = 17, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -563,9 +603,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [45] = { + [48] = { .act_hid = BNXT_ULP_ACT_HID_0669, - .act_pattern_id = 15, + .act_pattern_id = 18, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -574,9 +614,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [46] = { + [49] = { .act_hid = BNXT_ULP_ACT_HID_0256, - .act_pattern_id = 16, + .act_pattern_id = 19, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -586,9 +626,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [47] = { + [50] = { .act_hid = BNXT_ULP_ACT_HID_03bc, - .act_pattern_id = 17, + .act_pattern_id = 20, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -597,9 +637,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [48] = { + [51] = { + .act_hid = BNXT_ULP_ACT_HID_0300, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [52] = { .act_hid = BNXT_ULP_ACT_HID_0656, - .act_pattern_id = 18, + .act_pattern_id = 22, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -610,9 +662,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [49] = { + [53] = { .act_hid = BNXT_ULP_ACT_HID_03a9, - .act_pattern_id = 19, + .act_pattern_id = 23, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -624,7 +676,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [50] = { + [54] = { .act_hid = BNXT_ULP_ACT_HID_021b, .act_pattern_id = 0, .app_sig = 0, @@ -632,7 +684,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [51] = { + [55] = { .act_hid = BNXT_ULP_ACT_HID_021c, .act_pattern_id = 1, .app_sig = 0, @@ -641,7 +693,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [52] = { + [56] = { .act_hid = BNXT_ULP_ACT_HID_021e, .act_pattern_id = 2, .app_sig = 0, @@ -651,7 +703,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [53] = { + [57] = { .act_hid = BNXT_ULP_ACT_HID_063f, .act_pattern_id = 3, .app_sig = 0, @@ -662,7 +714,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [54] = { + [58] = { .act_hid = BNXT_ULP_ACT_HID_0510, .act_pattern_id = 4, .app_sig = 0, @@ -672,7 +724,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [55] = { + [59] = { .act_hid = BNXT_ULP_ACT_HID_03c6, .act_pattern_id = 5, .app_sig = 0, @@ -681,7 +733,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [56] = { + [60] = { .act_hid = BNXT_ULP_ACT_HID_0082, .act_pattern_id = 6, .app_sig = 0, @@ -693,7 +745,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [57] = { + [61] = { .act_hid = BNXT_ULP_ACT_HID_06bb, .act_pattern_id = 7, .app_sig = 0, @@ -704,7 +756,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [58] = { + [62] = { .act_hid = BNXT_ULP_ACT_HID_021d, .act_pattern_id = 8, .app_sig = 0, @@ -713,7 +765,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [59] = { + [63] = { .act_hid = BNXT_ULP_ACT_HID_0641, .act_pattern_id = 9, .app_sig = 0, @@ -725,7 +777,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [60] = { + [64] = { .act_hid = BNXT_ULP_ACT_HID_0512, .act_pattern_id = 10, .app_sig = 0, @@ -736,7 +788,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [61] = { + [65] = { .act_hid = BNXT_ULP_ACT_HID_03c8, .act_pattern_id = 11, .app_sig = 0, @@ -746,7 +798,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [62] = { + [66] = { .act_hid = BNXT_ULP_ACT_HID_0084, .act_pattern_id = 12, .app_sig = 0, @@ -759,7 +811,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [63] = { + [67] = { .act_hid = BNXT_ULP_ACT_HID_06bd, .act_pattern_id = 13, .app_sig = 0, @@ -771,7 +823,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [64] = { + [68] = { .act_hid = BNXT_ULP_ACT_HID_06d7, .act_pattern_id = 0, .app_sig = 0, @@ -780,7 +832,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [65] = { + [69] = { .act_hid = BNXT_ULP_ACT_HID_02c4, .act_pattern_id = 1, .app_sig = 0, @@ -790,7 +842,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [66] = { + [70] = { .act_hid = BNXT_ULP_ACT_HID_042a, .act_pattern_id = 2, .app_sig = 0, @@ -799,10 +851,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [67] = { - .act_hid = BNXT_ULP_ACT_HID_06c4, + [71] = { + .act_hid = BNXT_ULP_ACT_HID_036e, .act_pattern_id = 3, .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [72] = { + .act_hid = BNXT_ULP_ACT_HID_06c4, + .act_pattern_id = 4, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | @@ -810,9 +872,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [68] = { + [73] = { .act_hid = BNXT_ULP_ACT_HID_0417, - .act_pattern_id = 4, + .act_pattern_id = 5, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -822,9 +884,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [69] = { + [74] = { .act_hid = BNXT_ULP_ACT_HID_06d9, - .act_pattern_id = 5, + .act_pattern_id = 6, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -832,9 +894,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [70] = { + [75] = { .act_hid = BNXT_ULP_ACT_HID_02c6, - .act_pattern_id = 6, + .act_pattern_id = 7, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -843,9 +905,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [71] = { + [76] = { .act_hid = BNXT_ULP_ACT_HID_042c, - .act_pattern_id = 7, + .act_pattern_id = 8, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -853,9 +915,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [72] = { + [77] = { + .act_hid = BNXT_ULP_ACT_HID_0370, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [78] = { .act_hid = BNXT_ULP_ACT_HID_06c6, - .act_pattern_id = 8, + .act_pattern_id = 10, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -865,9 +938,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [73] = { + [79] = { .act_hid = BNXT_ULP_ACT_HID_0419, - .act_pattern_id = 9, + .act_pattern_id = 11, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -878,9 +951,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [74] = { + [80] = { .act_hid = BNXT_ULP_ACT_HID_0119, - .act_pattern_id = 10, + .act_pattern_id = 12, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -888,9 +961,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [75] = { + [81] = { .act_hid = BNXT_ULP_ACT_HID_046f, - .act_pattern_id = 11, + .act_pattern_id = 13, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -899,9 +972,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [76] = { + [82] = { .act_hid = BNXT_ULP_ACT_HID_05d5, - .act_pattern_id = 12, + .act_pattern_id = 14, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -909,9 +982,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [77] = { + [83] = { + .act_hid = BNXT_ULP_ACT_HID_0519, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [84] = { .act_hid = BNXT_ULP_ACT_HID_0106, - .act_pattern_id = 13, + .act_pattern_id = 16, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -921,9 +1005,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [78] = { + [85] = { .act_hid = BNXT_ULP_ACT_HID_05c2, - .act_pattern_id = 14, + .act_pattern_id = 17, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -934,9 +1018,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [79] = { + [86] = { .act_hid = BNXT_ULP_ACT_HID_011b, - .act_pattern_id = 15, + .act_pattern_id = 18, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -945,9 +1029,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [80] = { + [87] = { .act_hid = BNXT_ULP_ACT_HID_0471, - .act_pattern_id = 16, + .act_pattern_id = 19, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -957,9 +1041,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [81] = { + [88] = { .act_hid = BNXT_ULP_ACT_HID_05d7, - .act_pattern_id = 17, + .act_pattern_id = 20, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -968,9 +1052,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [82] = { + [89] = { + .act_hid = BNXT_ULP_ACT_HID_051b, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [90] = { .act_hid = BNXT_ULP_ACT_HID_0108, - .act_pattern_id = 18, + .act_pattern_id = 22, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -981,9 +1077,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [83] = { + [91] = { .act_hid = BNXT_ULP_ACT_HID_05c4, - .act_pattern_id = 19, + .act_pattern_id = 23, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -995,7 +1091,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [84] = { + [92] = { .act_hid = BNXT_ULP_ACT_HID_00a2, .act_pattern_id = 0, .app_sig = 0, @@ -1004,7 +1100,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [85] = { + [93] = { .act_hid = BNXT_ULP_ACT_HID_00a4, .act_pattern_id = 1, .app_sig = 0, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index c016e1940a..fcd460e707 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 20 17:59:14 2021 */ +/* date: Thu Aug 26 17:43:36 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -20,7 +20,7 @@ #define BNXT_ULP_CLASS_HID_SHFTL 28 #define BNXT_ULP_CLASS_HID_MASK 65535 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 -#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86 +#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 94 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 #define BNXT_ULP_ACT_HID_HIGH_PRIME 3793 #define BNXT_ULP_ACT_HID_SHFTR 27 @@ -29,7 +29,7 @@ #define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110 #define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50 -#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278 +#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 277 #define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 @@ -50,11 +50,11 @@ #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313 #define ULP_THOR_CLASS_COND_LIST_SIZE 55 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 -#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35 +#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1 #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536 -#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39 +#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 41 #define ULP_THOR_ACT_TMPL_LIST_SIZE 7 #define ULP_THOR_ACT_TBL_LIST_SIZE 36 #define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16 @@ -2224,21 +2224,25 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_04bc = 0x04bc, BNXT_ULP_ACT_HID_00a9 = 0x00a9, BNXT_ULP_ACT_HID_020f = 0x020f, + BNXT_ULP_ACT_HID_0153 = 0x0153, BNXT_ULP_ACT_HID_04a9 = 0x04a9, BNXT_ULP_ACT_HID_01fc = 0x01fc, BNXT_ULP_ACT_HID_04be = 0x04be, BNXT_ULP_ACT_HID_00ab = 0x00ab, BNXT_ULP_ACT_HID_0211 = 0x0211, + BNXT_ULP_ACT_HID_0155 = 0x0155, BNXT_ULP_ACT_HID_04ab = 0x04ab, BNXT_ULP_ACT_HID_01fe = 0x01fe, BNXT_ULP_ACT_HID_0667 = 0x0667, BNXT_ULP_ACT_HID_0254 = 0x0254, BNXT_ULP_ACT_HID_03ba = 0x03ba, + BNXT_ULP_ACT_HID_02fe = 0x02fe, BNXT_ULP_ACT_HID_0654 = 0x0654, BNXT_ULP_ACT_HID_03a7 = 0x03a7, BNXT_ULP_ACT_HID_0669 = 0x0669, BNXT_ULP_ACT_HID_0256 = 0x0256, BNXT_ULP_ACT_HID_03bc = 0x03bc, + BNXT_ULP_ACT_HID_0300 = 0x0300, BNXT_ULP_ACT_HID_0656 = 0x0656, BNXT_ULP_ACT_HID_03a9 = 0x03a9, BNXT_ULP_ACT_HID_021b = 0x021b, @@ -2258,21 +2262,25 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_06d7 = 0x06d7, BNXT_ULP_ACT_HID_02c4 = 0x02c4, BNXT_ULP_ACT_HID_042a = 0x042a, + BNXT_ULP_ACT_HID_036e = 0x036e, BNXT_ULP_ACT_HID_06c4 = 0x06c4, BNXT_ULP_ACT_HID_0417 = 0x0417, BNXT_ULP_ACT_HID_06d9 = 0x06d9, BNXT_ULP_ACT_HID_02c6 = 0x02c6, BNXT_ULP_ACT_HID_042c = 0x042c, + BNXT_ULP_ACT_HID_0370 = 0x0370, BNXT_ULP_ACT_HID_06c6 = 0x06c6, BNXT_ULP_ACT_HID_0419 = 0x0419, BNXT_ULP_ACT_HID_0119 = 0x0119, BNXT_ULP_ACT_HID_046f = 0x046f, BNXT_ULP_ACT_HID_05d5 = 0x05d5, + BNXT_ULP_ACT_HID_0519 = 0x0519, BNXT_ULP_ACT_HID_0106 = 0x0106, BNXT_ULP_ACT_HID_05c2 = 0x05c2, BNXT_ULP_ACT_HID_011b = 0x011b, BNXT_ULP_ACT_HID_0471 = 0x0471, BNXT_ULP_ACT_HID_05d7 = 0x05d7, + BNXT_ULP_ACT_HID_051b = 0x051b, BNXT_ULP_ACT_HID_0108 = 0x0108, BNXT_ULP_ACT_HID_05c4 = 0x05c4, BNXT_ULP_ACT_HID_00a2 = 0x00a2, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 684fa66f48..84be09b368 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Aug 17 12:16:42 2021 */ +/* date: Thu Aug 26 17:43:36 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -2121,7 +2121,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 2048 }, { .app_id = 0, @@ -2249,7 +2249,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 2048 }, { .app_id = 0, @@ -2263,14 +2263,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, - .count = 32 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 272 diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 68c1e292b2..95205a2421 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 20 18:05:25 2021 */ +/* date: Wed Aug 25 16:41:37 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c index 578ede8bba..4a2d201c2d 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Jun 1 16:05:30 2021 */ +/* date: Wed Aug 25 14:37:06 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -35,7 +35,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { /* act_tid: 3, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, + .num_tbls = 7, .start_tbl_idx = 12, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, @@ -46,30 +46,30 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, - .start_tbl_idx = 18, + .start_tbl_idx = 19, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 20, + .cond_start_idx = 21, .cond_nums = 0 } }, /* act_tid: 5, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 23, + .num_tbls = 7, + .start_tbl_idx = 24, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 28, + .cond_start_idx = 29, .cond_nums = 0 } }, /* act_tid: 6, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, - .start_tbl_idx = 29, + .start_tbl_idx = 31, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 0 } } }; @@ -322,6 +322,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 34, .result_num_fields = 2 }, + { /* act_tid: 3, , table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 15, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, { /* act_tid: 3, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, @@ -332,7 +343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 15, + .cond_start_idx = 16, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -351,7 +362,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 16, + .cond_start_idx = 17, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, @@ -370,7 +381,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, + .cond_start_idx = 18, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, @@ -389,7 +400,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, @@ -410,7 +421,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 18, + .cond_start_idx = 19, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -429,7 +440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 19, + .cond_start_idx = 20, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -449,7 +460,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 21, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -468,7 +479,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 21, + .cond_start_idx = 22, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -489,7 +500,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 23, + .cond_start_idx = 24, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -508,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 25, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -528,7 +539,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 26, + .cond_start_idx = 27, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -538,6 +549,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 11 }, + { /* act_tid: 5, , table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 29, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, { /* act_tid: 5, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, @@ -548,7 +570,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 28, + .cond_start_idx = 30, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -567,7 +589,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, + .cond_start_idx = 31, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, @@ -586,7 +608,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 32, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, @@ -605,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 33, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, @@ -626,7 +648,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, + .cond_start_idx = 33, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -645,7 +667,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, + .cond_start_idx = 34, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -665,7 +687,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -684,7 +706,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 36, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, @@ -705,7 +727,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 37, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, @@ -726,7 +748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 38, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -747,7 +769,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 39, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -766,7 +788,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, + .cond_start_idx = 40, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -844,6 +866,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, + /* cond_execute: act_tid: 3, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, @@ -900,6 +927,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN }, + /* cond_execute: act_tid: 5, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 02/22] net/bnxt: add support for multi root capability 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 01/22] net/bnxt: add NAT support for dest IP and port combination Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 03/22] net/bnxt: fix out of bounds issue in hash list Ajit Khaparde ` (21 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Mike Baucom, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 195484 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Update driver to read the multi root capability and ignore pci address check while creating ulp session when multi root capability is enabled in the hardware. DPDK HSI version updated from 1.10.2.44 to 1.10.2.68. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/bnxt.h | 3 + drivers/net/bnxt/bnxt_hwrm.c | 8 + drivers/net/bnxt/hsi_struct_def_dpdk.h | 4061 ++++++++++++++++++++---- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 10 +- 4 files changed, 3523 insertions(+), 559 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 39bd739c7b..97e281a2fc 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -723,6 +723,9 @@ struct bnxt { uint16_t chip_num; #define CHIP_NUM_58818 0xd818 #define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818) +#define BNXT_FLAGS2_MULTIROOT_EN BIT(4) +#define BNXT_MULTIROOT_EN(bp) \ + ((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN) uint32_t fw_cap; #define BNXT_FW_CAP_HOT_RESET BIT(0) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 3fefd558d8..94a7daf632 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -3363,6 +3363,7 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp) { struct hwrm_func_qcfg_input req = {0}; struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; + uint16_t flags; int rc; if (!BNXT_VF_IS_TRUSTED(bp)) @@ -3386,6 +3387,13 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp) bp->parent->fid = rte_le_to_cpu_16(resp->fid); bp->parent->port_id = rte_le_to_cpu_16(resp->port_id); + flags = rte_le_to_cpu_16(resp->flags); + /* check for the multi-root support */ + if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) { + bp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN; + PMD_DRV_LOG(DEBUG, "PF enabled with multi root capability\n"); + } + HWRM_UNLOCK(); return 0; diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 4d7efb19f4..0c08171dec 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -657,6 +657,12 @@ struct cmd_nums { #define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0) /* PTP - Query extended PTP configuration. */ #define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1) + /* The command is used to allocate KTLS crypto key contexts. */ + #define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2) + /* The is the new API to configure backing stores. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2 UINT32_C(0x1a3) + /* The is the new API to query backing store configurations. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2 UINT32_C(0x1a4) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -714,6 +720,18 @@ struct cmd_nums { * calculated during firmware boot. */ #define HWRM_MFG_GET_NVM_MEASUREMENT UINT32_C(0x214) + /* Retrieves the PSOC status and provisioning information. */ + #define HWRM_MFG_PSOC_QSTATUS UINT32_C(0x215) + /* + * This command allows manufacturing tool to determine which selftests + * are available to be run. + */ + #define HWRM_MFG_SELFTEST_QLIST UINT32_C(0x216) + /* + * This command allows manufacturing tool to request which selftests + * to run. + */ + #define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217) /* Experimental */ #define HWRM_TF UINT32_C(0x2bc) /* Experimental */ @@ -1056,8 +1074,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 44 -#define HWRM_VERSION_STR "1.10.2.44" +#define HWRM_VERSION_RSVD 68 +#define HWRM_VERSION_STR "1.10.2.68" /**************** * hwrm_ver_get * @@ -1357,6 +1375,12 @@ struct hwrm_ver_get_output { */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \ UINT32_C(0x4000) + /* + * If set to 1, then firmware supports secure boot. + * If set to 0, then firmware doesn't support secure boot. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE \ + UINT32_C(0x8000) /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. @@ -1449,7 +1473,7 @@ struct hwrm_ver_get_output { * backing store not been available. * For Example, PCIe hot-plug: * Hot plug timing is system dependent. It generally takes up to - * 600 miliseconds for firmware to clear DEV_NOT_RDY flag. + * 600 milliseconds for firmware to clear DEV_NOT_RDY flag. * If set to 0, device is ready to accept all HWRM commands. */ #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY \ @@ -2263,7 +2287,7 @@ struct crypto_presync_bd_cmd { uint32_t end_tcp_seq_num; /* * For TLS1.2, an explicit nonce is used as part of the IV (concatenated - * with the SALT). For retans packets, this field is extracted from the + * with the SALT). For retrans packets, this field is extracted from the * TLS record, field right after the TLS Header and stored in the * context. This field needs to be stored in context as TCP segmentation * could have split the field into multiple TCP packets. This value is @@ -3497,10 +3521,10 @@ struct cfa_cmpls_cmp_data_msg { #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK \ UINT32_C(0xf0000000) #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 28 - /* TX configrable flow processing block. */ + /* TX configurable flow processing block. */ #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA \ (UINT32_C(0x2) << 28) - /* RX configrable flow processing block. */ + /* RX configurable flow processing block. */ #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA \ (UINT32_C(0x3) << 28) #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \ @@ -8283,8 +8307,14 @@ struct hwrm_async_event_cmpl_reset_notify { /* Fast reset */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \ (UINT32_C(0x4) << 8) + /* + * Reset was a result of a firmware activation. That is, the + * fw_activation flag was set in a FW_RESET operation. + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION \ + (UINT32_C(0x5) << 8) #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION /* * Minimum time before driver should attempt access - units 100ms ticks. * Range 0-65535 @@ -10244,8 +10274,21 @@ struct hwrm_async_event_cmpl_error_report_base { */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \ UINT32_C(0x2) + /* + * There was a low level error with an NVM write or erase. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM \ + UINT32_C(0x3) + /* + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD } __rte_packed; /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ @@ -10386,6 +10429,162 @@ struct hwrm_async_event_cmpl_error_report_invalid_signal { HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL } __rte_packed; +/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_nvm { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Indicates the address where error was detected */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK \ + UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT \ + 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * There was a low level error with an NVM operation. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR + /* The specific type of NVM error */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT \ + 8 + /* + * There was a low level error with an NVM write operation. + * Verification of written data did not match. + * event_data2 will be the failing address. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE \ + (UINT32_C(0x1) << 8) + /* + * There was a low level error with an NVM erase operation. + * All the bits were not erased. + * event_data2 will be the failing address. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE \ + (UINT32_C(0x2) << 8) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT \ + 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD +} __rte_packed; + /* metadata_base_msg (size:64b/8B) */ struct metadata_base_msg { uint16_t md_type_link; @@ -11204,6 +11403,18 @@ struct hwrm_func_vf_cfg_input { */ #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ UINT32_C(0x800) + /* + * This bit must be '1' for the num_tx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the num_rx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS \ + UINT32_C(0x2000) /* * The maximum transmission unit requested on the function. * The HWRM should make sure that the mtu of @@ -11353,7 +11564,10 @@ struct hwrm_func_vf_cfg_input { uint16_t num_stat_ctxs; /* The number of HW ring groups requested for the VF. */ uint16_t num_hw_ring_grps; - uint8_t unused_0[4]; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; } __rte_packed; /* hwrm_func_vf_cfg_output (size:128b/16B) */ @@ -11423,7 +11637,7 @@ struct hwrm_func_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcaps_output (size:704b/88B) */ +/* hwrm_func_qcaps_output (size:768b/96B) */ struct hwrm_func_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -11787,7 +12001,13 @@ struct hwrm_func_qcaps_output { * (max_tx_rings) to the function. */ uint16_t max_sp_tx_rings; - uint8_t unused_0[2]; + /* + * The maximum number of MSI-X vectors that may be allocated across + * all VFs for the function. This is valid only on the PF with SR-IOV + * enabled. Returns zero if this command is called on a PF with + * SR-IOV disabled or on a VF. + */ + uint16_t max_msix_vfs; uint32_t flags_ext; /* * If 1, the device can be configured to set the ECN bits in the @@ -11911,7 +12131,9 @@ struct hwrm_func_qcaps_output { UINT32_C(0x80000) /* * When this bit is '1', the NIC supports configuration of - * partition_min_bw and partition_max_bw. + * partition_min_bw and partition_max_bw. Configuration of a + * minimum guaranteed bandwidth is only supported if the + * min_bw_supported flag is also set. */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PARTITION_BW_SUPPORTED \ UINT32_C(0x100000) @@ -11928,10 +12150,39 @@ struct hwrm_func_qcaps_output { * When this bit is '1', the firmware supports HWRM_PORT_EP_TX_CFG * and HWRM_PORT_EP_TX_QCFG for endpoint rate control, and additions * to HWRM_QUEUE_GLOBAL_CFG and HWRM_QUEUE_GLOBAL_QCFG for receive - * rate control. + * rate control. Configuration of a minimum guaranteed bandwidth + * is only supported if the min_bw_supported flag is also set. */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EP_RATE_CONTROL \ UINT32_C(0x800000) + /* + * When this bit is '1', the firmware supports enforcement of + * minimum guaranteed bandwidth. A minimum guaranteed bandwidth + * could be configured for a partition or for an endpoint. Firmware + * only sets this flag if one or both of the ep_rate_control and + * partition_bw_supported flags are set. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_MIN_BW_SUPPORTED \ + UINT32_C(0x1000000) + /* + * When this bit is '1', HW supports TX coalesced completion + * records. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_COAL_CMPL_CAP \ + UINT32_C(0x2000000) + /* + * When this bit is '1', it indicates the FW has full support + * for all backing store types with the BACKING_STORE_CFG/QCFG + * V2 APIs. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_SUPPORTED \ + UINT32_C(0x4000000) + /* + * When this bit is '1', it indicates the FW forces to use the + * BACKING_STORE_CFG/QCFG V2 APIs. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_REQUIRED \ + UINT32_C(0x8000000) /* The maximum number of SCHQs supported by this device. */ uint8_t max_schqs; uint8_t mpc_chnls_cap; @@ -11965,7 +12216,12 @@ struct hwrm_func_qcaps_output { * to the primate processor block. */ #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10) - uint8_t unused_1; + /* + * Maximum number of Key Contexts supported per HWRM + * function call for allocating Key Contexts. + */ + uint16_t max_key_ctxs_alloc; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12023,7 +12279,7 @@ struct hwrm_func_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcfg_output (size:832b/104B) */ +/* hwrm_func_qcfg_output (size:896b/112B) */ struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -12614,7 +12870,11 @@ struct hwrm_func_qcfg_output { * value is used if ring MTU is not specified. */ uint16_t host_mtu; - uint8_t unused_3; + /* Number of Tx Key Contexts allocated. */ + uint16_t alloc_tx_key_ctxs; + /* Number of Rx Key Contexts allocated. */ + uint16_t alloc_rx_key_ctxs; + uint8_t unused_3[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12630,7 +12890,7 @@ struct hwrm_func_qcfg_output { *****************/ -/* hwrm_func_cfg_input (size:832b/104B) */ +/* hwrm_func_cfg_input (size:896b/112B) */ struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -13076,6 +13336,18 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \ UINT32_C(0x20000000) + /* + * This bit must be '1' for the number of Tx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS \ + UINT32_C(0x40000000) + /* + * This bit must be '1' for the number of Rx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS \ + UINT32_C(0x80000000) /* * This field can be used by the admin PF to configure * mtu of foster PFs. @@ -13527,6 +13799,11 @@ struct hwrm_func_cfg_input { * ring that is assigned to a function has a valid mtu. */ uint16_t host_mtu; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; + uint8_t unused_0[4]; } __rte_packed; /* hwrm_func_cfg_output (size:128b/16B) */ @@ -13550,6 +13827,33 @@ struct hwrm_func_cfg_output { uint8_t valid; } __rte_packed; +/* hwrm_func_cfg_cmd_err (size:64b/8B) */ +struct hwrm_func_cfg_cmd_err { + /* command specific error codes for the cmd_err field in hwrm_err_output */ + uint8_t code; + /* Unknown error. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* The partition minimum bandwidth is out of range. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE \ + UINT32_C(0x1) + /* The minimum bandwidth is more than the maximum bandwidth. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX \ + UINT32_C(0x2) + /* + * The NIC does not support enforcement of a minimum guaranteed + * bandwidth for a partition. + */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED \ + UINT32_C(0x3) + /* Partition bandwidths must be specified as a percentage. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT \ + UINT32_C(0x4) + #define HWRM_FUNC_CFG_CMD_ERR_CODE_LAST \ + HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT + uint8_t unused_0[7]; +} __rte_packed; + /******************** * hwrm_func_qstats * ********************/ @@ -14103,6 +14407,13 @@ struct hwrm_func_drv_rgtr_input { */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \ UINT32_C(0x100) + /* + * When this bit is 1, the function's driver is indicating the + * support of handling the NPAR 1.2 feature where the s-tag may be + * a value other than 0x8100 or 0x88a8. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \ + UINT32_C(0x200) uint32_t enables; /* * This bit must be '1' for the os_type field to be @@ -14664,7 +14975,7 @@ struct hwrm_func_resource_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_resource_qcaps_output (size:448b/56B) */ +/* hwrm_func_resource_qcaps_output (size:512b/64B) */ struct hwrm_func_resource_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -14739,6 +15050,14 @@ struct hwrm_func_resource_qcaps_output { */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output @@ -14755,7 +15074,7 @@ struct hwrm_func_resource_qcaps_output { *****************************/ -/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ +/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ struct hwrm_func_vf_resource_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -14829,6 +15148,14 @@ struct hwrm_func_vf_resource_cfg_input { */ #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; uint8_t unused_0[2]; } __rte_packed; @@ -14858,7 +15185,11 @@ struct hwrm_func_vf_resource_cfg_output { uint16_t reserved_stat_ctx; /* Reserved number of ring groups */ uint16_t reserved_hw_ring_grps; - uint8_t unused_0[7]; + /* Actual number of Tx Key Contexts reserved */ + uint16_t reserved_tx_key_ctxs; + /* Actual number of Rx Key Contexts reserved */ + uint16_t reserved_rx_key_ctxs; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -14924,7 +15255,10 @@ struct hwrm_func_backing_store_qcaps_output { * this many QP context entries, even if RoCE will not be used. */ uint16_t qp_min_qp1_entries; - /* Maximum number of QP context entries that can be used for L2. */ + /* + * Maximum number of QP context entries that can be used for L2 and + * mid-path. + */ uint16_t qp_max_l2_entries; /* Number of bytes that must be allocated for each context entry. */ uint16_t qp_entry_size; @@ -15141,8 +15475,13 @@ struct hwrm_func_backing_store_qcaps_output { * function. */ uint32_t rkc_max_entries; + /* + * Number of mid-path TQM rings to be used for allocating + * backing stores. + */ + uint8_t mp_tqm_rings_count; /* Reserved for future. */ - uint8_t rsvd[7]; + uint8_t rsvd1[6]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18132,7 +18471,7 @@ struct hwrm_error_recovery_qcfg_output { /*************************** * hwrm_func_echo_response * - ****************************/ + ***************************/ /* hwrm_func_echo_response_input (size:192b/24B) */ @@ -18152,10 +18491,10 @@ struct hwrm_func_echo_response_input { uint16_t seq_id; /* * The target ID of the command: - * 0x0-0xFFF8 - The function ID - * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * 0xFFFD - Reserved for user-space HWRM interface - * 0xFFFF - HWRM + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ uint16_t target_id; /* @@ -18190,104 +18529,1400 @@ struct hwrm_func_echo_response_output { uint8_t valid; } __rte_packed; -/*********************** - * hwrm_func_vlan_qcfg * - ***********************/ - - -/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ -struct hwrm_func_vlan_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[6]; -} __rte_packed; - -/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ -struct hwrm_func_vlan_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint64_t unused_0; - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; - /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. - */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; - /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. - */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd2; - /* Future use. */ - uint32_t rsvd3; - uint8_t unused_3[3]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/********************** - * hwrm_func_vlan_cfg * - **********************/ +/************************** + * hwrm_func_ptp_pin_qcfg * + **************************/ -/* hwrm_func_vlan_cfg_input (size:384b/48B) */ -struct hwrm_func_vlan_cfg_input { +/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_pin_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * The number of TSIO pins that are configured on this board + * Up to 4 pins can be returned in the response. + */ + uint8_t num_pins; + /* Pin state */ + uint8_t state; + /* + * When this bit is '1', TSIO pin 0 is enabled. + * When this bit is '0', TSIO pin 0 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED \ + UINT32_C(0x1) + /* + * When this bit is '1', TSIO pin 1 is enabled. + * When this bit is '0', TSIO pin 1 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED \ + UINT32_C(0x2) + /* + * When this bit is '1', TSIO pin 2 is enabled. + * When this bit is '0', TSIO pin 2 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED \ + UINT32_C(0x4) + /* + * When this bit is '1', TSIO pin 3 is enabled. + * When this bit is '0', TSIO pin 3 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED \ + UINT32_C(0x8) + /* Type of function for Pin #0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT + /* Type of function for Pin #1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT + /* Type of function for Pin #2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT + /* Type of function for Pin #3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_func_ptp_pin_cfg * + *************************/ + + +/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_pin_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the pin0_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE \ + UINT32_C(0x1) + /* + * This bit must be '1' for the pin0_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the pin1_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the pin1_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE \ + UINT32_C(0x8) + /* + * This bit must be '1' for the pin2_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE \ + UINT32_C(0x10) + /* + * This bit must be '1' for the pin2_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE \ + UINT32_C(0x20) + /* + * This bit must be '1' for the pin3_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE \ + UINT32_C(0x40) + /* + * This bit must be '1' for the pin3_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE \ + UINT32_C(0x80) + /* Enable or disable functionality of Pin #0. */ + uint8_t pin0_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED + /* Configure function for TSIO pin#0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #1. */ + uint8_t pin1_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED + /* Configure function for TSIO pin#1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #2. */ + uint8_t pin2_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED + /* Configure function for TSIO pin#2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #3. */ + uint8_t pin3_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED + /* Configure function for TSIO pin#3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_func_ptp_cfg * + *********************/ + + +/* hwrm_func_ptp_cfg_input (size:320b/40B) */ +struct hwrm_func_ptp_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the ptp_pps_event field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT \ + UINT32_C(0x1) + /* + * This bit must be '1' for the ptp_freq_adj_dll_source field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the ptp_freq_adj_dll_phase field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the ptp_freq_adj_ext_period field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD \ + UINT32_C(0x8) + /* + * This bit must be '1' for the ptp_freq_adj_ext_up field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP \ + UINT32_C(0x10) + /* + * This bit must be '1' for the ptp_freq_adj_ext_phase field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE \ + UINT32_C(0x20) + /* This field is used to enable interrupt for a specific PPS event. */ + uint8_t ptp_pps_event; + /* + * When this bit is set to '1', interrupt is enabled for internal + * PPS event. Latches timestamp on PPS_OUT TSIO Pin. If user does + * not configure PPS_OUT on a TSIO pin, then firmware will allocate + * PPS_OUT to an unallocated pin. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL \ + UINT32_C(0x1) + /* + * When this bit is set to '1', interrupt is enabled for external + * PPS event. Latches timestamp on PPS_IN TSIO pin. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL \ + UINT32_C(0x2) + /* + * This field is used to set the source signal used to discipline + * PHC (PTP Hardware Clock) + */ + uint8_t ptp_freq_adj_dll_source; + /* No source is selected. Use servo to discipline PHC */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE \ + UINT32_C(0x0) + /* TSIO Pin #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 \ + UINT32_C(0x1) + /* TSIO Pin #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 \ + UINT32_C(0x2) + /* TSIO Pin #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 \ + UINT32_C(0x3) + /* TSIO Pin #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 \ + UINT32_C(0x4) + /* Port #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 \ + UINT32_C(0x5) + /* Port #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 \ + UINT32_C(0x6) + /* Port #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 \ + UINT32_C(0x7) + /* Port #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 \ + UINT32_C(0x8) + /* Invalid signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID \ + UINT32_C(0xff) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID + /* + * This field is used to provide phase adjustment for DLL + * used to discipline PHC (PTP Hardware clock) + */ + uint8_t ptp_freq_adj_dll_phase; + /* No Phase adjustment. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE \ + UINT32_C(0x0) + /* 4Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K \ + UINT32_C(0x1) + /* 8Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K \ + UINT32_C(0x2) + /* 10Mhz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M \ + UINT32_C(0x3) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M + uint8_t unused_0[3]; + /* + * Period in nanoseconds (ns) for external signal + * input. + */ + uint32_t ptp_freq_adj_ext_period; + /* + * Up time in nanoseconds (ns) of the duty cycle + * of the external signal. This value should be + * less than ptp_freq_adj_ext_period. + */ + uint32_t ptp_freq_adj_ext_up; + /* + * Phase value is provided. This field provides the + * least significant 32 bits of the phase input. The + * most significant 16 bits come from + * ptp_freq_adj_ext_phase_upper field. Setting this + * field requires setting ptp_freq_adj_ext_period + * field as well to identify the external signal + * pin. + */ + uint32_t ptp_freq_adj_ext_phase_lower; + /* + * Phase value is provided. The lower 16 bits of this field is used + * with the 32 bit value from ptp_freq_adj_ext_phase_lower + * to provide a 48 bit value input for Phase. + */ + uint32_t ptp_freq_adj_ext_phase_upper; +} __rte_packed; + +/* hwrm_func_ptp_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ts_query * + **************************/ + + +/* hwrm_func_ptp_ts_query_input (size:192b/24B) */ +struct hwrm_func_ptp_ts_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* If set, the response includes PPS event timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1) + /* If set, the response includes PTM timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_ptp_ts_query_output (size:320b/40B) */ +struct hwrm_func_ptp_ts_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Timestamp value of last PPS event latched. */ + uint64_t pps_event_ts; + /* PTM local timestamp value. */ + uint64_t ptm_res_local_ts; + /* PTM Master timestamp value. */ + uint64_t ptm_pmstr_ts; + /* PTM Master propagation delay */ + uint32_t ptm_mstr_prop_dly; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_func_ptp_ext_cfg * + *************************/ + + +/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_ext_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the phc_master_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the phc_sec_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the phc_sec_mode field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the failover_timer field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER \ + UINT32_C(0x8) + /* + * This field is used to configure the Master function. Only this + * function can modify or condition the PHC. Only driver calls from + * this function are allowed to adjust frequency of PHC or configure + * PPS functionality. + * If driver does not specify this FID, then firmware will auto select + * the first function that makes the call to modify PHC as the Master. + */ + uint16_t phc_master_fid; + /* + * This field is used to configure the secondary function. This + * function becomes the Master function in case of failover from + * Master function. + * If driver does not specify this FID, firmware will auto select + * the last non-master function to make a call to condition PHC as + * secondary. + */ + uint16_t phc_sec_fid; + /* + * This field is used to configure conditions under which a function + * can become a secondary function. + */ + uint8_t phc_sec_mode; + /* + * Immediately failover to the current secondary function. If there + * is no secondary function available, failover does not happen. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0) + /* + * All functions (PF and VF) can be used during auto selection + * of a secondary function. This is not used in case of admin + * configured secondary function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1) + /* + * Only PF's can be selected as a secondary function during auto + * selection. This is not used in case of admin configured secondary + * function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2) + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_LAST \ + HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY + uint8_t unused_0; + /* + * This field indicates the failover time is milliseconds. If the + * timeout expires, firmware will failover PTP configurability from + * current master to secondary fid. + * 0 - Failover timer is automatically selected based on the last + * adjFreq() call. If adjFreq() is not called for 3 * (last interval) + * the failover kicks in. For example, if last interval between + * adjFreq() calls was 2 seconds and the next adjFreq() is not made for + * at least 6 seconds, then secondary takes over as master to condition + * PHC. Firmware rounds up the failover timer to be a multiple of 250 + * ms. Firmware checks every 250 ms to see if timer expired. + * 0xFFFFFFFF - If driver specifies this value, then failover never + * happens. Admin or auto selected Master will always be used for + * conditioning PHC. + * X - If driver specifies any other value, this is admin indicated + * failover timeout. If no adjFreq() call is made within this timeout + * value, then failover happens. This value should be a multiple of + * 250 ms. Firmware checks every 250 ms to see if timer expired. + */ + uint32_t failover_timer; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_ext_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ext_qcfg * + **************************/ + + +/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_ext_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ +struct hwrm_func_ptp_ext_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Firmware returns the current PHC master function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_master_fid; + /* + * Firmware returns the current PHC secondary function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_sec_fid; + /* + * Firmware returns the last non-master/non-secondary function to + * make a call to condition PHC. + */ + uint16_t phc_active_fid0; + /* + * Firmware returns the second last non-master/non-secondary function + * to make a call to condition PHC. + */ + uint16_t phc_active_fid1; + /* + * Timestamp indicating the last time a failover happened. The master + * and secondary functions in the failover event is indicated in the + * next two fields. + */ + uint32_t last_failover_event; + /* + * Last failover happened from this function. This was the master + * function at the time of failover. + */ + uint16_t from_fid; + /* + * Last failover happened to this function. This was the secondary + * function at the time of failover. + */ + uint16_t to_fid; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_func_key_ctx_alloc * + ***************************/ + + +/* hwrm_func_key_ctx_alloc_input (size:320b/40B) */ +struct hwrm_func_key_ctx_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Function ID. */ + uint16_t fid; + /* Number of Key Contexts to be allocated. */ + uint16_t num_key_ctxs; + /* DMA buffer size in bytes. */ + uint32_t dma_bufr_size_bytes; + /* Key Context type. */ + uint8_t key_ctx_type; + /* Tx Key Context. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0) + /* Rx KTLS Context. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1) + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST \ + HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX + uint8_t unused_0[7]; + /* Host DMA address to send back KTLS context IDs. */ + uint64_t host_dma_addr; +} __rte_packed; + +/* hwrm_func_key_ctx_alloc_output (size:128b/16B) */ +struct hwrm_func_key_ctx_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Actual number of Key Contexts allocated. */ + uint16_t num_key_ctxs_allocated; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************** + * hwrm_func_backing_store_cfg_v2 * + **********************************/ + + +/* hwrm_func_backing_store_cfg_v2_input (size:320b/40B) */ +struct hwrm_func_backing_store_cfg_v2_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Type of backing store to be configured. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP \ + UINT32_C(0x0) + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ \ + UINT32_C(0x1) + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ \ + UINT32_C(0x2) + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* MRAV. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM \ + UINT32_C(0xf) + /* Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC \ + UINT32_C(0x13) + /* Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING + /* + * Instance of the backing store type. It is zero-based, + * which means "0" indicates the first instance. For backing + * stores with single instance only, leave this field to 0. + */ + uint16_t instance; + /* Control flags. */ + uint32_t flags; + /* + * When set, the firmware only uses on-chip resources and + * does not expect any backing store to be provided by the + * host driver. This mode provides minimal L2 functionality + * (e.g. limited L2 resources, no RoCE). + */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE \ + UINT32_C(0x1) + /* Page directory. */ + uint64_t page_dir; + /* Number of entries */ + uint32_t num_entries; + /* Number of bytes allocated for each entry */ + uint16_t entry_size; + /* Page size and pbl level. */ + uint8_t page_size_pbl_level; + /* PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2 + /* Page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G + uint8_t rsvd; +} __rte_packed; + +/* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */ +struct hwrm_func_backing_store_cfg_v2_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t rsvd0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been completely + * written. When writing a command completion or response to + * an internal processor, the order of writes has to be such + * that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************************** + * hwrm_func_backing_store_qcfg_v2 * + ***********************************/ + + +/* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */ +struct hwrm_func_backing_store_qcfg_v2_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Type of backing store to be configured. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QP \ + UINT32_C(0x0) + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ \ + UINT32_C(0x1) + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ \ + UINT32_C(0x2) + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* MRAV. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM \ + UINT32_C(0xf) + /* Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TKC \ + UINT32_C(0x13) + /* Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING + /* + * Instance of the backing store type. It is zero-based, + * which means "0" indicates the first instance. For backing + * stores with single instance only, leave this field to 0. + */ + uint16_t instance; + uint8_t rsvd[4]; +} __rte_packed; + +/* hwrm_func_backing_store_qcfg_v2_output (size:256b/32B) */ +struct hwrm_func_backing_store_qcfg_v2_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Type of backing store to be configured. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QP \ + UINT32_C(0x0) + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRQ \ + UINT32_C(0x1) + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CQ \ + UINT32_C(0x2) + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* MRAV. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM \ + UINT32_C(0xf) + /* Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TKC \ + UINT32_C(0x13) + /* Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING + /* + * Instance of the backing store type. It is zero-based, + * which means "0" indicates the first instance. For backing + * stores with single instance only, leave this field to 0. + */ + uint16_t instance; + /* Control flags. */ + uint32_t flags; + /* Page directory. */ + uint64_t page_dir; + /* Number of entries */ + uint32_t num_entries; + /* Page size and pbl level. */ + uint8_t page_size_pbl_level; + /* PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2 + /* Page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G + uint8_t rsvd[2]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been completely + * written. When writing a command completion or response to + * an internal processor, the order of writes has to be such + * that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_func_vlan_qcfg * + ***********************/ + + +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ +struct hwrm_func_vlan_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ +struct hwrm_func_vlan_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint64_t unused_0; + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd2; + /* Future use. */ + uint32_t rsvd3; + uint8_t unused_3[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_vlan_cfg * + **********************/ + + +/* hwrm_func_vlan_cfg_input (size:384b/48B) */ +struct hwrm_func_vlan_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -19853,7 +21488,7 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0) /* Full duplex will be requested. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1) - /* Both Half and Full dupex will be requested. */ + /* Both Half and Full duplex will be requested. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2) #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \ HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH @@ -20690,20 +22325,44 @@ struct hwrm_port_phy_qcfg_output { /* 1G_baseCX */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \ UINT32_C(0x1b) - /* 100G_BASECR4 */ + /* 200G_BASECR4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \ UINT32_C(0x1c) - /* 100G_BASESR4 */ + /* 200G_BASESR4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \ UINT32_C(0x1d) - /* 100G_BASELR4 */ + /* 200G_BASELR4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \ UINT32_C(0x1e) - /* 100G_BASEER4 */ + /* 200G_BASEER4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \ UINT32_C(0x1f) + /* 50G_BASECR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASECR \ + UINT32_C(0x20) + /* 50G_BASESR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASESR \ + UINT32_C(0x21) + /* 50G_BASELR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASELR \ + UINT32_C(0x22) + /* 50G_BASEER */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASEER \ + UINT32_C(0x23) + /* 100G_BASECR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR2 \ + UINT32_C(0x24) + /* 100G_BASESR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR2 \ + UINT32_C(0x25) + /* 100G_BASELR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR2 \ + UINT32_C(0x26) + /* 100G_BASEER2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 \ + UINT32_C(0x27) #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 + HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 /* This value represents a media type. */ uint8_t media_type; /* Unknown */ @@ -20780,7 +22439,7 @@ struct hwrm_port_phy_qcfg_output { * the speed of the link partner. * * Parallel detection is used when a autonegotiation capable - * device is connected to a link parter that is not capable + * device is connected to a link partner that is not capable * of autonegotiation. */ uint8_t parallel_detect; @@ -20789,7 +22448,7 @@ struct hwrm_port_phy_qcfg_output { * the speed of the link partner. * * Parallel detection is used when a autonegotiation capable - * device is connected to a link parter that is not capable + * device is connected to a link partner that is not capable * of autonegotiation. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1) @@ -21398,6 +23057,12 @@ struct hwrm_port_mac_cfg_input { */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \ UINT32_C(0x200) + /* + * This bit must be '1' for the ptp_adj_phase field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE \ + UINT32_C(0x400) /* Port ID of port that is to be configured. */ uint16_t port_id; /* @@ -21590,7 +23255,12 @@ struct hwrm_port_mac_cfg_input { * of sync timer updates (measured in parts per billion). */ int32_t ptp_freq_adj_ppb; - uint8_t unused_1[4]; + /* + * This unsigned field specifies the phase offset to be applied + * to the PHC (PTP Hardware Clock). This field is specified in + * nanoseconds. + */ + uint32_t ptp_adj_phase; } __rte_packed; /* hwrm_port_mac_cfg_output (size:128b/16B) */ @@ -21741,7 +23411,7 @@ struct hwrm_port_mac_qcfg_output { * indicates higher priority. * For example, a value of 0-3 is returned where 0 is being * the lowest priority and 3 is being the highest priority. - * # If the correspoding CoS mapping is not enabled, then this + * # If the corresponding CoS mapping is not enabled, then this * field should be ignored. * # This value indicates the normalized priority value retained * in the HWRM. @@ -21790,7 +23460,7 @@ struct hwrm_port_mac_qcfg_output { * indicates higher priority. * For example, a value of 0-3 is returned where 0 is being * the lowest priority and 3 is being the highest priority. - * # If the correspoding CoS mapping is not enabled, then this + * # If the corresponding CoS mapping is not enabled, then this * field should be ignored. * # This value indicates the normalized priority value retained * in the HWRM. @@ -21804,7 +23474,7 @@ struct hwrm_port_mac_qcfg_output { * indicates higher priority. * For example, a value of 0-3 is returned where 0 is being * the lowest priority and 3 is being the highest priority. - * # If the correspoding CoS mapping is not enabled, then this + * # If the corresponding CoS mapping is not enabled, then this * field should be ignored. * # This value indicates the normalized priority value retained * in the HWRM. @@ -21991,7 +23661,7 @@ struct hwrm_port_mac_ptp_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ +/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ struct hwrm_port_mac_ptp_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -22024,10 +23694,23 @@ struct hwrm_port_mac_ptp_qcfg_output { */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ UINT32_C(0x8) + /* + * When this bit is set to '1', two specific registers for current + * time (ts_ref_clock_reg_lower and ts_ref_clock_reg_upper) are + * directly accessible by the host. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK \ + UINT32_C(0x10) uint8_t unused_0[3]; - /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for RX. */ uint32_t rx_ts_reg_off_seq_id; @@ -22045,9 +23728,15 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t rx_ts_reg_off_fifo_adv; /* PTP timestamp granularity for RX. */ uint32_t rx_ts_reg_off_granularity; - /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for TX. */ uint32_t tx_ts_reg_off_seq_id; @@ -22055,6 +23744,10 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t tx_ts_reg_off_fifo; /* PTP timestamp granularity for TX. */ uint32_t tx_ts_reg_off_granularity; + /* Offset of register to get lower 32 bits of current time. */ + uint32_t ts_ref_clock_reg_lower; + /* Offset of register to get upper 32 bits of current time. */ + uint32_t ts_ref_clock_reg_upper; uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output @@ -22082,7 +23775,7 @@ struct tx_port_stats { /* Total Number of 1024-1518 Bytes frames transmitted */ uint64_t tx_1024b_1518b_frames; /* - * Total Number of each good VLAN (exludes FCS errors) + * Total Number of each good VLAN (excludes FCS errors) * frame transmitted which is 1519 to 1522 bytes in length * inclusive (excluding framing bits but including FCS bytes). */ @@ -22223,7 +23916,7 @@ struct rx_port_stats { /* Total Number of 1024-1518 Bytes frames received */ uint64_t rx_1024b_1518b_frames; /* - * Total Number of each good VLAN (exludes FCS errors) + * Total Number of each good VLAN (excludes FCS errors) * frame received which is 1519 to 1522 bytes in length * inclusive (excluding framing bits but including FCS bytes). */ @@ -22578,7 +24271,7 @@ struct tx_port_stats_ext { } __rte_packed; /* Port Rx Statistics extended Format */ -/* rx_port_stats_ext (size:3648b/456B) */ +/* rx_port_stats_ext (size:3776b/472B) */ struct rx_port_stats_ext { /* Number of times link state changed to down */ uint64_t link_down_events; @@ -22660,7 +24353,7 @@ struct rx_port_stats_ext { uint64_t rx_buffer_passed_threshold; /* * The number of symbol errors that wasn't corrected by FEC correction - * alogirithm + * algorithm */ uint64_t rx_pcs_symbol_err; /* The number of corrected bits on the port according to active FEC */ @@ -22697,6 +24390,13 @@ struct rx_port_stats_ext { uint64_t rx_discard_packets_cos6; /* Total number of rx discard packets count on cos queue 7 */ uint64_t rx_discard_packets_cos7; + /* Total number of FEC blocks corrected by the FEC function in the PHY */ + uint64_t rx_fec_corrected_blocks; + /* + * Total number of FEC blocks determined to be uncorrectable by the + * FEC function in the PHY + */ + uint64_t rx_fec_uncorrectable_blocks; } __rte_packed; /* @@ -23718,8 +25418,10 @@ struct hwrm_port_phy_qcaps_output { #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3) /* 4-port device */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4) + /* 12-port device */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12 UINT32_C(0xc) #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \ - HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 + HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12 /* * This is a bit mask to indicate what speeds are supported * as forced speeds on this link. @@ -23823,7 +25525,7 @@ struct hwrm_port_phy_qcaps_output { * for EEE on this link. * For each speed that can be autonegotiated when EEE is enabled * on this link, the corresponding mask bit shall be set to '1'. - * This field is only valid when the eee_suppotred is set to '1'. + * This field is only valid when the eee_supported is set to '1'. */ uint16_t supported_speeds_eee_mode; /* Reserved */ @@ -23901,7 +25603,28 @@ struct hwrm_port_phy_qcaps_output { UINT32_C(0x2) #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G \ UINT32_C(0x4) - uint8_t unused_0[3]; + /* More PHY capability flags */ + uint16_t flags2; + /* + * If set to 1, then this field indicates that + * 802.3x flow control is not supported. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED \ + UINT32_C(0x1) + /* + * If set to 1, then this field indicates that + * priority-based flow control is not supported. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED \ + UINT32_C(0x2) + /* + * Number of internal ports for this device. This field allows the FW + * to advertise how many internal ports are present. Manufacturing + * tools uses this to determine how many internal ports should have + * the PRBS test run on them. This field always return 0 unless NVM + * option "HPTN_MODE" is set to 1. + */ + uint8_t internal_port_cnt; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -25190,7 +26913,13 @@ struct hwrm_port_prbs_test_input { * use this entire buffer or less than the entire buffer, but never more. */ uint16_t data_len; - uint16_t unused_0; + uint16_t flags; + /* + * If set, the port_id field should be interpreted as an internal + * port. The internal port id range is returned in port_phy_qcaps + * response internal_port_cnt field. + */ + #define HWRM_PORT_PRBS_TEST_INPUT_FLAGS_INTERNAL UINT32_C(0x1) uint32_t unused_1; /* Port ID of port where PRBS test to be run. */ uint16_t port_id; @@ -25487,14 +27216,14 @@ struct hwrm_port_sfp_sideband_cfg_input { /* * This bit along with rs1 configures the current speed of the dual * rate module. If these pins are GNDed then the speed can be changed - * by driectly writing to EEPROM. + * by directly writing to EEPROM. */ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \ UINT32_C(0x1) /* * This bit along with rs0 configures the current speed of the dual * rate module. If these pins are GNDed then the speed can be changed - * by driectly writing to EEPROM. + * by directly writing to EEPROM. */ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \ UINT32_C(0x2) @@ -25618,16 +27347,16 @@ struct hwrm_port_sfp_sideband_qcfg_output { #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \ UINT32_C(0x2) /* - * This bit along with rs1 indiactes the current speed of the dual + * This bit along with rs1 indicates the current speed of the dual * rate module.If these pins are grounded then the speed can be - * changed by driectky writing to EEPROM. + * changed by directly writing to EEPROM. */ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \ UINT32_C(0x4) /* - * This bit along with rs0 indiactes the current speed of the dual + * This bit along with rs0 indicates the current speed of the dual * rate module.If these pins are grounded then the speed can be - * changed by driectky writing to EEPROM. + * changed by directly writing to EEPROM. */ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \ UINT32_C(0x8) @@ -25981,6 +27710,315 @@ struct hwrm_port_tx_fir_qcfg_output { uint8_t valid; } __rte_packed; +/*********************** + * hwrm_port_ep_tx_cfg * + ***********************/ + + +/* hwrm_port_ep_tx_cfg_input (size:256b/32B) */ +struct hwrm_port_ep_tx_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* When this bit is '1', the value in the ep0_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1) + /* When this bit is '1', the value in the ep0_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2) + /* When this bit is '1', the value in the ep1_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4) + /* When this bit is '1', the value in the ep1_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8) + /* When this bit is '1', the value in the ep2_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10) + /* When this bit is '1', the value in the ep2_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20) + /* When this bit is '1', the value in the ep3_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40) + /* When this bit is '1', the value in the ep3_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80) + /* A port index, from 0 to the number of front panel ports, minus 1. */ + uint8_t port_id; + uint8_t unused; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set of + * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of + * the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_output (size:128b/16B) */ +struct hwrm_port_ep_tx_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_cmd_err (size:64b/8B) */ +struct hwrm_port_ep_tx_cfg_cmd_err { + /* + * command specific error codes for the cmd_err field in + * hwrm_err_output + */ + uint8_t code; + /* Unknown error. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* The port ID is invalid */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID \ + UINT32_C(0x1) + /* One of the PCIe endpoints configured is not active. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE \ + UINT32_C(0x2) + /* A minimum bandwidth is out of range. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE \ + UINT32_C(0x3) + /* + * One endpoint's minimum bandwidth is more than its maximum + * bandwidth. + */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX \ + UINT32_C(0x4) + /* The sum of the minimum bandwidths on the port is more than 100%. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM \ + UINT32_C(0x5) + /* + * The NIC does not support enforcement of a minimum guaranteed + * bandwidth for an endpoint. + */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED \ + UINT32_C(0x6) + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_LAST \ + HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED + uint8_t unused_0[7]; +} __rte_packed; + +/************************ + * hwrm_port_ep_tx_qcfg * + ************************/ + + +/* hwrm_port_ep_tx_qcfg_input (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The port whose endpoint rate limits are queried. */ + uint8_t port_id; + uint8_t unused[7]; +} __rte_packed; + +/* hwrm_port_ep_tx_qcfg_output (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /*********************** * hwrm_queue_qportcfg * ***********************/ @@ -26097,6 +28135,13 @@ struct hwrm_queue_qportcfg_output { */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ UINT32_C(0x1) + /* + * If this flag is set to '1', then service_profile will carry + * either lossy/lossless type and the new service_profile_type + * field will be used to determine if the queue is for L2/ROCE/CNP. + */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE \ + UINT32_C(0x2) /* * Bitmask indicating which queues can be configured by the * hwrm_queue_pfcenable_cfg command. @@ -30198,17 +32243,409 @@ struct hwrm_queue_vlanpri2pri_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure VLAN priority to user priority mapping on this port. - */ - uint8_t port_id; - uint8_t unused_0[7]; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure VLAN priority to user priority mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ +struct hwrm_queue_vlanpri2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * User priority assigned to VLAN priority 0. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri0_user_pri_id; + /* + * User priority assigned to VLAN priority 1. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri1_user_pri_id; + /* + * User priority assigned to VLAN priority 2. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri2_user_pri_id; + /* + * User priority assigned to VLAN priority 3. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri3_user_pri_id; + /* + * User priority assigned to VLAN priority 4. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri4_user_pri_id; + /* + * User priority assigned to VLAN priority 5. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri5_user_pri_id; + /* + * User priority assigned to VLAN priority 6. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri6_user_pri_id; + /* + * User priority assigned to VLAN priority 7. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri7_user_pri_id; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_queue_vlanpri2pri_cfg * + ******************************/ + + +/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ +struct hwrm_queue_vlanpri2pri_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vlanpri0_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the vlanpri1_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the vlanpri2_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vlanpri3_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the vlanpri4_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the vlanpri5_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the vlanpri6_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the vlanpri7_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ + UINT32_C(0x80) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure VLAN priority to user priority mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[3]; + /* + * User priority assigned to VLAN priority 0. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri0_user_pri_id; + /* + * User priority assigned to VLAN priority 1. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri1_user_pri_id; + /* + * User priority assigned to VLAN priority 2. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri2_user_pri_id; + /* + * User priority assigned to VLAN priority 3. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri3_user_pri_id; + /* + * User priority assigned to VLAN priority 4. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri4_user_pri_id; + /* + * User priority assigned to VLAN priority 5. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri5_user_pri_id; + /* + * User priority assigned to VLAN priority 6. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri6_user_pri_id; + /* + * User priority assigned to VLAN priority 7. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri7_user_pri_id; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_vlanpri2pri_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_queue_global_cfg * + *************************/ + + +/* hwrm_queue_global_cfg_input (size:192b/24B) */ +struct hwrm_queue_global_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. + */ + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0) + /* + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT + uint8_t unused_0; + uint16_t enables; + /* This bit must be '1' when the mode field is configured. */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1) + /* + * This bit must be '1' when the maximum bandwidth for queue group 0 + * (g0_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2) + /* + * This bit must be '1' when the maximum bandwidth for queue group 1 + * (g1_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4) + /* + * This bit must be '1' when the maximum bandwidth for queue group 2 + * (g2_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8) + /* + * This bit must be '1' when the maximum bandwidth for queue group 3 + * (g3_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW \ + UINT32_C(0x10) + /* + * Specifies the maximum receive rate, as a percentage of total link + * bandwidth, of the receive traffic through queue group 0. A value + * of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. + */ + uint8_t g0_max_bw; + /* + * Specifies the maximum rate of the traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. + */ + uint8_t g1_max_bw; + /* + * Specifies the maximum rate of the traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. + */ + uint8_t g2_max_bw; + /* + * Specifies the maximum receive rate, in Mbps, of the receive traffic + * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0 + * indicates no rate limit. + */ + uint8_t g3_max_bw; +} __rte_packed; + +/* hwrm_queue_global_cfg_output (size:128b/16B) */ +struct hwrm_queue_global_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_queue_global_qcfg * + **************************/ + + +/* hwrm_queue_global_qcfg_input (size:128b/16B) */ +struct hwrm_queue_global_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; } __rte_packed; -/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ -struct hwrm_queue_vlanpri2pri_qcfg_output { +/* hwrm_queue_global_qcfg_output (size:320b/40B) */ +struct hwrm_queue_global_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30217,209 +32654,95 @@ struct hwrm_queue_vlanpri2pri_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Port or PCIe endpoint id to be mapped for buffer pool 0. */ + uint8_t buffer_pool_id0_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 1. */ + uint8_t buffer_pool_id1_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 2. */ + uint8_t buffer_pool_id2_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 3. */ + uint8_t buffer_pool_id3_map; + /* Size of buffer pool 0 (KBytes). */ + uint32_t buffer_pool_id0_size; + /* Size of buffer pool 1 (KBytes). */ + uint32_t buffer_pool_id1_size; + /* Size of buffer pool 2 (KBytes). */ + uint32_t buffer_pool_id2_size; + /* Size of buffer pool 3 (KBytes). */ + uint32_t buffer_pool_id3_size; + uint16_t flags; /* - * User priority assigned to VLAN priority 0. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri0_user_pri_id; - /* - * User priority assigned to VLAN priority 1. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri1_user_pri_id; - /* - * User priority assigned to VLAN priority 2. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri2_user_pri_id; - /* - * User priority assigned to VLAN priority 3. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri3_user_pri_id; - /* - * User priority assigned to VLAN priority 4. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri4_user_pri_id; - /* - * User priority assigned to VLAN priority 5. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri5_user_pri_id; - /* - * User priority assigned to VLAN priority 6. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri6_user_pri_id; - /* - * User priority assigned to VLAN priority 7. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. - */ - uint8_t vlanpri7_user_pri_id; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/****************************** - * hwrm_queue_vlanpri2pri_cfg * - ******************************/ - - -/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ -struct hwrm_queue_vlanpri2pri_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Enumeration denoting whether the rx buffer pool mapping is + * per port or per PCIe endpoint */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the vlanpri0_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING \ UINT32_C(0x1) /* - * This bit must be '1' for the vlanpri1_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ - UINT32_C(0x2) - /* - * This bit must be '1' for the vlanpri2_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ - UINT32_C(0x4) - /* - * This bit must be '1' for the vlanpri3_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ - UINT32_C(0x8) - /* - * This bit must be '1' for the vlanpri4_user_pri_id field to be - * configured. + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a port. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ - UINT32_C(0x10) - /* - * This bit must be '1' for the vlanpri5_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ - UINT32_C(0x20) - /* - * This bit must be '1' for the vlanpri6_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ - UINT32_C(0x40) - /* - * This bit must be '1' for the vlanpri7_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ - UINT32_C(0x80) - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure VLAN priority to user priority mapping on this port. - */ - uint8_t port_id; - uint8_t unused_0[3]; - /* - * User priority assigned to VLAN priority 0. This value can only - * be changed before traffic has started. - */ - uint8_t vlanpri0_user_pri_id; + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT \ + UINT32_C(0x0) /* - * User priority assigned to VLAN priority 1. This value can only - * be changed before traffic has started. + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a PCIe endpoint. */ - uint8_t vlanpri1_user_pri_id; + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT \ + UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT /* - * User priority assigned to VLAN priority 2. This value can only - * be changed before traffic has started. + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. */ - uint8_t vlanpri2_user_pri_id; + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0) /* - * User priority assigned to VLAN priority 3. This value can only - * be changed before traffic has started. + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues */ - uint8_t vlanpri3_user_pri_id; + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT + uint8_t unused_0; /* - * User priority assigned to VLAN priority 4. This value can only - * be changed before traffic has started. + * Reports the rate limit applied to traffic through receive CoS queue + * group 0. The rate limit is a percentage of total link bandwidth. A + * value of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. */ - uint8_t vlanpri4_user_pri_id; + uint8_t g0_max_bw; /* - * User priority assigned to VLAN priority 5. This value can only - * be changed before traffic has started. + * Reports the rate limit applied to traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. */ - uint8_t vlanpri5_user_pri_id; + uint8_t g1_max_bw; /* - * User priority assigned to VLAN priority 6. This value can only - * be changed before traffic has started. + * Reports the rate limit applied to traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. */ - uint8_t vlanpri6_user_pri_id; + uint8_t g2_max_bw; /* - * User priority assigned to VLAN priority 7. This value can only - * be changed before traffic has started. + * Reports the rate limit applied to traffic through receive CoS queue + * group 3 (for port 3 or PCIe endpoint 3). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. */ - uint8_t vlanpri7_user_pri_id; -} __rte_packed; - -/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_vlanpri2pri_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint8_t g3_max_bw; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -30567,6 +32890,12 @@ struct hwrm_vnic_update_input { */ #define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID \ UINT32_C(0x4) + /* + * This bit must be '1' for the rss_hash_function field to be + * configured. + */ + #define HWRM_VNIC_UPDATE_INPUT_ENABLES_RSS_HASH_FUNCTION_VALID \ + UINT32_C(0x8) /* * This will update the context variable with the same name if * the corresponding enable is set. @@ -30612,7 +32941,32 @@ struct hwrm_vnic_update_input { * the mru of the port the function is associated with. */ uint16_t mru; - uint8_t unused_1[4]; + /* + * Used to choose the RSS hash algorithm based on which HW + * can select the destination ring + */ + uint8_t rss_hash_function; + /* + * NIC calculates the RSS hash using the Toeplitz algorithm on L3/L4 + * headers and uses the hash to select the ring. + */ + #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_TOEPLITZ UINT32_C(0x0) + /* + * NIC calculates the RSS hash using the XOR algorithm on L3/L4 + * headers and uses the hash to select the ring. + */ + #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_XOR UINT32_C(0x1) + /* + * In this mode, RSS hash is calculated with Toeplitz and reported + * in the RX completion. However, the ring selection algorithm is + * based on the checksum. In this mode, only the innermost L3/L4 + * packet checksums are used. So this hash function mode will not + * be exposed/valid when the outer RSS mode is enabled. + */ + #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_CHECKSUM UINT32_C(0x2) + #define HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_LAST \ + HWRM_VNIC_UPDATE_INPUT_RSS_HASH_FUNCTION_CHECKSUM + uint8_t unused_1[3]; } __rte_packed; /* hwrm_vnic_update_output (size:128b/16B) */ @@ -31282,7 +33636,7 @@ struct hwrm_vnic_qcaps_output { * ability to steer incoming packets from one CoS queue to one * VNIC. This optional feature can then be enabled * using HWRM_VNIC_CFG on any VNIC. This feature is only - * available when NVM option “enable_cos_classfication” is set + * available when NVM option “enable_cos_classification” is set * to 1. If set to '0', firmware does not support this feature. */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \ @@ -31292,7 +33646,7 @@ struct hwrm_vnic_qcaps_output { * the use of RX V2 and RX TPA start V2 completion records for all * the RX rings of a VNIC. Once set, this feature is mandatory to * be used for the RX rings of the VNIC. Additionally, two new RX - * checksum features supported by these ompletion records can be + * checksum features supported by these completion records can be * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the * HW and the firmware does not support this feature. */ @@ -31324,6 +33678,48 @@ struct hwrm_vnic_qcaps_output { */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \ UINT32_C(0x1000) + /* + * When this bit is set '1', it indicates that firmware returns + * INVALID_PARAM error, if host drivers choose invalid hash type + * bit combinations in vnic_rss_cfg. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP \ + UINT32_C(0x2000) + /* + * When this bit is set '1', it indicates that firmware supports + * the hash_type include and exclude flags in hwrm_vnic_rss_cfg. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_TYPE_DELTA_CAP \ + UINT32_C(0x4000) + /* + * When this bit is '1', it indicates that HW is capable + * of calculating the RSS hash using Toeplitz algorithm. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_FUNCTION_TOEPLITZ_CAP \ + UINT32_C(0x8000) + /* + * When this bit is '1', it indicates that HW is capable + * of calculating the RSS hash using XOR algorithm. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_FUNCTION_XOR_CAP \ + UINT32_C(0x10000) + /* + * When this bit is '1', it indicates that HW is capable + * of using checksum algorithm. + * In this mode, RSS hash is calculated with Toeplitz and reported + * in the RX completion. However, the ring selection algorithm is + * based on the checksum. In this mode, only the innermost L3/L4 + * packet checksums are used. So this hash function mode will not + * be exposed/valid when the outer RSS mode is enabled. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_FUNCTION_CHKSM_CAP \ + UINT32_C(0x20000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPV6 flow labels. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPV6_FLOW_LABEL_CAP \ + UINT32_C(0x40000) /* * This field advertises the maximum concurrent TPA aggregations * supported by the VNIC on new devices that support TPA v2. @@ -31603,7 +33999,7 @@ struct hwrm_vnic_rss_cfg_input { #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) /* * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 + * over source and destination IPv6 addresses of IPv6 * packets. */ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) @@ -31674,7 +34070,62 @@ struct hwrm_vnic_rss_cfg_input { uint64_t hash_key_tbl_addr; /* Index to the rss indirection table. */ uint16_t rss_ctx_idx; - uint8_t unused_1[6]; + uint8_t flags; + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to add to the current + * hash. Zeroes designate the hash_type state bits that should remain + * unchanged, if possible. If this constraint on the existing state + * cannot be satisfied, then the implementation should preference + * adding other headers so as to honor the request to add the + * specified headers. It is an error to set this flag concurrently + * with hash_type_exclude. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to remove from the + * current hash. Zeroes designate the hash_type state bits that + * should remain unchanged, if possible. If this constraint on the + * existing state cannot be satisfied, then the implementation should + * preference removing other headers so as to honor the request to + * remove the specified headers. It is an error to set this flag + * concurrently with hash_type_include. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE \ + UINT32_C(0x2) + /* + * Used to choose the RSS hash algorithm based on which HW + * can select the destination ring + */ + uint8_t rss_hash_function; + /* + * NIC calculates the RSS hash using the Toeplitz algorithm on L3/L4 + * headers and uses the hash to select the ring. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_TOEPLITZ \ + UINT32_C(0x0) + /* + * NIC calculates the RSS hash using the XOR algorithm on L3/L4 + * headers and uses the hash to select the ring. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_XOR \ + UINT32_C(0x1) + /* + * In this mode, RSS hash is calculated with Toeplitz and reported + * in the RX completion. However, the ring selection algorithm is + * based on the checksum. In this mode, only the innermost L3/L4 + * packet checksums are used. So this hash function mode will not + * be exposed/valid when the outer RSS mode is enabled. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_CHECKSUM \ + UINT32_C(0x2) + #define HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_LAST \ + HWRM_VNIC_RSS_CFG_INPUT_RSS_HASH_FUNCTION_CHECKSUM + uint8_t unused_1[4]; } __rte_packed; /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ @@ -31790,7 +34241,7 @@ struct hwrm_vnic_rss_qcfg_output { #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) /* * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 + * over source and destination IPv6 addresses of IPv6 * packets. */ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) @@ -31851,7 +34302,35 @@ struct hwrm_vnic_rss_qcfg_output { */ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ UINT32_C(0x10) - uint8_t unused_1[6]; + /* + * Used to choose the RSS hash algorithm based on which HW + * can select the destination ring + */ + uint8_t rss_hash_function; + /* + * NIC calculates the RSS hash using the Toeplitz algorithm on L3/L4 + * headers and uses the hash to select the ring. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_TOEPLITZ \ + UINT32_C(0x0) + /* + * NIC calculates the RSS hash using the XOR algorithm on L3/L4 + * headers and uses the hash to select the ring. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_XOR \ + UINT32_C(0x1) + /* + * In this mode, RSS hash is calculated with Toeplitz and reported + * in the RX completion. However, the ring selection algorithm is + * based on the checksum. In this mode, only the innermost L3/L4 + * packet checksums are used. So this hash function mode will not + * be exposed/valid when the outer RSS mode is enabled. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_CHECKSUM \ + UINT32_C(0x2) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_LAST \ + HWRM_VNIC_RSS_QCFG_OUTPUT_RSS_HASH_FUNCTION_CHECKSUM + uint8_t unused_1[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -32426,7 +34905,47 @@ struct hwrm_ring_alloc_input { #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5) #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \ HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ - uint8_t unused_0; + /* + * This field controls the number of packets transmitted before a TX + * completion is generated. Non-zero values for the field are only + * valid if HWRM_FUNC_QCAPS indicates that the TX coalesced completion + * records capability is supported. + */ + uint8_t cmpl_coal_cnt; + /* Generates a legacy TX completion on every packet. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF UINT32_C(0x0) + /* Generates a TX coalesced completion for up to 4 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_4 UINT32_C(0x1) + /* Generates a TX coalesced completion for up to 8 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_8 UINT32_C(0x2) + /* Generates a TX coalesced completion for up to 12 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_12 UINT32_C(0x3) + /* Generates a TX coalesced completion for up to 16 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_16 UINT32_C(0x4) + /* Generates a TX coalesced completion for up to 24 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_24 UINT32_C(0x5) + /* Generates a TX coalesced completion for up to 32 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_32 UINT32_C(0x6) + /* Generates a TX coalesced completion for up to 48 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_48 UINT32_C(0x7) + /* Generates a TX coalesced completion for up to 64 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_64 UINT32_C(0x8) + /* Generates a TX coalesced completion for up to 96 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_96 UINT32_C(0x9) + /* Generates a TX coalesced completion for up to 128 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_128 UINT32_C(0xa) + /* Generates a TX coalesced completion for up to 192 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_192 UINT32_C(0xb) + /* Generates a TX coalesced completion for up to 256 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_256 UINT32_C(0xc) + /* Generates a TX coalesced completion for up to 320 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_320 UINT32_C(0xd) + /* Generates a TX coalesced completion for up to 384 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_384 UINT32_C(0xe) + /* Generates a TX coalesced completion up to the last packet. (Maximum coalescing). */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX UINT32_C(0xf) + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_LAST \ + HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX /* Ring allocation flags. */ uint16_t flags; /* @@ -36754,6 +39273,14 @@ struct hwrm_cfa_ntuple_filter_alloc_input { */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \ UINT32_C(0x20) + /* + * Setting of this flag indicates that when the ntuple filter is + * created, the L2 context should not be used in the filter. This + * allows packet from different L2 contexts to match and be directed + * to the same destination. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_NO_L2_CONTEXT \ + UINT32_C(0x40) uint32_t enables; /* * This bit must be '1' for the l2_filter_id field to be @@ -37276,6 +39803,14 @@ struct hwrm_cfa_ntuple_filter_cfg_input { */ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \ UINT32_C(0x2) + /* + * Setting of this flag indicates that when the ntuple filter is + * created, the L2 context should not be used in the filter. This + * allows packet from different L2 contexts to match and be directed + * to the same destination. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_NO_L2_CONTEXT \ + UINT32_C(0x4) /* This value is an opaque id into CFA data structures. */ uint64_t ntuple_filter_id; /* @@ -39611,7 +42146,7 @@ struct hwrm_cfa_flow_alloc_cmd_err { #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3) /* No more wild-card TCAM */ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4) - /* Hash collsion in exact match tables */ + /* Hash collision in exact match tables */ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5) /* Key is already installed */ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6) @@ -42974,6 +45509,12 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_LAG_SUPPORTED \ UINT32_C(0x20000) + /* + * If set to 1, firmware is capable installing ntuple rules without + * additional classification on the L2 Context. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED \ + UINT32_C(0x40000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -43062,6 +45603,161 @@ struct hwrm_cfa_tflib_output { uint8_t valid; } __rte_packed; +/********************************** + * hwrm_cfa_lag_group_member_rgtr * + **********************************/ + + +/* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t mode; + /* + * Transmit only on the active port. Automatically failover + * to backup port. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP \ + UINT32_C(0x1) + /* + * Transmit based on packet header ntuple hash. Packet with only + * layer 2 headers will hash using the destination MAC, source MAC + * and Ethertype fields. Packets with layer 3 (IP) headers will + * hash using the destination MAC, source MAC, IP protocol/next + * header, source IP address and destination IP address. Packets + * with layer 4 (TCP/UDP) headers will hash using the destination + * MAC, source MAC, IP protocol/next header, source IP address, + * destination IP address, source port and destination port fields. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR \ + UINT32_C(0x2) + /* Transmit packets on all specified ports. */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST \ + UINT32_C(0x3) + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST \ + HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST + /* + * Supports up to 5 ports. bit0 = port 0, bit1 = port 1, + * bit2 = port 2, bit3 = port 4, bit4 = loopback port + */ + uint8_t port_bitmap; + /* Specify the active port when active-backup mode is specified */ + uint8_t active_port; + uint8_t unused_0[5]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************************ + * hwrm_cfa_lag_group_member_unrgtr * + ************************************/ + + +/* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /*********** * hwrm_tf * ***********/ @@ -43175,7 +45871,7 @@ struct hwrm_tf_version_get_input { uint64_t resp_addr; } __rte_packed; -/* hwrm_tf_version_get_output (size:128b/16B) */ +/* hwrm_tf_version_get_output (size:256b/32B) */ struct hwrm_tf_version_get_output { /* The specific error status for the command. */ uint16_t error_code; @@ -43192,7 +45888,14 @@ struct hwrm_tf_version_get_output { /* Version Update number. */ uint8_t update; /* unused. */ - uint8_t unused0[4]; + uint8_t unused0[5]; + /* + * This field is used to indicate device's capabilities and + * configurations. + */ + uint64_t dev_caps_cfg; + /* unused. */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -43263,8 +45966,13 @@ struct hwrm_tf_session_open_output { * the newly created session. */ uint32_t fw_session_client_id; + /* This field is used to return the status of fw session to host. */ uint32_t flags; - /* Indicates if the shared session has been created. */ + /* + * Indicates if the shared session has been created. Shared session + * should be the first session created ever. Its fw_rm_client_id + * should be 1. The AFM session's fw_rm_client_id is 0. + */ #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \ UINT32_C(0x1) /* @@ -43745,7 +46453,7 @@ struct hwrm_tf_session_resc_qcaps_input { #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX @@ -43802,8 +46510,13 @@ struct hwrm_tf_session_resc_qcaps_output { * qcaps_size. */ uint16_t size; + /* + * SRAM profile number that sets the partition of SRAM memory + * between TF and AFM within the 4 internal memory banks (Thor). + */ + uint8_t sram_profile; /* unused. */ - uint16_t unused0; + uint8_t unused0; /* unused. */ uint8_t unused1[7]; /* @@ -43860,7 +46573,7 @@ struct hwrm_tf_session_resc_alloc_input { #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX @@ -43959,7 +46672,7 @@ struct hwrm_tf_session_resc_free_input { #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX @@ -44043,7 +46756,7 @@ struct hwrm_tf_session_resc_flush_input { #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX @@ -44124,134 +46837,143 @@ struct hwrm_tf_session_resc_info_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX + /* + * Defines the array size of the provided req_addr and + * resv_addr array buffers. Should be set to the number of + * request entries. + */ + uint16_t req_size; + /* + * This is the DMA address for the request input data array + * buffer. Array is of tf_rm_resc_req_entry type. Size of the + * array buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t req_addr; + /* + * This is the DMA address for the resc output data array + * buffer. Array is of tf_rm_resc_entry type. Size of the array + * buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t resc_addr; +} __rte_packed; + +/* hwrm_tf_session_resc_info_output (size:128b/16B) */ +struct hwrm_tf_session_resc_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Size of the returned tf_rm_resc_entry data array. The value + * cannot exceed the req_size defined by the input msg. The data + * array is returned using the resv_addr specified DMA + * address also provided by the input msg. + */ + uint16_t size; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/* TruFlow RM capability of a resource. */ +/* tf_rm_resc_req_entry (size:64b/8B) */ +struct tf_rm_resc_req_entry { + /* Type of the resource, defined globally in HCAPI RM. */ + uint32_t type; + /* Minimum value. */ + uint16_t min; + /* Maximum value. */ + uint16_t max; +} __rte_packed; + +/* TruFlow RM reservation information. */ +/* tf_rm_resc_entry (size:64b/8B) */ +struct tf_rm_resc_entry { + /* Type of the resource, defined globally in HCAPI RM. */ + uint32_t type; + /* Start offset. */ + uint16_t start; + /* Number of resources. */ + uint16_t stride; +} __rte_packed; + +/************************ + * hwrm_tf_tbl_type_get * + ************************/ + + +/* hwrm_tf_tbl_type_get_input (size:256b/32B) */ +struct hwrm_tf_tbl_type_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX - /* - * Defines the array size of the provided req_addr and - * resv_addr array buffers. Should be set to the number of - * request entries. - */ - uint16_t req_size; - /* - * This is the DMA address for the request input data array - * buffer. Array is of tf_rm_resc_req_entry type. Size of the - * array buffer is provided by the 'req_size' field in this - * message. - */ - uint64_t req_addr; - /* - * This is the DMA address for the resc output data array - * buffer. Array is of tf_rm_resc_entry type. Size of the array - * buffer is provided by the 'req_size' field in this - * message. - */ - uint64_t resc_addr; -} __rte_packed; - -/* hwrm_tf_session_resc_info_output (size:128b/16B) */ -struct hwrm_tf_session_resc_info_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* - * Size of the returned tf_rm_resc_entry data array. The value - * cannot exceed the req_size defined by the input msg. The data - * array is returned using the resv_addr specified DMA - * address also provided by the input msg. - */ - uint16_t size; - /* unused. */ - uint8_t unused0[5]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. - */ - uint8_t valid; -} __rte_packed; - -/* TruFlow RM capability of a resource. */ -/* tf_rm_resc_req_entry (size:64b/8B) */ -struct tf_rm_resc_req_entry { - /* Type of the resource, defined globally in HCAPI RM. */ - uint32_t type; - /* Minimum value. */ - uint16_t min; - /* Maximum value. */ - uint16_t max; -} __rte_packed; - -/* TruFlow RM reservation information. */ -/* tf_rm_resc_entry (size:64b/8B) */ -struct tf_rm_resc_entry { - /* Type of the resource, defined globally in HCAPI RM. */ - uint32_t type; - /* Start offset. */ - uint16_t start; - /* Number of resources. */ - uint16_t stride; -} __rte_packed; - -/************************ - * hwrm_tf_tbl_type_get * - ************************/ - - -/* hwrm_tf_tbl_type_get_input (size:256b/32B) */ -struct hwrm_tf_tbl_type_get_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Control flags. */ - uint16_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entry on read. + */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* @@ -44337,7 +47059,7 @@ struct hwrm_tf_tbl_type_set_input { #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX @@ -44819,7 +47541,7 @@ struct hwrm_tf_ext_em_qcaps_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \ @@ -44997,7 +47719,7 @@ struct hwrm_tf_ext_em_op_input { #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX @@ -45104,7 +47826,7 @@ struct hwrm_tf_ext_em_cfg_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \ @@ -45309,7 +48031,7 @@ struct hwrm_tf_ext_em_qcfg_input { #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX @@ -45335,7 +48057,7 @@ struct hwrm_tf_ext_em_qcfg_output { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ @@ -45475,7 +48197,7 @@ struct hwrm_tf_em_insert_input { #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX @@ -45556,7 +48278,7 @@ struct hwrm_tf_em_hash_insert_input { #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX @@ -45637,13 +48359,13 @@ struct hwrm_tf_em_delete_input { #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX /* Unused0 */ uint16_t unused0; - /* EM internal flow hanndle. */ + /* EM internal flow handle. */ uint64_t flow_handle; /* EM Key value */ uint64_t em_key[8]; @@ -45785,7 +48507,7 @@ struct hwrm_tf_tcam_set_input { #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX @@ -45815,8 +48537,8 @@ struct hwrm_tf_tcam_set_input { /* unused. */ uint8_t unused0[6]; /* - * TCAM key located at offset 0, mask located at mask_offsec - * and result at result_offsec for the device. + * TCAM key located at offset 0, mask located at mask_offset + * and result at result_offset for the device. */ uint8_t dev_data[88]; } __rte_packed; @@ -45887,7 +48609,7 @@ struct hwrm_tf_tcam_get_input { #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX @@ -45923,8 +48645,8 @@ struct hwrm_tf_tcam_get_output { /* unused. */ uint8_t unused0[4]; /* - * TCAM key located at offset 0, mask located at mask_offsec - * and result at result_offsec for the device. + * TCAM key located at offset 0, mask located at mask_offset + * and result at result_offset for the device. */ uint8_t dev_data[272]; /* unused. */ @@ -45983,7 +48705,7 @@ struct hwrm_tf_tcam_move_input { #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX @@ -46066,7 +48788,7 @@ struct hwrm_tf_tcam_free_input { #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX @@ -46149,7 +48871,7 @@ struct hwrm_tf_global_cfg_set_input { #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX @@ -46233,7 +48955,7 @@ struct hwrm_tf_global_cfg_get_input { #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX @@ -46308,7 +49030,7 @@ struct hwrm_tf_if_tbl_get_input { #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX @@ -46397,7 +49119,7 @@ struct hwrm_tf_if_tbl_set_input { #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX @@ -46481,13 +49203,22 @@ struct hwrm_tf_tbl_type_bulk_get_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entries on read. + */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* @@ -48261,7 +50992,7 @@ struct hwrm_nvm_get_dir_info_output { ******************/ -/* hwrm_nvm_write_input (size:384b/48B) */ +/* hwrm_nvm_write_input (size:448b/56B) */ struct hwrm_nvm_write_input { /* The HWRM command request type. */ uint16_t req_type; @@ -48306,13 +51037,19 @@ struct hwrm_nvm_write_input { * The 0-based instance of the combined Directory Entry Type and Extension. */ uint16_t dir_ordinal; - /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */ + /* + * The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file + * bnxnvm_defs.h). + */ uint16_t dir_ext; - /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ + /* + * Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file + * bnxnvm_defs.h). + */ uint16_t dir_attr; /* - * Length of data to write, in bytes.May be - * less than or equal to the allocated size for the directory entry. + * Length of data to write, in bytes. May be less than or equal to the + * allocated size for the directory entry. * The data length stored in the directory entry will be updated to * reflect this value once the write is complete. */ @@ -48326,18 +51063,47 @@ struct hwrm_nvm_write_input { */ #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ UINT32_C(0x1) + /* + * This flag indicates the sender wants to modify a continuous + * NVRAM area using a batch of this HWRM requests. The + * offset of a request must be continuous to the end of previous + * request's. Firmware does not update the directory entry until + * receiving the last request, which is indicated by the batch_last + * flag. This flag is set usually when a sender does not have a + * block of memory that is big enough to hold the entire NVRAM + * data for send at one time. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE \ + UINT32_C(0x2) + /* + * This flag can be used only when the batch_mode flag is set. It + * indicates this request is the last of batch requests. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST \ + UINT32_C(0x4) /* * The requested length of the allocated NVM for the item, in bytes. - * This value may be greater than or equal to the specified data length (dir_data_length). + * This value may be greater than or equal to the specified data + * length (dir_data_length). * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, which may - * be greater than the requested item length. - * The purpose for allocating more than the required number of bytes for - * an item's data is to pre-allocate extra storage (padding) to accommodate - * the potential future growth of an item (e.g. upgraded firmware with - * a size increase, log growth, expanded configuration data). + * The response will contain the actual allocated item length, + * which may be greater than the requested item length. + * The purpose for allocating more than the required number of bytes + * for an item's data is to pre-allocate extra storage (padding) to + * accommodate the potential future growth of an item (e.g. upgraded + * firmware with a size increase, log growth, expanded configuration data). */ uint32_t dir_item_length; + /* + * 32-bit offset of data blob from where data is being written. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t offset; + /* + * Length of data to be written.Should be non-zero. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t len; uint32_t unused_0; } __rte_packed; @@ -48353,7 +51119,8 @@ struct hwrm_nvm_write_output { uint16_t resp_len; /* * Length of the allocated NVM for the item, in bytes. The value may be - * greater than or equal to the specified data length or the requested item length. + * greater than or equal to the specified data length or the requested + * item length. * The actual item length used when creating a new directory entry will * be a multiple of an NVM block size. */ @@ -48564,7 +51331,8 @@ struct hwrm_nvm_find_dir_entry_output { uint32_t dir_data_length; /* * Firmware version. - * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format. + * Only valid if the directory entry is for embedded firmware stored + * in APE_BIN Format. */ uint32_t fw_ver; /* Directory ordinal. */ @@ -48849,7 +51617,10 @@ struct hwrm_nvm_mod_dir_entry_input { * extension flag definitions). */ uint16_t dir_ext; - /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */ + /* + * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute + * flag definitions). + */ uint16_t dir_attr; /* * If valid, then this field updates the checksum @@ -48924,8 +51695,10 @@ struct hwrm_nvm_verify_update_input { /* * The Directory Entry Extension flags. * The "UPDATE" extension flag must be set in this value. - * A corresponding directory entry with the same type and ordinal values but *without* - * the "UPDATE" extension flag must also exist. The other flags of the extension must + * A corresponding directory entry with the same type and ordinal + * values but *without* + * the "UPDATE" extension flag must also exist. The other flags of + * the extension must * be identical between the active and update entries. */ uint16_t dir_ext; @@ -49012,20 +51785,25 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \ HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL uint16_t flags; - /* If set to 1, then securely erase all unused locations in persistent storage. */ + /* + * If set to 1, then securely erase all unused locations in + * persistent storage. + */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \ UINT32_C(0x1) /* - * If set to 1, then unspecified images, images not in the package file, - * will be safely deleted. - * When combined with erase_unused_space then unspecified images will be - * securely erased. + * If set to 1, then unspecified images, images not in the package + * file, will be safely deleted. + * When combined with erase_unused_space then unspecified images will + * be securely erased. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ UINT32_C(0x2) /* - * If set to 1, FW will defragment the NVM if defragmentation is required for the update. - * Allow additional time for this command to complete if this bit is set to 1. + * If set to 1, FW will defragment the NVM if defragmentation is + * required for the update. + * Allow additional time for this command to complete if this bit is + * set to 1. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \ UINT32_C(0x4) @@ -49055,12 +51833,94 @@ struct hwrm_nvm_install_update_output { * A value of 0 indicates that no items were successfully installed. */ uint64_t installed_items; - /* result is 8 b */ + /* result is 8 b corresponding to BCMRETVAL error codes */ uint8_t result; /* There was no problem with the package installation. */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0) + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS \ + UINT32_C(0x0) + /* Generic failure */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_FAILURE \ + UINT32_C(0xff) + /* Allocation error malloc failure */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_MALLOC_FAILURE \ + UINT32_C(0xfd) + /* NVM install error due to invalid index */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_INDEX_PARAMETER \ + UINT32_C(0xfb) + /* NVM install error due to invalid type */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TYPE_PARAMETER \ + UINT32_C(0xf3) + /* Invalid package due to invalid prerequisite */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PREREQUISITE \ + UINT32_C(0xf2) + /* Invalid package due to invalid file header */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_FILE_HEADER \ + UINT32_C(0xec) + /* Invalid package due to invalid format */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_SIGNATURE \ + UINT32_C(0xeb) + /* Invalid package due to invalid property stream */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_STREAM \ + UINT32_C(0xea) + /* Invalid package due to invalid property length */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_LENGTH \ + UINT32_C(0xe9) + /* Invalid package due to invalid manifest */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_MANIFEST \ + UINT32_C(0xe8) + /* Invalid package due to invalid trailer */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TRAILER \ + UINT32_C(0xe7) + /* Invalid package due to invalid checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_CHECKSUM \ + UINT32_C(0xe6) + /* Invalid package due to invalid item checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_ITEM_CHECKSUM \ + UINT32_C(0xe5) + /* Invalid package due to invalid length */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DATA_LENGTH \ + UINT32_C(0xe4) + /* Invalid package due to invalid directive */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DIRECTIVE \ + UINT32_C(0xe1) + /* Invalid device due to unsupported chip revision */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_CHIP_REV \ + UINT32_C(0xce) + /* Invalid device due to unsupported device ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_DEVICE_ID \ + UINT32_C(0xcd) + /* Invalid device due to unsupported subsystem vendor */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_VENDOR \ + UINT32_C(0xcc) + /* Invalid device due to unsupported subsystem ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_ID \ + UINT32_C(0xcb) + /* Invalid device due to unsupported product ID or customer ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_PLATFORM \ + UINT32_C(0xc5) + /* Invalid package due to duplicate item */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_DUPLICATE_ITEM \ + UINT32_C(0xc4) + /* Invalid package due to zero length item */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ZERO_LENGTH_ITEM \ + UINT32_C(0xc3) + /* NVM integrity error checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_CHECKSUM_ERROR \ + UINT32_C(0xb9) + /* NVM integrity error */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_DATA_ERROR \ + UINT32_C(0xb8) + /* Authentication error */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_AUTHENTICATION_ERROR \ + UINT32_C(0xb7) + /* NVM install error item not found */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_NOT_FOUND \ + UINT32_C(0xb0) + /* NVM install error item locked */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED \ + UINT32_C(0xa7) #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \ - HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS + HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED /* problem_item is 8 b */ uint8_t problem_item; /* There was no problem with any packaged items. */ @@ -49116,13 +51976,19 @@ struct hwrm_nvm_install_update_cmd_err { */ uint8_t code; /* Unknown error */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) /* Unable to complete operation due to fragmentation */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR \ + UINT32_C(0x1) /* nvm is completely full. */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE \ + UINT32_C(0x2) + /* Firmware update failed due to Anti-rollback. */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \ + UINT32_C(0x3) #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \ - HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE + HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK uint8_t unused_0[7]; } __rte_packed; @@ -49290,12 +52156,13 @@ struct hwrm_nvm_get_variable_output { /* size of data of the actual variable retrieved in bits */ uint16_t data_len; /* - * option_num is the option number for the data retrieved. It is possible in the - * future that the option number returned would be different than requested. This - * condition could occur if an option is deprecated and a new option id is defined - * with similar characteristics, but has a slightly different definition. This - * also makes it convenient for the caller to identify the variable result with - * the option id from the response. + * option_num is the option number for the data retrieved. It is + * possible in the future that the option number returned would be + * different than requested. This condition could occur if an option is + * deprecated and a new option id is defined with similar + * characteristics, but has a slightly different definition. This + * also makes it convenient for the caller to identify the variable + * result with the option id from the response. */ uint16_t option_num; /* reserved. */ @@ -49405,8 +52272,8 @@ struct hwrm_nvm_set_variable_input { uint16_t index_3; uint8_t flags; /* - * When this bit is 1, flush internal cache after this write operation - * (see hwrm_nvm_flush command.) + * When this bit is 1, flush internal cache after this write + * operation (see hwrm_nvm_flush command.) */ #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \ UINT32_C(0x1) @@ -49558,9 +52425,15 @@ struct hwrm_nvm_validate_option_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; uint8_t result; - /* indicates that the value provided for the option is not matching with the saved data. */ + /* + * indicates that the value provided for the option is not matching + * with the saved data. + */ #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0) - /* indicates that the value provided for the option is matching the saved data. */ + /* + * indicates that the value provided for the option is matching the + * saved data. + */ #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1) #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \ HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH @@ -49589,6 +52462,84 @@ struct hwrm_nvm_validate_option_cmd_err { uint8_t unused_0[7]; } __rte_packed; +/******************* + * hwrm_nvm_defrag * + *******************/ + + +/* hwrm_nvm_defrag_input (size:192b/24B) */ +struct hwrm_nvm_defrag_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* This bit must be '1' to perform NVM defragmentation. */ + #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_nvm_defrag_output (size:128b/16B) */ +struct hwrm_nvm_defrag_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_nvm_defrag_cmd_err (size:64b/8B) */ +struct hwrm_nvm_defrag_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* NVM defragmentation could not be performed */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1) + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST \ + HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL + uint8_t unused_0[7]; +} __rte_packed; + /**************** * hwrm_oem_cmd * ****************/ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index bd57229968..dbc8a3c5bb 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1010,13 +1010,15 @@ ulp_context_initialized(struct bnxt_ulp_session_state *session, bool *init) * pointer, otherwise allocate a new session. */ static struct bnxt_ulp_session_state * -ulp_get_session(struct rte_pci_addr *pci_addr) +ulp_get_session(struct bnxt *bp, struct rte_pci_addr *pci_addr) { struct bnxt_ulp_session_state *session; + /* if multi root capability is enabled, then ignore the pci bus id */ STAILQ_FOREACH(session, &bnxt_ulp_session_list, next) { if (session->pci_info.domain == pci_addr->domain && - session->pci_info.bus == pci_addr->bus) { + (BNXT_MULTIROOT_EN(bp) || + session->pci_info.bus == pci_addr->bus)) { return session; } } @@ -1044,7 +1046,7 @@ ulp_session_init(struct bnxt *bp, pthread_mutex_lock(&bnxt_ulp_global_mutex); - session = ulp_get_session(pci_addr); + session = ulp_get_session(bp, pci_addr); if (!session) { /* Not Found the session Allocate a new one */ session = rte_zmalloc("bnxt_ulp_session", @@ -1547,7 +1549,7 @@ bnxt_ulp_port_deinit(struct bnxt *bp) pci_dev = RTE_DEV_TO_PCI(bp->eth_dev->device); pci_addr = &pci_dev->addr; pthread_mutex_lock(&bnxt_ulp_global_mutex); - session = ulp_get_session(pci_addr); + session = ulp_get_session(bp, pci_addr); pthread_mutex_unlock(&bnxt_ulp_global_mutex); /* session not found then just exit */ -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 03/22] net/bnxt: fix out of bounds issue in hash list 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 01/22] net/bnxt: add NAT support for dest IP and port combination Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 02/22] net/bnxt: add support for multi root capability Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 04/22] net/bnxt: add clear on read support Ajit Khaparde ` (20 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev Cc: Kishore Padmanabha, stable, Venkat Duvvuru, Mike Baucom, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 3050 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> The number of hash bucket list calculation is fixed. Added check to avoid the out of bounds condition. Fixes: 0001cc58d362 ("net/bnxt: support generic hash table") Cc: stable@dpdk.org Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c index 3c6e7fe924..84c83de35c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c @@ -16,20 +16,21 @@ int32_t ulp_bit_alloc_list_alloc(struct bit_alloc_list *blist, { uint64_t bentry; uint32_t idx = 0, jdx = 0; + uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES; /* Iterate all numbers that have all 1's */ do { bentry = blist->bdata[idx++]; - } while (bentry == -1UL && idx < blist->bsize); + } while (bentry == -1UL && idx <= bsize_64); - if (idx < blist->bsize) { + if (idx <= bsize_64) { if (bentry) jdx = __builtin_clzl(~bentry); *index = ((idx - 1) * ULP_INDEX_BITMAP_SIZE) + jdx; ULP_INDEX_BITMAP_SET(blist->bdata[(idx - 1)], jdx); return 0; } - jdx = (uint32_t)(blist->bsize * ULP_INDEX_BITMAP_SIZE); + jdx = (uint32_t)(bsize_64 * ULP_INDEX_BITMAP_SIZE); BNXT_TF_DBG(ERR, "bit allocator is full reached max:%x\n", jdx); return -1; } @@ -39,9 +40,10 @@ int32_t ulp_bit_alloc_list_dealloc(struct bit_alloc_list *blist, uint32_t index) { uint32_t idx = 0, jdx; + uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES; idx = index / ULP_INDEX_BITMAP_SIZE; - if (idx >= blist->bsize) { + if (idx >= bsize_64) { BNXT_TF_DBG(ERR, "invalid bit index %x:%x\n", idx, blist->bsize); return -EINVAL; @@ -127,7 +129,8 @@ ulp_gen_hash_tbl_list_init(struct ulp_hash_create_params *cparams, hash_tbl->hash_mask = size - 1; /* allocate the memory for the bit allocator */ - size = (cparams->num_key_entries / sizeof(uint64_t)) + 1; + size = (cparams->num_key_entries / sizeof(uint64_t)); + size = ULP_BYTE_ROUND_OFF_8(size); hash_tbl->bit_list.bsize = size; hash_tbl->bit_list.bdata = rte_zmalloc("Generic hash bit alloc", size, ULP_BUFFER_ALIGN_64_BYTE); @@ -311,7 +314,12 @@ ulp_gen_hash_tbl_list_add(struct ulp_gen_hash_tbl *hash_tbl, BNXT_TF_DBG(ERR, "Error in bit list alloc\n"); return -ENOMEM; } - + if (key_index > hash_tbl->num_key_entries) { + BNXT_TF_DBG(ERR, "reached max size %u:%u\n", key_index, + hash_tbl->num_key_entries); + ulp_bit_alloc_list_dealloc(&hash_tbl->bit_list, key_index); + return -ENOMEM; + } /* Update the hash entry */ ULP_HASH_BUCKET_MARK_INUSE(bucket, (uint16_t)key_index); -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 04/22] net/bnxt: add clear on read support 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (2 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 03/22] net/bnxt: fix out of bounds issue in hash list Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 05/22] net/bnxt: add capability option for socket redirect Ajit Khaparde ` (19 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev Cc: Farah Smith, Kishore Padmanabha, Venkat Duvvuru, Randy Schacher, Shahaji Bhosle [-- Attachment #1: Type: text/plain, Size: 7396 bytes --] From: Farah Smith <farah.smith@broadcom.com> Add clear on read stats support for Thor. Currently, the flow stats are not cleared after they are read from the FW. This patch adds support for clear on read. Since clear on read support is added for flow stats in Thor, the flow accumulation is enabled on Thor as well. Signed-off-by: Farah Smith <farah.smith@broadcom.com> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_core/tf_msg.c | 24 ++++++++++++++++++++---- drivers/net/bnxt/tf_core/tf_msg.h | 6 ++++-- drivers/net/bnxt/tf_core/tf_tbl.c | 6 ++++-- drivers/net/bnxt/tf_core/tf_tbl_sram.c | 13 +++++++++++-- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 3 ++- 5 files changed, 41 insertions(+), 11 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 0fbb2fe837..ea6e2af7ce 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -1851,7 +1851,8 @@ tf_msg_get_tbl_entry(struct tf *tfp, uint16_t hcapi_type, uint16_t size, uint8_t *data, - uint32_t index) + uint32_t index, + bool clear_on_read) { int rc; struct hwrm_tf_tbl_type_get_input req = { 0 }; @@ -1860,6 +1861,7 @@ tf_msg_get_tbl_entry(struct tf *tfp, uint8_t fw_session_id; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t flags = 0; /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); @@ -1889,10 +1891,16 @@ tf_msg_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } + flags = (dir == TF_DIR_TX ? + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX : + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX); + + if (clear_on_read) + flags |= HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ; /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); - req.flags = tfp_cpu_to_le_16(dir); + req.flags = tfp_cpu_to_le_16(flags); req.type = tfp_cpu_to_le_32(hcapi_type); req.index = tfp_cpu_to_le_32(index); @@ -2105,7 +2113,8 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint32_t starting_idx, uint16_t num_entries, uint16_t entry_sz_in_bytes, - uint64_t physical_mem_addr) + uint64_t physical_mem_addr, + bool clear_on_read) { int rc; struct tfp_send_msg_parms parms = { 0 }; @@ -2115,6 +2124,7 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint8_t fw_session_id; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t flags = 0; /* Retrieve the session information */ rc = tf_session_get_session(tfp, &tfs); @@ -2144,10 +2154,16 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } + flags = (dir == TF_DIR_TX ? + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX : + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX); + + if (clear_on_read) + flags |= HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ; /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); - req.flags = tfp_cpu_to_le_16(dir); + req.flags = tfp_cpu_to_le_16(flags); req.type = tfp_cpu_to_le_32(hcapi_type); req.start_index = tfp_cpu_to_le_32(starting_idx); req.num_entries = tfp_cpu_to_le_32(num_entries); diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index b26b15bfa3..718bc2f3b2 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -652,7 +652,8 @@ int tf_msg_get_tbl_entry(struct tf *tfp, uint16_t hcapi_type, uint16_t size, uint8_t *data, - uint32_t index); + uint32_t index, + bool clear_on_read); /* HWRM Tunneled messages */ @@ -704,7 +705,8 @@ int tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint32_t starting_idx, uint16_t num_entries, uint16_t entry_sz_in_bytes, - uint64_t physical_mem_addr); + uint64_t physical_mem_addr, + bool clear_on_read); /** * Sends Set message of a IF Table Type element to the firmware. diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 0a8720e7b6..12eca36491 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -441,7 +441,8 @@ tf_tbl_get(struct tf *tfp, hcapi_type, parms->data_sz_in_bytes, parms->data, - parms->idx); + parms->idx, + false); if (rc) { TFP_DRV_LOG(ERR, "%s, Get failed, type:%s, rc:%s\n", @@ -526,7 +527,8 @@ tf_tbl_bulk_get(struct tf *tfp, parms->starting_idx, parms->num_entries, parms->entry_sz_in_bytes, - parms->physical_mem_addr); + parms->physical_mem_addr, + false); if (rc) { TFP_DRV_LOG(ERR, "%s, Bulk get failed, type:%s, rc:%s\n", diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c index 636811bc2d..567f912dfa 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c +++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c @@ -539,6 +539,7 @@ tf_tbl_sram_get(struct tf *tfp, struct tf_tbl_sram_get_info_parms iparms = { 0 }; struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; void *sram_handle = NULL; + bool clear_on_read = false; TF_CHECK_PARMS3(tfp, parms, parms->data); @@ -608,6 +609,8 @@ tf_tbl_sram_get(struct tf *tfp, strerror(-rc)); return rc; } + if (parms->type == TF_TBL_TYPE_ACT_STATS_64) + clear_on_read = true; /* Get the entry */ rc = tf_msg_get_tbl_entry(tfp, @@ -615,7 +618,8 @@ tf_tbl_sram_get(struct tf *tfp, hcapi_type, parms->data_sz_in_bytes, parms->data, - parms->idx); + parms->idx, + clear_on_read); if (rc) { TFP_DRV_LOG(ERR, "%s, Get failed, type:%s, rc:%s\n", @@ -643,6 +647,7 @@ tf_tbl_sram_bulk_get(struct tf *tfp, struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; bool allocated = false; void *sram_handle = NULL; + bool clear_on_read = false; TF_CHECK_PARMS2(tfp, parms); @@ -728,6 +733,9 @@ tf_tbl_sram_bulk_get(struct tf *tfp, return rc; } + if (parms->type == TF_TBL_TYPE_ACT_STATS_64) + clear_on_read = true; + /* Get the entries */ rc = tf_msg_bulk_get_tbl_entry(tfp, parms->dir, @@ -735,7 +743,8 @@ tf_tbl_sram_bulk_get(struct tf *tfp, parms->starting_idx, parms->num_entries, parms->entry_sz_in_bytes, - parms->physical_mem_addr); + parms->physical_mem_addr, + clear_on_read); if (rc) { TFP_DRV_LOG(ERR, "%s, Bulk get failed, type:%s, rc:%s\n", diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index dbc8a3c5bb..f1763e2519 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1483,7 +1483,8 @@ bnxt_ulp_port_init(struct bnxt *bp) goto jump_to_error; } - if (devid != BNXT_ULP_DEVICE_ID_THOR && BNXT_ACCUM_STATS_EN(bp)) + /* set the accumulation of the stats */ + if (BNXT_ACCUM_STATS_EN(bp)) bp->ulp_ctx->cfg_data->accum_stats = true; BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init, accum_stats:%d\n", -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 05/22] net/bnxt: add capability option for socket redirect 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (3 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 04/22] net/bnxt: add clear on read support Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 06/22] net/bnxt: remove unused functions Ajit Khaparde ` (18 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Mike Baucom, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 7146 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Added support for socket redirect feature capability so applications can enable or disable this feature. This patch contains the template changes. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 11 +++++++++-- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 6 +++++- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 10 ++++++++-- .../tf_ulp/generic_templates/ulp_template_db_enum.h | 8 +++++--- .../tf_ulp/generic_templates/ulp_template_db_tbl.c | 5 +++-- 5 files changed, 30 insertions(+), 10 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index f1763e2519..2ac1a8625f 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -301,13 +301,14 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, } int32_t -bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, uint8_t app_id, uint32_t dev_id) { struct bnxt_ulp_app_capabilities_info *info; uint32_t num = 0; uint16_t i; bool found = false; + struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx; if (ULP_APP_DEV_UNSUPPORTED_ENABLED(ulp_ctx->cfg_data->ulp_flags)) { BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", @@ -334,6 +335,12 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, if (info[i].flags & BNXT_ULP_APP_CAP_UNICAST_ONLY) ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_APP_UNICAST_ONLY; + if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) { + /* Enable socket direction only if MR is enabled in fw*/ + if (BNXT_MULTIROOT_EN(bp)) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_SOCKET_DIRECT; + } } if (!found) { BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", @@ -832,7 +839,7 @@ ulp_ctx_init(struct bnxt *bp, } BNXT_TF_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id); - rc = bnxt_ulp_cntxt_app_caps_init(bp->ulp_ctx, bp->app_id, devid); + rc = bnxt_ulp_cntxt_app_caps_init(bp, bp->app_id, devid); if (rc) { BNXT_TF_DBG(ERR, "Unable to set caps for app(%x)/dev(%x)\n", bp->app_id, devid); diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 006df9cbc5..68f1470c61 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -13,6 +13,7 @@ #include "rte_version.h" #include "rte_ethdev.h" +#include "bnxt.h" #include "ulp_template_db_enum.h" #include "ulp_tun.h" #include "bnxt_tf_common.h" @@ -33,12 +34,15 @@ #define BNXT_ULP_APP_DEV_UNSUPPORTED 0x4 #define BNXT_ULP_HIGH_AVAIL_ENABLED 0x8 #define BNXT_ULP_APP_UNICAST_ONLY 0x10 +#define BNXT_ULP_APP_SOCKET_DIRECT 0x20 + #define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED) #define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\ BNXT_ULP_SHARED_SESSION_ENABLED) #define ULP_APP_DEV_UNSUPPORTED_ENABLED(flag) ((flag) &\ BNXT_ULP_APP_DEV_UNSUPPORTED) #define ULP_HIGH_AVAIL_IS_ENABLED(flag) ((flag) & BNXT_ULP_HIGH_AVAIL_ENABLED) +#define ULP_SOCKET_DIRECT_IS_ENABLED(flag) ((flag) & BNXT_ULP_APP_SOCKET_DIRECT) enum bnxt_ulp_flow_mem_type { BNXT_ULP_FLOW_MEM_TYPE_INT = 0, @@ -287,7 +291,7 @@ struct bnxt_ulp_app_capabilities_info * bnxt_ulp_app_cap_list_get(uint32_t *num_entries); int32_t -bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, uint8_t app_id, uint32_t dev_id); struct bnxt_ulp_resource_resv_info * diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 2fec79a388..272195f6a2 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -115,9 +115,11 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FLOW_SIG_ID, params->flow_sig_id); + if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags)) + return; + /* update the WC Priority flag */ - if (!bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags) && - ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) { + if (ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) { enum ulp_ha_mgr_region region = ULP_HA_REGION_LOW; int32_t rc; @@ -129,6 +131,10 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG, 1); } + + /* Update the socket direct flag */ + if (ULP_SOCKET_DIRECT_IS_ENABLED(ulp_flags)) + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT, 1); } /* Function to create the rte flow. */ diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index fcd460e707..31a94c14dc 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Aug 26 17:43:36 2021 */ +/* date: Thu Sep 9 11:11:05 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -211,7 +211,8 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 71, BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72, BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73, - BNXT_ULP_CF_IDX_LAST = 74 + BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74, + BNXT_ULP_CF_IDX_LAST = 75 }; enum bnxt_ulp_cond_list_opc { @@ -582,7 +583,8 @@ enum bnxt_ulp_template_type { enum bnxt_ulp_app_cap { BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001, BNXT_ULP_APP_CAP_HOT_UPGRADE_EN = 0x00000002, - BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004 + BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004, + BNXT_ULP_APP_CAP_SOCKET_DIRECT = 0x00000008 }; enum bnxt_ulp_fdb_resource_flags { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 84be09b368..5383e2cd70 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Aug 26 17:43:36 2021 */ +/* date: Thu Sep 9 11:11:05 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -347,7 +347,8 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { .device_id = BNXT_ULP_DEVICE_ID_THOR, .flags = BNXT_ULP_APP_CAP_SHARED_EN | BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | - BNXT_ULP_APP_CAP_UNICAST_ONLY + BNXT_ULP_APP_CAP_UNICAST_ONLY | + BNXT_ULP_APP_CAP_SOCKET_DIRECT }, { .app_id = 2, -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 06/22] net/bnxt: remove unused functions 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (4 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 05/22] net/bnxt: add capability option for socket redirect Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 07/22] net/bnxt: address ISO C90 compilation error Ajit Khaparde ` (17 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev [-- Attachment #1: Type: text/plain, Size: 7007 bytes --] Remove unused functions from the code. Specifically the following functions are being removed. void bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, uint8_t *mac, uint8_t *parent_mac); uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); uint16_t bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); struct bnxt *bnxt_get_bp(uint16_t port); uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, enum bnxt_ulp_intf_type type); uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); uint16_t bnxt_get_phy_port_id(uint16_t port); uint16_t bnxt_get_vport(uint16_t port); enum bnxt_ulp_intf_type bnxt_get_interface_type(uint16_t port); Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/bnxt.h | 13 --- drivers/net/bnxt/bnxt_ethdev.c | 203 --------------------------------- 2 files changed, 216 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 97e281a2fc..4ab9ebd049 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -1054,19 +1054,6 @@ int32_t bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); int32_t bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); -void bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, - uint8_t *mac, uint8_t *parent_mac); -uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); -struct bnxt *bnxt_get_bp(uint16_t port); -uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, - enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_phy_port_id(uint16_t port); -uint16_t bnxt_get_vport(uint16_t port); -enum bnxt_ulp_intf_type -bnxt_get_interface_type(uint16_t port); int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev); void bnxt_cancel_fc_thread(struct bnxt *bp); diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 257e6b0d6a..2ab0cf3784 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -5047,209 +5047,6 @@ static void bnxt_config_vf_req_fwd(struct bnxt *bp) BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); } -struct bnxt * -bnxt_get_bp(uint16_t port) -{ - struct bnxt *bp; - struct rte_eth_dev *dev; - - if (!rte_eth_dev_is_valid_port(port)) { - PMD_DRV_LOG(ERR, "Invalid port %d\n", port); - return NULL; - } - - dev = &rte_eth_devices[port]; - if (!is_bnxt_supported(dev)) { - PMD_DRV_LOG(ERR, "Device %d not supported\n", port); - return NULL; - } - - bp = (struct bnxt *)dev->data->dev_private; - if (!BNXT_TRUFLOW_EN(bp)) { - PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); - return NULL; - } - - return bp; -} - -uint16_t -bnxt_get_svif(uint16_t port_id, bool func_svif, - enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->svif; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return func_svif ? bp->func_svif : bp->port_svif; -} - -void -bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, - uint8_t *mac, uint8_t *parent_mac) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF && - type != BNXT_ULP_INTF_TYPE_PF) - return; - - eth_dev = &rte_eth_devices[port]; - bp = eth_dev->data->dev_private; - memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN); - - if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF) - memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN); -} - -uint16_t -bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF) - return 0; - - eth_dev = &rte_eth_devices[port]; - bp = eth_dev->data->dev_private; - - return bp->parent->vnic; -} -uint16_t -bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt_vnic_info *vnic; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->dflt_vnic_id; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - vnic = BNXT_GET_DEFAULT_VNIC(bp); - - return vnic->fw_vnic_id; -} - -uint16_t -bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->fw_fid; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return bp->fw_fid; -} - -enum bnxt_ulp_intf_type -bnxt_get_interface_type(uint16_t port) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) - return BNXT_ULP_INTF_TYPE_VF_REP; - - bp = eth_dev->data->dev_private; - if (BNXT_PF(bp)) - return BNXT_ULP_INTF_TYPE_PF; - else if (BNXT_VF_IS_TRUSTED(bp)) - return BNXT_ULP_INTF_TYPE_TRUSTED_VF; - else if (BNXT_VF(bp)) - return BNXT_ULP_INTF_TYPE_VF; - - return BNXT_ULP_INTF_TYPE_INVALID; -} - -uint16_t -bnxt_get_phy_port_id(uint16_t port_id) -{ - struct bnxt_representor *vfr; - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; -} - -uint16_t -bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->fw_fid - 1; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; -} - -uint16_t -bnxt_get_vport(uint16_t port_id) -{ - return (1 << bnxt_get_phy_port_id(port_id)); -} - static void bnxt_alloc_error_recovery_info(struct bnxt *bp) { struct bnxt_error_recovery_info *info = bp->recovery_info; -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 07/22] net/bnxt: address ISO C90 compilation error 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (5 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 06/22] net/bnxt: remove unused functions Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 08/22] net/bnxt: enable wildcard match for ingress flows Ajit Khaparde ` (16 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Mike Baucom, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 275652 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> The flow signature is of type unsigned long value and needs to be suffixed with UL. This patch takes care of that. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- .../generic_templates/ulp_template_db_class.c | 1986 ++++++++--------- 1 file changed, 993 insertions(+), 993 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c index ad3866243d..1d1e6463e0 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 6 11:15:47 2021 */ +/* date: Thu Sep 16 13:12:05 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -1016,7 +1016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55dd, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1031,7 +1031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1df1, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4104, + .flow_sig_id = 4104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1047,7 +1047,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e55, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1063,7 +1063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0649, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 6152, + .flow_sig_id = 6152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1080,7 +1080,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1011, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1095,7 +1095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40e9, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 16392, + .flow_sig_id = 16392UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1111,7 +1111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e99, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1127,7 +1127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06ad, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 24584, + .flow_sig_id = 24584UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1144,7 +1144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_38c7, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1160,7 +1160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00fb, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32776, + .flow_sig_id = 32776UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1177,7 +1177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_24d3, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1194,7 +1194,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_559b, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32840, + .flow_sig_id = 32840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1212,7 +1212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5003, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1229,7 +1229,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1837, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1247,7 +1247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bef, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1265,7 +1265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0403, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49224, + .flow_sig_id = 49224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1284,7 +1284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d3f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1300,7 +1300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0543, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131080, + .flow_sig_id = 131080UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1317,7 +1317,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_292b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1334,7 +1334,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59e3, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131144, + .flow_sig_id = 131144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1352,7 +1352,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d3b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1369,7 +1369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_254f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196616, + .flow_sig_id = 196616UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1387,7 +1387,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4917, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1405,7 +1405,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_113b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196680, + .flow_sig_id = 196680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1424,7 +1424,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55fd, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1440,7 +1440,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1dd1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 4104, + .flow_sig_id = 4104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1457,7 +1457,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e75, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1474,7 +1474,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0669, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 6152, + .flow_sig_id = 6152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1492,7 +1492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ba1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1509,7 +1509,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c69, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 12296, + .flow_sig_id = 12296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1527,7 +1527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0439, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1545,7 +1545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34e1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 14344, + .flow_sig_id = 14344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1564,7 +1564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0465, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1581,7 +1581,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_352d, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 20488, + .flow_sig_id = 20488UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1599,7 +1599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55b1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1617,7 +1617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1da5, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 22536, + .flow_sig_id = 22536UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1636,7 +1636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_32fd, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1654,7 +1654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_63a5, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 28680, + .flow_sig_id = 28680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1673,7 +1673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1b75, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1692,7 +1692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c3d, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 30728, + .flow_sig_id = 30728UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1712,7 +1712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1031, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1728,7 +1728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40c9, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 16392, + .flow_sig_id = 16392UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1745,7 +1745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3eb9, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1762,7 +1762,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_068d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24584, + .flow_sig_id = 24584UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1780,7 +1780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5039, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1797,7 +1797,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_180d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1815,7 +1815,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15fd, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1833,7 +1833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46b5, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 57352, + .flow_sig_id = 57352UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1852,7 +1852,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_303d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1869,7 +1869,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_60f5, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 81928, + .flow_sig_id = 81928UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1887,7 +1887,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ea5, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1905,7 +1905,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2689, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 90120, + .flow_sig_id = 90120UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1924,7 +1924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0771, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1942,7 +1942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3809, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1961,7 +1961,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35f9, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -1980,7 +1980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66b1, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 122888, + .flow_sig_id = 122888UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2000,7 +2000,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_559d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2016,7 +2016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1db1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 4104, + .flow_sig_id = 4104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2033,7 +2033,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e15, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2050,7 +2050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0609, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 6152, + .flow_sig_id = 6152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2068,7 +2068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1bc1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2085,7 +2085,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c09, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 12296, + .flow_sig_id = 12296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2103,7 +2103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0459, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2121,7 +2121,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3481, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14344, + .flow_sig_id = 14344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2140,7 +2140,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0405, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2157,7 +2157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_354d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 20488, + .flow_sig_id = 20488UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2175,7 +2175,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55d1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2193,7 +2193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1dc5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 22536, + .flow_sig_id = 22536UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2212,7 +2212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_329d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2230,7 +2230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_63c5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 28680, + .flow_sig_id = 28680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2249,7 +2249,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1b15, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2268,7 +2268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c5d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 30728, + .flow_sig_id = 30728UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2288,7 +2288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1051, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2304,7 +2304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40a9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16392, + .flow_sig_id = 16392UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2321,7 +2321,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ed9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2338,7 +2338,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06ed, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 24584, + .flow_sig_id = 24584UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2356,7 +2356,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5059, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2373,7 +2373,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_186d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2391,7 +2391,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_159d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2409,7 +2409,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46d5, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 57352, + .flow_sig_id = 57352UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2428,7 +2428,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_305d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2445,7 +2445,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6095, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 81928, + .flow_sig_id = 81928UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2463,7 +2463,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ec5, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2481,7 +2481,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26e9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 90120, + .flow_sig_id = 90120UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2500,7 +2500,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0711, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2518,7 +2518,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3869, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2537,7 +2537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3599, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2556,7 +2556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66d1, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 122888, + .flow_sig_id = 122888UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2576,7 +2576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_38e7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2593,7 +2593,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00db, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32776, + .flow_sig_id = 32776UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2611,7 +2611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_24f3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2629,7 +2629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55bb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32840, + .flow_sig_id = 32840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2648,7 +2648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5023, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2666,7 +2666,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1817, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2685,7 +2685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bcf, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2704,7 +2704,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0423, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49224, + .flow_sig_id = 49224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2724,7 +2724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_58e3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2742,7 +2742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20d7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98312, + .flow_sig_id = 98312UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2761,7 +2761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_448f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2780,7 +2780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0ce3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98376, + .flow_sig_id = 98376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2800,7 +2800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_076b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2819,7 +2819,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3813, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2839,7 +2839,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5bcb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2859,7 +2859,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_243f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114760, + .flow_sig_id = 114760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2880,7 +2880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_144b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2898,7 +2898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4573, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163848, + .flow_sig_id = 163848UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2917,7 +2917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0057, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2936,7 +2936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_311f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163912, + .flow_sig_id = 163912UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2956,7 +2956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2b87, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2975,7 +2975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c4f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180232, + .flow_sig_id = 180232UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -2995,7 +2995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1793, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3015,7 +3015,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_485b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180296, + .flow_sig_id = 180296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3036,7 +3036,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3447, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3055,7 +3055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_650f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229384, + .flow_sig_id = 229384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3075,7 +3075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2053, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3095,7 +3095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_511b, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229448, + .flow_sig_id = 229448UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3116,7 +3116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4b83, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3136,7 +3136,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13f7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245768, + .flow_sig_id = 245768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3157,7 +3157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_37af, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3178,7 +3178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6857, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245832, + .flow_sig_id = 245832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3200,7 +3200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d1f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3217,7 +3217,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0563, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131080, + .flow_sig_id = 131080UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3235,7 +3235,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_290b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3253,7 +3253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59c3, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131144, + .flow_sig_id = 131144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3272,7 +3272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d1b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3290,7 +3290,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_256f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196616, + .flow_sig_id = 196616UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3309,7 +3309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4937, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3328,7 +3328,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_111b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196680, + .flow_sig_id = 196680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3348,7 +3348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f4b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3366,7 +3366,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_275f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393224, + .flow_sig_id = 393224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3385,7 +3385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4b67, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3404,7 +3404,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_134b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393288, + .flow_sig_id = 393288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3424,7 +3424,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1683, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3443,7 +3443,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_475b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458760, + .flow_sig_id = 458760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3463,7 +3463,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_02bf, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3483,7 +3483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3377, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458824, + .flow_sig_id = 458824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3504,7 +3504,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19db, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3522,7 +3522,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4a93, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655368, + .flow_sig_id = 655368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3541,7 +3541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_05f7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3560,7 +3560,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_368f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655432, + .flow_sig_id = 655432UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3580,7 +3580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39c7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3599,7 +3599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_022b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720904, + .flow_sig_id = 720904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3619,7 +3619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_25f3, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3639,7 +3639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_568b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720968, + .flow_sig_id = 720968UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3660,7 +3660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c37, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3679,7 +3679,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_041b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917512, + .flow_sig_id = 917512UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3699,7 +3699,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2823, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3719,7 +3719,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_58fb, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917576, + .flow_sig_id = 917576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3740,7 +3740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c33, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3760,7 +3760,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2407, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983048, + .flow_sig_id = 983048UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3781,7 +3781,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_482f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3802,7 +3802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1033, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983112, + .flow_sig_id = 983112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3824,7 +3824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3887, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3841,7 +3841,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00bb, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32776, + .flow_sig_id = 32776UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3859,7 +3859,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2493, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3877,7 +3877,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55db, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32840, + .flow_sig_id = 32840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3896,7 +3896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5043, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3914,7 +3914,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1877, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49160, + .flow_sig_id = 49160UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3933,7 +3933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3baf, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3952,7 +3952,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0443, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49224, + .flow_sig_id = 49224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3972,7 +3972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5883, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -3990,7 +3990,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20b7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98312, + .flow_sig_id = 98312UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4009,7 +4009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_44ef, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4028,7 +4028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c83, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98376, + .flow_sig_id = 98376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4048,7 +4048,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_070b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4067,7 +4067,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3873, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114696, + .flow_sig_id = 114696UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4087,7 +4087,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5bab, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4107,7 +4107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_245f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114760, + .flow_sig_id = 114760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4128,7 +4128,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_142b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4146,7 +4146,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4513, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163848, + .flow_sig_id = 163848UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4165,7 +4165,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0037, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4184,7 +4184,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_317f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163912, + .flow_sig_id = 163912UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4204,7 +4204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2be7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4223,7 +4223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c2f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180232, + .flow_sig_id = 180232UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4243,7 +4243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_17f3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4263,7 +4263,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_483b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180296, + .flow_sig_id = 180296UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4284,7 +4284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3427, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4303,7 +4303,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_656f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229384, + .flow_sig_id = 229384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4323,7 +4323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2033, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4343,7 +4343,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_517b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229448, + .flow_sig_id = 229448UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4364,7 +4364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4be3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4384,7 +4384,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1397, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245768, + .flow_sig_id = 245768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4405,7 +4405,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_37cf, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4426,7 +4426,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6837, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245832, + .flow_sig_id = 245832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4448,7 +4448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d7f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4465,7 +4465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0503, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131080, + .flow_sig_id = 131080UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4483,7 +4483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_296b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4501,7 +4501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59a3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131144, + .flow_sig_id = 131144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4520,7 +4520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d7b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4538,7 +4538,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_250f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196616, + .flow_sig_id = 196616UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4557,7 +4557,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4957, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4576,7 +4576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_117b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196680, + .flow_sig_id = 196680UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4596,7 +4596,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f2b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4614,7 +4614,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_273f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393224, + .flow_sig_id = 393224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4633,7 +4633,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4b07, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4652,7 +4652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_132b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393288, + .flow_sig_id = 393288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4672,7 +4672,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_16e3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4691,7 +4691,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_473b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458760, + .flow_sig_id = 458760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4711,7 +4711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_02df, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4731,7 +4731,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3317, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458824, + .flow_sig_id = 458824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4752,7 +4752,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19bb, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4770,7 +4770,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4af3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655368, + .flow_sig_id = 655368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4789,7 +4789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0597, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4808,7 +4808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_36ef, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655432, + .flow_sig_id = 655432UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4828,7 +4828,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39a7, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4847,7 +4847,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_024b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720904, + .flow_sig_id = 720904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4867,7 +4867,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2593, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4887,7 +4887,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_56eb, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720968, + .flow_sig_id = 720968UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4908,7 +4908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c57, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4927,7 +4927,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_047b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917512, + .flow_sig_id = 917512UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4947,7 +4947,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2843, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4967,7 +4967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_589b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917576, + .flow_sig_id = 917576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -4988,7 +4988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c53, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5008,7 +5008,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2467, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983048, + .flow_sig_id = 983048UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5029,7 +5029,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_484f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5050,7 +5050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1053, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983112, + .flow_sig_id = 983112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -5072,7 +5072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ce1, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5086,7 +5086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4579, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5101,7 +5101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1735, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5115,7 +5115,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_45bd, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5130,7 +5130,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3feb, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5145,7 +5145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bf7, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5161,7 +5161,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5727, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5177,7 +5177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4333, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5194,7 +5194,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4453, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5209,7 +5209,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_304f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5225,7 +5225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_645f, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5241,7 +5241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_504b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5258,7 +5258,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5cc1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5273,7 +5273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4559, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5289,7 +5289,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2285, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5305,7 +5305,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b1d, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5322,7 +5322,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b49, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5338,7 +5338,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c95, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5355,7 +5355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39c1, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5372,7 +5372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2259, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5390,7 +5390,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1715, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5405,7 +5405,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_459d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5421,7 +5421,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_571d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5437,7 +5437,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cd1, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5454,7 +5454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3711, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5470,7 +5470,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6599, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5487,7 +5487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e55, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5504,7 +5504,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3cdd, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5522,7 +5522,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ca1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5537,7 +5537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4539, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5553,7 +5553,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_22e5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5569,7 +5569,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b7d, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5586,7 +5586,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b29, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5602,7 +5602,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5cf5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5619,7 +5619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39a1, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5636,7 +5636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2239, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5654,7 +5654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1775, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5669,7 +5669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_45fd, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5685,7 +5685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_577d, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5701,7 +5701,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cb1, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5718,7 +5718,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3771, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5734,7 +5734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_65f9, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5751,7 +5751,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e35, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5768,7 +5768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3cbd, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5786,7 +5786,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3fcb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5802,7 +5802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bd7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5819,7 +5819,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5707, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5836,7 +5836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4313, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5854,7 +5854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5fc7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5871,7 +5871,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4bd3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5889,7 +5889,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e4f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5907,7 +5907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_632f, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5926,7 +5926,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1baf, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5943,7 +5943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_07bb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5961,7 +5961,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_32eb, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5979,7 +5979,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ef7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -5998,7 +5998,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bab, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6016,7 +6016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_27b7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6035,7 +6035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52e7, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6054,7 +6054,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ef3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6074,7 +6074,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4473, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6090,7 +6090,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_306f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6107,7 +6107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_647f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6124,7 +6124,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_506b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6142,7 +6142,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66af, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6159,7 +6159,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_525b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6177,7 +6177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1de7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6195,7 +6195,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0993, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6214,7 +6214,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_213f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6231,7 +6231,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d2b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6249,7 +6249,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_413b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6267,7 +6267,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2cd7, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6286,7 +6286,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_436b, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6304,7 +6304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2f07, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6323,7 +6323,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6317, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6342,7 +6342,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4f03, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6362,7 +6362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3fab, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6378,7 +6378,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bb7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6395,7 +6395,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5767, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6412,7 +6412,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4373, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6430,7 +6430,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5fa7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6447,7 +6447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4bb3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6465,7 +6465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e2f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6483,7 +6483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_634f, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6502,7 +6502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1bcf, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6519,7 +6519,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_07db, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6537,7 +6537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_328b, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6555,7 +6555,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1e97, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6574,7 +6574,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3bcb, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6592,7 +6592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_27d7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6611,7 +6611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5287, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6630,7 +6630,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3e93, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6650,7 +6650,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4413, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6666,7 +6666,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_300f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6683,7 +6683,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_641f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6700,7 +6700,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_500b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6718,7 +6718,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66cf, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6735,7 +6735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_523b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6753,7 +6753,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1d87, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6771,7 +6771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09f3, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6790,7 +6790,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_215f, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6807,7 +6807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d4b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6825,7 +6825,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_415b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6843,7 +6843,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2cb7, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6862,7 +6862,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_430b, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6880,7 +6880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2f67, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6899,7 +6899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_6377, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6918,7 +6918,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4f63, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -6938,7 +6938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29b5, .class_tid = 1, .hdr_sig_id = 0, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -6953,7 +6953,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29ad, .class_tid = 1, .hdr_sig_id = 1, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -6968,7 +6968,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29b7, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -6984,7 +6984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1583, .class_tid = 1, .hdr_sig_id = 2, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7001,7 +7001,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29af, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7017,7 +7017,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_159b, .class_tid = 1, .hdr_sig_id = 3, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7034,7 +7034,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2995, .class_tid = 1, .hdr_sig_id = 4, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7050,7 +7050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_298d, .class_tid = 1, .hdr_sig_id = 5, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7066,7 +7066,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29f5, .class_tid = 1, .hdr_sig_id = 6, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7082,7 +7082,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29ed, .class_tid = 1, .hdr_sig_id = 7, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7098,7 +7098,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2997, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7115,7 +7115,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15a3, .class_tid = 1, .hdr_sig_id = 8, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7133,7 +7133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_298f, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7150,7 +7150,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15bb, .class_tid = 1, .hdr_sig_id = 9, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7168,7 +7168,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29f7, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7185,7 +7185,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15c3, .class_tid = 1, .hdr_sig_id = 10, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7203,7 +7203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29ef, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 8, + .flow_sig_id = 8UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7220,7 +7220,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15db, .class_tid = 1, .hdr_sig_id = 11, - .flow_sig_id = 72, + .flow_sig_id = 72UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -7238,7 +7238,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1151, .class_tid = 1, .hdr_sig_id = 12, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 3, .app_sig = 0, .hdr_sig = { .bits = @@ -7255,7 +7255,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_315d, .class_tid = 1, .hdr_sig_id = 12, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 3, .app_sig = 0, .hdr_sig = { .bits = @@ -7273,7 +7273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3612, .class_tid = 2, .hdr_sig_id = 0, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -7292,7 +7292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_66da, .class_tid = 2, .hdr_sig_id = 0, - .flow_sig_id = 81928, + .flow_sig_id = 81928UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -7312,7 +7312,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e082, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7332,7 +7332,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ab46, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7353,7 +7353,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c82a, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7374,7 +7374,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f9a2, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7396,7 +7396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d8ce, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 538184704, + .flow_sig_id = 538184704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7417,7 +7417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a2d2, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 538192896, + .flow_sig_id = 538192896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7439,7 +7439,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c076, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 540281856, + .flow_sig_id = 540281856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7461,7 +7461,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f1ee, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 540290048, + .flow_sig_id = 540290048UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7484,7 +7484,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a96e, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1075055616, + .flow_sig_id = 1075055616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7505,7 +7505,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dae6, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1075063808, + .flow_sig_id = 1075063808UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7527,7 +7527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c7aa, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1077152768, + .flow_sig_id = 1077152768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7549,7 +7549,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c26e, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1077160960, + .flow_sig_id = 1077160960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7572,7 +7572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a0fa, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1611926528, + .flow_sig_id = 1611926528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7594,7 +7594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d272, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1611934720, + .flow_sig_id = 1611934720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7617,7 +7617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fff6, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1614023680, + .flow_sig_id = 1614023680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7640,7 +7640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e16e, .class_tid = 2, .hdr_sig_id = 1, - .flow_sig_id = 1614031872, + .flow_sig_id = 1614031872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7664,7 +7664,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e165, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7684,7 +7684,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aaa1, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7705,7 +7705,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c9cd, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7726,7 +7726,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f845, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7748,7 +7748,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_90f9, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7769,7 +7769,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c371, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7791,7 +7791,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e19d, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7813,7 +7813,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d015, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7836,7 +7836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8c09, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7857,7 +7857,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_be89, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7879,7 +7879,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ddad, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7901,7 +7901,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cc2d, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7924,7 +7924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a4d9, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7946,7 +7946,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d759, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7969,7 +7969,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f27d, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -7992,7 +7992,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e4fd, .class_tid = 2, .hdr_sig_id = 2, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8016,7 +8016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ecf6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8037,7 +8037,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a732, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8059,7 +8059,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c45e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8081,7 +8081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f5d6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8104,7 +8104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d4ba, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 538184704, + .flow_sig_id = 538184704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8126,7 +8126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aea6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 538192896, + .flow_sig_id = 538192896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8149,7 +8149,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cc02, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 540281856, + .flow_sig_id = 540281856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8172,7 +8172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fd9a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 540290048, + .flow_sig_id = 540290048UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8196,7 +8196,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a51a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1075055616, + .flow_sig_id = 1075055616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8218,7 +8218,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d692, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1075063808, + .flow_sig_id = 1075063808UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8241,7 +8241,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cbde, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1077152768, + .flow_sig_id = 1077152768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8264,7 +8264,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce1a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1077160960, + .flow_sig_id = 1077160960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8288,7 +8288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ac8e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1611926528, + .flow_sig_id = 1611926528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8311,7 +8311,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_de06, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1611934720, + .flow_sig_id = 1611934720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8335,7 +8335,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f382, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1614023680, + .flow_sig_id = 1614023680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8359,7 +8359,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ed1a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 1614031872, + .flow_sig_id = 1614031872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8384,7 +8384,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9d6a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8406,7 +8406,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cee2, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8429,7 +8429,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ec0e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8452,7 +8452,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dd86, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8476,7 +8476,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_852e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2685668352, + .flow_sig_id = 2685668352UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8499,7 +8499,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b6a6, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2685676544, + .flow_sig_id = 2685676544UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8523,7 +8523,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_eb82, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2687765504, + .flow_sig_id = 2687765504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8547,7 +8547,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c50a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 2687773696, + .flow_sig_id = 2687773696UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8572,7 +8572,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ccca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3222539264, + .flow_sig_id = 3222539264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8595,7 +8595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8706, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3222547456, + .flow_sig_id = 3222547456UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8619,7 +8619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d38e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3224636416, + .flow_sig_id = 3224636416UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8643,7 +8643,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d5ca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3224644608, + .flow_sig_id = 3224644608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8668,7 +8668,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b48e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3759410176, + .flow_sig_id = 3759410176UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8692,7 +8692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8e8a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3759418368, + .flow_sig_id = 3759418368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8717,7 +8717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_db02, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3761507328, + .flow_sig_id = 3761507328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8742,7 +8742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dd8e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 3761515520, + .flow_sig_id = 3761515520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8768,7 +8768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_819a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8790,7 +8790,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b31a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8813,7 +8813,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d03e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8836,7 +8836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c1be, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8860,7 +8860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_890e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4833152000, + .flow_sig_id = 4833152000UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8883,7 +8883,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ba8e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4833160192, + .flow_sig_id = 4833160192UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8907,7 +8907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dfaa, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4835249152, + .flow_sig_id = 4835249152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8931,7 +8931,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c93a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 4835257344, + .flow_sig_id = 4835257344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8956,7 +8956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b11a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5370022912, + .flow_sig_id = 5370022912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -8979,7 +8979,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8b4e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5370031104, + .flow_sig_id = 5370031104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9003,7 +9003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c79e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5372120064, + .flow_sig_id = 5372120064UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9027,7 +9027,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d9da, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5372128256, + .flow_sig_id = 5372128256UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9052,7 +9052,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b88e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5906893824, + .flow_sig_id = 5906893824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9076,7 +9076,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ea0e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5906902016, + .flow_sig_id = 5906902016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9101,7 +9101,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cf0a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5908990976, + .flow_sig_id = 5908990976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9126,7 +9126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c18e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 5908999168, + .flow_sig_id = 5908999168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9152,7 +9152,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a94a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9175,7 +9175,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_daca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9199,7 +9199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ffee, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9223,7 +9223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e96e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9248,7 +9248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_910e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6980635648, + .flow_sig_id = 6980635648UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9272,7 +9272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c28e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6980643840, + .flow_sig_id = 6980643840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9297,7 +9297,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e7aa, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6982732800, + .flow_sig_id = 6982732800UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9322,7 +9322,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d12a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 6982740992, + .flow_sig_id = 6982740992UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9348,7 +9348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d8ca, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7517506560, + .flow_sig_id = 7517506560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9372,7 +9372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_930e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7517514752, + .flow_sig_id = 7517514752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9397,7 +9397,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ef4e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7519603712, + .flow_sig_id = 7519603712UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9422,7 +9422,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e18a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 7519611904, + .flow_sig_id = 7519611904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9448,7 +9448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c08e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8054377472, + .flow_sig_id = 8054377472UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9473,7 +9473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9a8a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8054385664, + .flow_sig_id = 8054385664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9499,7 +9499,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d70a, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8056474624, + .flow_sig_id = 8056474624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9525,7 +9525,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e90e, .class_tid = 2, .hdr_sig_id = 3, - .flow_sig_id = 8056482816, + .flow_sig_id = 8056482816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9552,7 +9552,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_edd9, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9573,7 +9573,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a61d, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9595,7 +9595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c571, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9617,7 +9617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f4f9, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9640,7 +9640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9c45, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9662,7 +9662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cfcd, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9685,7 +9685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ed21, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9708,7 +9708,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dca9, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9732,7 +9732,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_80b5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9754,7 +9754,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b235, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9777,7 +9777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d111, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9800,7 +9800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c091, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9824,7 +9824,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a865, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9847,7 +9847,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dbe5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9871,7 +9871,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fec1, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9895,7 +9895,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e841, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9920,7 +9920,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8e85, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8591248384, + .flow_sig_id = 8591248384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9942,7 +9942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b80d, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8591256576, + .flow_sig_id = 8591256576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9965,7 +9965,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_df65, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8593345536, + .flow_sig_id = 8593345536UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -9988,7 +9988,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ceed, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 8593353728, + .flow_sig_id = 8593353728UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10012,7 +10012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9645, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10738732032, + .flow_sig_id = 10738732032UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10035,7 +10035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c1cd, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10738740224, + .flow_sig_id = 10738740224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10059,7 +10059,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e725, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10740829184, + .flow_sig_id = 10740829184UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10083,7 +10083,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d6ad, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 10740837376, + .flow_sig_id = 10740837376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10108,7 +10108,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9aa5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12886215680, + .flow_sig_id = 12886215680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10131,7 +10131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b425, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12886223872, + .flow_sig_id = 12886223872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10155,7 +10155,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_eb05, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12888312832, + .flow_sig_id = 12888312832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10179,7 +10179,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_da85, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 12888321024, + .flow_sig_id = 12888321024UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10204,7 +10204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a265, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15033699328, + .flow_sig_id = 15033699328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10228,7 +10228,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dde5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15033707520, + .flow_sig_id = 15033707520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10253,7 +10253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f0c5, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15035796480, + .flow_sig_id = 15035796480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10278,7 +10278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e245, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 15035804672, + .flow_sig_id = 15035804672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10304,7 +10304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8b8f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17181182976, + .flow_sig_id = 17181182976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10326,7 +10326,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a517, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17181191168, + .flow_sig_id = 17181191168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10349,7 +10349,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d86b, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17183280128, + .flow_sig_id = 17183280128UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10372,7 +10372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cbf3, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 17183288320, + .flow_sig_id = 17183288320UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10396,7 +10396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_934f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19328666624, + .flow_sig_id = 19328666624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10419,7 +10419,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c2c7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19328674816, + .flow_sig_id = 19328674816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10443,7 +10443,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e02b, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19330763776, + .flow_sig_id = 19330763776UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10467,7 +10467,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d3a3, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 19330771968, + .flow_sig_id = 19330771968UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10492,7 +10492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_87a7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21476150272, + .flow_sig_id = 21476150272UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10515,7 +10515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b137, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21476158464, + .flow_sig_id = 21476158464UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10539,7 +10539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d403, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21478247424, + .flow_sig_id = 21478247424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10563,7 +10563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c793, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 21478255616, + .flow_sig_id = 21478255616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10588,7 +10588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_af67, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23623633920, + .flow_sig_id = 23623633920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10612,7 +10612,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dee7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23623642112, + .flow_sig_id = 23623642112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10637,7 +10637,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fdc3, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23625731072, + .flow_sig_id = 23625731072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10662,7 +10662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ef43, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 23625739264, + .flow_sig_id = 23625739264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10688,7 +10688,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8dbf, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25771117568, + .flow_sig_id = 25771117568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10711,7 +10711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_bf07, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25771125760, + .flow_sig_id = 25771125760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10735,7 +10735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d21f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25773214720, + .flow_sig_id = 25773214720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10759,7 +10759,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cde7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 25773222912, + .flow_sig_id = 25773222912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10784,7 +10784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_956f, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27918601216, + .flow_sig_id = 27918601216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10808,7 +10808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c4c7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27918609408, + .flow_sig_id = 27918609408UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10833,7 +10833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fbcf, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27920698368, + .flow_sig_id = 27920698368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10858,7 +10858,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d5a7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 27920706560, + .flow_sig_id = 27920706560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10884,7 +10884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9957, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30066084864, + .flow_sig_id = 30066084864UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10908,7 +10908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cb27, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30066093056, + .flow_sig_id = 30066093056UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10933,7 +10933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ee37, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30068182016, + .flow_sig_id = 30068182016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10958,7 +10958,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d987, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 30068190208, + .flow_sig_id = 30068190208UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -10984,7 +10984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a107, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32213568512, + .flow_sig_id = 32213568512UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11009,7 +11009,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d0e7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32213576704, + .flow_sig_id = 32213576704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11035,7 +11035,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f7e7, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32215665664, + .flow_sig_id = 32215665664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11061,7 +11061,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c827, .class_tid = 2, .hdr_sig_id = 4, - .flow_sig_id = 32215673856, + .flow_sig_id = 32215673856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11088,7 +11088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f76a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11109,7 +11109,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_bcae, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11131,7 +11131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dfc2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11153,7 +11153,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ee4a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11176,7 +11176,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cf26, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 538184704, + .flow_sig_id = 538184704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11198,7 +11198,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b53a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 538192896, + .flow_sig_id = 538192896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11221,7 +11221,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d79e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 540281856, + .flow_sig_id = 540281856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11244,7 +11244,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e606, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 540290048, + .flow_sig_id = 540290048UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11268,7 +11268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_be86, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1075055616, + .flow_sig_id = 1075055616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11290,7 +11290,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cd0e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1075063808, + .flow_sig_id = 1075063808UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11313,7 +11313,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d042, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1077152768, + .flow_sig_id = 1077152768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11336,7 +11336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d586, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1077160960, + .flow_sig_id = 1077160960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11360,7 +11360,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b712, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1611926528, + .flow_sig_id = 1611926528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11383,7 +11383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c59a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1611934720, + .flow_sig_id = 1611934720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11407,7 +11407,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e81e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1614023680, + .flow_sig_id = 1614023680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11431,7 +11431,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f686, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 1614031872, + .flow_sig_id = 1614031872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11456,7 +11456,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_86f6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11478,7 +11478,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d57e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11501,7 +11501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f792, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11524,7 +11524,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c61a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11548,7 +11548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9eb2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2685668352, + .flow_sig_id = 2685668352UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11571,7 +11571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ad3a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2685676544, + .flow_sig_id = 2685676544UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11595,7 +11595,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f01e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2687765504, + .flow_sig_id = 2687765504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11619,7 +11619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_de96, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 2687773696, + .flow_sig_id = 2687773696UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11644,7 +11644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d756, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3222539264, + .flow_sig_id = 3222539264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11667,7 +11667,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9c9a, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3222547456, + .flow_sig_id = 3222547456UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11691,7 +11691,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c812, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3224636416, + .flow_sig_id = 3224636416UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11715,7 +11715,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce56, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3224644608, + .flow_sig_id = 3224644608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11740,7 +11740,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_af12, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3759410176, + .flow_sig_id = 3759410176UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11764,7 +11764,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9516, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3759418368, + .flow_sig_id = 3759418368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11789,7 +11789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c09e, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3761507328, + .flow_sig_id = 3761507328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11814,7 +11814,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c612, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 3761515520, + .flow_sig_id = 3761515520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11840,7 +11840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9a06, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11862,7 +11862,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a886, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11885,7 +11885,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cba2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11908,7 +11908,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_da22, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11932,7 +11932,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9292, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4833152000, + .flow_sig_id = 4833152000UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11955,7 +11955,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a112, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4833160192, + .flow_sig_id = 4833160192UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -11979,7 +11979,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c436, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4835249152, + .flow_sig_id = 4835249152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12003,7 +12003,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d2a6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 4835257344, + .flow_sig_id = 4835257344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12028,7 +12028,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aa86, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5370022912, + .flow_sig_id = 5370022912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12051,7 +12051,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_90d2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5370031104, + .flow_sig_id = 5370031104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12075,7 +12075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dc02, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5372120064, + .flow_sig_id = 5372120064UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12099,7 +12099,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c246, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5372128256, + .flow_sig_id = 5372128256UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12124,7 +12124,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a312, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5906893824, + .flow_sig_id = 5906893824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12148,7 +12148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f192, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5906902016, + .flow_sig_id = 5906902016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12173,7 +12173,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d496, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5908990976, + .flow_sig_id = 5908990976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12198,7 +12198,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_da12, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 5908999168, + .flow_sig_id = 5908999168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12224,7 +12224,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b2d6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12247,7 +12247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c156, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12271,7 +12271,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e472, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12295,7 +12295,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f2f2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12320,7 +12320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8a92, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6980635648, + .flow_sig_id = 6980635648UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12344,7 +12344,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d912, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6980643840, + .flow_sig_id = 6980643840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12369,7 +12369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fc36, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6982732800, + .flow_sig_id = 6982732800UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12394,7 +12394,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cab6, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 6982740992, + .flow_sig_id = 6982740992UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12420,7 +12420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c356, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7517506560, + .flow_sig_id = 7517506560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12444,7 +12444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8892, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7517514752, + .flow_sig_id = 7517514752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12469,7 +12469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f4d2, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7519603712, + .flow_sig_id = 7519603712UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12494,7 +12494,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fa16, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 7519611904, + .flow_sig_id = 7519611904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12520,7 +12520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_db12, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8054377472, + .flow_sig_id = 8054377472UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12545,7 +12545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8116, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8054385664, + .flow_sig_id = 8054385664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12571,7 +12571,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cc96, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8056474624, + .flow_sig_id = 8056474624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12597,7 +12597,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f292, .class_tid = 2, .hdr_sig_id = 5, - .flow_sig_id = 8056482816, + .flow_sig_id = 8056482816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12624,7 +12624,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e84d, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12645,7 +12645,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a389, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12667,7 +12667,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c0e5, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12689,7 +12689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f16d, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12712,7 +12712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_99d1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12734,7 +12734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ca59, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12757,7 +12757,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e8b5, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12780,7 +12780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d93d, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12804,7 +12804,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8521, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12826,7 +12826,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b7a1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12849,7 +12849,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d485, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12872,7 +12872,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c505, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12896,7 +12896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_adf1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12919,7 +12919,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_de71, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12943,7 +12943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fb55, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12967,7 +12967,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_edd5, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -12992,7 +12992,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8b11, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8591248384, + .flow_sig_id = 8591248384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13014,7 +13014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_bd99, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8591256576, + .flow_sig_id = 8591256576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13037,7 +13037,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_daf1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8593345536, + .flow_sig_id = 8593345536UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13060,7 +13060,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cb79, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 8593353728, + .flow_sig_id = 8593353728UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13084,7 +13084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_93d1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10738732032, + .flow_sig_id = 10738732032UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13107,7 +13107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c459, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10738740224, + .flow_sig_id = 10738740224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13131,7 +13131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e2b1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10740829184, + .flow_sig_id = 10740829184UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13155,7 +13155,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d339, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 10740837376, + .flow_sig_id = 10740837376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13180,7 +13180,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9f31, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12886215680, + .flow_sig_id = 12886215680UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13203,7 +13203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b1b1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12886223872, + .flow_sig_id = 12886223872UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13227,7 +13227,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ee91, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12888312832, + .flow_sig_id = 12888312832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13251,7 +13251,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_df11, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 12888321024, + .flow_sig_id = 12888321024UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13276,7 +13276,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a7f1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15033699328, + .flow_sig_id = 15033699328UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13300,7 +13300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d871, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15033707520, + .flow_sig_id = 15033707520UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13325,7 +13325,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f551, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15035796480, + .flow_sig_id = 15035796480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13350,7 +13350,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e7d1, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 15035804672, + .flow_sig_id = 15035804672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13376,7 +13376,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8e1b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17181182976, + .flow_sig_id = 17181182976UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13398,7 +13398,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a083, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17181191168, + .flow_sig_id = 17181191168UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13421,7 +13421,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ddff, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17183280128, + .flow_sig_id = 17183280128UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13444,7 +13444,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce67, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 17183288320, + .flow_sig_id = 17183288320UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13468,7 +13468,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_96db, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19328666624, + .flow_sig_id = 19328666624UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13491,7 +13491,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c753, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19328674816, + .flow_sig_id = 19328674816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13515,7 +13515,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e5bf, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19330763776, + .flow_sig_id = 19330763776UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13539,7 +13539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d637, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 19330771968, + .flow_sig_id = 19330771968UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13564,7 +13564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8233, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21476150272, + .flow_sig_id = 21476150272UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13587,7 +13587,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b4a3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21476158464, + .flow_sig_id = 21476158464UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13611,7 +13611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d197, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21478247424, + .flow_sig_id = 21478247424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13635,7 +13635,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c207, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 21478255616, + .flow_sig_id = 21478255616UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13660,7 +13660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_aaf3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23623633920, + .flow_sig_id = 23623633920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13684,7 +13684,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_db73, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23623642112, + .flow_sig_id = 23623642112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13709,7 +13709,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f857, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23625731072, + .flow_sig_id = 23625731072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13734,7 +13734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ead7, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 23625739264, + .flow_sig_id = 23625739264UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13760,7 +13760,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_882b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25771117568, + .flow_sig_id = 25771117568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13783,7 +13783,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ba93, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25771125760, + .flow_sig_id = 25771125760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13807,7 +13807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d78b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25773214720, + .flow_sig_id = 25773214720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13831,7 +13831,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c873, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 25773222912, + .flow_sig_id = 25773222912UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13856,7 +13856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_90fb, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27918601216, + .flow_sig_id = 27918601216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13880,7 +13880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c153, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27918609408, + .flow_sig_id = 27918609408UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13905,7 +13905,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_fe5b, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27920698368, + .flow_sig_id = 27920698368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13930,7 +13930,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d033, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 27920706560, + .flow_sig_id = 27920706560UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13956,7 +13956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9cc3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30066084864, + .flow_sig_id = 30066084864UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -13980,7 +13980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ceb3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30066093056, + .flow_sig_id = 30066093056UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14005,7 +14005,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_eba3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30068182016, + .flow_sig_id = 30068182016UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14030,7 +14030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dc13, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 30068190208, + .flow_sig_id = 30068190208UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14056,7 +14056,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a493, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32213568512, + .flow_sig_id = 32213568512UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14081,7 +14081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d573, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32213576704, + .flow_sig_id = 32213576704UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14107,7 +14107,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_f273, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32215665664, + .flow_sig_id = 32215665664UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14133,7 +14133,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_cdb3, .class_tid = 2, .hdr_sig_id = 6, - .flow_sig_id = 32215673856, + .flow_sig_id = 32215673856UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -14160,7 +14160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ff35, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 1313792, + .flow_sig_id = 1313792UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14181,7 +14181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_b4f1, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 1321984, + .flow_sig_id = 1321984UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14203,7 +14203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d79d, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 3410944, + .flow_sig_id = 3410944UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14225,7 +14225,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_e615, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 3419136, + .flow_sig_id = 3419136UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14248,7 +14248,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_8ea9, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2148797440, + .flow_sig_id = 2148797440UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14270,7 +14270,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_dd21, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2148805632, + .flow_sig_id = 2148805632UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14293,7 +14293,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ffcd, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2150894592, + .flow_sig_id = 2150894592UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14316,7 +14316,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ce45, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 2150902784, + .flow_sig_id = 2150902784UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14340,7 +14340,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_9259, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4296281088, + .flow_sig_id = 4296281088UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14362,7 +14362,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_a0d9, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4296289280, + .flow_sig_id = 4296289280UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14385,7 +14385,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c3fd, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4298378240, + .flow_sig_id = 4298378240UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14408,7 +14408,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_d27d, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 4298386432, + .flow_sig_id = 4298386432UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14432,7 +14432,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ba89, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6443764736, + .flow_sig_id = 6443764736UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14455,7 +14455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_c909, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6443772928, + .flow_sig_id = 6443772928UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14479,7 +14479,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_ec2d, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6445861888, + .flow_sig_id = 6445861888UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14503,7 +14503,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_faad, .class_tid = 2, .hdr_sig_id = 7, - .flow_sig_id = 6445870080, + .flow_sig_id = 6445870080UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -14528,7 +14528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34c6, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14543,7 +14543,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c22, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4100, + .flow_sig_id = 4100UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14559,7 +14559,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cbe, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14575,7 +14575,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_179a, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 6148, + .flow_sig_id = 6148UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14592,7 +14592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59be, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14607,7 +14607,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_515a, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 16388, + .flow_sig_id = 16388UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14623,7 +14623,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c72, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14639,7 +14639,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_171e, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 24580, + .flow_sig_id = 24580UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14656,7 +14656,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19c8, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14672,7 +14672,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_112c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32772, + .flow_sig_id = 32772UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14689,7 +14689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d68, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14706,7 +14706,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_444c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32836, + .flow_sig_id = 32836UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14724,7 +14724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e8c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14741,7 +14741,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09e0, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14759,7 +14759,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1af0, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14777,7 +14777,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15d4, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49220, + .flow_sig_id = 49220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14796,7 +14796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1dd0, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14812,7 +14812,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14f4, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131076, + .flow_sig_id = 131076UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14829,7 +14829,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_70b0, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14846,7 +14846,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4854, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131140, + .flow_sig_id = 131140UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14864,7 +14864,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3dd4, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14881,7 +14881,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34f8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196612, + .flow_sig_id = 196612UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14899,7 +14899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09e8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14917,7 +14917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_008c, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196676, + .flow_sig_id = 196676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14936,7 +14936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34e6, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14952,7 +14952,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c02, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4100, + .flow_sig_id = 4100UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14969,7 +14969,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c9e, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -14986,7 +14986,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_17ba, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 6148, + .flow_sig_id = 6148UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15004,7 +15004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_429e, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15021,7 +15021,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5dba, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 12292, + .flow_sig_id = 12292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15039,7 +15039,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a16, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15057,7 +15057,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2532, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 14340, + .flow_sig_id = 14340UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15076,7 +15076,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2da2, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15093,7 +15093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_24fe, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 20484, + .flow_sig_id = 20484UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15111,7 +15111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_355a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15129,7 +15129,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c76, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 22532, + .flow_sig_id = 22532UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15148,7 +15148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13e6, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15166,7 +15166,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7276, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 28676, + .flow_sig_id = 28676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15185,7 +15185,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_42d2, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15204,7 +15204,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5dee, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 30724, + .flow_sig_id = 30724UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15224,7 +15224,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59de, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15240,7 +15240,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_513a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 16388, + .flow_sig_id = 16388UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15257,7 +15257,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c12, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15274,7 +15274,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_177e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 24580, + .flow_sig_id = 24580UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15292,7 +15292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0e92, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15309,7 +15309,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09fe, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15327,7 +15327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c1a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15345,7 +15345,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5746, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 57348, + .flow_sig_id = 57348UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15364,7 +15364,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_79da, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15381,7 +15381,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7106, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 81924, + .flow_sig_id = 81924UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15399,7 +15399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c1e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15417,7 +15417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_377a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 90116, + .flow_sig_id = 90116UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15436,7 +15436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e9e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15454,7 +15454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29fa, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15473,7 +15473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14d2, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15492,7 +15492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7742, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 122884, + .flow_sig_id = 122884UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15512,7 +15512,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3706, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15528,7 +15528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0fe2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4100, + .flow_sig_id = 4100UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15545,7 +15545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1f7e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15562,7 +15562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_145a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 6148, + .flow_sig_id = 6148UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15580,7 +15580,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_417e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15597,7 +15597,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e5a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 12292, + .flow_sig_id = 12292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15615,7 +15615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29f6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15633,7 +15633,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26d2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 14340, + .flow_sig_id = 14340UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15652,7 +15652,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e42, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15669,7 +15669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_271e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 20484, + .flow_sig_id = 20484UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15687,7 +15687,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_36ba, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15705,7 +15705,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0f96, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 22532, + .flow_sig_id = 22532UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15724,7 +15724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1006, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15742,7 +15742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7196, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 28676, + .flow_sig_id = 28676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15761,7 +15761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4132, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15780,7 +15780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e0e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 30724, + .flow_sig_id = 30724UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15800,7 +15800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59fe, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15816,7 +15816,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_511a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 16388, + .flow_sig_id = 16388UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15833,7 +15833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c32, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15850,7 +15850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_175e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 24580, + .flow_sig_id = 24580UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15868,7 +15868,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0eb2, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15885,7 +15885,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09de, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15903,7 +15903,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5c3a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15921,7 +15921,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5766, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 57348, + .flow_sig_id = 57348UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15940,7 +15940,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_79fa, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15957,7 +15957,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7126, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 81924, + .flow_sig_id = 81924UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15975,7 +15975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3c3e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -15993,7 +15993,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_375a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 90116, + .flow_sig_id = 90116UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16012,7 +16012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2ebe, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16030,7 +16030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29da, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16049,7 +16049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14f2, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16068,7 +16068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7762, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 122884, + .flow_sig_id = 122884UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16088,7 +16088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_19e8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16105,7 +16105,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_110c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32772, + .flow_sig_id = 32772UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16123,7 +16123,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d48, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16141,7 +16141,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_446c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32836, + .flow_sig_id = 32836UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16160,7 +16160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0eac, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16178,7 +16178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09c0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16197,7 +16197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ad0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16216,7 +16216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15f4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49220, + .flow_sig_id = 49220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16236,7 +16236,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39ec, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16254,7 +16254,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3100, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98308, + .flow_sig_id = 98308UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16273,7 +16273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0210, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16292,7 +16292,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1d34, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98372, + .flow_sig_id = 98372UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16312,7 +16312,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2ea0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16331,7 +16331,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29c4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16351,7 +16351,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ad4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16371,7 +16371,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35e8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114756, + .flow_sig_id = 114756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16392,7 +16392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d80, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16410,7 +16410,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_54a4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163844, + .flow_sig_id = 163844UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16429,7 +16429,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_29b4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16448,7 +16448,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20c8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163908, + .flow_sig_id = 163908UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16468,7 +16468,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7244, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16487,7 +16487,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d98, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180228, + .flow_sig_id = 180228UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16507,7 +16507,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e68, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16527,7 +16527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_598c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180292, + .flow_sig_id = 180292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16548,7 +16548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1248, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16567,7 +16567,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_74d8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229380, + .flow_sig_id = 229380UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16587,7 +16587,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_49a8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16607,7 +16607,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40cc, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229444, + .flow_sig_id = 229444UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16628,7 +16628,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b0c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16648,7 +16648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0220, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245764, + .flow_sig_id = 245764UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16669,7 +16669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1730, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16690,7 +16690,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7980, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245828, + .flow_sig_id = 245828UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16712,7 +16712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1db0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16729,7 +16729,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1494, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131076, + .flow_sig_id = 131076UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16747,7 +16747,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_70d0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16765,7 +16765,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4834, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131140, + .flow_sig_id = 131140UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16784,7 +16784,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3db4, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16802,7 +16802,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3498, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196612, + .flow_sig_id = 196612UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16821,7 +16821,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0988, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16840,7 +16840,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00ec, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196676, + .flow_sig_id = 196676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16860,7 +16860,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3f44, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16878,7 +16878,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_36a8, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393220, + .flow_sig_id = 393220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16897,7 +16897,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b58, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16916,7 +16916,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_02bc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393284, + .flow_sig_id = 393284UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16936,7 +16936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f48, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16955,7 +16955,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_56ac, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458756, + .flow_sig_id = 458756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16975,7 +16975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2b5c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -16995,7 +16995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2280, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458820, + .flow_sig_id = 458820UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17016,7 +17016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4000, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17034,7 +17034,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5b64, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655364, + .flow_sig_id = 655364UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17053,7 +17053,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2c14, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17072,7 +17072,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2778, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655428, + .flow_sig_id = 655428UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17092,7 +17092,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_18f8, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17111,7 +17111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13dc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720900, + .flow_sig_id = 720900UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17131,7 +17131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c18, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17151,7 +17151,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_477c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720964, + .flow_sig_id = 720964UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17172,7 +17172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1a88, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17191,7 +17191,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15ec, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917508, + .flow_sig_id = 917508UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17211,7 +17211,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e28, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17231,7 +17231,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_490c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917572, + .flow_sig_id = 917572UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17252,7 +17252,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a8c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17272,7 +17272,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35f0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983044, + .flow_sig_id = 983044UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17293,7 +17293,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06e0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17314,7 +17314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01c4, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983108, + .flow_sig_id = 983108UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17336,7 +17336,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1a08, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17353,7 +17353,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_12ec, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32772, + .flow_sig_id = 32772UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17371,7 +17371,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4ea8, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17389,7 +17389,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_478c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32836, + .flow_sig_id = 32836UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17408,7 +17408,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d4c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17426,7 +17426,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0a20, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49156, + .flow_sig_id = 49156UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17445,7 +17445,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1930, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17464,7 +17464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1614, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49220, + .flow_sig_id = 49220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17484,7 +17484,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a0c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17502,7 +17502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_32e0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98308, + .flow_sig_id = 98308UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17521,7 +17521,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01f0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17540,7 +17540,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ed4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98372, + .flow_sig_id = 98372UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17560,7 +17560,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2d40, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17579,7 +17579,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a24, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114692, + .flow_sig_id = 114692UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17599,7 +17599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3934, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17619,7 +17619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3608, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114756, + .flow_sig_id = 114756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17640,7 +17640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5e60, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17658,7 +17658,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5744, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163844, + .flow_sig_id = 163844UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17677,7 +17677,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a54, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17696,7 +17696,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2328, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163908, + .flow_sig_id = 163908UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17716,7 +17716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_71a4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17735,7 +17735,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e78, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180228, + .flow_sig_id = 180228UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17755,7 +17755,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5d88, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17775,7 +17775,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5a6c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180292, + .flow_sig_id = 180292UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17796,7 +17796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_11a8, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17815,7 +17815,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7738, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229380, + .flow_sig_id = 229380UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17835,7 +17835,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4a48, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17855,7 +17855,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_432c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229444, + .flow_sig_id = 229444UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17876,7 +17876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_08ec, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17896,7 +17896,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01c0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245764, + .flow_sig_id = 245764UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17917,7 +17917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14d0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17938,7 +17938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7a60, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245828, + .flow_sig_id = 245828UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17960,7 +17960,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1d90, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17977,7 +17977,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_14b4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131076, + .flow_sig_id = 131076UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -17995,7 +17995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_70f0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18013,7 +18013,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4814, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131140, + .flow_sig_id = 131140UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18032,7 +18032,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d94, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18050,7 +18050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_34b8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196612, + .flow_sig_id = 196612UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18069,7 +18069,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_09a8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18088,7 +18088,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_00cc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196676, + .flow_sig_id = 196676UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18108,7 +18108,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3f64, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18126,7 +18126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3688, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393220, + .flow_sig_id = 393220UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18145,7 +18145,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0b78, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18164,7 +18164,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_029c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393284, + .flow_sig_id = 393284UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18184,7 +18184,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5f68, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18203,7 +18203,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_568c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458756, + .flow_sig_id = 458756UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18223,7 +18223,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2b7c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18243,7 +18243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_22a0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458820, + .flow_sig_id = 458820UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18264,7 +18264,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4020, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18282,7 +18282,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5b44, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655364, + .flow_sig_id = 655364UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18301,7 +18301,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2c34, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18320,7 +18320,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2758, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655428, + .flow_sig_id = 655428UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18340,7 +18340,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_18d8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18359,7 +18359,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_13fc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720900, + .flow_sig_id = 720900UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18379,7 +18379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4c38, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18399,7 +18399,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_475c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720964, + .flow_sig_id = 720964UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18420,7 +18420,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1aa8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18439,7 +18439,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_15cc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917508, + .flow_sig_id = 917508UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18459,7 +18459,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e08, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18479,7 +18479,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_492c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917572, + .flow_sig_id = 917572UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18500,7 +18500,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3aac, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18520,7 +18520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_35d0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983044, + .flow_sig_id = 983044UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18541,7 +18541,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06c0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18562,7 +18562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_01e4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983108, + .flow_sig_id = 983108UL, .flow_pattern_id = 0, .app_sig = 0, .hdr_sig = { .bits = @@ -18584,7 +18584,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d32, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18598,7 +18598,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_54aa, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18613,7 +18613,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0686, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18627,7 +18627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_540e, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18642,7 +18642,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e3c, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18657,7 +18657,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a20, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18673,7 +18673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46f0, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18689,7 +18689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52e4, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18706,7 +18706,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55e4, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18721,7 +18721,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_21f8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18737,7 +18737,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_75e8, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18753,7 +18753,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_41fc, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18770,7 +18770,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d12, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18785,7 +18785,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_548a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18801,7 +18801,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3356, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18817,7 +18817,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1ace, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18834,7 +18834,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1a9a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18850,7 +18850,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4d46, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18867,7 +18867,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2812, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18884,7 +18884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_338a, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18902,7 +18902,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06e6, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18917,7 +18917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_546e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18933,7 +18933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46ee, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18949,7 +18949,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d22, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18966,7 +18966,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26e2, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18982,7 +18982,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_746a, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -18999,7 +18999,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1fa6, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19016,7 +19016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2d2e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19034,7 +19034,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4ef2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4096, + .flow_sig_id = 4096UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19049,7 +19049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_576a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 6144, + .flow_sig_id = 6144UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19065,7 +19065,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_30b6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 12288, + .flow_sig_id = 12288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19081,7 +19081,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_192e, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 14336, + .flow_sig_id = 14336UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19098,7 +19098,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_197a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 20480, + .flow_sig_id = 20480UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19114,7 +19114,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4ea6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 22528, + .flow_sig_id = 22528UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19131,7 +19131,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2bf2, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 28672, + .flow_sig_id = 28672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19148,7 +19148,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_306a, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 30720, + .flow_sig_id = 30720UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19166,7 +19166,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_06c6, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 16384, + .flow_sig_id = 16384UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19181,7 +19181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_544e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 24576, + .flow_sig_id = 24576UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19197,7 +19197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46ce, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19213,7 +19213,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0d02, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 57344, + .flow_sig_id = 57344UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19230,7 +19230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_26c2, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 81920, + .flow_sig_id = 81920UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19246,7 +19246,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_744a, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 90112, + .flow_sig_id = 90112UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19263,7 +19263,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1f86, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19280,7 +19280,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2d0e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 122880, + .flow_sig_id = 122880UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19298,7 +19298,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2e1c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19314,7 +19314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3a00, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19331,7 +19331,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_46d0, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19348,7 +19348,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52c4, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19366,7 +19366,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4e10, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19383,7 +19383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5a04, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19401,7 +19401,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1f98, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19419,7 +19419,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_72f8, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19438,7 +19438,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0a78, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19455,7 +19455,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_166c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19473,7 +19473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_233c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19491,7 +19491,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0f20, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19510,7 +19510,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2a7c, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19528,7 +19528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3660, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19547,7 +19547,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4330, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19566,7 +19566,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2f24, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19586,7 +19586,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5584, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19602,7 +19602,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2198, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19619,7 +19619,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7588, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19636,7 +19636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_419c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19654,7 +19654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7758, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19671,7 +19671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_43ac, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19689,7 +19689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c10, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19707,7 +19707,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1864, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19726,7 +19726,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_30c8, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19743,7 +19743,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cdc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19761,7 +19761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_50cc, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19779,7 +19779,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d20, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19798,7 +19798,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_529c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19816,7 +19816,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ef0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19835,7 +19835,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_72e0, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19854,7 +19854,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ef4, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19874,7 +19874,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2dfc, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32768, + .flow_sig_id = 32768UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19890,7 +19890,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_39e0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 32832, + .flow_sig_id = 32832UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19907,7 +19907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4530, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49152, + .flow_sig_id = 49152UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19924,7 +19924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5124, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 49216, + .flow_sig_id = 49216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19942,7 +19942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_4df0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98304, + .flow_sig_id = 98304UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19959,7 +19959,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_59e4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 98368, + .flow_sig_id = 98368UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19977,7 +19977,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1c78, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114688, + .flow_sig_id = 114688UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -19995,7 +19995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7118, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 114752, + .flow_sig_id = 114752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20014,7 +20014,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0998, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163840, + .flow_sig_id = 163840UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20031,7 +20031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_158c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 163904, + .flow_sig_id = 163904UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20049,7 +20049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_20dc, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180224, + .flow_sig_id = 180224UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20067,7 +20067,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0cc0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 180288, + .flow_sig_id = 180288UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20086,7 +20086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_299c, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229376, + .flow_sig_id = 229376UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20104,7 +20104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3580, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 229440, + .flow_sig_id = 229440UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20123,7 +20123,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_40d0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245760, + .flow_sig_id = 245760UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20142,7 +20142,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_2cc4, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 245824, + .flow_sig_id = 245824UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20162,7 +20162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_55a4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131072, + .flow_sig_id = 131072UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20178,7 +20178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_21b8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 131136, + .flow_sig_id = 131136UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20195,7 +20195,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_75a8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196608, + .flow_sig_id = 196608UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20212,7 +20212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_41bc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 196672, + .flow_sig_id = 196672UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20230,7 +20230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_7778, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393216, + .flow_sig_id = 393216UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20247,7 +20247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_438c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 393280, + .flow_sig_id = 393280UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20265,7 +20265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0c30, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458752, + .flow_sig_id = 458752UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20283,7 +20283,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1844, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 458816, + .flow_sig_id = 458816UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20302,7 +20302,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_30e8, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655360, + .flow_sig_id = 655360UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20319,7 +20319,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_1cfc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 655424, + .flow_sig_id = 655424UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20337,7 +20337,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_50ec, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720896, + .flow_sig_id = 720896UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20355,7 +20355,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3d00, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 720960, + .flow_sig_id = 720960UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20374,7 +20374,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_52bc, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917504, + .flow_sig_id = 917504UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20392,7 +20392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ed0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 917568, + .flow_sig_id = 917568UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20411,7 +20411,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_72c0, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983040, + .flow_sig_id = 983040UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20430,7 +20430,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_5ed4, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 983104, + .flow_sig_id = 983104UL, .flow_pattern_id = 1, .app_sig = 0, .hdr_sig = { .bits = @@ -20450,7 +20450,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3866, .class_tid = 3, .hdr_sig_id = 0, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20465,7 +20465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_381e, .class_tid = 3, .hdr_sig_id = 1, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20480,7 +20480,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3860, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20496,7 +20496,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0454, .class_tid = 3, .hdr_sig_id = 2, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20513,7 +20513,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3818, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20529,7 +20529,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_042c, .class_tid = 3, .hdr_sig_id = 3, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20546,7 +20546,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3846, .class_tid = 3, .hdr_sig_id = 4, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20562,7 +20562,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_387e, .class_tid = 3, .hdr_sig_id = 5, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20578,7 +20578,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ba6, .class_tid = 3, .hdr_sig_id = 6, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20594,7 +20594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_385e, .class_tid = 3, .hdr_sig_id = 7, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20610,7 +20610,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3840, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20627,7 +20627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0474, .class_tid = 3, .hdr_sig_id = 8, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20645,7 +20645,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3878, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20662,7 +20662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_044c, .class_tid = 3, .hdr_sig_id = 9, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20680,7 +20680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3ba0, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20697,7 +20697,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_0794, .class_tid = 3, .hdr_sig_id = 10, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20715,7 +20715,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_3858, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 4, + .flow_sig_id = 4UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = @@ -20732,7 +20732,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { .class_hid = BNXT_ULP_CLASS_HID_046c, .class_tid = 3, .hdr_sig_id = 11, - .flow_sig_id = 68, + .flow_sig_id = 68UL, .flow_pattern_id = 2, .app_sig = 0, .hdr_sig = { .bits = -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 08/22] net/bnxt: enable wildcard match for ingress flows 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (6 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 07/22] net/bnxt: address ISO C90 compilation error Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 09/22] net/bnxt: support inner IP header for GRE tunnel flows Ajit Khaparde ` (15 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Mike Baucom [-- Attachment #1: Type: text/plain, Size: 45053 bytes --] Enabled wildcard match support for ipv4 ingress flows. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> --- .../generic_templates/ulp_template_db_enum.h | 4 +- .../ulp_template_db_thor_class.c | 251 +++++++++--------- 2 files changed, 125 insertions(+), 130 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index 31a94c14dc..8706e45f28 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 11:11:05 2021 */ +/* date: Thu Sep 9 12:11:08 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -48,7 +48,7 @@ #define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2323 #define ULP_THOR_CLASS_IDENT_LIST_SIZE 38 #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313 -#define ULP_THOR_CLASS_COND_LIST_SIZE 55 +#define ULP_THOR_CLASS_COND_LIST_SIZE 54 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 95205a2421..54bc032b0c 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Aug 25 16:41:37 2021 */ +/* date: Thu Sep 9 12:11:08 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -18,9 +18,9 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .num_tbls = 28, .start_tbl_idx = 0, .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 0, - .cond_nums = 1 } + .cond_nums = 0 } }, /* class_tid: 2, ingress */ [2] = { @@ -29,7 +29,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 28, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 } }, /* class_tid: 3, egress */ @@ -39,7 +39,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 52, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 0 } }, /* class_tid: 4, ingress */ @@ -49,7 +49,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 70, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 } }, /* class_tid: 5, egress */ @@ -59,7 +59,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 91, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 } } }; @@ -74,7 +74,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -96,7 +96,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 5, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -117,7 +117,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -136,7 +136,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -149,7 +149,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -176,7 +176,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -196,7 +196,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -209,7 +209,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 4, + .cond_start_idx = 3, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -228,7 +228,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 5, + .cond_start_idx = 4, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -240,7 +240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 6, + .cond_start_idx = 5, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -259,7 +259,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 7, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -277,7 +277,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 7, + .cond_start_idx = 6, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -307,7 +307,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -328,7 +328,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -349,7 +349,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -368,7 +368,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 6, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -381,7 +381,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 9, + .cond_start_idx = 8, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, @@ -398,7 +398,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 10, + .cond_start_idx = 9, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, @@ -415,7 +415,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 11, + .cond_start_idx = 10, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -443,7 +443,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 13, + .cond_start_idx = 12, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -473,7 +473,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -494,7 +494,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 14, + .cond_start_idx = 13, .cond_nums = 3 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -519,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, + .cond_start_idx = 16, .cond_nums = 3 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -544,7 +544,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 19, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -569,7 +569,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 22, + .cond_start_idx = 21, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -594,7 +594,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 23, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -619,7 +619,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 25, + .cond_start_idx = 24, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -644,7 +644,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 27, + .cond_start_idx = 26, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -670,7 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -691,7 +691,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -710,7 +710,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -723,7 +723,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -750,7 +750,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -770,7 +770,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -783,7 +783,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 30, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -802,7 +802,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, + .cond_start_idx = 30, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -815,7 +815,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -842,7 +842,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -862,7 +862,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -875,7 +875,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, + .cond_start_idx = 32, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -894,7 +894,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 33, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -906,7 +906,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 34, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -925,7 +925,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -943,7 +943,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -973,7 +973,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -994,7 +994,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -1016,7 +1016,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1035,7 +1035,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1048,7 +1048,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 36, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, @@ -1065,7 +1065,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1093,7 +1093,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1114,7 +1114,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1140,7 +1140,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1159,7 +1159,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -1172,7 +1172,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 40, + .cond_start_idx = 39, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1191,7 +1191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 41, + .cond_start_idx = 40, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1203,7 +1203,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 42, + .cond_start_idx = 41, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -1222,7 +1222,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -1240,7 +1240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1270,7 +1270,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1291,7 +1291,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -1312,7 +1312,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1331,7 +1331,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1344,7 +1344,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 44, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, @@ -1361,7 +1361,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 44, + .cond_start_idx = 43, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1389,7 +1389,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1419,7 +1419,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1440,7 +1440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1465,7 +1465,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 47, + .cond_start_idx = 46, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1490,7 +1490,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1517,7 +1517,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, @@ -1536,7 +1536,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1558,7 +1558,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1577,7 +1577,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1590,7 +1590,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1619,7 +1619,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1640,7 +1640,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -1657,7 +1657,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -1676,7 +1676,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -1696,7 +1696,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1716,7 +1716,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -1729,7 +1729,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 50, + .cond_start_idx = 49, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1748,7 +1748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 50, + .cond_start_idx = 49, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1761,7 +1761,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, @@ -1780,7 +1780,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1802,7 +1802,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1821,7 +1821,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1834,7 +1834,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1861,7 +1861,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1882,7 +1882,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1899,7 +1899,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1918,7 +1918,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, @@ -1938,7 +1938,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1960,7 +1960,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1979,7 +1979,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1992,7 +1992,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -2019,7 +2019,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2040,7 +2040,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, @@ -2057,7 +2057,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, @@ -2076,7 +2076,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2095,7 +2095,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF, @@ -2114,7 +2114,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2133,7 +2133,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -2146,7 +2146,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, @@ -2165,7 +2165,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2188,7 +2188,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0, @@ -2207,7 +2207,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, @@ -2227,7 +2227,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2246,7 +2246,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2265,7 +2265,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -2278,7 +2278,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -2306,7 +2306,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, @@ -2323,7 +2323,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -2350,7 +2350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2373,7 +2373,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2391,7 +2391,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -2406,11 +2406,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { }; struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { - /* cond_reject: thor, class_tid: 1 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH - }, /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */ { .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 09/22] net/bnxt: support inner IP header for GRE tunnel flows 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (7 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 08/22] net/bnxt: enable wildcard match for ingress flows Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 10/22] net/bnxt: get TruFlow version Ajit Khaparde ` (14 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Mike Baucom, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 2945 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> This change allows adding IP header matches for GRE flows that does not specify outer IP header in the flow match pattern. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 7 ++++--- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 40da953f06..605c29223c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -1119,7 +1119,8 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, /* Set the ipv4 header bitmap and computed l3 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) { + ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6) || + ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV4); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1); inner_flag = 1; @@ -1245,7 +1246,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, /* Set the ipv6 header bitmap and computed l3 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) { + ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6) || + ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV6); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1); inner_flag = 1; @@ -2127,7 +2129,6 @@ ulp_rte_vxlan_decap_act_handler(const struct rte_flow_action *action_item BNXT_ULP_ACT_BIT_VXLAN_DECAP); /* Update computational field with tunnel decap info */ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN_DECAP, 1); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1); return BNXT_TF_RC_SUCCESS; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index d3bfb8c12d..7d1bc06a3e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -27,7 +27,7 @@ #define BNXT_ULP_PROTO_HDR_UDP_NUM 4 #define BNXT_ULP_PROTO_HDR_TCP_NUM 9 #define BNXT_ULP_PROTO_HDR_VXLAN_NUM 4 -#define BNXT_ULP_PROTO_HDR_GRE_NUM 6 +#define BNXT_ULP_PROTO_HDR_GRE_NUM 2 #define BNXT_ULP_PROTO_HDR_ICMP_NUM 5 #define BNXT_ULP_PROTO_HDR_MAX 128 #define BNXT_ULP_PROTO_HDR_ENCAP_MAX 64 -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 10/22] net/bnxt: get TruFlow version 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (8 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 09/22] net/bnxt: support inner IP header for GRE tunnel flows Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 11/22] net/bnxt: increase flow scale for Thor Ajit Khaparde ` (13 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev Cc: Jay Ding, Venkat Duvvuru, Farah Smith, Randy Schacher, Peter Spreadborough [-- Attachment #1: Type: text/plain, Size: 18919 bytes --] From: Jay Ding <jay.ding@broadcom.com> Implement tf_get_version that returns TruFlow version numbers and CFA resources capbilities. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_core/tf_core.c | 29 ++++++++ drivers/net/bnxt/tf_core/tf_core.h | 75 ++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device.h | 50 ++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p4.c | 65 +++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p4.h | 79 +++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p58.c | 65 +++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p58.h | 87 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_msg.c | 35 ++++++++++ drivers/net/bnxt/tf_core/tf_msg.h | 19 ++++++ 9 files changed, 502 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 936102c804..86dfec0eb4 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1802,3 +1802,32 @@ int tf_get_session_info(struct tf *tfp, return 0; } + +int tf_get_version(struct tf *tfp, + struct tf_get_version_parms *parms) +{ + int rc; + struct tf_dev_info dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_WH && + parms->device_type != TF_DEVICE_TYPE_THOR && + parms->device_type != TF_DEVICE_TYPE_SR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + rc = tf_msg_get_version(parms->bp, &dev, parms); + if (rc) + return rc; + + return 0; +} diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index fb02c2b161..ba9881c69d 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2363,4 +2363,79 @@ struct tf_get_if_tbl_entry_parms { int tf_get_if_tbl_entry(struct tf *tfp, struct tf_get_if_tbl_entry_parms *parms); +/** + * tf_get_version parameters definition. + */ +struct tf_get_version_parms { + /** + * [in] device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] bp + * The pointer to the parent bp struct. This is only used for HWRM + * message passing within the portability layer. The type is struct + * bnxt. + */ + void *bp; + + /* [out] major + * + * Version Major number. + */ + uint8_t major; + + /* [out] minor + * + * Version Minor number. + */ + uint8_t minor; + + /* [out] update + * + * Version Update number. + */ + uint8_t update; + + /** + * [out] dev_ident_caps + * + * fw available identifier resource list + */ + uint32_t dev_ident_caps; + + /** + * [out] dev_tbl_caps + * + * fw available table resource list + */ + uint32_t dev_tbl_caps; + + /** + * [out] dev_tcam_caps + * + * fw available tcam resource list + */ + uint32_t dev_tcam_caps; + + /** + * [out] dev_em_caps + * + * fw available em resource list + */ + uint32_t dev_em_caps; +}; + +/** + * Get tf fw version + * + * Used to retrieve Truflow fw version information. + * + * Returns success or failure code. + */ +int tf_get_version(struct tf *tfp, + struct tf_get_version_parms *parms); #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 9b0c037db0..88bd4515ff 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -6,6 +6,7 @@ #ifndef _TF_DEVICE_H_ #define _TF_DEVICE_H_ +#include "cfa_resource_types.h" #include "tf_core.h" #include "tf_identifier.h" #include "tf_tbl.h" @@ -36,6 +37,21 @@ struct tf_dev_info { const struct tf_dev_ops *ops; }; +/** + * This structure can be used to translate the CFA resource type to TF type. + */ +struct tf_hcapi_resource_map { + /** + * Truflow module type associated with this resource type. + */ + enum tf_module_type module_type; + + /** + * Bitmap of TF sub-type for the element. + */ + uint32_t type_caps; +}; + /** * @page device Device * @@ -1037,6 +1053,34 @@ struct tf_dev_ops { */ uint64_t (*tf_dev_cfa_key_hash)(uint64_t *key_data, uint16_t bitlen); + + /** + * Translate the CFA resource type to Truflow type + * + * [in] hcapi_types + * CFA resource type bitmap + * + * [out] ident_types + * Pointer to identifier type bitmap + * + * [out] tcam_types + * Pointer to tcam type bitmap + * + * [out] tbl_types + * Pointer to table type bitmap + * + * [out] em_types + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_map_hcapi_caps)(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps); }; /** @@ -1047,4 +1091,10 @@ extern const struct tf_dev_ops tf_dev_ops_p4; extern const struct tf_dev_ops tf_dev_ops_p58_init; extern const struct tf_dev_ops tf_dev_ops_p58; +/** + * Supported device resource type mapping structures + */ +extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1]; +extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1]; + #endif /* _TF_DEVICE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 826cd0cdbc..8089785b82 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -271,6 +271,67 @@ static bool tf_dev_p4_is_sram_managed(struct tf *tfp __rte_unused, { return false; } + +/** + * Device specific function that maps the hcapi resource types + * to Truflow type. + * + * [in] hcapi_caps + * CFA resource type bitmap + * + * [out] ident_caps + * Pointer to identifier type bitmap + * + * [out] tcam_caps + * Pointer to tcam type bitmap + * + * [out] tbl_caps + * Pointer to table type bitmap + * + * [out] em_caps + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p4_map_hcapi_caps(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps) +{ + uint32_t i; + + *ident_caps = 0; + *tcam_caps = 0; + *tbl_caps = 0; + *em_caps = 0; + + for (i = 0; i <= CFA_RESOURCE_TYPE_P4_LAST; i++) { + if (hcapi_caps & 1ULL << i) { + switch (tf_hcapi_res_map_p4[i].module_type) { + case TF_MODULE_TYPE_IDENTIFIER: + *ident_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_TABLE: + *tbl_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_TCAM: + *tcam_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_EM: + *em_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + default: + return -EINVAL; + } + } + } + + return 0; +} + /** * Truflow P4 device specific functions */ @@ -321,6 +382,7 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = NULL, + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps }; /** @@ -382,5 +444,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = tf_dev_p4_word_align, - .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash + .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index c1357913f1..e84c0f9e83 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -157,4 +157,83 @@ struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = { TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK }, }; + +const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { + [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW + }, + [CFA_RESOURCE_TYPE_P4_PROF_FUNC] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC + }, + [CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF + }, + [CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW + }, + [CFA_RESOURCE_TYPE_P4_PROF_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM + }, + [CFA_RESOURCE_TYPE_P4_WC_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM + }, + [CFA_RESOURCE_TYPE_P4_SP_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_SP_TCAM + }, + [CFA_RESOURCE_TYPE_P4_NAT_IPV4] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_MODIFY_IPV4 + }, + [CFA_RESOURCE_TYPE_P4_METER_PROF] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF + }, + [CFA_RESOURCE_TYPE_P4_METER] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST + }, + [CFA_RESOURCE_TYPE_P4_MIRROR] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG + }, + [CFA_RESOURCE_TYPE_P4_FULL_ACTION] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_FULL_ACT_RECORD + }, + [CFA_RESOURCE_TYPE_P4_MCG] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MCAST_GROUPS + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_8B + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_16B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_16B + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_64B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_64B + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4 + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6 + }, + [CFA_RESOURCE_TYPE_P4_COUNTER_64B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64 + }, + [CFA_RESOURCE_TYPE_P4_EM_REC] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD + }, + [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_TBL_SCOPE + }, +}; + #endif /* _TF_DEVICE_P4_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 47d7836a58..03e72b90f5 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -45,6 +45,7 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { [CFA_RESOURCE_TYPE_P58_WC_FKB] = "wc_fkb ", [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = "veb ", [CFA_RESOURCE_TYPE_P58_METADATA] = "metadata", + [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = "meter_dc", }; /** @@ -336,6 +337,66 @@ static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused, return 0; } +/** + * Device specific function that maps the hcapi resource types + * to Truflow type. + * + * [in] hcapi_caps + * CFA resource type bitmap + * + * [out] ident_caps + * Pointer to identifier type bitmap + * + * [out] tcam_caps + * Pointer to tcam type bitmap + * + * [out] tbl_caps + * Pointer to table type bitmap + * + * [out] em_caps + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_map_hcapi_caps(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps) +{ + uint32_t i; + + *ident_caps = 0; + *tcam_caps = 0; + *tbl_caps = 0; + *em_caps = 0; + + for (i = 0; i <= CFA_RESOURCE_TYPE_P58_LAST; i++) { + if (hcapi_caps & 1ULL << i) { + switch (tf_hcapi_res_map_p58[i].module_type) { + case TF_MODULE_TYPE_IDENTIFIER: + *ident_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_TABLE: + *tbl_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_TCAM: + *tcam_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_EM: + *em_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + default: + return -EINVAL; + } + } + } + + return 0; +} + /** * Truflow P58 device specific functions */ @@ -386,6 +447,7 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = NULL, + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps }; /** @@ -448,5 +510,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = tf_dev_p58_word_align, - .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash + .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index 3e8759f2df..f6e66936f3 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -209,4 +209,91 @@ struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = { TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_INTERVAL_CFG }, }; + +const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { + [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW + }, + [CFA_RESOURCE_TYPE_P58_PROF_FUNC] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC + }, + [CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF + }, + [CFA_RESOURCE_TYPE_P58_EM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW + }, + [CFA_RESOURCE_TYPE_P58_PROF_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM + }, + [CFA_RESOURCE_TYPE_P58_WC_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM + }, + [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_VEB_TCAM + }, + [CFA_RESOURCE_TYPE_P58_EM_FKB] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_EM_FKB + }, + [CFA_RESOURCE_TYPE_P58_WC_FKB] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_WC_FKB + }, + [CFA_RESOURCE_TYPE_P58_METER_PROF] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF + }, + [CFA_RESOURCE_TYPE_P58_METER] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST + }, + [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_DROP_CNT + }, + [CFA_RESOURCE_TYPE_P58_MIRROR] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG + }, + [CFA_RESOURCE_TYPE_P58_METADATA] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METADATA + }, + /* Resources in bank 1 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_FULL_ACT_RECORD + | 1 << TF_TBL_TYPE_COMPACT_ACT_RECORD + }, + /* Resources in bank 2 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_ACT_ENCAP_8B | + 1 << TF_TBL_TYPE_ACT_ENCAP_16B | + 1 << TF_TBL_TYPE_ACT_ENCAP_32B | + 1 << TF_TBL_TYPE_ACT_ENCAP_64B | + 1 << TF_TBL_TYPE_ACT_MODIFY_8B | + 1 << TF_TBL_TYPE_ACT_MODIFY_16B | + 1 << TF_TBL_TYPE_ACT_MODIFY_32B | + 1 << TF_TBL_TYPE_ACT_MODIFY_64B + + }, + /* Resources in bank 0 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_ACT_SP_SMAC | + 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4 | + 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6 + }, + /* Resources in bank 3 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64 + }, + [CFA_RESOURCE_TYPE_P58_EM_REC] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD + }, +}; #endif /* _TF_DEVICE_P58_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index ea6e2af7ce..25bf026658 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -2306,3 +2306,38 @@ tf_msg_set_if_tbl_entry(struct tf *tfp, return 0; } + +int +tf_msg_get_version(struct bnxt *bp, + struct tf_dev_info *dev, + struct tf_get_version_parms *params) + +{ + int rc; + struct hwrm_tf_version_get_input req = { 0 }; + struct hwrm_tf_version_get_output resp = { 0 }; + struct tfp_send_msg_parms parms = { 0 }; + + /* Populate the request */ + parms.tf_type = HWRM_TF_VERSION_GET, + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(bp, + &parms); + + params->major = resp.major; + params->minor = resp.minor; + params->update = resp.update; + + dev->ops->tf_dev_map_hcapi_caps(resp.dev_caps_cfg, + ¶ms->dev_ident_caps, + ¶ms->dev_tcam_caps, + ¶ms->dev_tbl_caps, + ¶ms->dev_em_caps); + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 718bc2f3b2..08d20cdd7a 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -738,4 +738,23 @@ int tf_msg_set_if_tbl_entry(struct tf *tfp, int tf_msg_get_if_tbl_entry(struct tf *tfp, struct tf_if_tbl_get_parms *params); +/** + * Send get version request to the firmware. + * + * [in] bp + * Pointer to bnxt handle + * + * [in] dev + * Pointer to the associated device + * + * [in/out] parms + * Pointer to the version info parameter + * + * Returns: + * 0 on Success else internal Truflow error + */ +int +tf_msg_get_version(struct bnxt *bp, + struct tf_dev_info *dev, + struct tf_get_version_parms *parms); #endif /* _TF_MSG_H_ */ -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 11/22] net/bnxt: increase flow scale for Thor 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (9 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 10/22] net/bnxt: get TruFlow version Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 12/22] net/bnxt: remove devargs for stats accumulation Ajit Khaparde ` (12 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Shahaji Bhosle, Kishore Padmanabha, Venkat Duvvuru, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 8091 bytes --] From: Shahaji Bhosle <sbhosle@broadcom.com> * Updated defines and data types to allow 256 VFRs. * Increased the encap record cache to support 256 to 4K entries. So VxLAN connections can be scaled to 4K entries. Signed-off-by: Shahaji Bhosle <sbhosle@broadcom.com> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/bnxt.h | 6 +++++- drivers/net/bnxt/bnxt_cpr.c | 2 +- drivers/net/bnxt/bnxt_ethdev.c | 18 +++++++++--------- drivers/net/bnxt/bnxt_reps.c | 3 +-- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 2 +- .../generic_templates/ulp_template_db_tbl.c | 8 ++++---- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 6 +++--- 7 files changed, 24 insertions(+), 21 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 4ab9ebd049..54039ba1a9 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -240,7 +240,11 @@ struct bnxt_parent_info { struct bnxt_pf_info { #define BNXT_FIRST_PF_FID 1 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) -#define BNXT_MAX_VF_REPS 64 +#define BNXT_MAX_VF_REPS_WH 64 +#define BNXT_MAX_VF_REPS_TH 256 +#define BNXT_MAX_VF_REPS(bp) \ + (BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_TH : \ + BNXT_MAX_VF_REPS_WH) #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) #define BNXT_FIRST_VF_FID 128 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) diff --git a/drivers/net/bnxt/bnxt_cpr.c b/drivers/net/bnxt/bnxt_cpr.c index 63ff02a198..6bb70d516e 100644 --- a/drivers/net/bnxt/bnxt_cpr.c +++ b/drivers/net/bnxt/bnxt_cpr.c @@ -74,7 +74,7 @@ bnxt_process_default_vnic_change(struct bnxt *bp, BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT; PMD_DRV_LOG(INFO, "async event received vf_id 0x%x\n", vf_fid); - for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) { + for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS(bp); vf_id++) { eth_dev = bp->rep_info[vf_id].vfr_eth_dev; if (!eth_dev) continue; diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 2ab0cf3784..90836401b7 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1172,7 +1172,7 @@ void bnxt_print_link_info(struct rte_eth_dev *eth_dev) struct rte_eth_link *link = ð_dev->data->dev_link; if (link->link_status) - PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", + PMD_DRV_LOG(DEBUG, "Port %d Link Up - speed %u Mbps - %s\n", eth_dev->data->port_id, (uint32_t)link->link_speed, (link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ? @@ -6025,7 +6025,7 @@ static int bnxt_init_rep_info(struct bnxt *bp) return 0; bp->rep_info = rte_zmalloc("bnxt_rep_info", - sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, + sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS(bp), 0); if (!bp->rep_info) { PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); @@ -6067,7 +6067,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, { struct rte_eth_dev *vf_rep_eth_dev; char name[RTE_ETH_NAME_MAX_LEN]; - struct bnxt *backing_bp; + struct bnxt *backing_bp = backing_eth_dev->data->dev_private; + uint16_t max_vf_reps = BNXT_MAX_VF_REPS(backing_bp); + uint16_t num_rep; int i, ret = 0; struct rte_kvargs *kvlist = NULL; @@ -6080,9 +6082,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, return -ENOTSUP; } num_rep = eth_da->nb_representor_ports; - if (num_rep > BNXT_MAX_VF_REPS) { + if (num_rep > max_vf_reps) { PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", - num_rep, BNXT_MAX_VF_REPS); + num_rep, max_vf_reps); return -EINVAL; } @@ -6093,8 +6095,6 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, return -EINVAL; } - backing_bp = backing_eth_dev->data->dev_private; - if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { PMD_DRV_LOG(ERR, "Not a PF or trusted VF. No Representor support\n"); @@ -6114,9 +6114,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, .parent_dev = backing_eth_dev }; - if (representor.vf_id >= BNXT_MAX_VF_REPS) { + if (representor.vf_id >= max_vf_reps) { PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", - representor.vf_id, BNXT_MAX_VF_REPS); + representor.vf_id, max_vf_reps); continue; } diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c index 19da24b41d..60aaa56299 100644 --- a/drivers/net/bnxt/bnxt_reps.c +++ b/drivers/net/bnxt/bnxt_reps.c @@ -210,7 +210,6 @@ int bnxt_representor_init(struct rte_eth_dev *eth_dev, void *params) eth_dev->data->dev_link.link_status = link->link_status; eth_dev->data->dev_link.link_autoneg = link->link_autoneg; - PMD_DRV_LOG(INFO, "calling bnxt_print_link_info\n"); bnxt_print_link_info(eth_dev); PMD_DRV_LOG(INFO, @@ -842,7 +841,7 @@ int bnxt_rep_stop_all(struct bnxt *bp) if (!bp->rep_info) return 0; - for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) { + for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS(bp); vf_id++) { rep_eth_dev = bp->rep_info[vf_id].vfr_eth_dev; if (!rep_eth_dev) continue; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 68f1470c61..960a5a0c93 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -262,7 +262,7 @@ bnxt_ulp_cntxt_ptr2_ulp_flags_get(struct bnxt_ulp_context *ulp_ctx, uint32_t *flags); int32_t -bnxt_ulp_get_df_rule_info(uint8_t port_id, struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_get_df_rule_info(uint16_t port_id, struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_df_rule_info *info); struct bnxt_ulp_vfr_rule_info* diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 5383e2cd70..e43e341927 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 11:11:05 2021 */ +/* date: Thu Sep 16 11:49:55 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -164,12 +164,12 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE", - .result_num_entries = 256, + .name = "EGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE", + .result_num_entries = 4096, .result_num_bytes = 6, .key_num_bytes = 17, .num_buckets = 8, - .hash_tbl_entries = 1024, + .hash_tbl_entries = 16384, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index d8336d164e..01233c0f5e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -441,7 +441,7 @@ void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global) { struct bnxt_ulp_df_rule_info *info; - uint8_t port_id; + uint16_t port_id; if (!BNXT_TRUFLOW_EN(bp) || BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev)) @@ -505,7 +505,7 @@ int32_t bnxt_ulp_create_df_rules(struct bnxt *bp) { struct bnxt_ulp_df_rule_info *info; - uint8_t port_id; + uint16_t port_id; int rc = 0; if (!BNXT_TRUFLOW_EN(bp) || @@ -562,7 +562,7 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev) struct rte_eth_dev *parent_dev = vfr->parent_dev; struct bnxt *bp = parent_dev->data->dev_private; uint16_t vfr_port_id = vfr_ethdev->data->port_id; - uint8_t port_id; + uint16_t port_id; int rc; if (!bp || !BNXT_TRUFLOW_EN(bp)) -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 12/22] net/bnxt: remove devargs for stats accumulation 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (10 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 11/22] net/bnxt: increase flow scale for Thor Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 13/22] net/bnxt: fix clang compiler warnings Ajit Khaparde ` (11 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Mike Baucom [-- Attachment #1: Type: text/plain, Size: 6867 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> The accumulation of flow counters is not determined by the application device arguments anymore. Instead it is now dictated by the platform capabilities whether to do software based accumulation or not. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/bnxt.h | 3 -- drivers/net/bnxt/bnxt_ethdev.c | 53 ---------------------------- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 8 ----- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 1 - drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 12 +++---- 5 files changed, 4 insertions(+), 73 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 54039ba1a9..04b994e5ec 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -718,11 +718,8 @@ struct bnxt { uint32_t flags2; #define BNXT_FLAGS2_PTP_TIMESYNC_ENABLED BIT(0) #define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1) -#define BNXT_FLAGS2_ACCUM_STATS_EN BIT(2) #define BNXT_P5_PTP_TIMESYNC_ENABLED(bp) \ ((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED) -#define BNXT_ACCUM_STATS_EN(bp) \ - ((bp)->flags2 & BNXT_FLAGS2_ACCUM_STATS_EN) uint16_t chip_num; #define CHIP_NUM_58818 0xd818 diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 90836401b7..4413b5d72e 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -87,7 +87,6 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { { .vendor_id = 0, /* sentinel */ }, }; -#define BNXT_DEVARG_ACCUM_STATS "accum-stats" #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" #define BNXT_DEVARG_REPRESENTOR "representor" @@ -101,7 +100,6 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { static const char *const bnxt_dev_args[] = { BNXT_DEVARG_REPRESENTOR, - BNXT_DEVARG_ACCUM_STATS, BNXT_DEVARG_FLOW_XSTAT, BNXT_DEVARG_MAX_NUM_KFLOWS, BNXT_DEVARG_REP_BASED_PF, @@ -114,12 +112,6 @@ static const char *const bnxt_dev_args[] = { NULL }; -/* - * accum-stats == false to disable flow counter accumulation - * accum-stats == true to enable flow counter accumulation - */ -#define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1) - /* * app-id = an non-negative 8-bit number */ @@ -5290,45 +5282,6 @@ static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) return 0; } -static int -bnxt_parse_devarg_accum_stats(__rte_unused const char *key, - const char *value, void *opaque_arg) -{ - struct bnxt *bp = opaque_arg; - unsigned long accum_stats; - char *end = NULL; - - if (!value || !opaque_arg) { - PMD_DRV_LOG(ERR, - "Invalid parameter passed to accum-stats devargs.\n"); - return -EINVAL; - } - - accum_stats = strtoul(value, &end, 10); - if (end == NULL || *end != '\0' || - (accum_stats == ULONG_MAX && errno == ERANGE)) { - PMD_DRV_LOG(ERR, - "Invalid parameter passed to accum-stats devargs.\n"); - return -EINVAL; - } - - if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) { - PMD_DRV_LOG(ERR, - "Invalid value passed to accum-stats devargs.\n"); - return -EINVAL; - } - - if (accum_stats) { - bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN; - PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n"); - } else { - bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN; - PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n"); - } - - return 0; -} - static int bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, const char *value, void *opaque_arg) @@ -5681,12 +5634,6 @@ bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) if (ret) goto err; - /* - * Handler for "accum-stats" devarg. - * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1" - */ - rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS, - bnxt_parse_devarg_accum_stats, bp); /* * Handler for "max_num_kflows" devarg. * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 2ac1a8625f..7deacd1f3e 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1490,14 +1490,6 @@ bnxt_ulp_port_init(struct bnxt *bp) goto jump_to_error; } - /* set the accumulation of the stats */ - if (BNXT_ACCUM_STATS_EN(bp)) - bp->ulp_ctx->cfg_data->accum_stats = true; - - BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init, accum_stats:%d\n", - bp->eth_dev->data->port_id, - bp->ulp_ctx->cfg_data->accum_stats); - /* set the unicast mode */ if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(bp->ulp_ctx, &ulp_flags)) { BNXT_TF_DBG(ERR, "Error in getting ULP context flags\n"); diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 960a5a0c93..17c6898196 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -92,7 +92,6 @@ struct bnxt_ulp_data { #define BNXT_ULP_TUN_ENTRY_INVALID -1 #define BNXT_ULP_MAX_TUN_CACHE_ENTRIES 16 struct bnxt_tun_cache_entry tun_tbl[BNXT_ULP_MAX_TUN_CACHE_ENTRIES]; - bool accum_stats; uint8_t app_id; uint8_t num_shared_clients; struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES]; diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c index d6b4f93d31..92243083b5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c @@ -396,21 +396,17 @@ static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt, return rc; } - /* TBD - Get PKT/BYTE COUNT SHIFT/MASK from Template */ + /* PKT/BYTE COUNT SHIFT/MASK are device specific */ sw_cntr_indx = hw_cntr_id - fc_info->shadow_hw_tbl[dir].start_idx; sw_acc_tbl_entry = &fc_info->sw_acc_tbl[dir][sw_cntr_indx]; + /* Some dpdk applications may accumulate the flow counters while some * may not. In cases where the application is accumulating the counters * the PMD need not do the accumulation itself and viceversa to report * the correct flow counters. */ - if (ctxt->cfg_data->accum_stats) { - sw_acc_tbl_entry->pkt_count += FLOW_CNTR_PKTS(stats, dparms); - sw_acc_tbl_entry->byte_count += FLOW_CNTR_BYTES(stats, dparms); - } else { - sw_acc_tbl_entry->pkt_count = FLOW_CNTR_PKTS(stats, dparms); - sw_acc_tbl_entry->byte_count = FLOW_CNTR_BYTES(stats, dparms); - } + sw_acc_tbl_entry->pkt_count += FLOW_CNTR_PKTS(stats, dparms); + sw_acc_tbl_entry->byte_count += FLOW_CNTR_BYTES(stats, dparms); /* Update the parent counters if it is child flow */ if (sw_acc_tbl_entry->pc_flow_idx & FLOW_CNTR_PC_FLOW_VALID) { -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 13/22] net/bnxt: fix clang compiler warnings 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (11 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 12/22] net/bnxt: remove devargs for stats accumulation Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 14/22] net/bnxt: update log messages in TruFlow path Ajit Khaparde ` (10 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Shahaji Bhosle, Venkat Duvvuru [-- Attachment #1: Type: text/plain, Size: 1933 bytes --] From: Shahaji Bhosle <sbhosle@broadcom.com> Typecast flow_item type, action_item type and the ENUMs to uint32_t before comparing. Bugzilla ID: 821 Fixes: bdf4a3c6316b ("net/bnxt: support tunnel offload") Signed-off-by: Shahaji Bhosle <sbhosle@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 605c29223c..d21c088d59 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -137,10 +137,10 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[], /* Parse all the items in the pattern */ while (item && item->type != RTE_FLOW_ITEM_TYPE_END) { - if (item->type >= (uint32_t) + if (item->type >= (typeof(item->type)) BNXT_RTE_FLOW_ITEM_TYPE_END) { if (item->type >= - (uint32_t)BNXT_RTE_FLOW_ITEM_TYPE_LAST) + (typeof(item->type))BNXT_RTE_FLOW_ITEM_TYPE_LAST) goto hdr_parser_error; /* get the header information */ hdr_info = &ulp_vendor_hdr_info[item->type - @@ -186,9 +186,9 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[], /* Parse all the items in the pattern */ while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) { if (action_item->type >= - (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_END) { + (typeof(action_item->type))BNXT_RTE_FLOW_ACTION_TYPE_END) { if (action_item->type >= - (uint32_t)BNXT_RTE_FLOW_ACTION_TYPE_LAST) + (typeof(action_item->type))BNXT_RTE_FLOW_ACTION_TYPE_LAST) goto act_parser_error; /* get the header information from bnxt actinfo table */ hdr_info = &ulp_vendor_act_info[action_item->type - -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 14/22] net/bnxt: update log messages in TruFlow path 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (12 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 13/22] net/bnxt: fix clang compiler warnings Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 15/22] net/bnxt: add support for socket direct feature Ajit Khaparde ` (9 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Shahaji Bhosle, Mike Baucom [-- Attachment #1: Type: text/plain, Size: 4081 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Some of the error level log messages are made debug level messages. When Truflow is not enabled then Truflow init error messages are moved to debug level instead. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 24 ++++++++++++------------ drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 7deacd1f3e..21f71d6445 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1396,16 +1396,16 @@ bnxt_ulp_port_init(struct bnxt *bp) uint32_t ulp_flags; int32_t rc = 0; - if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { - BNXT_TF_DBG(ERR, - "Skip ulp init for port: %d, not a TVF or PF\n", + if (!BNXT_TRUFLOW_EN(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ulp init for port: %d, TF is not enabled\n", bp->eth_dev->data->port_id); return rc; } - if (!BNXT_TRUFLOW_EN(bp)) { - BNXT_TF_DBG(ERR, - "Skip ulp init for port: %d, truflow is not enabled\n", + if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ulp init for port: %d, not a TVF or PF\n", bp->eth_dev->data->port_id); return rc; } @@ -1520,16 +1520,16 @@ bnxt_ulp_port_deinit(struct bnxt *bp) struct rte_pci_device *pci_dev; struct rte_pci_addr *pci_addr; - if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { - BNXT_TF_DBG(ERR, - "Skip ULP deinit port:%d, not a TVF or PF\n", + if (!BNXT_TRUFLOW_EN(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ULP deinit for port:%d, TF is not enabled\n", bp->eth_dev->data->port_id); return; } - if (!BNXT_TRUFLOW_EN(bp)) { - BNXT_TF_DBG(ERR, - "Skip ULP deinit for port:%d, truflow is not enabled\n", + if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { + BNXT_TF_DBG(DEBUG, + "Skip ULP deinit port:%d, not a TVF or PF\n", bp->eth_dev->data->port_id); return; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index 01233c0f5e..8790d7ac0d 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -323,7 +323,7 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev, ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); if (!ulp_ctx) { BNXT_TF_DBG(ERR, - "ULP context is not initialized. Failed to create dflt flow.\n"); + "ULP is not init'ed. Fail to create dflt flow.\n"); return -EINVAL; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c index 79dc869e64..9968311c44 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c @@ -470,7 +470,7 @@ ulp_flow_db_init(struct bnxt_ulp_context *ulp_ctxt) } /* All good so return. */ - BNXT_TF_DBG(INFO, "FlowDB initialized with %d flows.\n", + BNXT_TF_DBG(DEBUG, "FlowDB initialized with %d flows.\n", flow_tbl->num_flows); return 0; error_free: diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c index 271520e1d3..9dffaef73b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c @@ -116,7 +116,7 @@ ulp_mark_db_init(struct bnxt_ulp_context *ctxt) mark_tbl->gfid_mask = (mark_tbl->gfid_num_entries / 2) - 1; mark_tbl->gfid_type_bit = (mark_tbl->gfid_num_entries / 2); - BNXT_TF_DBG(DEBUG, "GFID Max = 0x%08x\nGFID MASK = 0x%08x\n", + BNXT_TF_DBG(DEBUG, "GFID Max = 0x%08x GFID MASK = 0x%08x\n", mark_tbl->gfid_num_entries - 1, mark_tbl->gfid_mask); -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 15/22] net/bnxt: add support for socket direct feature 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (13 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 14/22] net/bnxt: update log messages in TruFlow path Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 16/22] net/bnxt: modify VF representor alloc sequence Ajit Khaparde ` (8 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Mike Baucom, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 394315 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Added support for socket direct feature. This feature allows to ignore the incoming interface and use other fields in the packet to identify the flow and forward. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 5 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 23 +- .../generic_templates/ulp_template_db_enum.h | 71 +- .../generic_templates/ulp_template_db_tbl.c | 3917 +++++++++++++---- .../ulp_template_db_thor_act.c | 150 +- .../ulp_template_db_thor_class.c | 660 +-- .../ulp_template_db_wh_plus_act.c | 242 +- .../ulp_template_db_wh_plus_class.c | 222 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 5 + 9 files changed, 3701 insertions(+), 1594 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 21f71d6445..b64279710b 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -337,9 +337,12 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, BNXT_ULP_APP_UNICAST_ONLY; if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) { /* Enable socket direction only if MR is enabled in fw*/ - if (BNXT_MULTIROOT_EN(bp)) + if (BNXT_MULTIROOT_EN(bp)) { ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_APP_SOCKET_DIRECT; + BNXT_TF_DBG(DEBUG, + "Socket Direct feature is enabled"); + } } } if (!found) { diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 272195f6a2..55885d1b8c 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -133,8 +133,27 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, } /* Update the socket direct flag */ - if (ULP_SOCKET_DIRECT_IS_ENABLED(ulp_flags)) - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT, 1); + if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_SVIF_IGNORE)) { + uint32_t ifindex; + uint16_t vport; + + /* Get the port db ifindex */ + if (ulp_port_db_dev_port_to_ulp_index(params->ulp_ctx, + params->port_id, + &ifindex)) { + BNXT_TF_DBG(ERR, "Invalid port id %u\n", + params->port_id); + return; + } + /* Update the phy port of the other interface */ + if (ulp_port_db_vport_get(params->ulp_ctx, ifindex, &vport)) { + BNXT_TF_DBG(ERR, "Invalid port if index %u\n", ifindex); + return; + } + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT_VPORT, + (vport == 1) ? 2 : 1); + } } /* Function to create the rte flow. */ diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index 8706e45f28..c01ae1601d 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,15 +3,15 @@ * All rights reserved. */ -/* date: Thu Sep 9 12:11:08 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ -#define BNXT_ULP_REGFILE_MAX_SZ 42 +#define BNXT_ULP_REGFILE_MAX_SZ 46 #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 -#define BNXT_ULP_GEN_TBL_MAX_SZ 16 +#define BNXT_ULP_GEN_TBL_MAX_SZ 18 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 65536 #define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 993 #define BNXT_ULP_CLASS_HID_LOW_PRIME 6701 @@ -26,11 +26,11 @@ #define BNXT_ULP_ACT_HID_SHFTR 27 #define BNXT_ULP_ACT_HID_SHFTL 26 #define BNXT_ULP_ACT_HID_MASK 2047 -#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8 -#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110 -#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50 -#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 277 -#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8 +#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 16 +#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 132 +#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 140 +#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 409 +#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 12 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 @@ -114,7 +114,8 @@ enum bnxt_ulp_hdr_bit { BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000, BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000, BNXT_ULP_HDR_BIT_F2 = 0x0000000000080000, - BNXT_ULP_HDR_BIT_LAST = 0x0000000000100000 + BNXT_ULP_HDR_BIT_SVIF_IGNORE = 0x0000000000100000, + BNXT_ULP_HDR_BIT_LAST = 0x0000000000200000 }; enum bnxt_ulp_accept_opc { @@ -212,7 +213,8 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72, BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73, BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74, - BNXT_ULP_CF_IDX_LAST = 75 + BNXT_ULP_CF_IDX_SOCKET_DIRECT_VPORT = 75, + BNXT_ULP_CF_IDX_LAST = 76 }; enum bnxt_ulp_cond_list_opc { @@ -427,21 +429,31 @@ enum bnxt_ulp_glb_rf_idx { BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 37, BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 38, BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 39, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 40, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 41, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 42, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 43, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 44, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 45, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 46, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 47, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 48, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 49, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 50, - BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 51, - BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 52, - BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 53, - BNXT_ULP_GLB_RF_IDX_LAST = 54 + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3 = 40, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 41, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 42, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 43, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 44, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 45, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 46, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 47, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3 = 48, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4 = 49, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5 = 50, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6 = 51, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7 = 52, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8 = 53, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9 = 54, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10 = 55, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 56, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 57, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 58, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 59, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2 = 60, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 61, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 62, + BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 63, + BNXT_ULP_GLB_RF_IDX_LAST = 64 }; enum bnxt_ulp_hdr_type { @@ -555,7 +567,11 @@ enum bnxt_ulp_rf_idx { BNXT_ULP_RF_IDX_PHY_PORT = 39, BNXT_ULP_RF_IDX_METADATA_PROF = 40, BNXT_ULP_RF_IDX_MODIFY_PTR = 41, - BNXT_ULP_RF_IDX_LAST = 42 + BNXT_ULP_RF_IDX_SOCK_DIR_SVIF = 42, + BNXT_ULP_RF_IDX_SOCK_DIR_PARIF = 43, + BNXT_ULP_RF_IDX_SOCK_DIR_ACT_PTR = 44, + BNXT_ULP_RF_IDX_SOCK_DIR_PARENT_MAC = 45, + BNXT_ULP_RF_IDX_LAST = 46 }; enum bnxt_ulp_shared_session { @@ -627,7 +643,8 @@ enum bnxt_ulp_resource_sub_type { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE = 6, - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7 + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE = 8 }; enum bnxt_ulp_act_prop_sz { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index e43e341927..d5aea4d456 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 16 11:49:55 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -171,6 +171,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { .num_buckets = 8, .hash_tbl_entries = 16384, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GEN_TABLE_SOCKET_DIRECT_CACHE", + .result_num_entries = 16, + .result_num_bytes = 14, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GEN_TABLE_SOCKET_DIRECT_CACHE", + .result_num_entries = 16, + .result_num_bytes = 14, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; @@ -371,6 +391,33 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY | + BNXT_ULP_APP_CAP_SOCKET_DIRECT + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .flags = BNXT_ULP_APP_CAP_SHARED_EN | + BNXT_ULP_APP_CAP_UNICAST_ONLY } }; @@ -439,6 +486,70 @@ struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .count = 1024 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 128 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 1024 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 128 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 2 + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 1024 } }; @@ -472,6 +583,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -560,6 +679,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -624,14 +751,6 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, - .direction = TF_DIR_RX - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX @@ -672,6 +791,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -760,6 +887,14 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX @@ -824,14 +959,6 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, - .direction = TF_DIR_RX - }, - { - .app_id = 2, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX @@ -843,509 +970,717 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = { .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, .direction = TF_DIR_RX - } -}; - -/* List of global tf resources required to be reserved per app/device */ -struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { + }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, .direction = TF_DIR_RX }, { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX + }, + { + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_METADATA, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0, - .direction = TF_DIR_TX + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX }, { - .app_id = 0, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX - }, - { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, .direction = TF_DIR_RX }, { - .app_id = 1, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX }, { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, .direction = TF_DIR_RX }, { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 1, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, + .direction = TF_DIR_RX + }, + { + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, - .direction = TF_DIR_TX + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0, .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1, + .direction = TF_DIR_RX }, { - .app_id = 2, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0, + .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1, + .direction = TF_DIR_RX + } +}; + +/* List of global tf resources required to be reserved per app/device */ +struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { + { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1353,7 +1688,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1361,7 +1696,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, @@ -1369,7 +1704,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1377,7 +1712,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1385,7 +1720,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1393,7 +1728,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1401,7 +1736,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1409,7 +1744,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, @@ -1417,7 +1752,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1425,7 +1760,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1433,7 +1768,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1441,7 +1776,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, @@ -1449,7 +1784,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1457,7 +1792,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1465,7 +1800,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1473,7 +1808,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, @@ -1481,7 +1816,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1489,7 +1824,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, @@ -1497,7 +1832,15 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1505,7 +1848,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1513,7 +1856,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1521,7 +1864,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1529,7 +1872,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1537,7 +1880,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1545,23 +1888,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6, - .direction = TF_DIR_RX - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_WC_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7, - .direction = TF_DIR_RX - }, - { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1569,7 +1896,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1577,7 +1904,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1585,7 +1912,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1593,7 +1920,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1601,7 +1928,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1609,7 +1936,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, @@ -1617,7 +1944,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1625,7 +1952,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, @@ -1633,427 +1960,2171 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .direction = TF_DIR_TX }, { - .app_id = 3, + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .direction = TF_DIR_TX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_METADATA, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0, + .direction = TF_DIR_TX + }, + { + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_EM_PROF, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, .direction = TF_DIR_RX }, { .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, .direction = TF_DIR_RX }, { - .app_id = 3, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1, + .direction = TF_DIR_TX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2, + .direction = TF_DIR_RX + }, + { + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 4, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + { + .app_id = 5, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX + } +}; + +/* List of tf resources required to be reserved per app/device */ +struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 422 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 191 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 6912 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 1023 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 511 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 15 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, + .count = 255 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 422 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 960 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 88 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 13168 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 292 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 148 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 191 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 6912 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 1023 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 511 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 223 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 255 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 488 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, + .count = 511 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 292 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 144 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 960 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 928 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 15232 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 5 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 31 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 2048 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 64 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 6 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 128 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4096 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 16384 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 63 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 8192 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 5 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 32 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 2048 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 100 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 272 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 128 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4096 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 16384 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_METADATA, + .count = 1 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 128 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 16 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 528 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 256 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, + .count = 2 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_WC_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_EM_PROF, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .count = 512 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .count = 256 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .count = 4 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 1, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .count = 2 + }, + { + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1, - .direction = TF_DIR_RX + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .count = 32 }, { - .app_id = 3, + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2, - .direction = TF_DIR_RX + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + .count = 4 }, { - .app_id = 3, + .app_id = 1, .device_id = BNXT_ULP_DEVICE_ID_THOR, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3, - .direction = TF_DIR_RX - } -}; - -/* List of tf resources required to be reserved per app/device */ -struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_EM_RECORD, + .count = 1024 + }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 6912 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 511 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 15 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, - .count = 255 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 88 + .count = 64 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 13168 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 148 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 6912 + .count = 128 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 511 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 223 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 255 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 488 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .count = 511 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 144 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 928 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 15232 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 272 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2061,15 +4132,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 32 + .count = 16 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2077,759 +4148,815 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 528 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 8192 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 5 + .count = 256 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 31 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 2048 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 64 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 272 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4096 + .count = 512 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 16384 + .count = 1024 }, { - .app_id = 0, + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .count = 32 + }, + { + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 272 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 512 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 8192 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 5 + .count = 256 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 2048 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 100 + .count = 4 }, { - .app_id = 0, + .app_id = 2, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .count = 32 + }, + { + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 272 + .count = 2 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4096 + .count = 4 }, { - .app_id = 0, + .app_id = 2, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 16384 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_METADATA, - .count = 1 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 422 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 4 + .count = 191 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 4 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 4 + .count = 192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 128 + .count = 8192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 128 + .count = 7168 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 4 + .count = 1023 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 4 + .count = 511 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 4 + .count = 15 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, - .count = 4 + .count = 255 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 422 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 960 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 88 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 13168 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 292 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 148 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 4 + .count = 191 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 4 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 4 + .count = 192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 128 + .count = 8192 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 128 + .count = 7168 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 4 + .count = 1023 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 4 + .count = 511 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 4 + .count = 223 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 4 + .count = 255 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 4 + .count = 488 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .count = 4 + .count = 511 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 292 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 144 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 960 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 928 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 15232 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 16 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 528 + .count = 4096 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 256 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_RX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, + .count = 1024 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 2048 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 6144 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 4 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 4 + .count = 63 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 4 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 512 + .count = 4096 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 256 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .count = 1 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 4 + .count = 32 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 4 + .count = 1024 }, { - .app_id = 1, + .app_id = 3, + .device_id = BNXT_ULP_DEVICE_ID_THOR, + .direction = TF_DIR_TX, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, + .count = 1024 + }, + { + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 2 + .count = 6 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 32 + .count = 128 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 4 + .count = 2048 }, { - .app_id = 1, + .app_id = 3, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 1024 + .count = 6144 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2837,7 +4964,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2845,7 +4972,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2853,7 +4980,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2861,7 +4988,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2869,7 +4996,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2877,7 +5004,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2885,7 +5012,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2893,7 +5020,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2901,7 +5028,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2909,7 +5036,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -2917,7 +5044,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -2925,7 +5052,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -2933,7 +5060,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -2941,15 +5068,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 64 + .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -2957,7 +5084,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2965,7 +5092,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2973,7 +5100,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2981,7 +5108,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2989,7 +5116,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -2997,7 +5124,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3005,7 +5132,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3013,7 +5140,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 128 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3021,7 +5148,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3029,7 +5156,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3037,7 +5164,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3045,7 +5172,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3053,7 +5180,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3061,7 +5188,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3069,7 +5196,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3077,7 +5204,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3085,7 +5212,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3093,7 +5220,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -3101,7 +5228,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3109,7 +5236,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3117,7 +5244,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3125,7 +5252,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3133,7 +5260,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 16 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3141,7 +5268,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3149,7 +5276,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 528 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3157,7 +5284,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 256 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3165,7 +5292,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3173,7 +5300,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3181,7 +5308,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3189,7 +5316,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3197,7 +5324,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3205,7 +5332,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3213,15 +5340,15 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 512 + .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -3229,7 +5356,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3237,7 +5364,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3245,7 +5372,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3253,7 +5380,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3261,7 +5388,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -3269,7 +5396,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3277,7 +5404,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 512 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3285,7 +5412,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 256 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3293,7 +5420,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3301,7 +5428,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3309,7 +5436,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -3317,7 +5444,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3325,7 +5452,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3333,7 +5460,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 2 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3341,7 +5468,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 32 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, @@ -3349,7 +5476,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 4 }, { - .app_id = 2, + .app_id = 4, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, @@ -3357,596 +5484,532 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 7168 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 511 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 15 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC, - .count = 255 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 422 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 88 + .count = 64 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 13168 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 148 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 191 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 192 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 8192 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 7168 + .count = 128 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, - .count = 1023 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 511 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .count = 223 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, - .count = 255 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 488 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6, - .count = 511 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 292 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 144 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 960 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 928 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 15232 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE, - .count = 1 + .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 16 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 4096 + .count = 528 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 256 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_RX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 2048 + .count = 512 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 6144 + .count = 1024 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_WC_PROF, - .count = 128 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .count = 63 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .resource_type = TF_IDENT_TYPE_EM_PROF, - .count = 128 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .count = 4096 + .count = 512 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, - .count = 1 + .count = 256 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, - .count = 32 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .count = 1024 - }, - { - .app_id = 3, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, - .count = 1024 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .count = 6 + .count = 2 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .count = 128 + .count = 32 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .count = 2048 + .count = 4 }, { - .app_id = 3, + .app_id = 5, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_EM_TBL_TYPE_EM_RECORD, - .count = 6144 + .count = 1024 } }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c index e49c1151d3..8869ab1c33 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Aug 17 12:16:42 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -1575,8 +1575,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}, + (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1607,7 +1607,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, + ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_DECAP_FUNC_NONE} @@ -1666,8 +1666,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1692,7 +1692,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, + ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1747,7 +1747,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, + ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_DECAP_FUNC_NONE} @@ -1806,8 +1806,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1832,7 +1832,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, + ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2149,7 +2149,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2168,7 +2168,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2187,7 +2187,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2206,7 +2206,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2373,8 +2373,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2393,8 +2393,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2413,8 +2413,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2433,8 +2433,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 3, , table: mod_record.ing_no_ttl */ @@ -2526,7 +2526,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2545,7 +2545,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2564,7 +2564,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2583,7 +2583,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2737,8 +2737,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2757,8 +2757,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2777,8 +2777,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -2797,8 +2797,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 3, , table: int_full_act_record.0 */ @@ -3593,7 +3593,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3612,7 +3612,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3631,7 +3631,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3650,7 +3650,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3817,8 +3817,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -3837,8 +3837,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -3857,8 +3857,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -3877,8 +3877,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 5, , table: mod_record.ing_no_ttl */ @@ -3970,7 +3970,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3989,7 +3989,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4008,7 +4008,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4027,7 +4027,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1}, + 1}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4181,8 +4181,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4201,8 +4201,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4221,8 +4221,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4241,8 +4241,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 5, , table: int_full_act_record.0 */ @@ -4526,8 +4526,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4546,8 +4546,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4566,8 +4566,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4586,8 +4586,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4833,8 +4833,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4853,8 +4853,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4873,8 +4873,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4893,8 +4893,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 54bc032b0c..2d464fb7c4 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 12:11:08 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -3232,8 +3232,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -3302,7 +3302,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -3492,7 +3492,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -3871,8 +3871,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -3987,8 +3987,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -4821,8 +4821,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -4835,8 +4835,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -4959,8 +4959,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -4973,8 +4973,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5037,8 +5037,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -5051,8 +5051,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5091,8 +5091,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -5105,8 +5105,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5153,8 +5153,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5358,8 +5358,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5383,8 +5383,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -5542,8 +5542,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -5612,7 +5612,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -5659,7 +5659,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_VALID_YES}, + ULP_THOR_SYM_L4_HDR_VALID_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_VALID_IGNORE} @@ -5749,7 +5749,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L3_HDR_TYPE_IPV6} @@ -5830,7 +5830,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -6209,8 +6209,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -6734,7 +6734,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L3_HDR_TYPE_IPV6} @@ -6815,7 +6815,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_TL2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_TL2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_TL2_VTAG_PRESENT_NO} @@ -6900,8 +6900,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -7018,8 +7018,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -7852,8 +7852,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -7866,8 +7866,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7990,8 +7990,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8004,8 +8004,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8056,8 +8056,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8070,8 +8070,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8110,8 +8110,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8124,8 +8124,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8187,8 +8187,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8383,8 +8383,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8397,8 +8397,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8413,8 +8413,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8427,8 +8427,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9359,8 +9359,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9373,8 +9373,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9497,8 +9497,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9511,8 +9511,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9575,8 +9575,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9589,8 +9589,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9629,8 +9629,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -9643,8 +9643,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9694,8 +9694,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9901,8 +9901,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9928,8 +9928,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10860,8 +10860,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -10874,8 +10874,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10998,8 +10998,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -11012,8 +11012,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -11064,8 +11064,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -11078,8 +11078,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -11118,8 +11118,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -11132,8 +11132,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -11195,8 +11195,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12335,8 +12335,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12349,8 +12349,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12473,8 +12473,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12487,8 +12487,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12551,8 +12551,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12565,8 +12565,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12605,8 +12605,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -12619,8 +12619,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12670,8 +12670,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -13810,8 +13810,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -13824,8 +13824,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -13948,8 +13948,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -13962,8 +13962,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14712,8 +14712,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -14726,8 +14726,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14778,8 +14778,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -14792,8 +14792,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14832,8 +14832,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -14846,8 +14846,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -14909,8 +14909,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -15093,8 +15093,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -15107,8 +15107,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -15123,8 +15123,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -15137,8 +15137,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -15345,8 +15345,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -15359,8 +15359,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16219,8 +16219,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16233,8 +16233,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16297,8 +16297,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16311,8 +16311,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16351,8 +16351,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16365,8 +16365,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16416,8 +16416,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16600,8 +16600,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16614,8 +16614,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16630,8 +16630,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16644,8 +16644,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -16852,8 +16852,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -16866,8 +16866,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -18434,7 +18434,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_I_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -19848,8 +19848,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -19862,8 +19862,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -19970,8 +19970,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -19984,8 +19984,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20168,8 +20168,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -20182,8 +20182,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20222,8 +20222,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -20236,8 +20236,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20284,8 +20284,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20489,8 +20489,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -20514,8 +20514,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -22120,8 +22120,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22134,8 +22134,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22242,8 +22242,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22256,8 +22256,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22428,8 +22428,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22442,8 +22442,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22482,8 +22482,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22496,8 +22496,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22559,8 +22559,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22755,8 +22755,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22769,8 +22769,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -22785,8 +22785,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -22799,8 +22799,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -23041,7 +23041,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -23231,7 +23231,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -24532,8 +24532,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24546,8 +24546,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24562,8 +24562,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24576,8 +24576,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24700,8 +24700,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24714,8 +24714,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24778,8 +24778,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24792,8 +24792,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24832,8 +24832,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, .field_info_spec = { @@ -24846,8 +24846,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -24894,8 +24894,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -25099,8 +25099,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -25124,8 +25124,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }, @@ -25345,7 +25345,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, + ULP_THOR_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L4_HDR_TYPE_UDP} @@ -25469,7 +25469,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, + ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L3_HDR_TYPE_IPV6} @@ -25548,7 +25548,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -26210,7 +26210,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, + ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_THOR_SYM_L2_VTAG_PRESENT_NO} @@ -27511,8 +27511,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -27525,8 +27525,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -27541,8 +27541,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -27555,8 +27555,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -27679,8 +27679,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -27693,8 +27693,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -27856,8 +27856,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -28052,8 +28052,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -28066,8 +28066,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -28082,8 +28082,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -28096,8 +28096,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29016,8 +29016,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -29030,8 +29030,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29046,8 +29046,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -29060,8 +29060,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29184,8 +29184,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -29198,8 +29198,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -29361,8 +29361,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -30489,8 +30489,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -30503,8 +30503,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -30519,8 +30519,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -30533,8 +30533,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -30657,8 +30657,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -30671,8 +30671,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -34679,8 +34679,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -35206,8 +35206,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -36920,8 +36920,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}, + (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, @@ -36991,8 +36991,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff}, + (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff, @@ -38986,8 +38986,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}, + (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff, @@ -39570,8 +39570,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c index 4a2d201c2d..16a921e6c8 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Aug 25 14:37:06 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -1210,8 +1210,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1239,8 +1239,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1295,7 +1295,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_NONE} @@ -1346,8 +1346,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_RF, .field_opr2 = { - (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1481,8 +1481,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1510,8 +1510,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -1566,7 +1566,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, + ULP_WP_SYM_DECAP_FUNC_THRU_TUN}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_NONE} @@ -1893,7 +1893,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1} + 1} }, { .description = "drop", @@ -2088,7 +2088,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - 1} + 1} }, { .description = "drop", @@ -2222,8 +2222,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_SRC2_POST, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - (1 >> 8) & 0xff, - 1 & 0xff} + (1 >> 8) & 0xff, + 1 & 0xff} }, /* act_tid: 3, , table: int_flow_counter_tbl.0 */ { @@ -2418,8 +2418,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2447,8 +2447,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2503,7 +2503,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -2662,8 +2662,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2691,8 +2691,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -2747,7 +2747,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -3853,8 +3853,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3882,8 +3882,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -3938,7 +3938,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -4097,8 +4097,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4126,8 +4126,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { @@ -4182,7 +4182,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, + ULP_WP_SYM_DECAP_FUNC_THRU_TL2}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_DECAP_FUNC_THRU_L2} @@ -4415,8 +4415,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4435,8 +4435,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4455,8 +4455,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4475,8 +4475,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4495,8 +4495,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4515,8 +4515,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4535,8 +4535,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4555,8 +4555,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4575,8 +4575,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4595,8 +4595,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4615,8 +4615,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4635,8 +4635,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4672,8 +4672,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4692,8 +4692,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4712,8 +4712,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4732,8 +4732,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4752,8 +4752,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4772,8 +4772,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4792,8 +4792,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4812,8 +4812,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -4832,8 +4832,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 6, , table: int_full_act_record.0 */ @@ -5264,8 +5264,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5284,8 +5284,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5304,8 +5304,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5324,8 +5324,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5344,8 +5344,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5364,8 +5364,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5384,8 +5384,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5404,8 +5404,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5424,8 +5424,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5444,8 +5444,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5464,8 +5464,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5484,8 +5484,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5521,8 +5521,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5541,8 +5541,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5561,8 +5561,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5581,8 +5581,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5601,8 +5601,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_UDP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5621,8 +5621,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5641,8 +5641,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5661,8 +5661,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { @@ -5681,8 +5681,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr2 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP } }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c index 4b9cb7fd5b..d1c3ebe065 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Aug 11 16:00:16 2021 */ +/* date: Fri Oct 8 11:41:10 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -2198,8 +2198,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -2218,8 +2218,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2261,8 +2261,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -2281,8 +2281,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2550,8 +2550,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -2570,8 +2570,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -2631,8 +2631,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -2701,7 +2701,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -3258,8 +3258,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -3383,7 +3383,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -3942,8 +3942,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -4702,8 +4702,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -4778,8 +4778,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4803,8 +4803,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4827,8 +4827,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -4980,8 +4980,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5005,8 +5005,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5029,8 +5029,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5182,8 +5182,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5207,8 +5207,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5231,8 +5231,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5398,8 +5398,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5423,8 +5423,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -5447,8 +5447,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -6746,7 +6746,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L3_HDR_TYPE_IPV4}, + ULP_WP_SYM_L3_HDR_TYPE_IPV4}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L3_HDR_TYPE_IPV6} @@ -7714,8 +7714,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -7734,8 +7734,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -7777,8 +7777,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -7797,8 +7797,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8066,8 +8066,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { @@ -8086,8 +8086,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_HF, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -8147,8 +8147,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -8217,7 +8217,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -8774,8 +8774,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -8899,7 +8899,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, + ULP_WP_SYM_L4_HDR_TYPE_TCP}, .field_src3 = BNXT_ULP_FIELD_SRC_CONST, .field_opr3 = { ULP_WP_SYM_L4_HDR_TYPE_UDP} @@ -9458,8 +9458,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -9576,8 +9576,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr3 = { (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, @@ -9652,8 +9652,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9677,8 +9677,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9701,8 +9701,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9854,8 +9854,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9879,8 +9879,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -9903,8 +9903,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10056,8 +10056,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10081,8 +10081,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10105,8 +10105,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10272,8 +10272,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10297,8 +10297,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -10321,8 +10321,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, @@ -12392,8 +12392,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -12409,8 +12409,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, @@ -12544,8 +12544,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -12561,8 +12561,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, @@ -13715,7 +13715,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { - ULP_WP_SYM_LOOPBACK_PARIF}, + ULP_WP_SYM_LOOPBACK_PARIF}, .field_src3 = BNXT_ULP_FIELD_SRC_CF, .field_opr3 = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, @@ -13887,8 +13887,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -13904,8 +13904,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, @@ -14039,8 +14039,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, @@ -14056,8 +14056,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_CF_IDX_O_L4 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr3 = { (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index d21c088d59..2ec3279239 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -685,6 +685,11 @@ ulp_rte_phy_port_hdr_handler(const struct rte_flow_item *item, hdr_field->size = sizeof(svif); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SVIF_FLAG, rte_be_to_cpu_16(svif)); + if (!mask) { + ULP_BITMAP_SET(params->hdr_bitmap.bits, + BNXT_ULP_HDR_BIT_SVIF_IGNORE); + memset(hdr_field->mask, 0xFF, sizeof(mask)); + } return BNXT_TF_RC_SUCCESS; } -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 16/22] net/bnxt: modify VF representor alloc sequence 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (14 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 15/22] net/bnxt: add support for socket direct feature Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 17/22] net/bnxt: add new TruFlow API to get SRAM resources Ajit Khaparde ` (7 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Venkat Duvvuru, Shahaji Bhosle [-- Attachment #1: Type: text/plain, Size: 3599 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> When the VF representor interface is created, the VF pair relationship is established between the VF and it is representor. If the pair already exists then the pair needs to be deleted before allocation. This could happen if the application is abruptly killed and restarted. If the deletion of an existing VF rep is not done then hw pipeline is not cleaned and a new allocation shall leave the hw in inconsistent state. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/bnxt_hwrm.c | 28 ++++++++++++++++++++++++++++ drivers/net/bnxt/bnxt_hwrm.h | 1 + drivers/net/bnxt/bnxt_reps.c | 6 ++++++ 3 files changed, 35 insertions(+) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 94a7daf632..67ed807dad 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -5994,6 +5994,34 @@ int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid, return rc; } +int bnxt_hwrm_cfa_pair_exists(struct bnxt *bp, struct bnxt_representor *rep_bp) +{ + struct hwrm_cfa_pair_info_output *resp = bp->hwrm_cmd_resp_addr; + struct hwrm_cfa_pair_info_input req = {0}; + int rc = 0; + + if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) { + PMD_DRV_LOG(DEBUG, + "Not a PF or trusted VF. Command not supported\n"); + return 0; + } + + HWRM_PREP(&req, HWRM_CFA_PAIR_INFO, BNXT_USE_CHIMP_MB); + snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d", + bp->eth_dev->data->name, rep_bp->vf_id); + req.flags = + rte_cpu_to_le_32(HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE); + + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); + HWRM_CHECK_RESULT(); + if (rc == HWRM_ERR_CODE_SUCCESS && strlen(resp->pair_name)) { + HWRM_UNLOCK(); + return !rc; + } + HWRM_UNLOCK(); + return rc; +} + int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp) { struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr; diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h index 72d486468c..f8f0556201 100644 --- a/drivers/net/bnxt/bnxt_hwrm.h +++ b/drivers/net/bnxt/bnxt_hwrm.h @@ -293,6 +293,7 @@ int bnxt_clear_one_vnic_filter(struct bnxt *bp, void bnxt_free_vf_info(struct bnxt *bp); int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid, uint16_t *first_vf_id); +int bnxt_hwrm_cfa_pair_exists(struct bnxt *bp, struct bnxt_representor *rep_bp); int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep); int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep); int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp); diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c index 60aaa56299..22b76b72b9 100644 --- a/drivers/net/bnxt/bnxt_reps.c +++ b/drivers/net/bnxt/bnxt_reps.c @@ -315,6 +315,12 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev) BNXT_TF_DBG(ERR, "Invalid arguments\n"); return 0; } + /* update the port id so you can backtrack to ethdev */ + vfr->dpdk_port_id = vfr_ethdev->data->port_id; + + /* If pair is present, then delete the pair */ + if (bnxt_hwrm_cfa_pair_exists(parent_bp, vfr)) + (void)bnxt_hwrm_cfa_pair_free(parent_bp, vfr); /* Update the ULP portdata base with the new VFR interface */ rc = ulp_port_db_dev_port_intf_update(parent_bp->ulp_ctx, vfr_ethdev); -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 17/22] net/bnxt: add new TruFlow API to get SRAM resources 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (15 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 16/22] net/bnxt: modify VF representor alloc sequence Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 18/22] net/bnxt: add TruFlow and AFM SRAM partitioning support Ajit Khaparde ` (6 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru, Farah Smith, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 12976 bytes --] From: Jay Ding <jay.ding@broadcom.com> Implement tf_get_sram_resources to return SRAM partition information, including bank count and SRAM profile number. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_core/tf_core.c | 86 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_core.h | 63 +++++++++++++++++ drivers/net/bnxt/tf_core/tf_device.h | 20 ++++++ drivers/net/bnxt/tf_core/tf_device_p4.c | 6 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 53 ++++++++++++++- drivers/net/bnxt/tf_core/tf_msg.c | 28 ++------ drivers/net/bnxt/tf_core/tf_msg.h | 6 +- drivers/net/bnxt/tf_core/tf_rm.c | 3 +- drivers/net/bnxt/tf_core/tf_sram_mgr.h | 10 --- 9 files changed, 237 insertions(+), 38 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 86dfec0eb4..346d220c87 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1831,3 +1831,89 @@ int tf_get_version(struct tf *tfp, return 0; } + +int tf_query_sram_resources(struct tf *tfp, + struct tf_query_sram_resources_parms *parms) +{ + int rc; + struct tf_dev_info dev; + uint16_t max_types; + struct tfp_calloc_parms cparms; + struct tf_rm_resc_req_entry *query; + enum tf_rm_resc_resv_strategy resv_strategy; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_THOR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + if (dev.ops->tf_dev_get_max_types == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return -EOPNOTSUPP; + } + + /* Need device max number of elements for the RM QCAPS */ + rc = dev.ops->tf_dev_get_max_types(tfp, &max_types); + if (rc) { + TFP_DRV_LOG(ERR, + "Get SRAM resc info failed, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Allocate memory for RM QCAPS request */ + cparms.nitems = max_types; + cparms.size = sizeof(struct tf_rm_resc_req_entry); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) + return rc; + + query = (struct tf_rm_resc_req_entry *)cparms.mem_va; + tfp->bp = parms->bp; + + /* Get Firmware Capabilities */ + rc = tf_msg_session_resc_qcaps(tfp, + &dev, + parms->dir, + max_types, + query, + &resv_strategy, + &parms->sram_profile); + if (rc) + return rc; + + if (dev.ops->tf_dev_get_sram_resources == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return -EOPNOTSUPP; + } + + rc = dev.ops->tf_dev_get_sram_resources((void *)query, + parms->bank_resc_count, + &parms->dynamic_sram_capable); + if (rc) { + TFP_DRV_LOG(ERR, + "Get SRAM resc info failed, rc:%s\n", + strerror(-rc)); + return rc; + } + + return 0; +} diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index ba9881c69d..078fd278a1 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -75,6 +75,17 @@ enum tf_wc_num_slice { TF_WC_TCAM_8_SLICE_PER_ROW = 8, }; +/** + * Bank identifier + */ +enum tf_sram_bank_id { + TF_SRAM_BANK_ID_0, /**< SRAM Bank 0 id */ + TF_SRAM_BANK_ID_1, /**< SRAM Bank 1 id */ + TF_SRAM_BANK_ID_2, /**< SRAM Bank 2 id */ + TF_SRAM_BANK_ID_3, /**< SRAM Bank 3 id */ + TF_SRAM_BANK_ID_MAX /**< SRAM Bank index limit */ +}; + /** * EEM record AR helper * @@ -2438,4 +2449,56 @@ struct tf_get_version_parms { */ int tf_get_version(struct tf *tfp, struct tf_get_version_parms *parms); + +/** + * tf_query_sram_resources parameter definition + */ +struct tf_query_sram_resources_parms { + /** + * [in] device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] bp + * The pointer to the parent bp struct. This is only used for HWRM + * message passing within the portability layer. The type is struct + * bnxt. + */ + void *bp; + + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + + /** + * [out] Bank resource count in 8 bytes entry + */ + + uint32_t bank_resc_count[TF_SRAM_BANK_ID_MAX]; + + /** + * [out] Dynamic SRAM Enable + */ + bool dynamic_sram_capable; + + /** + * [out] SRAM profile + */ + uint8_t sram_profile; +}; + +/** + * Get SRAM resources information + * + * Used to retrieve sram bank partition information + * + * Returns success or failure code. + */ +int tf_query_sram_resources(struct tf *tfp, + struct tf_query_sram_resources_parms *parms); + #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 88bd4515ff..9360eb1358 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1081,6 +1081,26 @@ struct tf_dev_ops { uint32_t *tcam_caps, uint32_t *tbl_caps, uint32_t *em_caps); + + /** + * Device specific function that retrieve the sram resource + * + * [in] query + * Point to resources query result + * + * [out] sram_bank_caps + * Pointer to SRAM bank capabilities + * + * [out] dynamic_sram_capable + * Pointer to dynamic sram capable + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_sram_resources)(void *query, + uint32_t *sram_bank_caps, + bool *dynamic_sram_capable); }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 8089785b82..cf0e919f9f 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -382,7 +382,8 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = NULL, - .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, + .tf_dev_get_sram_resources = NULL }; /** @@ -445,5 +446,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = tf_dev_p4_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, - .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, + .tf_dev_get_sram_resources = NULL }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 03e72b90f5..4687fa65dd 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -397,6 +397,53 @@ static int tf_dev_p58_map_hcapi_caps(uint64_t hcapi_caps, return 0; } +/** + * Device specific function that retrieve the sram resource + * + * [in] query + * Point to resources query result + * + * [out] sram_bank_caps + * Pointer to SRAM bank capabilities + * + * [out] dynamic_sram_capable + * Pointer to dynamic sram capable + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_get_sram_resources(void *q, + uint32_t *sram_bank_caps, + bool *dynamic_sram_capable) +{ + uint32_t i; + struct tf_rm_resc_req_entry *query = q; + + for (i = 0; i < CFA_RESOURCE_TYPE_P58_LAST + 1; i++) { + switch (query[i].type) { + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_0: + sram_bank_caps[0] = query[i].max; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_1: + sram_bank_caps[1] = query[i].max; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_2: + sram_bank_caps[2] = query[i].max; + break; + case CFA_RESOURCE_TYPE_P58_SRAM_BANK_3: + sram_bank_caps[3] = query[i].max; + break; + default: + break; + } + } + + *dynamic_sram_capable = false; + + return 0; +} + /** * Truflow P58 device specific functions */ @@ -447,7 +494,8 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = NULL, - .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources }; /** @@ -511,5 +559,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = tf_dev_p58_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, - .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources }; diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 25bf026658..fbc96d374c 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -380,39 +380,20 @@ tf_msg_session_resc_qcaps(struct tf *tfp, enum tf_dir dir, uint16_t size, struct tf_rm_resc_req_entry *query, - enum tf_rm_resc_resv_strategy *resv_strategy) + enum tf_rm_resc_resv_strategy *resv_strategy, + uint8_t *sram_profile) { int rc; int i; struct tfp_send_msg_parms parms = { 0 }; struct hwrm_tf_session_resc_qcaps_input req = { 0 }; struct hwrm_tf_session_resc_qcaps_output resp = { 0 }; - uint8_t fw_session_id; struct tf_msg_dma_buf qcaps_buf = { 0 }; struct tf_rm_resc_req_entry *data; int dma_size; - struct tf_session *tfs; - - /* Retrieve the session information */ - rc = tf_session_get_session_internal(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "Failed to lookup session, rc:%s\n", - strerror(-rc)); - return rc; - } TF_CHECK_PARMS3(tfp, query, resv_strategy); - rc = tf_session_get_fw_session_id(tfp, &fw_session_id); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Unable to lookup FW id, rc:%s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - /* Prepare DMA buffer */ dma_size = size * sizeof(struct tf_rm_resc_req_entry); rc = tf_msg_alloc_dma_buf(&qcaps_buf, dma_size); @@ -420,7 +401,7 @@ tf_msg_session_resc_qcaps(struct tf *tfp, return rc; /* Populate the request */ - req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); + req.fw_session_id = 0; req.flags = tfp_cpu_to_le_16(dir); req.qcaps_size = size; req.qcaps_addr = tfp_cpu_to_le_64(qcaps_buf.pa_addr); @@ -460,6 +441,9 @@ tf_msg_session_resc_qcaps(struct tf *tfp, *resv_strategy = resp.flags & HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK; + if (sram_profile != NULL) + *sram_profile = resp.sram_profile; + cleanup: tf_msg_free_dma_buf(&qcaps_buf); diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 08d20cdd7a..188b361d71 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -158,6 +158,9 @@ int tf_msg_session_qcfg(struct tf *tfp); * [out] resv_strategy * Pointer to the reservation strategy * + * [out] sram_profile + * Pointer to the sram profile + * * Returns: * 0 on Success else internal Truflow error */ @@ -166,7 +169,8 @@ int tf_msg_session_resc_qcaps(struct tf *tfp, enum tf_dir dir, uint16_t size, struct tf_rm_resc_req_entry *query, - enum tf_rm_resc_resv_strategy *resv_strategy); + enum tf_rm_resc_resv_strategy *resv_strategy, + uint8_t *sram_profile); /** * Sends session HW resource allocation request to TF Firmware diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index dd537aaece..d2045921b9 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -551,7 +551,8 @@ tf_rm_create_db(struct tf *tfp, parms->dir, max_types, query, - &resv_strategy); + &resv_strategy, + NULL); if (rc) return rc; diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h index 4abe3fb468..eb2156456a 100644 --- a/drivers/net/bnxt/tf_core/tf_sram_mgr.h +++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h @@ -28,16 +28,6 @@ #define TF_SRAM_MGR_BLOCK_SZ_BYTES 64 #define TF_SRAM_MGR_MIN_SLICE_BYTES 8 -/** - * Bank identifier - */ -enum tf_sram_bank_id { - TF_SRAM_BANK_ID_0, /**< SRAM Bank 0 id */ - TF_SRAM_BANK_ID_1, /**< SRAM Bank 1 id */ - TF_SRAM_BANK_ID_2, /**< SRAM Bank 2 id */ - TF_SRAM_BANK_ID_3, /**< SRAM Bank 3 id */ - TF_SRAM_BANK_ID_MAX /**< SRAM Bank index limit */ -}; /** * TF slice size. -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 18/22] net/bnxt: add TruFlow and AFM SRAM partitioning support 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (16 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 17/22] net/bnxt: add new TruFlow API to get SRAM resources Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 19/22] net/bnxt: add Tx TruFlow table config for P4 device Ajit Khaparde ` (5 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru, Randy Schacher, Farah Smith [-- Attachment #1: Type: text/plain, Size: 24863 bytes --] From: Jay Ding <jay.ding@broadcom.com> Implement set/get_sram_policy which support both rx/tx direction truflow type the specific SRAM bank. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_core/tf_core.c | 82 ++++++ drivers/net/bnxt/tf_core/tf_core.h | 66 ++++- drivers/net/bnxt/tf_core/tf_device.c | 7 +- drivers/net/bnxt/tf_core/tf_device.h | 34 ++- drivers/net/bnxt/tf_core/tf_device_p4.c | 8 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 311 ++++++++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p58.h | 118 +-------- drivers/net/bnxt/tf_core/tf_tbl.c | 2 +- 8 files changed, 503 insertions(+), 125 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 346d220c87..90ff93946b 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1917,3 +1917,85 @@ int tf_query_sram_resources(struct tf *tfp, return 0; } + +int tf_set_sram_policy(struct tf *tfp, + struct tf_set_sram_policy_parms *parms) +{ + int rc = 0; + struct tf_dev_info dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_THOR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + if (dev.ops->tf_dev_set_sram_policy == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + rc = dev.ops->tf_dev_set_sram_policy(parms->dir, parms->bank_id); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: SRAM policy set failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + return rc; +} + +int tf_get_sram_policy(struct tf *tfp, + struct tf_get_sram_policy_parms *parms) +{ + int rc = 0; + struct tf_dev_info dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_THOR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + if (dev.ops->tf_dev_get_sram_policy == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + rc = dev.ops->tf_dev_get_sram_policy(parms->dir, parms->bank_id); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: SRAM policy get failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 078fd278a1..b2886355fa 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2455,7 +2455,7 @@ int tf_get_version(struct tf *tfp, */ struct tf_query_sram_resources_parms { /** - * [in] device type + * [in] Device type * * Device type for the session. */ @@ -2501,4 +2501,68 @@ struct tf_query_sram_resources_parms { int tf_query_sram_resources(struct tf *tfp, struct tf_query_sram_resources_parms *parms); +/** + * tf_set_sram_policy parameter definition + */ +struct tf_set_sram_policy_parms { + /** + * [in] Device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + + /** + * [in] Array of Bank id for each truflow tbl type + */ + uint8_t *bank_id; +}; + +/** + * Set SRAM policy + * + * Used to assign SRAM bank index to all truflow table type. + * + * Returns success or failure code. + */ +int tf_set_sram_policy(struct tf *tfp, + struct tf_set_sram_policy_parms *parms); + +/** + * tf_get_sram_policy parameter definition + */ +struct tf_get_sram_policy_parms { + /** + * [in] Device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + + /** + * [out] Array of Bank id for each truflow tbl type + */ + uint8_t bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1]; +}; + +/** + * Get SRAM policy + * + * Used to get the assigned bank of table types. + * + * Returns success or failure code. + */ +int tf_get_sram_policy(struct tf *tfp, + struct tf_get_sram_policy_parms *parms); + #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 25a7166bbb..40db546604 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -415,11 +415,14 @@ tf_dev_bind_p58(struct tf *tfp, } rsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX, - tf_tbl_p58, + tf_tbl_p58[TF_DIR_RX], + (uint16_t *)resources->tbl_cnt); + rsv_cnt += tf_dev_reservation_check(TF_TBL_TYPE_MAX, + tf_tbl_p58[TF_DIR_TX], (uint16_t *)resources->tbl_cnt); if (rsv_cnt) { tbl_cfg.num_elements = TF_TBL_TYPE_MAX; - tbl_cfg.cfg = tf_tbl_p58; + tbl_cfg.cfg = tf_tbl_p58[TF_DIR_RX]; tbl_cfg.resources = resources; rc = tf_tbl_bind(tfp, &tbl_cfg); if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 9360eb1358..3d5de988c4 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1083,7 +1083,7 @@ struct tf_dev_ops { uint32_t *em_caps); /** - * Device specific function that retrieve the sram resource + * Device specific function that retrieves the sram resource * * [in] query * Point to resources query result @@ -1101,6 +1101,38 @@ struct tf_dev_ops { int (*tf_dev_get_sram_resources)(void *query, uint32_t *sram_bank_caps, bool *dynamic_sram_capable); + + /** + * Device specific function that sets the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [in] band_id + * SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_set_sram_policy)(enum tf_dir dir, + uint8_t *bank_id); + + /** + * Device specific function that gets the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [in] band_id + * pointer to SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_sram_policy)(enum tf_dir dir, + uint8_t *bank_id); }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index cf0e919f9f..244bd08914 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -383,7 +383,9 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = NULL, .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, - .tf_dev_get_sram_resources = NULL + .tf_dev_get_sram_resources = NULL, + .tf_dev_set_sram_policy = NULL, + .tf_dev_get_sram_policy = NULL, }; /** @@ -447,5 +449,7 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_word_align = tf_dev_p4_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps, - .tf_dev_get_sram_resources = NULL + .tf_dev_get_sram_resources = NULL, + .tf_dev_set_sram_policy = NULL, + .tf_dev_get_sram_policy = NULL, }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 4687fa65dd..3c1c3a2de1 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -48,6 +48,235 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = "meter_dc", }; +struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { + [TF_DIR_RX][TF_TBL_TYPE_EM_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_WC_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_DROP_CNT] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METADATA] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, + 0, 0 + }, + /* Policy - ARs in bank 1 */ + [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 8, + }, + /* Policy - Encaps in bank 2 */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - Modify in bank 2 with Encaps */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - SP in bank 0 */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 8, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 4, + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 2, + }, + /* Policy - Stats in bank 3 */ + [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_EM_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_WC_FKB] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_DROP_CNT] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METADATA] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, + 0, 0 + }, + /* Policy - ARs in bank 1 */ + [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + .slices = 8, + }, + /* Policy - Encaps in bank 2 */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - Modify in bank 2 with Encaps */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_8B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_16B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_32B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 2, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_64B] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + .slices = 1, + }, + /* Policy - SP in bank 0 */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 8, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 4, + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, + .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + .slices = 2, + }, + /* Policy - Stats in bank 3 */ + [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = { + .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, + .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, + .slices = 8, + }, +}; + /** * Device specific function that retrieves the MAX number of HCAPI * types the device supports. @@ -444,6 +673,80 @@ static int tf_dev_p58_get_sram_resources(void *q, return 0; } +int sram_bank_hcapi_type[] = { + CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, + CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, + CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, + CFA_RESOURCE_TYPE_P58_SRAM_BANK_3 +}; + +/** + * Device specific function that set the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [in] band_id + * SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_set_sram_policy(enum tf_dir dir, + uint8_t *bank_id) +{ + struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; + uint8_t type; + uint8_t parent[TF_SRAM_BANK_ID_MAX] = { 0xFF, 0xFF, 0xFF, 0xFF }; + + for (type = TF_TBL_TYPE_FULL_ACT_RECORD; + type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++) { + if (bank_id[type] > 3) + return -EINVAL; + + rm_cfg[type].hcapi_type = sram_bank_hcapi_type[bank_id[type]]; + if (parent[bank_id[type]] == 0xFF) { + parent[bank_id[type]] = type; + rm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT; + rm_cfg[type].parent_subtype = 0; + if (rm_cfg[type].slices == 0) + rm_cfg[type].slices = 1; + } else { + rm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD; + rm_cfg[type].parent_subtype = parent[bank_id[type]]; + } + } + + return 0; +} + +/** + * Device specific function that get the sram policy + * + * [in] dir + * Receive or transmit direction + * + * [out] band_id + * pointer to SRAM bank id + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_get_sram_policy(enum tf_dir dir, + uint8_t *bank_id) +{ + struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; + uint8_t type; + + for (type = TF_TBL_TYPE_FULL_ACT_RECORD; + type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++) + bank_id[type] = rm_cfg[type].hcapi_type - CFA_RESOURCE_TYPE_P58_SRAM_BANK_0; + + return 0; +} + /** * Truflow P58 device specific functions */ @@ -495,7 +798,9 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = NULL, .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, - .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources, + .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy, + .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy, }; /** @@ -560,5 +865,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_word_align = tf_dev_p58_word_align, .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, - .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources + .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources, + .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy, + .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy, }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index f6e66936f3..61c856b767 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -12,6 +12,8 @@ #include "tf_if_tbl.h" #include "tf_global_cfg.h" +extern struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX]; + struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = { [TF_IDENT_TYPE_L2_CTXT_HIGH] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH, @@ -58,122 +60,6 @@ struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = { }, }; -struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { - [TF_TBL_TYPE_EM_FKB] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, - 0, 0 - }, - [TF_TBL_TYPE_WC_FKB] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, - 0, 0 - }, - [TF_TBL_TYPE_METER_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, - 0, 0 - }, - [TF_TBL_TYPE_METER_INST] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, - 0, 0 - }, - [TF_TBL_TYPE_METER_DROP_CNT] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, - 0, 0 - }, - [TF_TBL_TYPE_MIRROR_CONFIG] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, - 0, 0 - }, - [TF_TBL_TYPE_METADATA] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, - 0, 0 - }, - /* Policy - ARs in bank 1 */ - [TF_TBL_TYPE_FULL_ACT_RECORD] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 4, - }, - [TF_TBL_TYPE_COMPACT_ACT_RECORD] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 8, - }, - /* Policy - Encaps in bank 2 */ - [TF_TBL_TYPE_ACT_ENCAP_8B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 8, - }, - [TF_TBL_TYPE_ACT_ENCAP_16B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 4, - }, - [TF_TBL_TYPE_ACT_ENCAP_32B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 2, - }, - [TF_TBL_TYPE_ACT_ENCAP_64B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, - }, - /* Policy - Modify in bank 2 with Encaps */ - [TF_TBL_TYPE_ACT_MODIFY_8B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 8, - }, - [TF_TBL_TYPE_ACT_MODIFY_16B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 4, - }, - [TF_TBL_TYPE_ACT_MODIFY_32B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 2, - }, - [TF_TBL_TYPE_ACT_MODIFY_64B] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, - }, - /* Policy - SP in bank 0 */ - [TF_TBL_TYPE_ACT_SP_SMAC] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 8, - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 4, - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, - .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 2, - }, - /* Policy - Stats in bank 3 */ - [TF_TBL_TYPE_ACT_STATS_64] = { - .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, - .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, - .slices = 8, - }, -}; - struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_EM_RECORD] = { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC, diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 12eca36491..3fb22b52ac 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -58,10 +58,10 @@ tf_tbl_bind(struct tf *tfp, db_cfg.num_elements = parms->num_elements; db_cfg.module = TF_MODULE_TYPE_TABLE; db_cfg.num_elements = parms->num_elements; - db_cfg.cfg = parms->cfg; for (d = 0; d < TF_DIR_MAX; d++) { db_cfg.dir = d; + db_cfg.cfg = &parms->cfg[d ? TF_TBL_TYPE_MAX : 0]; db_cfg.alloc_cnt = parms->resources->tbl_cnt[d].cnt; db_cfg.rm_db = (void *)&tbl_db->tbl_db[d]; if (tf_session_is_shared_session(tfs) && -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 19/22] net/bnxt: add Tx TruFlow table config for P4 device 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (17 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 18/22] net/bnxt: add TruFlow and AFM SRAM partitioning support Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 20/22] net/bnxt: remove 2 slice wildcard entries Ajit Khaparde ` (4 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Venkat Duvvuru, Farah Smith, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 7163 bytes --] From: Jay Ding <jay.ding@broadcom.com> Add TX direction TruFlow table type config to be compatible with other devices. For P4 device, the TX cfg is duplicated from RX. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_core/tf_device.c | 4 +- drivers/net/bnxt/tf_core/tf_device_p4.c | 107 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p4.h | 58 +------------ 3 files changed, 111 insertions(+), 58 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 40db546604..4c416270b6 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -131,11 +131,11 @@ tf_dev_bind_p4(struct tf *tfp, } rsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX, - tf_tbl_p4, + tf_tbl_p4[TF_DIR_RX], (uint16_t *)resources->tbl_cnt); if (rsv_cnt) { tbl_cfg.num_elements = TF_TBL_TYPE_MAX; - tbl_cfg.cfg = tf_tbl_p4; + tbl_cfg.cfg = tf_tbl_p4[TF_DIR_RX]; tbl_cfg.resources = resources; rc = tf_tbl_bind(tfp, &tbl_cfg); if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 244bd08914..a6a59b8a07 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -59,6 +59,113 @@ const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = "tb_scope", }; +struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { + [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_MCAST_GROUPS] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_MCAST_GROUPS] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, + 0, 0 + }, +}; + /** * Device specific function that retrieves the MAX number of HCAPI * types the device supports. diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index e84c0f9e83..86de525995 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -12,6 +12,8 @@ #include "tf_if_tbl.h" #include "tf_global_cfg.h" +extern struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX]; + struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = { [TF_IDENT_TYPE_L2_CTXT_HIGH] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH, @@ -58,62 +60,6 @@ struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = { }, }; -struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = { - [TF_TBL_TYPE_FULL_ACT_RECORD] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, - 0, 0 - }, - [TF_TBL_TYPE_MCAST_GROUPS] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_8B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_16B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_64B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, - 0, 0 - }, - [TF_TBL_TYPE_ACT_STATS_64] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_MODIFY_IPV4] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, - 0, 0 - }, - [TF_TBL_TYPE_METER_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, - 0, 0 - }, - [TF_TBL_TYPE_METER_INST] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, - 0, 0 - }, - [TF_TBL_TYPE_MIRROR_CONFIG] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, - 0, 0 - }, - -}; - struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_TBL_SCOPE] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE, -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 20/22] net/bnxt: remove 2 slice wildcard entries 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (18 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 19/22] net/bnxt: add Tx TruFlow table config for P4 device Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 21/22] net/bnxt: check mismatch of control and physical port Ajit Khaparde ` (3 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Mike Baucom, Venkat Duvvuru, Kishore Padmanabha, Randy Schacher [-- Attachment #1: Type: text/plain, Size: 1402 bytes --] From: Mike Baucom <michael.baucom@broadcom.com> Remove 2-slice wildcard entries for scale. The type-5 wildcard IPv6 flows are removed in order to increase the scale for app-id=3. The app no longer supports 2-slice wildcard entries. Signed-off-by: Mike Baucom <michael.baucom@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index b64279710b..fd211bbc3f 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -462,7 +462,7 @@ ulp_ctx_shared_session_open(struct bnxt *bp, parms.shadow_copy = true; parms.bp = bp; - if (app_id == 0 || app_id == 3) + if (app_id == 0) parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW; else parms.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW; @@ -584,7 +584,7 @@ ulp_ctx_session_open(struct bnxt *bp, return rc; params.bp = bp; - if (app_id == 0 || app_id == 3) + if (app_id == 0) params.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW; else params.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW; -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 21/22] net/bnxt: check mismatch of control and physical port 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (19 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 20/22] net/bnxt: remove 2 slice wildcard entries Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 22/22] net/bnxt: use enum for bank ID Ajit Khaparde ` (2 subsequent siblings) 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Kishore Padmanabha, Mike Baucom, Shahaji Bhosle [-- Attachment #1: Type: text/plain, Size: 3329 bytes --] From: Kishore Padmanabha <kishore.padmanabha@broadcom.com> During the parsing of the ingress port ignore for a flow, added check to match the control port and the physical port that is configured to be ignored. If they do not match then the configuration to setup the svif ignore shall fail. Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_ulp/ulp_port_db.c | 23 +++++++++++++++++++++++ drivers/net/bnxt/tf_ulp/ulp_port_db.h | 13 +++++++++++++ drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 12 ++++++++++++ 3 files changed, 48 insertions(+) diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c index 5e7c1d1c17..f8ffb567b5 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c @@ -679,3 +679,26 @@ ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt, } return -EINVAL; } + +/* + * Api to get the phy port for a given port id. + * + * ulp_ctxt [in] Ptr to ulp context + * port_id [in] device port id + * phy_port [out] phy_port of the dpdk port_id + * + * Returns 0 on success or negative number on failure. + */ +int32_t +ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id, uint16_t *phy_port) +{ + struct ulp_func_if_info *info; + + info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id); + if (info) { + *phy_port = info->phy_port_id; + return 0; + } + return -EINVAL; +} diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h index 740c186e12..b112f1a216 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h @@ -314,4 +314,17 @@ int32_t ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt, uint32_t port_id, uint8_t **vnic); +/* + * Api to get the phy port for a given port id. + * + * ulp_ctxt [in] Ptr to ulp context + * port_id [in] device port id + * phy_port [out] phy_port of the dpdk port_id + * + * Returns 0 on success or negative number on failure. + */ +int32_t +ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt, + uint32_t port_id, uint16_t *phy_port); + #endif /* _ULP_PORT_DB_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 2ec3279239..f4274dd634 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -686,6 +686,18 @@ ulp_rte_phy_port_hdr_handler(const struct rte_flow_item *item, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SVIF_FLAG, rte_be_to_cpu_16(svif)); if (!mask) { + uint32_t port_id = 0; + uint16_t phy_port = 0; + + /* Validate the control port */ + port_id = ULP_COMP_FLD_IDX_RD(params, + BNXT_ULP_CF_IDX_DEV_PORT_ID); + if (ulp_port_db_phy_port_get(params->ulp_ctx, + port_id, &phy_port) || + (uint16_t)port_spec->index != phy_port) { + BNXT_TF_DBG(ERR, "Mismatch of control and phy_port\n"); + return BNXT_TF_RC_PARSE_ERR; + } ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF_IGNORE); memset(hdr_field->mask, 0xFF, sizeof(mask)); -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH v5 22/22] net/bnxt: use enum for bank ID 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (20 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 21/22] net/bnxt: check mismatch of control and physical port Ajit Khaparde @ 2021-11-04 21:58 ` Ajit Khaparde 2021-11-05 0:57 ` [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow Ajit Khaparde 2021-11-05 11:10 ` Ferruh Yigit 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-04 21:58 UTC (permalink / raw) To: dev; +Cc: Jay Ding, Steve Rempe, Farah Smith [-- Attachment #1: Type: text/plain, Size: 6704 bytes --] From: Jay Ding <jay.ding@broadcom.com> Instead of integer, using enum tf_sram_bank_id for bank id in tf_set_sram_policy_parms. Add index check against the allocation of the meter instance for meter drop count because there is no reason to access it if the corresponding meter entry is not allocated. Signed-off-by: Jay Ding <jay.ding@broadcom.com> Reviewed-by: Steve Rempe <steve.rempe@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/tf_core/tf_core.h | 4 +- drivers/net/bnxt/tf_core/tf_device.h | 4 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 10 ++-- drivers/net/bnxt/tf_core/tf_tbl.c | 75 ++++++++++++------------ 4 files changed, 47 insertions(+), 46 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index b2886355fa..f891d7a48f 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2520,7 +2520,7 @@ struct tf_set_sram_policy_parms { /** * [in] Array of Bank id for each truflow tbl type */ - uint8_t *bank_id; + enum tf_sram_bank_id bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1]; }; /** @@ -2552,7 +2552,7 @@ struct tf_get_sram_policy_parms { /** * [out] Array of Bank id for each truflow tbl type */ - uint8_t bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1]; + enum tf_sram_bank_id bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1]; }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 3d5de988c4..bfb5de4370 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -1116,7 +1116,7 @@ struct tf_dev_ops { * - (-EINVAL) on failure. */ int (*tf_dev_set_sram_policy)(enum tf_dir dir, - uint8_t *bank_id); + enum tf_sram_bank_id *bank_id); /** * Device specific function that gets the sram policy @@ -1132,7 +1132,7 @@ struct tf_dev_ops { * - (-EINVAL) on failure. */ int (*tf_dev_get_sram_policy)(enum tf_dir dir, - uint8_t *bank_id); + enum tf_sram_bank_id *bank_id); }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 3c1c3a2de1..30c0af7eef 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -673,7 +673,7 @@ static int tf_dev_p58_get_sram_resources(void *q, return 0; } -int sram_bank_hcapi_type[] = { +static int sram_bank_hcapi_type[] = { CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, @@ -694,15 +694,15 @@ int sram_bank_hcapi_type[] = { * - (-EINVAL) on failure. */ static int tf_dev_p58_set_sram_policy(enum tf_dir dir, - uint8_t *bank_id) + enum tf_sram_bank_id *bank_id) { struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; uint8_t type; uint8_t parent[TF_SRAM_BANK_ID_MAX] = { 0xFF, 0xFF, 0xFF, 0xFF }; for (type = TF_TBL_TYPE_FULL_ACT_RECORD; - type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++) { - if (bank_id[type] > 3) + type <= TF_TBL_TYPE_ACT_MODIFY_64B; type++) { + if (bank_id[type] >= TF_SRAM_BANK_ID_MAX) return -EINVAL; rm_cfg[type].hcapi_type = sram_bank_hcapi_type[bank_id[type]]; @@ -735,7 +735,7 @@ static int tf_dev_p58_set_sram_policy(enum tf_dir dir, * - (-EINVAL) on failure. */ static int tf_dev_p58_get_sram_policy(enum tf_dir dir, - uint8_t *bank_id) + enum tf_sram_bank_id *bank_id) { struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; uint8_t type; diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 3fb22b52ac..f18e4ba346 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -307,28 +307,28 @@ tf_tbl_set(struct tf *tfp, } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; - - /* Do not check meter drop counter because it is not allocated - * resources + /* Verify that the entry has been previously allocated. + * for meter drop counter, check the corresponding meter + * entry */ - if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) { - /* Verify that the entry has been previously allocated */ - aparms.rm_db = tbl_db->tbl_db[parms->dir]; + aparms.rm_db = tbl_db->tbl_db[parms->dir]; + if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) aparms.subtype = parms->type; - aparms.allocated = &allocated; - aparms.index = parms->idx; - rc = tf_rm_is_allocated(&aparms); - if (rc) - return rc; + else + aparms.subtype = TF_TBL_TYPE_METER_INST; + aparms.allocated = &allocated; + aparms.index = parms->idx; + rc = tf_rm_is_allocated(&aparms); + if (rc) + return rc; - if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { - TFP_DRV_LOG(ERR, - "%s, Invalid or not allocated, type:%s, idx:%d\n", - tf_dir_2_str(parms->dir), - tf_tbl_type_2_str(parms->type), - parms->idx); - return -EINVAL; - } + if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { + TFP_DRV_LOG(ERR, + "%s, Invalid or not allocated, type:%s, idx:%d\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + parms->idx); + return -EINVAL; } /* Set the entry */ @@ -398,27 +398,28 @@ tf_tbl_get(struct tf *tfp, } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; - /* Do not check meter drop counter because it is not allocated - * resources. + /* Verify that the entry has been previously allocated. + * for meter drop counter, check the corresponding meter + * entry */ - if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) { - /* Verify that the entry has been previously allocated */ - aparms.rm_db = tbl_db->tbl_db[parms->dir]; + aparms.rm_db = tbl_db->tbl_db[parms->dir]; + if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) aparms.subtype = parms->type; - aparms.index = parms->idx; - aparms.allocated = &allocated; - rc = tf_rm_is_allocated(&aparms); - if (rc) - return rc; + else + aparms.subtype = TF_TBL_TYPE_METER_INST; + aparms.index = parms->idx; + aparms.allocated = &allocated; + rc = tf_rm_is_allocated(&aparms); + if (rc) + return rc; - if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { - TFP_DRV_LOG(ERR, - "%s, Invalid or not allocated index, type:%s, idx:%d\n", - tf_dir_2_str(parms->dir), - tf_tbl_type_2_str(parms->type), - parms->idx); - return -EINVAL; - } + if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { + TFP_DRV_LOG(ERR, + "%s, Invalid or not allocated index, type:%s, idx:%d\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + parms->idx); + return -EINVAL; } /* Set the entry */ -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (21 preceding siblings ...) 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 22/22] net/bnxt: use enum for bank ID Ajit Khaparde @ 2021-11-05 0:57 ` Ajit Khaparde 2021-11-05 11:10 ` Ferruh Yigit 23 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-05 0:57 UTC (permalink / raw) To: dpdk-dev On Thu, Nov 4, 2021 at 2:58 PM Ajit Khaparde <ajit.khaparde@broadcom.com> wrote: > > Enhancements include: > * Scaling numbers on Thor > * Inner IP header support for GRE tunnel flows > * Enable wildcard match for ingress flows > * Add clear on read for flow stats on Thor > * Add nat support for dest IP and port combination > * Remove 2-slice WC support > * Add support for socket redirect feature > * Add new API TruFlow get SRAM resources > * Remove accumulation of stats devargs argument > * Add TruFlow and AFM SRAM partitioning support > > V2: > * Compilation fixes > * Remove 2-slice WC support > * Add support for socket redirect feature > * Add new API TruFlow get SRAM resources > * Remove accumulation of stats devargs argument > * Add TruFlow and AFM SRAM partitioning support > > V3: > * Added one more patch (use enum for bank ID) > > V4: > * Fixed typos in patch 2/20 > * Fix checkpatch warnings > * Updated commit logs > * Rebased the patches to latest dpdk-next-net > > V5: > * Split couple of patches into cleanup and code change patch > * Fixed typo in some patches > * Address review comments > * Rebased patches to latest dpdk-next-net Patchset applied to dpdk-next-net-brcm. > > Ajit Khaparde (2): > net/bnxt: remove unused functions > net/bnxt: enable wildcard match for ingress flows > > Farah Smith (1): > net/bnxt: add clear on read support > > Jay Ding (5): > net/bnxt: get TruFlow version > net/bnxt: add new TruFlow API to get SRAM resources > net/bnxt: add TruFlow and AFM SRAM partitioning support > net/bnxt: add Tx TruFlow table config for P4 device > net/bnxt: use enum for bank ID > > Kishore Padmanabha (11): > net/bnxt: add NAT support for dest IP and port combination > net/bnxt: add support for multi root capability > net/bnxt: fix out of bounds issue in hash list > net/bnxt: add capability option for socket redirect > net/bnxt: address ISO C90 compilation error > net/bnxt: support inner IP header for GRE tunnel flows > net/bnxt: remove devargs for stats accumulation > net/bnxt: update log messages in TruFlow path > net/bnxt: add support for socket direct feature > net/bnxt: modify VF representor alloc sequence > net/bnxt: check mismatch of control and physical port > > Mike Baucom (1): > net/bnxt: remove 2 slice wildcard entries > > Shahaji Bhosle (2): > net/bnxt: increase flow scale for Thor > net/bnxt: fix clang compiler warnings > > drivers/net/bnxt/bnxt.h | 25 +- > drivers/net/bnxt/bnxt_cpr.c | 2 +- > drivers/net/bnxt/bnxt_ethdev.c | 274 +- > drivers/net/bnxt/bnxt_hwrm.c | 36 + > drivers/net/bnxt/bnxt_hwrm.h | 1 + > drivers/net/bnxt/bnxt_reps.c | 9 +- > drivers/net/bnxt/hsi_struct_def_dpdk.h | 4061 ++++++++++++++--- > drivers/net/bnxt/tf_core/tf_core.c | 197 + > drivers/net/bnxt/tf_core/tf_core.h | 202 + > drivers/net/bnxt/tf_core/tf_device.c | 11 +- > drivers/net/bnxt/tf_core/tf_device.h | 102 + > drivers/net/bnxt/tf_core/tf_device_p4.c | 178 +- > drivers/net/bnxt/tf_core/tf_device_p4.h | 137 +- > drivers/net/bnxt/tf_core/tf_device_p58.c | 421 +- > drivers/net/bnxt/tf_core/tf_device_p58.h | 205 +- > drivers/net/bnxt/tf_core/tf_msg.c | 87 +- > drivers/net/bnxt/tf_core/tf_msg.h | 31 +- > drivers/net/bnxt/tf_core/tf_rm.c | 3 +- > drivers/net/bnxt/tf_core/tf_sram_mgr.h | 10 - > drivers/net/bnxt/tf_core/tf_tbl.c | 83 +- > drivers/net/bnxt/tf_core/tf_tbl_sram.c | 13 +- > drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 59 +- > drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 9 +- > drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 29 +- > .../generic_templates/ulp_template_db_act.c | 376 +- > .../generic_templates/ulp_template_db_class.c | 1986 ++++---- > .../generic_templates/ulp_template_db_enum.h | 91 +- > .../generic_templates/ulp_template_db_tbl.c | 3946 ++++++++++++---- > .../ulp_template_db_thor_act.c | 150 +- > .../ulp_template_db_thor_class.c | 909 ++-- > .../ulp_template_db_wh_plus_act.c | 336 +- > .../ulp_template_db_wh_plus_class.c | 222 +- > drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 8 +- > drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 12 +- > drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 2 +- > drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 20 +- > drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +- > drivers/net/bnxt/tf_ulp/ulp_port_db.c | 23 + > drivers/net/bnxt/tf_ulp/ulp_port_db.h | 13 + > drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 32 +- > drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +- > 41 files changed, 10250 insertions(+), 4065 deletions(-) > > -- > 2.30.1 (Apple Git-130) > ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde ` (22 preceding siblings ...) 2021-11-05 0:57 ` [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow Ajit Khaparde @ 2021-11-05 11:10 ` Ferruh Yigit 2021-11-05 11:30 ` Thomas Monjalon ` (3 more replies) 23 siblings, 4 replies; 118+ messages in thread From: Ferruh Yigit @ 2021-11-05 11:10 UTC (permalink / raw) To: Ajit Khaparde, dev; +Cc: Thomas Monjalon, David Marchand On 11/4/2021 9:58 PM, Ajit Khaparde wrote: > Enhancements include: > * Scaling numbers on Thor > * Inner IP header support for GRE tunnel flows > * Enable wildcard match for ingress flows > * Add clear on read for flow stats on Thor > * Add nat support for dest IP and port combination > * Remove 2-slice WC support > * Add support for socket redirect feature > * Add new API TruFlow get SRAM resources > * Remove accumulation of stats devargs argument > * Add TruFlow and AFM SRAM partitioning support > > V2: > * Compilation fixes > * Remove 2-slice WC support > * Add support for socket redirect feature > * Add new API TruFlow get SRAM resources > * Remove accumulation of stats devargs argument > * Add TruFlow and AFM SRAM partitioning support > > V3: > * Added one more patch (use enum for bank ID) > > V4: > * Fixed typos in patch 2/20 > * Fix checkpatch warnings > * Updated commit logs > * Rebased the patches to latest dpdk-next-net > > V5: > * Split couple of patches into cleanup and code change patch > * Fixed typo in some patches > * Address review comments > * Rebased patches to latest dpdk-next-net > > Ajit Khaparde (2): > net/bnxt: remove unused functions > net/bnxt: enable wildcard match for ingress flows > > Farah Smith (1): > net/bnxt: add clear on read support > > Jay Ding (5): > net/bnxt: get TruFlow version > net/bnxt: add new TruFlow API to get SRAM resources > net/bnxt: add TruFlow and AFM SRAM partitioning support > net/bnxt: add Tx TruFlow table config for P4 device > net/bnxt: use enum for bank ID > > Kishore Padmanabha (11): > net/bnxt: add NAT support for dest IP and port combination > net/bnxt: add support for multi root capability > net/bnxt: fix out of bounds issue in hash list > net/bnxt: add capability option for socket redirect > net/bnxt: address ISO C90 compilation error > net/bnxt: support inner IP header for GRE tunnel flows > net/bnxt: remove devargs for stats accumulation > net/bnxt: update log messages in TruFlow path > net/bnxt: add support for socket direct feature > net/bnxt: modify VF representor alloc sequence > net/bnxt: check mismatch of control and physical port > > Mike Baucom (1): > net/bnxt: remove 2 slice wildcard entries > > Shahaji Bhosle (2): > net/bnxt: increase flow scale for Thor > net/bnxt: fix clang compiler warnings > Hi Ajit, It would be good to updated the release notes for the above changes, but -rc2 is a day away and I don't want to block the set for this. Can you please send the documentation update separately? If it comes before next-net merged, I can squash it. ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow 2021-11-05 11:10 ` Ferruh Yigit @ 2021-11-05 11:30 ` Thomas Monjalon 2021-11-05 16:55 ` [dpdk-dev] [PATCH] doc: update release notes for bnxt PMD Ajit Khaparde ` (2 subsequent siblings) 3 siblings, 0 replies; 118+ messages in thread From: Thomas Monjalon @ 2021-11-05 11:30 UTC (permalink / raw) To: Ajit Khaparde, Ferruh Yigit; +Cc: dev, David Marchand 05/11/2021 12:10, Ferruh Yigit: > On 11/4/2021 9:58 PM, Ajit Khaparde wrote: > > Enhancements include: > > * Scaling numbers on Thor > > * Inner IP header support for GRE tunnel flows > > * Enable wildcard match for ingress flows > > * Add clear on read for flow stats on Thor > > * Add nat support for dest IP and port combination > > * Remove 2-slice WC support > > * Add support for socket redirect feature > > * Add new API TruFlow get SRAM resources > > * Remove accumulation of stats devargs argument > > * Add TruFlow and AFM SRAM partitioning support > > > > V2: > > * Compilation fixes > > * Remove 2-slice WC support > > * Add support for socket redirect feature > > * Add new API TruFlow get SRAM resources > > * Remove accumulation of stats devargs argument > > * Add TruFlow and AFM SRAM partitioning support > > > > V3: > > * Added one more patch (use enum for bank ID) > > > > V4: > > * Fixed typos in patch 2/20 > > * Fix checkpatch warnings > > * Updated commit logs > > * Rebased the patches to latest dpdk-next-net > > > > V5: > > * Split couple of patches into cleanup and code change patch > > * Fixed typo in some patches > > * Address review comments > > * Rebased patches to latest dpdk-next-net > > > > Ajit Khaparde (2): > > net/bnxt: remove unused functions > > net/bnxt: enable wildcard match for ingress flows > > > > Farah Smith (1): > > net/bnxt: add clear on read support > > > > Jay Ding (5): > > net/bnxt: get TruFlow version > > net/bnxt: add new TruFlow API to get SRAM resources > > net/bnxt: add TruFlow and AFM SRAM partitioning support > > net/bnxt: add Tx TruFlow table config for P4 device > > net/bnxt: use enum for bank ID > > > > Kishore Padmanabha (11): > > net/bnxt: add NAT support for dest IP and port combination > > net/bnxt: add support for multi root capability > > net/bnxt: fix out of bounds issue in hash list > > net/bnxt: add capability option for socket redirect > > net/bnxt: address ISO C90 compilation error > > net/bnxt: support inner IP header for GRE tunnel flows > > net/bnxt: remove devargs for stats accumulation > > net/bnxt: update log messages in TruFlow path > > net/bnxt: add support for socket direct feature > > net/bnxt: modify VF representor alloc sequence > > net/bnxt: check mismatch of control and physical port > > > > Mike Baucom (1): > > net/bnxt: remove 2 slice wildcard entries > > > > Shahaji Bhosle (2): > > net/bnxt: increase flow scale for Thor > > net/bnxt: fix clang compiler warnings > > > > Hi Ajit, > > It would be good to updated the release notes for the above changes, > but -rc2 is a day away and I don't want to block the set for this. > > Can you please send the documentation update separately? > If it comes before next-net merged, I can squash it. Each patch introducing a new feature should have a release notes update. Thank you Ferruh for noticing it. ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH] doc: update release notes for bnxt PMD 2021-11-05 11:10 ` Ferruh Yigit 2021-11-05 11:30 ` Thomas Monjalon @ 2021-11-05 16:55 ` Ajit Khaparde 2021-11-05 18:14 ` Ferruh Yigit 2021-11-05 16:57 ` [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow Ajit Khaparde 2021-11-05 18:46 ` [dpdk-dev] [PATCH] doc: update for bnxt PMD Ajit Khaparde 3 siblings, 1 reply; 118+ messages in thread From: Ajit Khaparde @ 2021-11-05 16:55 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit [-- Attachment #1: Type: text/plain, Size: 1089 bytes --] Update release notes for new functionality added to the bnxt PMD. Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- doc/guides/rel_notes/release_21_11.rst | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst index 3367a15c85..d8b9531af1 100644 --- a/doc/guides/rel_notes/release_21_11.rst +++ b/doc/guides/rel_notes/release_21_11.rst @@ -152,7 +152,14 @@ New Features * Added flow offload support for Thor. * Implement support for tunnel offload. - * Updated HWRM API to version 1.10.2.44 + * Updated HWRM API to version 1.10.2.68. + * Updated support for RTE_FLOW_ACTION_TYPE_RSS. + * Added support for socket redirection. + * Added support for inner IP header for GRE tunnel flows. + * Added NAT support for dest IP and port combination. + * Added TruFlow and AFM SRAM partitioning support. + * Added wildcard match support for ingress flows. + * Removed devargs for stats accumulation. * **Updated Cisco enic driver.** -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH] doc: update release notes for bnxt PMD 2021-11-05 16:55 ` [dpdk-dev] [PATCH] doc: update release notes for bnxt PMD Ajit Khaparde @ 2021-11-05 18:14 ` Ferruh Yigit 2021-11-05 18:22 ` Ajit Khaparde 0 siblings, 1 reply; 118+ messages in thread From: Ferruh Yigit @ 2021-11-05 18:14 UTC (permalink / raw) To: Ajit Khaparde; +Cc: dev On 11/5/2021 4:55 PM, Ajit Khaparde wrote: > Update release notes for new functionality added to the bnxt PMD. > > Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com> > --- > doc/guides/rel_notes/release_21_11.rst | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst > index 3367a15c85..d8b9531af1 100644 > --- a/doc/guides/rel_notes/release_21_11.rst > +++ b/doc/guides/rel_notes/release_21_11.rst > @@ -152,7 +152,14 @@ New Features > > * Added flow offload support for Thor. > * Implement support for tunnel offload. > - * Updated HWRM API to version 1.10.2.44 > + * Updated HWRM API to version 1.10.2.68. > + * Updated support for RTE_FLOW_ACTION_TYPE_RSS. I am not sure which commit this update corresponds to, can you please share the commit that this update should go? ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH] doc: update release notes for bnxt PMD 2021-11-05 18:14 ` Ferruh Yigit @ 2021-11-05 18:22 ` Ajit Khaparde 2021-11-05 18:38 ` Ferruh Yigit 0 siblings, 1 reply; 118+ messages in thread From: Ajit Khaparde @ 2021-11-05 18:22 UTC (permalink / raw) To: Ferruh Yigit; +Cc: dpdk-dev On Fri, Nov 5, 2021 at 11:14 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote: > > On 11/5/2021 4:55 PM, Ajit Khaparde wrote: > > Update release notes for new functionality added to the bnxt PMD. > > > > Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com> > > --- > > doc/guides/rel_notes/release_21_11.rst | 9 ++++++++- > > 1 file changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst > > index 3367a15c85..d8b9531af1 100644 > > --- a/doc/guides/rel_notes/release_21_11.rst > > +++ b/doc/guides/rel_notes/release_21_11.rst > > @@ -152,7 +152,14 @@ New Features > > > > * Added flow offload support for Thor. > > * Implement support for tunnel offload. > > - * Updated HWRM API to version 1.10.2.44 > > + * Updated HWRM API to version 1.10.2.68. > > + * Updated support for RTE_FLOW_ACTION_TYPE_RSS. > > I am not sure which commit this update corresponds to, can you please > share the commit that this update should go? I think you are looking for this - 239695f754cb ("net/bnxt: enhance RSS action support") Thanks Ajit ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH] doc: update release notes for bnxt PMD 2021-11-05 18:22 ` Ajit Khaparde @ 2021-11-05 18:38 ` Ferruh Yigit 2021-11-05 18:41 ` Ajit Khaparde 0 siblings, 1 reply; 118+ messages in thread From: Ferruh Yigit @ 2021-11-05 18:38 UTC (permalink / raw) To: Ajit Khaparde; +Cc: dpdk-dev, Thomas Monjalon On 11/5/2021 6:22 PM, Ajit Khaparde wrote: > On Fri, Nov 5, 2021 at 11:14 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote: >> >> On 11/5/2021 4:55 PM, Ajit Khaparde wrote: >>> Update release notes for new functionality added to the bnxt PMD. >>> >>> Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com> >>> --- >>> doc/guides/rel_notes/release_21_11.rst | 9 ++++++++- >>> 1 file changed, 8 insertions(+), 1 deletion(-) >>> >>> diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst >>> index 3367a15c85..d8b9531af1 100644 >>> --- a/doc/guides/rel_notes/release_21_11.rst >>> +++ b/doc/guides/rel_notes/release_21_11.rst >>> @@ -152,7 +152,14 @@ New Features >>> >>> * Added flow offload support for Thor. >>> * Implement support for tunnel offload. >>> - * Updated HWRM API to version 1.10.2.44 >>> + * Updated HWRM API to version 1.10.2.68. >>> + * Updated support for RTE_FLOW_ACTION_TYPE_RSS. >> >> I am not sure which commit this update corresponds to, can you please >> share the commit that this update should go? > I think you are looking for this - > 239695f754cb ("net/bnxt: enhance RSS action support") > Ahh, that is pre -rc1, and not related to the latest based code series either. Since original commit is part of -rc1, that can't be squashed of course, can you please send a separate patch for it, with proper fixes tag etc? Thanks, ferruh ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH] doc: update release notes for bnxt PMD 2021-11-05 18:38 ` Ferruh Yigit @ 2021-11-05 18:41 ` Ajit Khaparde 2021-11-05 18:42 ` Ferruh Yigit 0 siblings, 1 reply; 118+ messages in thread From: Ajit Khaparde @ 2021-11-05 18:41 UTC (permalink / raw) To: Ferruh Yigit; +Cc: dpdk-dev, Thomas Monjalon On Fri, Nov 5, 2021 at 11:38 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote: > > On 11/5/2021 6:22 PM, Ajit Khaparde wrote: > > On Fri, Nov 5, 2021 at 11:14 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote: > >> > >> On 11/5/2021 4:55 PM, Ajit Khaparde wrote: > >>> Update release notes for new functionality added to the bnxt PMD. > >>> > >>> Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com> > >>> --- > >>> doc/guides/rel_notes/release_21_11.rst | 9 ++++++++- > >>> 1 file changed, 8 insertions(+), 1 deletion(-) > >>> > >>> diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst > >>> index 3367a15c85..d8b9531af1 100644 > >>> --- a/doc/guides/rel_notes/release_21_11.rst > >>> +++ b/doc/guides/rel_notes/release_21_11.rst > >>> @@ -152,7 +152,14 @@ New Features > >>> > >>> * Added flow offload support for Thor. > >>> * Implement support for tunnel offload. > >>> - * Updated HWRM API to version 1.10.2.44 > >>> + * Updated HWRM API to version 1.10.2.68. > >>> + * Updated support for RTE_FLOW_ACTION_TYPE_RSS. > >> > >> I am not sure which commit this update corresponds to, can you please > >> share the commit that this update should go? > > I think you are looking for this - > > 239695f754cb ("net/bnxt: enhance RSS action support") > > > > Ahh, that is pre -rc1, and not related to the latest based code series either. > > Since original commit is part of -rc1, that can't be squashed of course, can > you please send a separate patch for it, with proper fixes tag etc? Sure. I will send a separate patch for that. Do you want me to respin a new patch for the remaining? Or you can remove the line and squash? > > Thanks, > ferruh ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH] doc: update release notes for bnxt PMD 2021-11-05 18:41 ` Ajit Khaparde @ 2021-11-05 18:42 ` Ferruh Yigit 2021-11-05 18:48 ` Ajit Khaparde 0 siblings, 1 reply; 118+ messages in thread From: Ferruh Yigit @ 2021-11-05 18:42 UTC (permalink / raw) To: Ajit Khaparde; +Cc: dpdk-dev, Thomas Monjalon On 11/5/2021 6:41 PM, Ajit Khaparde wrote: > On Fri, Nov 5, 2021 at 11:38 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote: >> >> On 11/5/2021 6:22 PM, Ajit Khaparde wrote: >>> On Fri, Nov 5, 2021 at 11:14 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote: >>>> >>>> On 11/5/2021 4:55 PM, Ajit Khaparde wrote: >>>>> Update release notes for new functionality added to the bnxt PMD. >>>>> >>>>> Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com> >>>>> --- >>>>> doc/guides/rel_notes/release_21_11.rst | 9 ++++++++- >>>>> 1 file changed, 8 insertions(+), 1 deletion(-) >>>>> >>>>> diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst >>>>> index 3367a15c85..d8b9531af1 100644 >>>>> --- a/doc/guides/rel_notes/release_21_11.rst >>>>> +++ b/doc/guides/rel_notes/release_21_11.rst >>>>> @@ -152,7 +152,14 @@ New Features >>>>> >>>>> * Added flow offload support for Thor. >>>>> * Implement support for tunnel offload. >>>>> - * Updated HWRM API to version 1.10.2.44 >>>>> + * Updated HWRM API to version 1.10.2.68. >>>>> + * Updated support for RTE_FLOW_ACTION_TYPE_RSS. >>>> >>>> I am not sure which commit this update corresponds to, can you please >>>> share the commit that this update should go? >>> I think you are looking for this - >>> 239695f754cb ("net/bnxt: enhance RSS action support") >>> >> >> Ahh, that is pre -rc1, and not related to the latest based code series either. >> >> Since original commit is part of -rc1, that can't be squashed of course, can >> you please send a separate patch for it, with proper fixes tag etc? > Sure. I will send a separate patch for that. > Do you want me to respin a new patch for the remaining? > Or you can remove the line and squash? Except 'RTE_FLOW_ACTION_TYPE_RSS' update, Squashed into relevant commits in next-net, thanks. ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH] doc: update release notes for bnxt PMD 2021-11-05 18:42 ` Ferruh Yigit @ 2021-11-05 18:48 ` Ajit Khaparde 0 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-05 18:48 UTC (permalink / raw) To: Ferruh Yigit; +Cc: dpdk-dev, Thomas Monjalon On Fri, Nov 5, 2021 at 11:42 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote: > > On 11/5/2021 6:41 PM, Ajit Khaparde wrote: > > On Fri, Nov 5, 2021 at 11:38 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote: > >> > >> On 11/5/2021 6:22 PM, Ajit Khaparde wrote: > >>> On Fri, Nov 5, 2021 at 11:14 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote: > >>>> > >>>> On 11/5/2021 4:55 PM, Ajit Khaparde wrote: > >>>>> Update release notes for new functionality added to the bnxt PMD. > >>>>> > >>>>> Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com> > >>>>> --- > >>>>> doc/guides/rel_notes/release_21_11.rst | 9 ++++++++- > >>>>> 1 file changed, 8 insertions(+), 1 deletion(-) > >>>>> > >>>>> diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst > >>>>> index 3367a15c85..d8b9531af1 100644 > >>>>> --- a/doc/guides/rel_notes/release_21_11.rst > >>>>> +++ b/doc/guides/rel_notes/release_21_11.rst > >>>>> @@ -152,7 +152,14 @@ New Features > >>>>> > >>>>> * Added flow offload support for Thor. > >>>>> * Implement support for tunnel offload. > >>>>> - * Updated HWRM API to version 1.10.2.44 > >>>>> + * Updated HWRM API to version 1.10.2.68. > >>>>> + * Updated support for RTE_FLOW_ACTION_TYPE_RSS. > >>>> > >>>> I am not sure which commit this update corresponds to, can you please > >>>> share the commit that this update should go? > >>> I think you are looking for this - > >>> 239695f754cb ("net/bnxt: enhance RSS action support") > >>> > >> > >> Ahh, that is pre -rc1, and not related to the latest based code series either. > >> > >> Since original commit is part of -rc1, that can't be squashed of course, can > >> you please send a separate patch for it, with proper fixes tag etc? > > Sure. I will send a separate patch for that. > > Do you want me to respin a new patch for the remaining? > > Or you can remove the line and squash? > > Except 'RTE_FLOW_ACTION_TYPE_RSS' update, Sent a patch [1] for this. Added the entry at the end of the list. Hopefully it will apply cleanly. Thanks [1] https://patchwork.dpdk.org/project/dpdk/patch/20211105184634.20546-1-ajit.khaparde@broadcom.com/ > Squashed into relevant commits in next-net, thanks. > ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow 2021-11-05 11:10 ` Ferruh Yigit 2021-11-05 11:30 ` Thomas Monjalon 2021-11-05 16:55 ` [dpdk-dev] [PATCH] doc: update release notes for bnxt PMD Ajit Khaparde @ 2021-11-05 16:57 ` Ajit Khaparde 2021-11-05 17:20 ` Ferruh Yigit 2021-11-05 18:46 ` [dpdk-dev] [PATCH] doc: update for bnxt PMD Ajit Khaparde 3 siblings, 1 reply; 118+ messages in thread From: Ajit Khaparde @ 2021-11-05 16:57 UTC (permalink / raw) To: Ferruh Yigit; +Cc: dpdk-dev, Thomas Monjalon, David Marchand On Fri, Nov 5, 2021 at 4:10 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote: > > On 11/4/2021 9:58 PM, Ajit Khaparde wrote: > > Enhancements include: > > * Scaling numbers on Thor > > * Inner IP header support for GRE tunnel flows > > * Enable wildcard match for ingress flows > > * Add clear on read for flow stats on Thor > > * Add nat support for dest IP and port combination > > * Remove 2-slice WC support > > * Add support for socket redirect feature > > * Add new API TruFlow get SRAM resources > > * Remove accumulation of stats devargs argument > > * Add TruFlow and AFM SRAM partitioning support > > > > V2: > > * Compilation fixes > > * Remove 2-slice WC support > > * Add support for socket redirect feature > > * Add new API TruFlow get SRAM resources > > * Remove accumulation of stats devargs argument > > * Add TruFlow and AFM SRAM partitioning support > > > > V3: > > * Added one more patch (use enum for bank ID) > > > > V4: > > * Fixed typos in patch 2/20 > > * Fix checkpatch warnings > > * Updated commit logs > > * Rebased the patches to latest dpdk-next-net > > > > V5: > > * Split couple of patches into cleanup and code change patch > > * Fixed typo in some patches > > * Address review comments > > * Rebased patches to latest dpdk-next-net > > > > Ajit Khaparde (2): > > net/bnxt: remove unused functions > > net/bnxt: enable wildcard match for ingress flows > > > > Farah Smith (1): > > net/bnxt: add clear on read support > > > > Jay Ding (5): > > net/bnxt: get TruFlow version > > net/bnxt: add new TruFlow API to get SRAM resources > > net/bnxt: add TruFlow and AFM SRAM partitioning support > > net/bnxt: add Tx TruFlow table config for P4 device > > net/bnxt: use enum for bank ID > > > > Kishore Padmanabha (11): > > net/bnxt: add NAT support for dest IP and port combination > > net/bnxt: add support for multi root capability > > net/bnxt: fix out of bounds issue in hash list > > net/bnxt: add capability option for socket redirect > > net/bnxt: address ISO C90 compilation error > > net/bnxt: support inner IP header for GRE tunnel flows > > net/bnxt: remove devargs for stats accumulation > > net/bnxt: update log messages in TruFlow path > > net/bnxt: add support for socket direct feature > > net/bnxt: modify VF representor alloc sequence > > net/bnxt: check mismatch of control and physical port > > > > Mike Baucom (1): > > net/bnxt: remove 2 slice wildcard entries > > > > Shahaji Bhosle (2): > > net/bnxt: increase flow scale for Thor > > net/bnxt: fix clang compiler warnings > > > > Hi Ajit, > > It would be good to updated the release notes for the above changes, > but -rc2 is a day away and I don't want to block the set for this. > > Can you please send the documentation update separately? > If it comes before next-net merged, I can squash it. Hi Ferruh, Done. Please let me know if you can pick it straight from patchwork. Otherwise I can merge in the subtree and you can pick from there. Please let me know. Thanks Ajit ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow 2021-11-05 16:57 ` [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow Ajit Khaparde @ 2021-11-05 17:20 ` Ferruh Yigit 0 siblings, 0 replies; 118+ messages in thread From: Ferruh Yigit @ 2021-11-05 17:20 UTC (permalink / raw) To: Ajit Khaparde; +Cc: dpdk-dev, Thomas Monjalon, David Marchand On 11/5/2021 4:57 PM, Ajit Khaparde wrote: > On Fri, Nov 5, 2021 at 4:10 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote: >> >> On 11/4/2021 9:58 PM, Ajit Khaparde wrote: >>> Enhancements include: >>> * Scaling numbers on Thor >>> * Inner IP header support for GRE tunnel flows >>> * Enable wildcard match for ingress flows >>> * Add clear on read for flow stats on Thor >>> * Add nat support for dest IP and port combination >>> * Remove 2-slice WC support >>> * Add support for socket redirect feature >>> * Add new API TruFlow get SRAM resources >>> * Remove accumulation of stats devargs argument >>> * Add TruFlow and AFM SRAM partitioning support >>> >>> V2: >>> * Compilation fixes >>> * Remove 2-slice WC support >>> * Add support for socket redirect feature >>> * Add new API TruFlow get SRAM resources >>> * Remove accumulation of stats devargs argument >>> * Add TruFlow and AFM SRAM partitioning support >>> >>> V3: >>> * Added one more patch (use enum for bank ID) >>> >>> V4: >>> * Fixed typos in patch 2/20 >>> * Fix checkpatch warnings >>> * Updated commit logs >>> * Rebased the patches to latest dpdk-next-net >>> >>> V5: >>> * Split couple of patches into cleanup and code change patch >>> * Fixed typo in some patches >>> * Address review comments >>> * Rebased patches to latest dpdk-next-net >>> >>> Ajit Khaparde (2): >>> net/bnxt: remove unused functions >>> net/bnxt: enable wildcard match for ingress flows >>> >>> Farah Smith (1): >>> net/bnxt: add clear on read support >>> >>> Jay Ding (5): >>> net/bnxt: get TruFlow version >>> net/bnxt: add new TruFlow API to get SRAM resources >>> net/bnxt: add TruFlow and AFM SRAM partitioning support >>> net/bnxt: add Tx TruFlow table config for P4 device >>> net/bnxt: use enum for bank ID >>> >>> Kishore Padmanabha (11): >>> net/bnxt: add NAT support for dest IP and port combination >>> net/bnxt: add support for multi root capability >>> net/bnxt: fix out of bounds issue in hash list >>> net/bnxt: add capability option for socket redirect >>> net/bnxt: address ISO C90 compilation error >>> net/bnxt: support inner IP header for GRE tunnel flows >>> net/bnxt: remove devargs for stats accumulation >>> net/bnxt: update log messages in TruFlow path >>> net/bnxt: add support for socket direct feature >>> net/bnxt: modify VF representor alloc sequence >>> net/bnxt: check mismatch of control and physical port >>> >>> Mike Baucom (1): >>> net/bnxt: remove 2 slice wildcard entries >>> >>> Shahaji Bhosle (2): >>> net/bnxt: increase flow scale for Thor >>> net/bnxt: fix clang compiler warnings >>> >> >> Hi Ajit, >> >> It would be good to updated the release notes for the above changes, >> but -rc2 is a day away and I don't want to block the set for this. >> >> Can you please send the documentation update separately? >> If it comes before next-net merged, I can squash it. > Hi Ferruh, > Done. Please let me know if you can pick it straight from patchwork. > Otherwise I can merge in the subtree and you can pick from there. > Please let me know. > I guess I can do it, let me try. ^ permalink raw reply [flat|nested] 118+ messages in thread
* [dpdk-dev] [PATCH] doc: update for bnxt PMD 2021-11-05 11:10 ` Ferruh Yigit ` (2 preceding siblings ...) 2021-11-05 16:57 ` [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow Ajit Khaparde @ 2021-11-05 18:46 ` Ajit Khaparde 2021-11-17 3:59 ` Ajit Khaparde 3 siblings, 1 reply; 118+ messages in thread From: Ajit Khaparde @ 2021-11-05 18:46 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit [-- Attachment #1: Type: text/plain, Size: 771 bytes --] Updated support for RTE_FLOW_ACTION_TYPE_RSS. Fixes: 239695f754cb ("net/bnxt: enhance RSS action support") Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- doc/guides/rel_notes/release_21_11.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst index 58ae29efa4..9a085ac11e 100644 --- a/doc/guides/rel_notes/release_21_11.rst +++ b/doc/guides/rel_notes/release_21_11.rst @@ -159,6 +159,7 @@ New Features * Added TruFlow and AFM SRAM partitioning support. * Added wildcard match support for ingress flows. * Removed devargs for stats accumulation. + * Updated support for RTE_FLOW_ACTION_TYPE_RSS. * **Updated Cisco enic driver.** -- 2.30.1 (Apple Git-130) ^ permalink raw reply [flat|nested] 118+ messages in thread
* Re: [PATCH] doc: update for bnxt PMD 2021-11-05 18:46 ` [dpdk-dev] [PATCH] doc: update for bnxt PMD Ajit Khaparde @ 2021-11-17 3:59 ` Ajit Khaparde 0 siblings, 0 replies; 118+ messages in thread From: Ajit Khaparde @ 2021-11-17 3:59 UTC (permalink / raw) To: dpdk-dev; +Cc: Ferruh Yigit On Fri, Nov 5, 2021 at 11:46 AM Ajit Khaparde <ajit.khaparde@broadcom.com> wrote: > > Updated support for RTE_FLOW_ACTION_TYPE_RSS. > > Fixes: 239695f754cb ("net/bnxt: enhance RSS action support") > > Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Patch applied to dpdk-next-net-brcm. Thanks > --- > doc/guides/rel_notes/release_21_11.rst | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst > index 58ae29efa4..9a085ac11e 100644 > --- a/doc/guides/rel_notes/release_21_11.rst > +++ b/doc/guides/rel_notes/release_21_11.rst > @@ -159,6 +159,7 @@ New Features > * Added TruFlow and AFM SRAM partitioning support. > * Added wildcard match support for ingress flows. > * Removed devargs for stats accumulation. > + * Updated support for RTE_FLOW_ACTION_TYPE_RSS. > > * **Updated Cisco enic driver.** > > -- > 2.30.1 (Apple Git-130) > ^ permalink raw reply [flat|nested] 118+ messages in thread
end of thread, other threads:[~2021-11-17 3:59 UTC | newest] Thread overview: 118+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-10-01 5:59 [dpdk-dev] [PATCH 0/9] fixes and enhancements to Truflow Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 1/9] net/bnxt: add nat support for dest IP and port combination Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 2/9] net/bnxt: support multi root capability flag Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 3/9] net/bnxt: fix the out of boundary issue in hash list Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 4/9] net/bnxt: add clear on read stats support for Thor Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 5/9] net/bnxt: add feature capability option for socket direct Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 6/9] net/bnxt: enable wildcard match for ingress flows Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 7/9] net/bnxt: support inner IP header for GRE tunnel flows Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 8/9] net/bnxt: get Truflow version Venkat Duvvuru 2021-10-01 5:59 ` [dpdk-dev] [PATCH 9/9] net/bnxt: increase scaling numbers on Thor Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 01/19] net/bnxt: add NAT support for dest IP and port combination Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 02/19] net/bnxt: add support for multi root capability Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 03/19] net/bnxt: fix the out of boundary issue in hash list Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 04/19] net/bnxt: add clear on read support Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 05/19] net/bnxt: add capability option for socket redirect Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 06/19] net/bnxt: enable wildcard match for ingress flows Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 07/19] net/bnxt: support inner IP header for GRE tunnel flows Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 08/19] net/bnxt: get TruFlow version Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 09/19] net/bnxt: increase flow scale for Thor Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 10/19] net/bnxt: remove accumulation of stats devargs argument Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 11/19] net/bnxt: fix clang compiler warnings Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 12/19] net/bnxt: updated the log messages Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 13/19] net/bnxt: add support for socket redirect feature Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 14/19] net/bnxt: delete the VF pair before VF representor alloc Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 15/19] net/bnxt: add new API TruFlow get SRAM resources Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 16/19] net/bnxt: add TruFlow and AFM SRAM partitioning support Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 17/19] net/bnxt: add Tx TruFlow table config for p4 Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 18/19] net/bnxt: remove 2-slice WC entries for scale Venkat Duvvuru 2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 19/19] net/bnxt: check for mismatch of control and physical port Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 01/20] net/bnxt: add NAT support for dest IP and port combination Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 02/20] net/bnxt: add support for multi root capability Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 03/20] net/bnxt: fix the out of boundary issue in hash list Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 04/20] net/bnxt: add clear on read support Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 05/20] net/bnxt: add capability option for socket redirect Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 06/20] net/bnxt: enable wildcard match for ingress flows Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 07/20] net/bnxt: support inner IP header for GRE tunnel flows Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 08/20] net/bnxt: get TruFlow version Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 09/20] net/bnxt: increase flow scale for Thor Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 10/20] net/bnxt: remove accumulation of stats devargs argument Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 11/20] net/bnxt: fix clang compiler warnings Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 12/20] net/bnxt: updated the log messages Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 13/20] net/bnxt: add support for socket direct feature Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 14/20] net/bnxt: delete the VF pair before VF representor alloc Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 15/20] net/bnxt: add new API TruFlow get SRAM resources Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 16/20] net/bnxt: add TruFlow and AFM SRAM partitioning support Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 17/20] net/bnxt: add Tx TruFlow table config for p4 device Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 18/20] net/bnxt: remove 2-slice WC entries for scale Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 19/20] net/bnxt: check for mismatch of control and physical port Venkat Duvvuru 2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 20/20] net/bnxt: use enum for bank ID Venkat Duvvuru 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 01/20] net/bnxt: add NAT support for dest IP and port combination Ajit Khaparde 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 02/20] net/bnxt: add support for multi root capability Ajit Khaparde 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 03/20] net/bnxt: fix out of bounds issue in hash list Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 04/20] net/bnxt: add clear on read support Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 05/20] net/bnxt: add capability option for socket redirect Ajit Khaparde 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 06/20] net/bnxt: enable wildcard match for ingress flows Ajit Khaparde 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 07/20] net/bnxt: support inner IP header for GRE tunnel flows Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 08/20] net/bnxt: get TruFlow version Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 09/20] net/bnxt: increase flow scale for Thor Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 10/20] net/bnxt: remove devargs for stats accumulation Ajit Khaparde 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 13:35 ` Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 11/20] net/bnxt: fix clang compiler warnings Ajit Khaparde 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 12/20] net/bnxt: update log messages in TruFlow path Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 13/20] net/bnxt: add support for socket direct feature Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 14/20] net/bnxt: modify VF representor alloc sequence Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 15/20] net/bnxt: add new TruFlow API to get SRAM resources Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 16/20] net/bnxt: add TruFlow and AFM SRAM partitioning support Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 17/20] net/bnxt: add Tx TruFlow table config for P4 device Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 18/20] net/bnxt: remove 2 slice WC entries Ajit Khaparde 2021-11-03 13:24 ` Ferruh Yigit 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 19/20] net/bnxt: check mismatch of control and physical port Ajit Khaparde 2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 20/20] net/bnxt: use enum for bank ID Ajit Khaparde 2021-11-03 3:40 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 01/22] net/bnxt: add NAT support for dest IP and port combination Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 02/22] net/bnxt: add support for multi root capability Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 03/22] net/bnxt: fix out of bounds issue in hash list Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 04/22] net/bnxt: add clear on read support Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 05/22] net/bnxt: add capability option for socket redirect Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 06/22] net/bnxt: remove unused functions Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 07/22] net/bnxt: address ISO C90 compilation error Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 08/22] net/bnxt: enable wildcard match for ingress flows Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 09/22] net/bnxt: support inner IP header for GRE tunnel flows Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 10/22] net/bnxt: get TruFlow version Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 11/22] net/bnxt: increase flow scale for Thor Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 12/22] net/bnxt: remove devargs for stats accumulation Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 13/22] net/bnxt: fix clang compiler warnings Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 14/22] net/bnxt: update log messages in TruFlow path Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 15/22] net/bnxt: add support for socket direct feature Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 16/22] net/bnxt: modify VF representor alloc sequence Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 17/22] net/bnxt: add new TruFlow API to get SRAM resources Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 18/22] net/bnxt: add TruFlow and AFM SRAM partitioning support Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 19/22] net/bnxt: add Tx TruFlow table config for P4 device Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 20/22] net/bnxt: remove 2 slice wildcard entries Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 21/22] net/bnxt: check mismatch of control and physical port Ajit Khaparde 2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 22/22] net/bnxt: use enum for bank ID Ajit Khaparde 2021-11-05 0:57 ` [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow Ajit Khaparde 2021-11-05 11:10 ` Ferruh Yigit 2021-11-05 11:30 ` Thomas Monjalon 2021-11-05 16:55 ` [dpdk-dev] [PATCH] doc: update release notes for bnxt PMD Ajit Khaparde 2021-11-05 18:14 ` Ferruh Yigit 2021-11-05 18:22 ` Ajit Khaparde 2021-11-05 18:38 ` Ferruh Yigit 2021-11-05 18:41 ` Ajit Khaparde 2021-11-05 18:42 ` Ferruh Yigit 2021-11-05 18:48 ` Ajit Khaparde 2021-11-05 16:57 ` [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow Ajit Khaparde 2021-11-05 17:20 ` Ferruh Yigit 2021-11-05 18:46 ` [dpdk-dev] [PATCH] doc: update for bnxt PMD Ajit Khaparde 2021-11-17 3:59 ` Ajit Khaparde
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