From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A5D72A0C4E; Tue, 2 Nov 2021 16:54:45 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 63EE7411ED; Tue, 2 Nov 2021 16:54:35 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 70015411CB for ; Tue, 2 Nov 2021 16:54:34 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A2CjgHS030466 for ; Tue, 2 Nov 2021 08:54:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=8PZbupBtoRf8HZhIBQJcFzXi9dmbWMcdfjbZguFy5YE=; b=EqjXj3TNObN8W6DMdYvhj0wtpquKjW1ta1hzqHIH32OIQXYPpcaqgf0hVT4xMP3X2Ojb u+XcJuaWuZjt+TF/SYeL6xfbfgu1ngt27CQ4vJFleWzmH3rIaIq0xEG/ggk0fssDTMcD Gck8052dHsXks9GcZqEmvuyAmLlDhTE160t4IfPUcAsgnHJ0juE+RFvG83r+4E1rr/1E j5+9VMBqPwySUh6LH+AHYXQxl9TgKNxVPgb+t/quygrEFu+ocomrS1WkEArmLZjbR9Qs Sknc1iiHZlGMgvoi8NTTNn85vBERkNIOE2CNN8y4tXVPcXdF8jtKb+2hlJg5ZWdEP3rk bA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3c35mbh5n1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 02 Nov 2021 08:54:33 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 2 Nov 2021 08:54:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 2 Nov 2021 08:54:31 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 39A3B5B6952; Tue, 2 Nov 2021 08:54:29 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Date: Tue, 2 Nov 2021 21:24:14 +0530 Message-ID: <20211102155421.486-3-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211102155421.486-1-ndabilpuram@marvell.com> References: <20211102155421.486-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: kwz2FBIJ5faJgASkREvXS0D8IFehbVdu X-Proofpoint-ORIG-GUID: kwz2FBIJ5faJgASkREvXS0D8IFehbVdu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-02_08,2021-11-02_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 3/9] common/cnxk: support flow control on LBK X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Support flow control enable/disable on LBK VF's as HW supports backpressure on LBK links. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix.c | 6 ++++++ drivers/common/cnxk/roc_nix_fc.c | 27 ++++++++++++++++++++------- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 949be80..fbfc550 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -414,6 +414,12 @@ roc_nix_dev_init(struct roc_nix *roc_nix) nix->reta_sz = reta_sz; nix->mtu = ROC_NIX_DEFAULT_HW_FRS; + /* Always start with full FC for LBK */ + if (nix->lbk_link) { + nix->rx_pause = 1; + nix->tx_pause = 1; + } + /* Register error and ras interrupts */ rc = nix_register_irqs(nix); if (rc) diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index 7eac7d0..ef46842 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -157,7 +157,7 @@ nix_fc_cq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) int roc_nix_fc_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) { - if (roc_nix_is_vf_or_sdp(roc_nix)) + if (roc_nix_is_vf_or_sdp(roc_nix) && !roc_nix_is_lbk(roc_nix)) return 0; if (fc_cfg->cq_cfg_valid) @@ -169,7 +169,7 @@ roc_nix_fc_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) int roc_nix_fc_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) { - if (roc_nix_is_vf_or_sdp(roc_nix)) + if (roc_nix_is_vf_or_sdp(roc_nix) && !roc_nix_is_lbk(roc_nix)) return 0; if (fc_cfg->cq_cfg_valid) @@ -188,8 +188,17 @@ roc_nix_fc_mode_get(struct roc_nix *roc_nix) enum roc_nix_fc_mode mode; int rc = -ENOSPC; - if (roc_nix_is_lbk(roc_nix)) - return ROC_NIX_FC_NONE; + /* Flow control on LBK link is always available */ + if (roc_nix_is_lbk(roc_nix)) { + if (nix->tx_pause && nix->rx_pause) + return ROC_NIX_FC_FULL; + else if (nix->rx_pause) + return ROC_NIX_FC_RX; + else if (nix->tx_pause) + return ROC_NIX_FC_TX; + else + return ROC_NIX_FC_NONE; + } req = mbox_alloc_msg_cgx_cfg_pause_frm(mbox); if (req == NULL) @@ -226,12 +235,16 @@ roc_nix_fc_mode_set(struct roc_nix *roc_nix, enum roc_nix_fc_mode mode) uint8_t tx_pause, rx_pause; int rc = -ENOSPC; - if (roc_nix_is_lbk(roc_nix)) - return NIX_ERR_OP_NOTSUP; - rx_pause = (mode == ROC_NIX_FC_FULL) || (mode == ROC_NIX_FC_RX); tx_pause = (mode == ROC_NIX_FC_FULL) || (mode == ROC_NIX_FC_TX); + /* Nothing much to do for LBK links */ + if (roc_nix_is_lbk(roc_nix)) { + nix->rx_pause = rx_pause; + nix->tx_pause = tx_pause; + return 0; + } + req = mbox_alloc_msg_cgx_cfg_pause_frm(mbox); if (req == NULL) return rc; -- 2.8.4