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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT054.mail.protection.outlook.com (10.13.174.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Wed, 3 Nov 2021 07:59:44 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 3 Nov 2021 07:59:39 +0000 From: Xueming Li To: CC: , Lior Margalit , , , Matan Azrad , Viacheslav Ovsiienko Date: Wed, 3 Nov 2021 15:58:29 +0800 Message-ID: <20211103075838.1486056-6-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211103075838.1486056-1-xuemingl@nvidia.com> References: <20210727034204.20649-1-xuemingl@nvidia.com> <20211103075838.1486056-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 11f2da48-b4c7-41e8-5d3b-08d99e9fe601 X-MS-TrafficTypeDiagnostic: BN7PR12MB2609: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:660; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(82310400003)(70586007)(450100002)(7696005)(36860700001)(70206006)(6286002)(508600001)(6916009)(86362001)(26005)(107886003)(2616005)(426003)(336012)(55016002)(8936002)(186003)(16526019)(83380400001)(47076005)(1076003)(36756003)(54906003)(316002)(4326008)(2906002)(356005)(5660300002)(7636003)(6666004)(8676002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2021 07:59:44.4394 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 11f2da48-b4c7-41e8-5d3b-08d99e9fe601 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR12MB2609 Subject: [dpdk-dev] [PATCH v3 05/14] net/mlx5: fix Rx queue memory allocation return value X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" If error happened during Rx queue mbuf allocation, boolean value returned. From description, return value should be error number. This patch returns negative error number. Fixes: 0f20acbf5eda ("net/mlx5: implement vectorized MPRQ burst") Cc: akozyrev@nvidia.com Cc: stable@dpdk.org Signed-off-by: Xueming Li --- drivers/net/mlx5/mlx5_rxq.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 9220bb2c15c..4567b43c1b6 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -129,7 +129,7 @@ rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl) * Pointer to RX queue structure. * * @return - * 0 on success, errno value on failure. + * 0 on success, negative errno value on failure. */ static int rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl) @@ -220,7 +220,7 @@ rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl) * Pointer to RX queue structure. * * @return - * 0 on success, errno value on failure. + * 0 on success, negative errno value on failure. */ int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl) @@ -233,7 +233,9 @@ rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl) */ if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq)) ret = rxq_alloc_elts_mprq(rxq_ctrl); - return (ret || rxq_alloc_elts_sprq(rxq_ctrl)); + if (ret == 0) + ret = rxq_alloc_elts_sprq(rxq_ctrl); + return ret; } /** -- 2.33.0