From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A7477A0C53; Wed, 3 Nov 2021 08:59:46 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 90D1B4114B; Wed, 3 Nov 2021 08:59:39 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 31D3C40E5A for ; Wed, 3 Nov 2021 08:59:38 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A35LRFX012160 for ; Wed, 3 Nov 2021 00:59:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=N19U1miPo4kqWCiMnVECz2CqcnLvqMOlPxKOyqkifv8=; b=Xwhu8JYhp9GDR7caIlhqRXMWS7o4yce9ff+3YvTQftUrPfd2lCCojR3yvv4WheqnD1E9 owPlUnDg8cC9xgfE9f8J5T+w3w/Sql6TaSB0E4eLZv/SuKAlwsL4KIQyTm85MlXR6/vX uDu7EDWzhBPguyMbJk6+I0aOdCWmCBm5VDyLPSlCgbBSXTpYV/oRfwh5qaK2GkD3RHJT /H1kj3Y0230VUr/nrtrrkLeBAkxE1N6tYIyP2IUU8xXyYMyKZN4IQbCzyIP1wuTZXZtl NNbJt4ofKIukzaa37dl+X7xhUZqdJwAzk8QQ2nQj1FnXITY0UxOY/qbHfBU2nb5G5stv jQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3c3dd8a92q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 03 Nov 2021 00:59:37 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 3 Nov 2021 00:59:35 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 3 Nov 2021 00:59:35 -0700 Received: from localhost.marvell.com (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id A16FB3F7048; Wed, 3 Nov 2021 00:59:33 -0700 (PDT) From: Harman Kalra To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Harman Kalra Date: Wed, 3 Nov 2021 13:29:14 +0530 Message-ID: <20211103075915.109838-1-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211101174407.81854-1-hkalra@marvell.com> References: <20211101174407.81854-1-hkalra@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: vErSI4sNGB1SeVJzZgM2Em5dlgK4ZuSj X-Proofpoint-GUID: vErSI4sNGB1SeVJzZgM2Em5dlgK4ZuSj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-03_02,2021-11-02_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2] common/cnxk: fix device MSIX greater than default value X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Handling the case where number of MSIX interrupts are greater than default value i.e. PLT_MAX_RXTX_INTR_VEC_ID. On PCI probe device is queried for supported MSIX interrupts, and respective interrupt resources are reallocated with this value. Same MSIX count should be used while registering new interrupt vectors. Fixes: 8cb5d08db940 ("interrupts: extend event list") Signed-off-by: Harman Kalra --- V2: * Corrected fixes commit which actually introduced this issue. drivers/common/cnxk/roc_irq.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/common/cnxk/roc_irq.c b/drivers/common/cnxk/roc_irq.c index 3b34467b96..7a24297d72 100644 --- a/drivers/common/cnxk/roc_irq.c +++ b/drivers/common/cnxk/roc_irq.c @@ -14,7 +14,8 @@ #include #define MSIX_IRQ_SET_BUF_LEN \ - (sizeof(struct vfio_irq_set) + sizeof(int) * (PLT_MAX_RXTX_INTR_VEC_ID)) + (sizeof(struct vfio_irq_set) + sizeof(int) * \ + (plt_intr_max_intr_get(intr_handle))) static int irq_get_info(struct plt_intr_handle *intr_handle) @@ -34,7 +35,7 @@ irq_get_info(struct plt_intr_handle *intr_handle) plt_base_dbg("Flags=0x%x index=0x%x count=0x%x max_intr_vec_id=0x%x", irq.flags, irq.index, irq.count, PLT_MAX_RXTX_INTR_VEC_ID); - if (irq.count > PLT_MAX_RXTX_INTR_VEC_ID) { + if (irq.count == 0) { plt_err("HW max=%d > PLT_MAX_RXTX_INTR_VEC_ID: %d", irq.count, PLT_MAX_RXTX_INTR_VEC_ID); plt_intr_max_intr_set(intr_handle, PLT_MAX_RXTX_INTR_VEC_ID); @@ -92,14 +93,6 @@ irq_init(struct plt_intr_handle *intr_handle) int32_t *fd_ptr; uint32_t i; - if (plt_intr_max_intr_get(intr_handle) > - PLT_MAX_RXTX_INTR_VEC_ID) { - plt_err("Max_intr=%d greater than PLT_MAX_RXTX_INTR_VEC_ID=%d", - plt_intr_max_intr_get(intr_handle), - PLT_MAX_RXTX_INTR_VEC_ID); - return -ERANGE; - } - len = sizeof(struct vfio_irq_set) + sizeof(int32_t) * plt_intr_max_intr_get(intr_handle); -- 2.18.0