From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 93C22A0C53; Wed, 3 Nov 2021 12:22:35 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 815CE41203; Wed, 3 Nov 2021 12:22:35 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E7E0D41203 for ; Wed, 3 Nov 2021 12:22:33 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A3BDl74012582; Wed, 3 Nov 2021 04:22:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=9mb4ALlNYfchvy9JmYrat2Dmpgy2uvTBiHHUtUttWnQ=; b=WqA3HCHlqSRE0rr6FnDD68HXma7iU815VBweHX8PZ6EUS2YB7ek3xO64pzDIzYEWlOu8 8AgzrHJ0RmwCpHJaisp1/4T/f/uKynkK08O7wtyuqJYVs4l4MG/LXCjtUUoXpI4suENi EfNc5yWiWd7oHs1IezjYtx09Sq1ZvbtH8mCfFk4F7njfzz0UKzF7M1CB967hdzJCCz49 CWUPic7npzBxoNPiF7sJeY/plB+3MZlA45hRsy9iGqeKkl4JRgicz8QyujY87+34MEG6 Tf9R71yTJSZb7TeUG8TCa6GrSKKCFLUs5bLytHODDAkjYUywJN9OKnDx8uF0oc9CqdQ6 Lw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3c3dd8b4wx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 03 Nov 2021 04:22:33 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 3 Nov 2021 04:22:31 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 3 Nov 2021 04:22:30 -0700 Received: from vvelumuri_asim.marvell.com (unknown [10.29.53.48]) by maili.marvell.com (Postfix) with ESMTP id CC7583F7041; Wed, 3 Nov 2021 04:22:28 -0700 (PDT) From: Vidya Sagar Velumuri To: , , , , , CC: , Date: Wed, 3 Nov 2021 11:22:10 +0000 Message-ID: <20211103112210.32650-2-vvelumuri@marvell.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211103112210.32650-1-vvelumuri@marvell.com> References: <20211103112210.32650-1-vvelumuri@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: _ONHuDd02ZW-WvCehuZyCfhMgClzXdyV X-Proofpoint-GUID: _ONHuDd02ZW-WvCehuZyCfhMgClzXdyV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-03_03,2021-11-03_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v1 2/2] crypto/cnxk: fix: supported iv length for zuc 256 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Fix supported IV length for ZUC 256 Add support in capability for 4 byte mac len for zuc 256 Pack the last 8 bytes of IV to 6 bytes by ignoring the 2 msb bits of each byte. Fixes: 29742632ac9e ("crypto/cnxk: support ZUC with 256-bit key") Cc: vvelumuri@marvell.com Signed-off-by: Vidya Sagar Velumuri Change-Id: I00e103323a4018e26452717fa31238aec668ec25 diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c index a53b489a04..b94ff851a3 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c @@ -874,8 +874,8 @@ cn10k_crypto_caps_update(struct rte_cryptodev_capabilities cnxk_caps[]) caps->sym.cipher.key_size.max = 32; caps->sym.cipher.key_size.increment = 16; - caps->sym.cipher.iv_size.max = 24; - caps->sym.cipher.iv_size.increment = 8; + caps->sym.cipher.iv_size.max = 25; + caps->sym.cipher.iv_size.increment = 1; } if ((caps->op == RTE_CRYPTO_OP_TYPE_SYMMETRIC) && @@ -886,8 +886,8 @@ cn10k_crypto_caps_update(struct rte_cryptodev_capabilities cnxk_caps[]) caps->sym.auth.key_size.increment = 16; caps->sym.auth.digest_size.max = 16; caps->sym.auth.digest_size.increment = 4; - caps->sym.auth.iv_size.max = 24; - caps->sym.auth.iv_size.increment = 8; + caps->sym.auth.iv_size.max = 25; + caps->sym.auth.iv_size.increment = 1; } } } diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index 7959c4c7af..e4e554e8b7 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -37,7 +37,24 @@ struct cnxk_se_sess { } __rte_cache_aligned; static inline void -pdcp_iv_copy(uint8_t *iv_d, uint8_t *iv_s, const uint8_t pdcp_alg_type) +cpt_pack_iv(uint8_t *iv_src, uint8_t *iv_dst) +{ + iv_dst[16] = iv_src[16]; + /* pack the last 8 bytes of IV to 6 bytes. + * discard the 2 MSB bits of each byte + */ + iv_dst[17] = (((iv_src[17] & 0x3f) << 2) | ((iv_src[18] >> 4) & 0x3)); + iv_dst[18] = (((iv_src[18] & 0xf) << 4) | ((iv_src[19] >> 2) & 0xf)); + iv_dst[19] = (((iv_src[19] & 0x3) << 6) | (iv_src[20] & 0x3f)); + + iv_dst[20] = (((iv_src[21] & 0x3f) << 2) | ((iv_src[22] >> 4) & 0x3)); + iv_dst[21] = (((iv_src[22] & 0xf) << 4) | ((iv_src[23] >> 2) & 0xf)); + iv_dst[22] = (((iv_src[23] & 0x3) << 6) | (iv_src[24] & 0x3f)); +} + +static inline void +pdcp_iv_copy(uint8_t *iv_d, uint8_t *iv_s, const uint8_t pdcp_alg_type, + uint8_t pack_iv) { uint32_t *iv_s_temp, iv_temp[4]; int j; @@ -56,6 +73,8 @@ pdcp_iv_copy(uint8_t *iv_d, uint8_t *iv_s, const uint8_t pdcp_alg_type) } else { /* ZUC doesn't need a swap */ memcpy(iv_d, iv_s, 16); + if (pack_iv) + cpt_pack_iv(iv_s, iv_d); } } @@ -984,6 +1003,7 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, uint64_t offset_ctrl; uint64_t *offset_vaddr; uint8_t *iv_s; + uint8_t pack_iv = 0; union cpt_inst_w4 cpt_inst_w4; se_ctx = params->ctx_buf.vaddr; @@ -999,6 +1019,11 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, iv_s = params->auth_iv_buf; iv_len = params->auth_iv_len; + if (iv_len == 25) { + iv_len -= 2; + pack_iv = 1; + } + /* * Microcode expects offsets in bytes * TODO: Rounding off @@ -1023,6 +1048,11 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, iv_s = params->iv_buf; iv_len = params->cipher_iv_len; + if (iv_len == 25) { + iv_len -= 2; + pack_iv = 1; + } + /* EEA3 or UEA2 */ /* * Microcode expects offsets in bytes @@ -1081,7 +1111,7 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN; uint8_t *iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN); - pdcp_iv_copy(iv_d, iv_s, pdcp_alg_type); + pdcp_iv_copy(iv_d, iv_s, pdcp_alg_type, pack_iv); *offset_vaddr = offset_ctrl; } else { @@ -1095,7 +1125,8 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, /* save space for iv */ offset_vaddr = m_vaddr; - m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + iv_len; + m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + + RTE_ALIGN_CEIL(iv_len, 8); cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE; @@ -1123,7 +1154,7 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, *offset_vaddr = offset_ctrl; iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN); - pdcp_iv_copy(iv_d, iv_s, pdcp_alg_type); + pdcp_iv_copy(iv_d, iv_s, pdcp_alg_type, pack_iv); /* input data */ size = inputlen - iv_len; -- 2.31.1