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intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT029.mail.protection.outlook.com (10.13.173.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Thu, 4 Nov 2021 12:35:24 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 4 Nov 2021 12:35:03 +0000 From: Xueming Li To: CC: Viacheslav Ovsiienko , , "Lior Margalit" , Matan Azrad , "David Christensen" , Ruifeng Wang , Bruce Richardson , Konstantin Ananyev Date: Thu, 4 Nov 2021 20:33:20 +0800 Message-ID: <20211104123320.1638915-15-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211104123320.1638915-1-xuemingl@nvidia.com> References: <20210727034204.20649-1-xuemingl@nvidia.com> <20211104123320.1638915-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1928e47d-8db3-4d6b-80da-08d99f8f9329 X-MS-TrafficTypeDiagnostic: DM6PR12MB3545: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:312; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(336012)(4326008)(2906002)(36860700001)(86362001)(8936002)(8676002)(5660300002)(83380400001)(186003)(16526019)(426003)(82310400003)(2616005)(508600001)(36756003)(54906003)(47076005)(316002)(70586007)(1076003)(70206006)(7696005)(6286002)(6916009)(55016002)(26005)(7636003)(356005)(6666004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 12:35:24.6187 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1928e47d-8db3-4d6b-80da-08d99f8f9329 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3545 Subject: [dpdk-dev] [PATCH v4 14/14] net/mlx5: add shared Rx queue port datapath support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Viacheslav Ovsiienko When receive packet, mlx5 PMD saves mbuf port number from RxQ data. To support shared RxQ, save port number into RQ context as user index. Received packet resolve port number from CQE user index which derived from RQ context. Legacy Verbs API doesn't support RQ user index setting, still read from RxQ port number. Signed-off-by: Xueming Li Signed-off-by: Viacheslav Ovsiienko Acked-by: Slava Ovsiienko --- drivers/net/mlx5/mlx5_devx.c | 1 + drivers/net/mlx5/mlx5_rx.c | 1 + drivers/net/mlx5/mlx5_rxq.c | 3 ++- drivers/net/mlx5/mlx5_rxtx_vec_altivec.h | 6 ++++++ drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 12 +++++++++++- drivers/net/mlx5/mlx5_rxtx_vec_sse.h | 8 +++++++- 6 files changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index d3d189ab7f2..a9f9f4af700 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -277,6 +277,7 @@ mlx5_rxq_create_devx_rq_resources(struct mlx5_rxq_priv *rxq) MLX5_WQ_END_PAD_MODE_NONE; rq_attr.wq_attr.pd = cdev->pdn; rq_attr.counter_set_id = priv->counter_set_id; + rq_attr.user_index = rte_cpu_to_be_16(priv->dev_data->port_id); if (rxq_data->shared) /* Create RMP based RQ. */ rxq->devx_rq.rmp = &rxq_ctrl->obj->devx_rmp; /* Create RQ using DevX API. */ diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c index 1ffa1b95b88..4d85f64accd 100644 --- a/drivers/net/mlx5/mlx5_rx.c +++ b/drivers/net/mlx5/mlx5_rx.c @@ -709,6 +709,7 @@ rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt, { /* Update packet information. */ pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe, mcqe); + pkt->port = unlikely(rxq->shared) ? cqe->user_index_low : rxq->port_id; if (rxq->rss_hash) { uint32_t rss_hash_res = 0; diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 8feb3e2c0fb..4515d531835 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -186,7 +186,8 @@ rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl) mbuf_init->data_off = RTE_PKTMBUF_HEADROOM; rte_mbuf_refcnt_set(mbuf_init, 1); mbuf_init->nb_segs = 1; - mbuf_init->port = rxq->port_id; + /* For shared queues port is provided in CQE */ + mbuf_init->port = rxq->shared ? 0 : rxq->port_id; if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF) mbuf_init->ol_flags = RTE_MBUF_F_EXTERNAL; /* diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h index 1d00c1c43d1..423e229508c 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h +++ b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h @@ -1189,6 +1189,12 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, /* D.5 fill in mbuf - rearm_data and packet_type. */ rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]); + if (unlikely(rxq->shared)) { + pkts[pos]->port = cq[pos].user_index_low; + pkts[pos + p1]->port = cq[pos + p1].user_index_low; + pkts[pos + p2]->port = cq[pos + p2].user_index_low; + pkts[pos + p3]->port = cq[pos + p3].user_index_low; + } if (rxq->hw_timestamp) { int offset = rxq->timestamp_offset; if (rxq->rt_timestamp) { diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h index aa36df29a09..b1d16baa619 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h +++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h @@ -787,7 +787,17 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, /* C.4 fill in mbuf - rearm_data and packet_type. */ rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag, opcode, &elts[pos]); - if (rxq->hw_timestamp) { + if (unlikely(rxq->shared)) { + elts[pos]->port = container_of(p0, struct mlx5_cqe, + pkt_info)->user_index_low; + elts[pos + 1]->port = container_of(p1, struct mlx5_cqe, + pkt_info)->user_index_low; + elts[pos + 2]->port = container_of(p2, struct mlx5_cqe, + pkt_info)->user_index_low; + elts[pos + 3]->port = container_of(p3, struct mlx5_cqe, + pkt_info)->user_index_low; + } + if (unlikely(rxq->hw_timestamp)) { int offset = rxq->timestamp_offset; if (rxq->rt_timestamp) { struct mlx5_dev_ctx_shared *sh = rxq->sh; diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h index b0fc29d7b9e..f3d838389e2 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h +++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h @@ -736,7 +736,13 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, *err |= _mm_cvtsi128_si64(opcode); /* D.5 fill in mbuf - rearm_data and packet_type. */ rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]); - if (rxq->hw_timestamp) { + if (unlikely(rxq->shared)) { + pkts[pos]->port = cq[pos].user_index_low; + pkts[pos + p1]->port = cq[pos + p1].user_index_low; + pkts[pos + p2]->port = cq[pos + p2].user_index_low; + pkts[pos + p3]->port = cq[pos + p3].user_index_low; + } + if (unlikely(rxq->hw_timestamp)) { int offset = rxq->timestamp_offset; if (rxq->rt_timestamp) { struct mlx5_dev_ctx_shared *sh = rxq->sh; -- 2.33.0