From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 00618A0C61; Fri, 5 Nov 2021 09:57:23 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D7E7840DDA; Fri, 5 Nov 2021 09:57:23 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 3458640689 for ; Fri, 5 Nov 2021 09:57:22 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A50SkhC026639; Fri, 5 Nov 2021 01:57:19 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=eHzWw/LJedDU+Oo6GQYv+6rWPe4FO4+dsTZq9Vv1jj0=; b=YhMkW7etzVRkEKw6Y2Ixx+cuax8jDbncPJEbLHbex2VfEkaIezJyS73rrNEjhgqyRliE 8mDbDz/dPrVRDksFMkDCfyq0rt3RM2hlTzPwLS8VAewP0iGs6QOW+yWMSCYeYocaVBDm ZvbzPiosUPU+eCP1vqJrfutWfQT+TJLPuWuI3oPEmA9QMdtC+B0GH7TGTqyJHYULdQ9k QWwdOZ9fV30mAhT4VymWcmjqtQcbQVdzkSN4o5IGkYLtepodWTAjnZCFacENKXmzYWic S4ZJRMjSIhY//OyrVVWkADtnMsYBJC8PHP0oil2RjG2C8qx/AV32giVuGDf9JHH1YF/L Iw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3c4t3gsrhy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 05 Nov 2021 01:57:18 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 5 Nov 2021 01:57:17 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 5 Nov 2021 01:57:17 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 1A8453F7043; Fri, 5 Nov 2021 01:57:14 -0700 (PDT) From: To: , , CC: , Pavan Nikhilesh Date: Fri, 5 Nov 2021 14:27:12 +0530 Message-ID: <20211105085712.3220-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211004100304.13602-1-pbhagavatula@marvell.com> References: <20211004100304.13602-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: 7pGlWK-bz7TKuuNPVQNane7PnWq2pcOO X-Proofpoint-GUID: 7pGlWK-bz7TKuuNPVQNane7PnWq2pcOO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-05_01,2021-11-03_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2] eal/arm: remove CASP constraints for GCC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh GCC now assigns even register pairs for CASP, the fix has also been backported to all stable releases of older GCC versions. Removing the manual register allocation allows GCC to inline the functions and pick optimal registers for performing CASP. Signed-off-by: Pavan Nikhilesh --- v2 Changes: - Remove unnecessary LSE_PREAMBLE for GCC (Ruifeng). lib/eal/arm/include/rte_atomic_64.h | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/lib/eal/arm/include/rte_atomic_64.h b/lib/eal/arm/include/rte_atomic_64.h index fa6f334c0d..6047911507 100644 --- a/lib/eal/arm/include/rte_atomic_64.h +++ b/lib/eal/arm/include/rte_atomic_64.h @@ -46,12 +46,8 @@ rte_atomic_thread_fence(int memorder) /*------------------------ 128 bit atomic operations -------------------------*/ #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS) -#if defined(RTE_CC_CLANG) -#define __LSE_PREAMBLE ".arch armv8-a+lse\n" -#else -#define __LSE_PREAMBLE "" -#endif +#if defined(RTE_CC_CLANG) #define __ATOMIC128_CAS_OP(cas_op_name, op_string) \ static __rte_noinline void \ cas_op_name(rte_int128_t *dst, rte_int128_t *old, rte_int128_t updated) \ @@ -65,7 +61,7 @@ cas_op_name(rte_int128_t *dst, rte_int128_t *old, rte_int128_t updated) \ register uint64_t x2 __asm("x2") = (uint64_t)updated.val[0]; \ register uint64_t x3 __asm("x3") = (uint64_t)updated.val[1]; \ asm volatile( \ - __LSE_PREAMBLE \ + ".arch armv8-a+lse\n" \ op_string " %[old0], %[old1], %[upd0], %[upd1], [%[dst]]" \ : [old0] "+r" (x0), \ [old1] "+r" (x1) \ @@ -76,13 +72,24 @@ cas_op_name(rte_int128_t *dst, rte_int128_t *old, rte_int128_t updated) \ old->val[0] = x0; \ old->val[1] = x1; \ } +#else +#define __ATOMIC128_CAS_OP(cas_op_name, op_string) \ +static __rte_always_inline void \ +cas_op_name(rte_int128_t *dst, rte_int128_t *old, rte_int128_t updated) \ +{ \ + asm volatile( \ + op_string " %[old], %H[old], %[upd], %H[upd], [%[dst]]" \ + : [old] "+r"(old->int128) \ + : [upd] "r"(updated.int128), [dst] "r"(dst) \ + : "memory"); \ +} +#endif __ATOMIC128_CAS_OP(__cas_128_relaxed, "casp") __ATOMIC128_CAS_OP(__cas_128_acquire, "caspa") __ATOMIC128_CAS_OP(__cas_128_release, "caspl") __ATOMIC128_CAS_OP(__cas_128_acq_rel, "caspal") -#undef __LSE_PREAMBLE #undef __ATOMIC128_CAS_OP #endif -- 2.17.1