From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
by inbox.dpdk.org (Postfix) with ESMTP id 5C140A0C61;
Fri, 5 Nov 2021 11:11:16 +0100 (CET)
Received: from [217.70.189.124] (localhost [127.0.0.1])
by mails.dpdk.org (Postfix) with ESMTP id 6CB0C41199;
Fri, 5 Nov 2021 11:11:12 +0100 (CET)
Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com
[67.231.148.174])
by mails.dpdk.org (Postfix) with ESMTP id E1A424118F
for <dev@dpdk.org>; Fri, 5 Nov 2021 11:11:10 +0100 (CET)
Received: from pps.filterd (m0045849.ppops.net [127.0.0.1])
by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A50PbOd014958;
Fri, 5 Nov 2021 03:11:06 -0700
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;
h=from : to : cc :
subject : date : message-id : in-reply-to : references : mime-version :
content-transfer-encoding : content-type; s=pfpt0220;
bh=SzDo/XeQ3s9Y3MCJ4lhh/CTIFMUOiYPEo7WAZxsqpSM=;
b=NCUd9ioMMlkoksrJfwObMnLUckg+8PmBN/W91fw3KoECwWUArpC35losVBKIGkSkKvnW
BZ8KiYS7qUIhz+bAa+ouUNLqBffx3icUtCSgc3KF1QH2kh1VptBelebeZpp8XawWY2pr
wP0TYmPb8cQgVysNm05DHC52rajEObjLVSOxCcXQLP481OkL8GnUyyWYhrm29eetYrWq
12c69Sc+So8Qpe4F3m2y1c4BvvRsZ4lwZmS9VA1VnwN4iv6pRvvclgaNJpss6kApaHW2
bwB9JPluS+5P40NEuFMHhIJOWBfFiFwBn8a8qOja612YY6PQAsXUL8RyQQzYI/5fd5rG fA==
Received: from dc5-exch02.marvell.com ([199.233.59.182])
by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3c4t2ft2f7-1
(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);
Fri, 05 Nov 2021 03:11:06 -0700
Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com
(10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;
Fri, 5 Nov 2021 03:11:04 -0700
Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com
(10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend
Transport; Fri, 5 Nov 2021 03:11:04 -0700
Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])
by maili.marvell.com (Postfix) with ESMTP id 12EBD5B692B;
Fri, 5 Nov 2021 03:11:01 -0700 (PDT)
From: <pbhagavatula@marvell.com>
To: <ruifeng.wang@arm.com>, <david.marchand@redhat.com>, <jerinj@marvell.com>,
Yipeng Wang <yipeng1.wang@intel.com>, Sameh Gobriel
<sameh.gobriel@intel.com>, Bruce Richardson <bruce.richardson@intel.com>,
Vladimir Medvedkin <vladimir.medvedkin@intel.com>
CC: <dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>
Date: Fri, 5 Nov 2021 15:40:54 +0530
Message-ID: <20211105101054.3422-2-pbhagavatula@marvell.com>
X-Mailer: git-send-email 2.17.1
In-Reply-To: <20211105101054.3422-1-pbhagavatula@marvell.com>
References: <20211004055255.12947-1-pbhagavatula@marvell.com>
<20211105101054.3422-1-pbhagavatula@marvell.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
X-Proofpoint-ORIG-GUID: i5otrHrMmqd-6i7ABaTkPJzow_IMgmnR
X-Proofpoint-GUID: i5otrHrMmqd-6i7ABaTkPJzow_IMgmnR
X-Proofpoint-Virus-Version: vendor=baseguard
engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475
definitions=2021-11-05_01,2021-11-03_01,2020-04-07_01
Subject: [dpdk-dev] [PATCH v5 2/2] hash: unify crc32 selection for x86 and
Arm
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>
From: Pavan Nikhilesh <pbhagavatula@marvell.com>
Merge crc32 hash calculation public API implementation for x86 and Arm.
Select the best available CRC32 algorithm when unsupported algorithm
on a given CPU architecture is requested by an application.
Previously, if an application directly includes `rte_crc_arm64.h`
without including `rte_hash_crc.h` it will fail to compile.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
.../{rte_crc_arm64.h => hash_crc_arm64.h} | 69 +-------
lib/hash/hash_crc_x86.h | 89 ++++++++++
lib/hash/meson.build | 1 -
lib/hash/rte_hash_crc.h | 154 +++++-------------
4 files changed, 143 insertions(+), 170 deletions(-)
rename lib/hash/{rte_crc_arm64.h => hash_crc_arm64.h} (65%)
diff --git a/lib/hash/rte_crc_arm64.h b/lib/hash/hash_crc_arm64.h
similarity index 65%
rename from lib/hash/rte_crc_arm64.h
rename to lib/hash/hash_crc_arm64.h
index b4628cfc09..172894335f 100644
--- a/lib/hash/rte_crc_arm64.h
+++ b/lib/hash/hash_crc_arm64.h
@@ -2,23 +2,8 @@
* Copyright(c) 2015 Cavium, Inc
*/
-#ifndef _RTE_CRC_ARM64_H_
-#define _RTE_CRC_ARM64_H_
-
-/**
- * @file
- *
- * RTE CRC arm64 Hash
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include <rte_cpuflags.h>
-#include <rte_branch_prediction.h>
-#include <rte_common.h>
+#ifndef _HASH_CRC_ARM64_H_
+#define _HASH_CRC_ARM64_H_
static inline uint32_t
crc32c_arm64_u8(uint8_t data, uint32_t init_val)
@@ -61,40 +46,8 @@ crc32c_arm64_u64(uint64_t data, uint32_t init_val)
}
/**
- * Allow or disallow use of arm64 SIMD instrinsics for CRC32 hash
- * calculation.
- *
- * @param alg
- * An OR of following flags:
- * - (CRC32_SW) Don't use arm64 crc intrinsics
- * - (CRC32_ARM64) Use ARMv8 CRC intrinsic if available
- *
- */
-static inline void
-rte_hash_crc_set_alg(uint8_t alg)
-{
- switch (alg) {
- case CRC32_ARM64:
- if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_CRC32))
- alg = CRC32_SW;
- /* fall-through */
- case CRC32_SW:
- crc32_alg = alg;
- /* fall-through */
- default:
- break;
- }
-}
-
-/* Setting the best available algorithm */
-RTE_INIT(rte_hash_crc_init_alg)
-{
- rte_hash_crc_set_alg(CRC32_ARM64);
-}
-
-/**
- * Use single crc32 instruction to perform a hash on a 1 byte value.
- * Fall back to software crc32 implementation in case arm64 crc intrinsics is
+ * Use single crc32 instruction to perform a hash on a byte value.
+ * Fall back to software crc32 implementation in case ARM CRC is
* not supported
*
* @param data
@@ -115,7 +68,7 @@ rte_hash_crc_1byte(uint8_t data, uint32_t init_val)
/**
* Use single crc32 instruction to perform a hash on a 2 bytes value.
- * Fall back to software crc32 implementation in case arm64 crc intrinsics is
+ * Fall back to software crc32 implementation in case ARM CRC is
* not supported
*
* @param data
@@ -136,7 +89,7 @@ rte_hash_crc_2byte(uint16_t data, uint32_t init_val)
/**
* Use single crc32 instruction to perform a hash on a 4 byte value.
- * Fall back to software crc32 implementation in case arm64 crc intrinsics is
+ * Fall back to software crc32 implementation in case ARM CRC is
* not supported
*
* @param data
@@ -157,7 +110,7 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
/**
* Use single crc32 instruction to perform a hash on a 8 byte value.
- * Fall back to software crc32 implementation in case arm64 crc intrinsics is
+ * Fall back to software crc32 implementation in case ARM CRC is
* not supported
*
* @param data
@@ -170,14 +123,10 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
static inline uint32_t
rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
{
- if (likely(crc32_alg == CRC32_ARM64))
+ if (likely(crc32_alg & CRC32_ARM64))
return crc32c_arm64_u64(data, init_val);
return crc32c_2words(data, init_val);
}
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _RTE_CRC_ARM64_H_ */
+#endif /* _HASH_CRC_ARM64_H_ */
diff --git a/lib/hash/hash_crc_x86.h b/lib/hash/hash_crc_x86.h
index b80a742afa..19eb3584e7 100644
--- a/lib/hash/hash_crc_x86.h
+++ b/lib/hash/hash_crc_x86.h
@@ -59,4 +59,93 @@ crc32c_sse42_u64(uint64_t data, uint64_t init_val)
return (uint32_t)init_val;
}
+/**
+ * Use single crc32 instruction to perform a hash on a byte value.
+ * Fall back to software crc32 implementation in case SSE4.2 is
+ * not supported
+ *
+ * @param data
+ * Data to perform hash on.
+ * @param init_val
+ * Value to initialise hash generator.
+ * @return
+ * 32bit calculated hash value.
+ */
+static inline uint32_t
+rte_hash_crc_1byte(uint8_t data, uint32_t init_val)
+{
+ if (likely(crc32_alg & CRC32_SSE42))
+ return crc32c_sse42_u8(data, init_val);
+
+ return crc32c_1byte(data, init_val);
+}
+
+/**
+ * Use single crc32 instruction to perform a hash on a 2 bytes value.
+ * Fall back to software crc32 implementation in case SSE4.2 is
+ * not supported
+ *
+ * @param data
+ * Data to perform hash on.
+ * @param init_val
+ * Value to initialise hash generator.
+ * @return
+ * 32bit calculated hash value.
+ */
+static inline uint32_t
+rte_hash_crc_2byte(uint16_t data, uint32_t init_val)
+{
+ if (likely(crc32_alg & CRC32_SSE42))
+ return crc32c_sse42_u16(data, init_val);
+
+ return crc32c_2bytes(data, init_val);
+}
+
+/**
+ * Use single crc32 instruction to perform a hash on a 4 byte value.
+ * Fall back to software crc32 implementation in case SSE4.2 is
+ * not supported
+ *
+ * @param data
+ * Data to perform hash on.
+ * @param init_val
+ * Value to initialise hash generator.
+ * @return
+ * 32bit calculated hash value.
+ */
+static inline uint32_t
+rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
+{
+ if (likely(crc32_alg & CRC32_SSE42))
+ return crc32c_sse42_u32(data, init_val);
+
+ return crc32c_1word(data, init_val);
+}
+
+/**
+ * Use single crc32 instruction to perform a hash on a 8 byte value.
+ * Fall back to software crc32 implementation in case SSE4.2 is
+ * not supported
+ *
+ * @param data
+ * Data to perform hash on.
+ * @param init_val
+ * Value to initialise hash generator.
+ * @return
+ * 32bit calculated hash value.
+ */
+static inline uint32_t
+rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
+{
+#ifdef RTE_ARCH_X86_64
+ if (likely(crc32_alg == CRC32_SSE42_x64))
+ return crc32c_sse42_u64(data, init_val);
+#endif
+
+ if (likely(crc32_alg & CRC32_SSE42))
+ return crc32c_sse42_u64_mimic(data, init_val);
+
+ return crc32c_2words(data, init_val);
+}
+
#endif
diff --git a/lib/hash/meson.build b/lib/hash/meson.build
index 12b1afc1c6..2281516754 100644
--- a/lib/hash/meson.build
+++ b/lib/hash/meson.build
@@ -10,7 +10,6 @@ headers = files(
'rte_thash_gfni.h',
)
indirect_headers += files(
- 'rte_crc_arm64.h',
'rte_thash_x86_gfni.h',
)
diff --git a/lib/hash/rte_hash_crc.h b/lib/hash/rte_hash_crc.h
index 1cc8f84fe2..ea5ef302b8 100644
--- a/lib/hash/rte_hash_crc.h
+++ b/lib/hash/rte_hash_crc.h
@@ -16,10 +16,12 @@ extern "C" {
#endif
#include <stdint.h>
-#include <rte_config.h>
-#include <rte_cpuflags.h>
+
#include <rte_branch_prediction.h>
#include <rte_common.h>
+#include <rte_config.h>
+#include <rte_cpuflags.h>
+#include <rte_log.h>
#include <hash_crc_sw.h>
@@ -32,137 +34,71 @@ extern "C" {
static uint8_t crc32_alg = CRC32_SW;
#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
-#include "rte_crc_arm64.h"
-#else
+#include "hash_crc_arm64.h"
+#elif defined(RTE_ARCH_X86)
#include "hash_crc_x86.h"
+#endif
/**
- * Allow or disallow use of SSE4.2 instrinsics for CRC32 hash
+ * Allow or disallow use of SSE4.2/ARMv8 intrinsics for CRC32 hash
* calculation.
*
* @param alg
* An OR of following flags:
- * - (CRC32_SW) Don't use SSE4.2 intrinsics
+ * - (CRC32_SW) Don't use SSE4.2/ARMv8 intrinsics (default non-[x86/ARMv8])
* - (CRC32_SSE42) Use SSE4.2 intrinsics if available
- * - (CRC32_SSE42_x64) Use 64-bit SSE4.2 intrinsic if available (default)
+ * - (CRC32_SSE42_x64) Use 64-bit SSE4.2 intrinsic if available (default x86)
+ * - (CRC32_ARM64) Use ARMv8 CRC intrinsic if available (default ARMv8)
*
*/
static inline void
rte_hash_crc_set_alg(uint8_t alg)
{
-#if defined(RTE_ARCH_X86)
- if (alg == CRC32_SSE42_x64 &&
- !rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T))
- alg = CRC32_SSE42;
-#endif
- crc32_alg = alg;
-}
-
-/* Setting the best available algorithm */
-RTE_INIT(rte_hash_crc_init_alg)
-{
- rte_hash_crc_set_alg(CRC32_SSE42_x64);
-}
-
-/**
- * Use single crc32 instruction to perform a hash on a byte value.
- * Fall back to software crc32 implementation in case SSE4.2 is
- * not supported
- *
- * @param data
- * Data to perform hash on.
- * @param init_val
- * Value to initialise hash generator.
- * @return
- * 32bit calculated hash value.
- */
-static inline uint32_t
-rte_hash_crc_1byte(uint8_t data, uint32_t init_val)
-{
+ switch (alg) {
+ case CRC32_SSE42_x64:
+ case CRC32_SSE42:
#if defined RTE_ARCH_X86
- if (likely(crc32_alg & CRC32_SSE42))
- return crc32c_sse42_u8(data, init_val);
+ if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T))
+ crc32_alg = CRC32_SSE42;
+ else
+ crc32_alg = alg;
#endif
-
- return crc32c_1byte(data, init_val);
-}
-
-/**
- * Use single crc32 instruction to perform a hash on a 2 bytes value.
- * Fall back to software crc32 implementation in case SSE4.2 is
- * not supported
- *
- * @param data
- * Data to perform hash on.
- * @param init_val
- * Value to initialise hash generator.
- * @return
- * 32bit calculated hash value.
- */
-static inline uint32_t
-rte_hash_crc_2byte(uint16_t data, uint32_t init_val)
-{
-#if defined RTE_ARCH_X86
- if (likely(crc32_alg & CRC32_SSE42))
- return crc32c_sse42_u16(data, init_val);
+#if defined RTE_ARCH_ARM64
+ RTE_LOG(WARNING, HASH,
+ "Incorrect CRC32 algorithm requested setting best available algorithm on the architecture\n");
+ rte_hash_crc_set_alg(CRC32_ARM64);
+#endif
+ break;
+ case CRC32_ARM64:
+#if defined RTE_ARCH_ARM64
+ if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_CRC32))
+ crc32_alg = CRC32_ARM64;
#endif
-
- return crc32c_2bytes(data, init_val);
-}
-
-/**
- * Use single crc32 instruction to perform a hash on a 4 byte value.
- * Fall back to software crc32 implementation in case SSE4.2 is
- * not supported
- *
- * @param data
- * Data to perform hash on.
- * @param init_val
- * Value to initialise hash generator.
- * @return
- * 32bit calculated hash value.
- */
-static inline uint32_t
-rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
-{
#if defined RTE_ARCH_X86
- if (likely(crc32_alg & CRC32_SSE42))
- return crc32c_sse42_u32(data, init_val);
+ RTE_LOG(WARNING, HASH,
+ "Incorrect CRC32 algorithm requested setting best available algorithm on the architecture\n");
+ rte_hash_crc_set_alg(CRC32_SSE42_x64);
#endif
-
- return crc32c_1word(data, init_val);
+ break;
+ case CRC32_SW:
+ default:
+ crc32_alg = CRC32_SW;
+ break;
+ }
}
-/**
- * Use single crc32 instruction to perform a hash on a 8 byte value.
- * Fall back to software crc32 implementation in case SSE4.2 is
- * not supported
- *
- * @param data
- * Data to perform hash on.
- * @param init_val
- * Value to initialise hash generator.
- * @return
- * 32bit calculated hash value.
- */
-static inline uint32_t
-rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
+/* Setting the best available algorithm */
+RTE_INIT(rte_hash_crc_init_alg)
{
-#ifdef RTE_ARCH_X86_64
- if (likely(crc32_alg == CRC32_SSE42_x64))
- return crc32c_sse42_u64(data, init_val);
-#endif
-
-#if defined RTE_ARCH_X86
- if (likely(crc32_alg & CRC32_SSE42))
- return crc32c_sse42_u64_mimic(data, init_val);
+#if defined(RTE_ARCH_X86)
+ rte_hash_crc_set_alg(CRC32_SSE42_x64);
+#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
+ rte_hash_crc_set_alg(CRC32_ARM64);
+#else
+ rte_hash_crc_set_alg(CRC32_SW);
#endif
-
- return crc32c_2words(data, init_val);
}
-#endif
-
/**
* Calculate CRC32 hash on user-supplied byte array.
*
--
2.17.1