From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E6873A0C4D; Mon, 8 Nov 2021 13:34:26 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1F5C741137; Mon, 8 Nov 2021 13:34:24 +0100 (CET) Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2042.outbound.protection.outlook.com [40.107.243.42]) by mails.dpdk.org (Postfix) with ESMTP id 592A541134; Mon, 8 Nov 2021 13:34:22 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lnd6wGQquT3FKT7X5jauOvxY9yisnD2eBnTgUP+FsGAgpkxqlAwDHq1t1FG1erEwd08CmYdTSrvcTWTmaH/LFsW0llO/5f4IbM5PxmCBUIcS4uGiv+TVHHzPzbiSNH/R4vm9R4ZaHNETVjaW1QfjwpihYDG1o506LexSJgVbvZzy0F1bZ5DHW2kCqqrRTvS2ZDZoJl8pSa+2C9GhjZzzismsYMRyMOirxkcLXtCnmH+Wk1OhJGdSzsHjGlYPHys7lkP0EYBovm9NqObkei+dxosYEggc4G4tZ61hImA7jOVl+rHg9hZj4NXzekJvyuQx4YSthC+LQhIh2/TXbXpQmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0GNYQmU9m+1XJe9jz7M8ChAo21Cw6UfHnflMol3JnLI=; b=ldjmSRXoPxVZBCUdZ6tc/64wSD2KjhEay0UTdmfT4kzfT/2j2Z462bnnSqFg+Kns4UAFsp1+lPhS8MJrjjQYYhQO5r7uuIV3dO7zZuQNvcanfAl+StilHFoseA221fQpm5XbUHOyfn/OZcPusJVGip8B5a3mjS0C0NUgTwi1OyiHZ4TWU9W+VDlPSgp+DTjebgRpO4iVQkLPyGUjnW8AetipDdgf+QIyT7oB54783vVVIL4bNTMQCxb1M0RtdBFHJAM07zBCz3nG+STx2ukIshSozFIdCNznF1dx9fJvYEYJDxuylj6NxhFULB5wMG79T5a8dYYodszmFsaYikPkww== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0GNYQmU9m+1XJe9jz7M8ChAo21Cw6UfHnflMol3JnLI=; b=NMbIfcx93ybXPWMsfOm6SpGobZ+iMBLyQCiHVLJ0TtrP7ZuegNxOmAqW0BaGRe1UE8Qe0H2JIn5UUjcxQ+YJOu1yeVxtVgwSmYQgKU06MJjqHcN1XI0UPjAhCkAnpEd1V7FHjvJzoSHkepqpLAhUDNlXeQIRVy70a8aTUOgWKnXjznCuPOVBzEmOEYp2De7UT5qZ+fyLtHgNp0GyEU4TYwY/bEAJwYtzKRPHF3hs4Aq3yHIbFQvQHzP54HOONBu0ybdwJZyTw5LeoIstjW1Zj1id3W+3trwgUQ234nO5OsWFTpQOeelXAfVVC1qGKGdomLa3T912VA6aS9Y5hT69NA== Received: from BN6PR17CA0011.namprd17.prod.outlook.com (2603:10b6:404:65::21) by BY5PR12MB4642.namprd12.prod.outlook.com (2603:10b6:a03:1f6::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.11; Mon, 8 Nov 2021 12:34:20 +0000 Received: from BN8NAM11FT004.eop-nam11.prod.protection.outlook.com (2603:10b6:404:65:cafe::5) by BN6PR17CA0011.outlook.office365.com (2603:10b6:404:65::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.16 via Frontend Transport; Mon, 8 Nov 2021 12:34:20 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT004.mail.protection.outlook.com (10.13.176.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Mon, 8 Nov 2021 12:34:19 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 8 Nov 2021 12:34:11 +0000 From: Raja Zidane To: CC: Matan Azrad , Date: Mon, 8 Nov 2021 12:33:51 +0000 Message-ID: <20211108123354.2194-2-rzidane@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211108123354.2194-1-rzidane@nvidia.com> References: <20211104124929.24899-1-rzidane@nvidia.com> <20211108123354.2194-1-rzidane@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b111ebd6-9e9a-4ae1-0922-08d9a2b4162e X-MS-TrafficTypeDiagnostic: BY5PR12MB4642: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3826; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: t4hhJqbH4s/ib2McIHmkCe28EyffikgnrrRJwe1ThXmAxsT60eETSDWySJnRoM36iJK4L7KXXt4wIfvqcX3bCUCr/RdvIVo54mqaMUSrCu5BZRf8V90kWE0gsF1R3AIn4nkeQ+jBDIIS79J6nF6o4pQX6AWM9N3unzrMLrWQqFCCzgWK27Rp7yiRYbc9TQiWF4uyBEwsH/DydaqrC/9+CVIS7XTY67Dyj3VRGcBfEMYaWZH7y1H9ieOWo7nUtGd2wxkNUxrB7bLBWpYFpUJW20/u8w3FKOMw8lpcbPEjyGW5G7X3dGIeVT76SbZT/MikjDI7X9ZCX+VswKIJIK3VZx0H5mE7GBARj7v4IzHRC680t2FRYetJE0ZnLxwwWApWbGxA014YvIFMVflI2H7Uve3DKjxHK33rhiFcZ+mJTrC4w8amvmPqkck+XwXBS6oyxmzfxqg4NlErimh89m7ZVdj2MniWyQRjLYBnMZu9UcNyAOVZ/tfufgn7VHXpXvHeQC0iZ+3JyfMmiU+DY3HQ7i3JMAYqpcvZDg043plevt4MMY/Loq1ucIG7C9pD5kPQFFC/Z4dPF4yRVRSfAMkkyGrCQx3MnAUZUNax/56SX/gtWrVPmxFTNjJsw8ZqYMXZnbRLa2IhKK2AMuWQ5QB/z4QIEdwazyg/GCXDxx4IxnFGscu0g7xE3XBCuRF+Vzgq X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(86362001)(55016002)(450100002)(186003)(16526019)(5660300002)(36756003)(1076003)(7696005)(356005)(336012)(83380400001)(6666004)(47076005)(6286002)(4326008)(26005)(8676002)(36860700001)(8936002)(316002)(7636003)(54906003)(82310400003)(508600001)(70206006)(6916009)(426003)(2906002)(2616005)(70586007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Nov 2021 12:34:19.7895 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b111ebd6-9e9a-4ae1-0922-08d9a2b4162e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT004.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4642 Subject: [dpdk-dev] [PATCH V2 1/4] common/mlx5: fix overflows in DevX queues size calculations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The HW QP/SQ/RQ/CQ queue sizes may be bigger than 64KB. The width of the variable handled the queue size is 16 bits which cannot contain the maximum queue size. Replace the size type to be uint32_t. Fixes: 9dab4d62b4dc ("common/mlx5: share DevX CQ creation") Fixes: 38f537635c15 ("common/mlx5: share DevX SQ creation") Fixes: f9213ab12cf9 ("common/mlx5: share DevX queue pair operations") Cc: stable@dpdk.org Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_common_devx.c | 16 ++++++++-------- drivers/common/mlx5/mlx5_common_devx.h | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/common/mlx5/mlx5_common_devx.c b/drivers/common/mlx5/mlx5_common_devx.c index 85b5282061..5afe6f2b9c 100644 --- a/drivers/common/mlx5/mlx5_common_devx.c +++ b/drivers/common/mlx5/mlx5_common_devx.c @@ -86,7 +86,7 @@ mlx5_devx_cq_create(void *ctx, struct mlx5_devx_cq *cq_obj, uint16_t log_desc_n, size_t alignment = MLX5_CQE_BUF_ALIGNMENT; uint32_t umem_size, umem_dbrec; uint32_t eqn; - uint16_t cq_size = 1 << log_desc_n; + uint32_t num_of_cqes = RTE_BIT32(log_desc_n); int ret; if (page_size == (size_t)-1 || alignment == (size_t)-1) { @@ -102,7 +102,7 @@ mlx5_devx_cq_create(void *ctx, struct mlx5_devx_cq *cq_obj, uint16_t log_desc_n, return -rte_errno; } /* Allocate memory buffer for CQEs and doorbell record. */ - umem_size = sizeof(struct mlx5_cqe) * cq_size; + umem_size = sizeof(struct mlx5_cqe) * num_of_cqes; umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); umem_size += MLX5_DBR_SIZE; umem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size, @@ -142,7 +142,7 @@ mlx5_devx_cq_create(void *ctx, struct mlx5_devx_cq *cq_obj, uint16_t log_desc_n, cq_obj->cq = cq; cq_obj->db_rec = RTE_PTR_ADD(cq_obj->umem_buf, umem_dbrec); /* Mark all CQEs initially as invalid. */ - mlx5_cq_init(cq_obj, cq_size); + mlx5_cq_init(cq_obj, num_of_cqes); return 0; error: ret = rte_errno; @@ -211,7 +211,7 @@ mlx5_devx_sq_create(void *ctx, struct mlx5_devx_sq *sq_obj, uint16_t log_wqbb_n, void *umem_buf = NULL; size_t alignment = MLX5_WQE_BUF_ALIGNMENT; uint32_t umem_size, umem_dbrec; - uint16_t sq_size = 1 << log_wqbb_n; + uint32_t num_of_wqbbs = RTE_BIT32(log_wqbb_n); int ret; if (alignment == (size_t)-1) { @@ -220,7 +220,7 @@ mlx5_devx_sq_create(void *ctx, struct mlx5_devx_sq *sq_obj, uint16_t log_wqbb_n, return -rte_errno; } /* Allocate memory buffer for WQEs and doorbell record. */ - umem_size = MLX5_WQE_SIZE * sq_size; + umem_size = MLX5_WQE_SIZE * num_of_wqbbs; umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); umem_size += MLX5_DBR_SIZE; umem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size, @@ -349,7 +349,7 @@ mlx5_devx_qp_destroy(struct mlx5_devx_qp *qp) * 0 on success, a negative errno value otherwise and rte_errno is set. */ int -mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint16_t log_wqbb_n, +mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint32_t log_wqbb_n, struct mlx5_devx_qp_attr *attr, int socket) { struct mlx5_devx_obj *qp = NULL; @@ -357,7 +357,7 @@ mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint16_t log_wqbb_n, void *umem_buf = NULL; size_t alignment = MLX5_WQE_BUF_ALIGNMENT; uint32_t umem_size, umem_dbrec; - uint16_t qp_size = 1 << log_wqbb_n; + uint32_t num_of_wqbbs = RTE_BIT32(log_wqbb_n); int ret; if (alignment == (size_t)-1) { @@ -366,7 +366,7 @@ mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint16_t log_wqbb_n, return -rte_errno; } /* Allocate memory buffer for WQEs and doorbell record. */ - umem_size = MLX5_WQE_SIZE * qp_size; + umem_size = MLX5_WQE_SIZE * num_of_wqbbs; umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); umem_size += MLX5_DBR_SIZE; umem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size, diff --git a/drivers/common/mlx5/mlx5_common_devx.h b/drivers/common/mlx5/mlx5_common_devx.h index 7ceac040f8..df92feebe2 100644 --- a/drivers/common/mlx5/mlx5_common_devx.h +++ b/drivers/common/mlx5/mlx5_common_devx.h @@ -89,7 +89,7 @@ void mlx5_devx_qp_destroy(struct mlx5_devx_qp *qp); __rte_internal int mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, - uint16_t log_wqbb_n, + uint32_t log_wqbb_n, struct mlx5_devx_qp_attr *attr, int socket); __rte_internal -- 2.17.1