From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A7166A0C4B; Mon, 8 Nov 2021 23:35:44 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6182C40151; Mon, 8 Nov 2021 23:35:44 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id CACD040040 for ; Mon, 8 Nov 2021 23:35:42 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A8I3aF9011733; Mon, 8 Nov 2021 14:35:41 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=5S/YupCozxkFH0kO+csW13mkBr4SJ7ObpD//u5R6eJU=; b=j7NVebrqFRxANbj4CqKE3G4MGQHtrYJmDbAW9J9dtiojSOxFvGnKYV0jpIGMVTHFDQbw ZY5pdLxLLtcdcLM6IW/D4Sz6VTe5TqDWZWEFNVhS/gOs3FE7j/ntqEH/R0tNjI8OYTPe 3uVF6Dz9VylxSowlyXmOm2ezZIaS3HYMPDqQRbwIZvFyhlbVcqMdvJxFhAi6XhhZLrKi 1YnaXKDqomY5SLDdLUbKoNjYJAhzoHxVKAm0LiKsXoLU6UUVZ1Tp8RaYa14GZLGXG9dw GqdkKnsSnzlUWUjunBRx4jipZp5k9uDrtjtJEXPhFJtJktElrsBSHgT0T2js4g5KJ8vD sw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3c726bk6h7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 08 Nov 2021 14:35:41 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 8 Nov 2021 14:35:40 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 8 Nov 2021 14:35:40 -0800 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 2A3815B6933; Mon, 8 Nov 2021 14:35:37 -0800 (PST) From: Volodymyr Fialko To: , Bruce Richardson , "Anatoly Burakov" CC: , Volodymyr Fialko , "David Marchand" Date: Mon, 8 Nov 2021 23:34:44 +0100 Message-ID: <20211108223444.3387640-1-vfialko@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: l4AGvP0AHYjJ10YR16jEEwFgxAJfjfY_ X-Proofpoint-GUID: l4AGvP0AHYjJ10YR16jEEwFgxAJfjfY_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-08_06,2021-11-08_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2] eal/arm64: support ASan X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch defines ASAN_SHADOW_OFFSET for arm64 according to the ASan documentation. This offset should cover all arm64 VMAs supported by ASan. Signed-off-by: Volodymyr Fialko Reviewed-by: David Marchand Acked-by: Jerin Jacob --- Changes since v1: - changed the subject - rewrite checks in "elif" manner --- config/meson.build | 2 +- doc/guides/prog_guide/asan.rst | 2 +- lib/eal/common/malloc_elem.h | 2 ++ 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/config/meson.build b/config/meson.build index 17b5bec406..7eb710c08d 100644 --- a/config/meson.build +++ b/config/meson.build @@ -428,7 +428,7 @@ if get_option('b_sanitize') == 'address' or get_option('b_sanitize') == 'address dpdk_extra_ldflags += '-lasan' endif - if is_linux and arch_subdir == 'x86' and dpdk_conf.get('RTE_ARCH_64') + if is_linux and arch_subdir in ['x86', 'arm'] and dpdk_conf.get('RTE_ARCH_64') dpdk_conf.set10('RTE_MALLOC_ASAN', true) endif endif diff --git a/doc/guides/prog_guide/asan.rst b/doc/guides/prog_guide/asan.rst index 6d1b871c93..28b2382fc7 100644 --- a/doc/guides/prog_guide/asan.rst +++ b/doc/guides/prog_guide/asan.rst @@ -33,7 +33,7 @@ Example:: "stty echo" command when an error occurs. ASan is aware of DPDK memory allocations, thanks to added instrumentation. -This is only enabled on x86_64 at the moment. +This is enabled on x86_64 and arm64 at the moment. Other architectures may have to define ASAN_SHADOW_OFFSET. Example heap-buffer-overflow error diff --git a/lib/eal/common/malloc_elem.h b/lib/eal/common/malloc_elem.h index 262d69bb3e..26e937cea0 100644 --- a/lib/eal/common/malloc_elem.h +++ b/lib/eal/common/malloc_elem.h @@ -106,6 +106,8 @@ malloc_elem_cookies_ok(const struct malloc_elem *elem) #ifdef RTE_ARCH_X86_64 #define ASAN_SHADOW_OFFSET 0x00007fff8000 +#elif defined(RTE_ARCH_ARM64) +#define ASAN_SHADOW_OFFSET 0x001000000000 #endif #define ASAN_SHADOW_GRAIN_SIZE 8 -- 2.25.1