From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0E41CA0C4B; Tue, 9 Nov 2021 05:40:10 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5BB5F4113D; Tue, 9 Nov 2021 05:39:51 +0100 (CET) Received: from EUR03-DB5-obe.outbound.protection.outlook.com (mail-eopbgr40051.outbound.protection.outlook.com [40.107.4.51]) by mails.dpdk.org (Postfix) with ESMTP id 69DA74111F for ; Tue, 9 Nov 2021 05:39:48 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZdGvdmf1hwifHBZU0JK3mtDkq4AhTxigOEO5DiYYswsk9Bt20Y6gDxRGDq59tejcC6uLQ8+C09qgTygz/TjCIu8JYjHzHhxHJ09m8UXe9gAiWa/69SDnNioLoi3fTPjsb5rjGiFKTSuI69h5bZ3pr85DV3wGnBCO7ldUBsycgvMAxANYxCcxh+fQSV4dkP1w+qdAWNJOaqzUYRnfXeJdZZPV6jqKC6Waeb0Sf8Yc7Mrg9C2bw78qmqpWkJ2TJEJO472RMf4B2StToswOr970ywkvLe3IvAnFbaNxwNK/ZTRtnaNV5mg19slVLahH3xMi5QNTHis2q7uheyRRH+cgQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Fjv0angOtDQ7rIgiWfLbUcqTFg1QH0I2fSV5kaL+cfM=; b=fmzSfQSA1Y0SC3myJNOnGOmqeh9S8xdnaGFd5Etb+kizI+SDmM/yOpLgJqYCns2tTj996FSTBgGnvrZSbXdxgjP/gFid4Dnu968BF3+VXaX87Ij7jehEV7e/dmwaxOpWo9BtC4JVPGcu6UU63kn2juXCyhTkfzXF/ngRr+Hi16mo8DKIrBkxH+7wS1jCLwCp3zVerZf2J/ViWPgRVf7WB+2XmqWD0z+kon/8KuhLBz6JUoz9DsFV3mdMuuOipINl4HA5h3bwT4TM0jOvWyAxLyo6iONugskw32CGJRjGVoDmTuGxpYAMYrizUtAGtk+KDkg1/1QhIgBKe6bWBKU5cw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Fjv0angOtDQ7rIgiWfLbUcqTFg1QH0I2fSV5kaL+cfM=; b=Y+KnlWNyi45VHGTTqk2bk03Ni7ucx5PHmjYpXIZZF6+x504A6ek0duiLtmxKR4Fo/EDRy8qFM2Ns/QcauI2+qsV9FZFDAjMqFooqINdtlEiZv8doIdkL39KLo28H2Jtx9xKpsbYM6txD7nJ3JXIpelcapvz0PaPmt2v3Kfwh3rw= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB6960.eurprd04.prod.outlook.com (2603:10a6:803:12d::10) by VI1PR04MB5630.eurprd04.prod.outlook.com (2603:10a6:803:e6::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.10; Tue, 9 Nov 2021 04:39:46 +0000 Received: from VI1PR04MB6960.eurprd04.prod.outlook.com ([fe80::11d9:6f32:90e:80c1]) by VI1PR04MB6960.eurprd04.prod.outlook.com ([fe80::11d9:6f32:90e:80c1%7]) with mapi id 15.20.4669.016; Tue, 9 Nov 2021 04:39:46 +0000 From: Gagandeep Singh To: dev@dpdk.org Cc: nipun.gupta@nxp.com, thomas@monjalon.net, Gagandeep Singh Date: Tue, 9 Nov 2021 10:09:09 +0530 Message-Id: <20211109043910.4016824-5-g.singh@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211109043910.4016824-1-g.singh@nxp.com> References: <20211108090704.3585175-2-g.singh@nxp.com> <20211109043910.4016824-1-g.singh@nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SI2P153CA0002.APCP153.PROD.OUTLOOK.COM (2603:1096:4:140::16) To VI1PR04MB6960.eurprd04.prod.outlook.com (2603:10a6:803:12d::10) MIME-Version: 1.0 Received: from lsv03457.swis.in-blr01.nxp.com (14.142.151.118) by SI2P153CA0002.APCP153.PROD.OUTLOOK.COM (2603:1096:4:140::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.5 via Frontend Transport; Tue, 9 Nov 2021 04:39:45 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 46690579-cafc-4bef-c244-08d9a33af50a X-MS-TrafficTypeDiagnostic: VI1PR04MB5630: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6yCykRl+9Q010yBcN2WgIHBGCn9LmTCU9n1AbsMeKhVALeN9Tb+gk6/W8AvfVsX0zwc5XJtK+VYLjBlHmqWQqu+53mUTUkpjeaXrzWYmAyV/sgk/OJr00A8qvLg4cP5G/Esrj18/u55sesdpM0iVW767gc0FSvNdkmQM/CCLvJf9TsWqvjaqzWr0iV5iyWwljuOqjLynrSCJVj+pyx+N304KfkhouXfcSaGDd133idy4MRkqFkaA7kezHBZg+TIQy8rxf0JUnQ3vymDJOutINA3MCI8lg+mWkoscyJ1JDPn0YQ31jyDkRJ5fXwthkNUtEJ9i6Fo6mAk/plEqQNElcVLZtm9ue4Muw7zYqkngmASaog0fCqDXpRpQ7+4QuzZ018QXfRtq9iuhFyZA13CbwQyWIvXtZuslyamy9wWCUUqXKlJKr79jDEB64gIwIeAjlziGhdNgWQZhG43T0VHY2hAnzCmV6ahecXBCJeTTBpFlB2xd/nBNDlnoiivWWp+PZeq0qUGErK5riEezKH7+Z7tJwGKOTgcb6uAqbCgJNISlumNJtQR+QshyHk4LK1cLP61c6/GLUYJMN+ymeVNkSHdJASBivBp4+ju8HBARfCUMI+sPtYrPtVmnEUqvepj5pZ+mdHo6wYfhAboYoW2+0DF5BrqSxL3ZDmk99+/EWq5YGZXPjk8eG2/mDzblEgV2OwxBZOPSXtJJvb09GqFwrm5Rn/gLmr8PydwsohRIVQI= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VI1PR04MB6960.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(55236004)(1006002)(6666004)(66946007)(26005)(52116002)(7696005)(186003)(316002)(508600001)(30864003)(1076003)(66556008)(2616005)(5660300002)(66476007)(8936002)(86362001)(956004)(4326008)(6916009)(2906002)(38350700002)(8676002)(36756003)(6486002)(83380400001)(38100700002)(110426009); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?YlRaBVAFEuXK28LZVGkHt/FGRSwITqQB3kt4Fd8Mo/CCnvJmou9q3F7FuQRG?= =?us-ascii?Q?VVwyyIJidz+Uaqt3v8jcJcvPGwcx0KQBn5LHEqgyrSK+hOC3KXqTAOLNnQgI?= =?us-ascii?Q?32KAM6QVRkrGEqAxF1PoW1PJTKbnSWB3UZ4xThcqbEysyCZYjWl16zk4aM24?= =?us-ascii?Q?i+dnbLi+obgwuo87pu3Ckb1426E+mFdTQxx1DtnbhjwePSFRDTrvMLgAfakk?= =?us-ascii?Q?4jV/ExDAwVW5Ykvna00iaJQaVHzMTREKJgZotpPMBKTzJ9AiwiDCsV2AEx9B?= =?us-ascii?Q?3sPwsQ0iPsMqoTNGkBWP3kf3tLjC4vYtnEwz0M7DLgt39EpK6t7uQ2h+GWuQ?= =?us-ascii?Q?lx8b25y0uckTiAyx3G33m++xL9EyhBA3qekpVqQvj+1ZcIfPghyRimyy9Krl?= =?us-ascii?Q?akIpRbXf4k0slmP9N0B3tURVKfV3/B0zl6v2tz7xDJE2aNqKiuNF42dCDmu7?= =?us-ascii?Q?Ybuq42pfPX8Mo6rTsnQBZNh780VtbLELUd19vQyTz/e4pJYlNOoxfbjWhi4Y?= =?us-ascii?Q?jyIu0JfoA4/G8R2jMO5FiJTIbskGhPjGymy3hakxtY7o2wlXFrmpdKP6ipKv?= =?us-ascii?Q?t7lqMIYA34gn4UcIBMfF+MWwyG0/Oypyog3PFETAbPEWO4EVlJw/2Q6R3FTm?= =?us-ascii?Q?FoBosE07JTXRmw8cslUDh2TRQWB17amySO60A6rjm43eBDDwFtnucga6SQsJ?= =?us-ascii?Q?6OwoREVBgD2lSZRxmVXg4sn2fMrr2kNGJ8132Nm+9/4H6GONAjgYiyDL7vM6?= =?us-ascii?Q?1H3wmD/Qy5fZ2xifHeaMVfgGlC8g/AB3i1NoZS7Q51A2S/GnzwwRIKCbXR+p?= =?us-ascii?Q?dW8oJx+0tM5Hj56eT5egynavuJWR1M0nC7UYLi09BmKjVt0ThIhmkIbxcs+i?= =?us-ascii?Q?uM3JQnJ1OUZvZilqmCVBvwDp8ZyOkShJqHAZujalDFSItR3lC7AWJVKGkrJg?= =?us-ascii?Q?y5IEnD6zwl0W38IBPuiOhJAXNGaA2sk3FXLD9DJsqeewm6ZS2QlT+WPA4wq8?= =?us-ascii?Q?q1ajikXgBftv3iJTTEDUqK4HfGsJ6EDaVqXrFL5vt6monA4E4FywK5qeq2E3?= =?us-ascii?Q?9P6ATPBb88+d4AbvXZdJvZ8sEWLBU0JrGuMRt8VEW7sQcHu9faobd4MaUhNb?= =?us-ascii?Q?PvTewSOSmoeAbO3ewZlE4F0ZQ+ffRsvQ5vc8o7Rv35U2ISNmcMbL25wgpTIs?= =?us-ascii?Q?bnOy+++0vb497iQyS/hlwZ0lbeKmqfS8iz3LHEAKO1b97W8p695Sf0Sxzp+h?= =?us-ascii?Q?JzJPN1CnymmVfYYmljDXALAFoF4z0inaMZs+TCp8L8fvkeE4ZELDntjX4Kcw?= =?us-ascii?Q?MF4SP5gUGUgQQeXHiMcEuMqAX0zcfiLW3793J6OqbXvZG1nUbn4dgU66zMG0?= =?us-ascii?Q?eyvZml0x/jHzmu+1NePbGtHd4XIifkPUKHpUt8yId5joS0jd5WbkKo7C67/Y?= =?us-ascii?Q?Vb574g4ysvSS1AaARdEGjx345hGK6kbqmkMwycnogkVu2s5hhqWcR8TZufNj?= =?us-ascii?Q?JT/AJSoRq8aKHbkJQl12jnOr8svEWUTPRdpuHZY8zLnjELugVhBpg3uZyUkT?= =?us-ascii?Q?XsgCWUse45A24l9TpDU=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 46690579-cafc-4bef-c244-08d9a33af50a X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB6960.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2021 04:39:46.8211 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: syFBDmPFWwoUbHJNVRUxlhb31slmhSexB1h7GyKCTkZfDkwgdqOXaXeM4rCQjB+o X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5630 Subject: [dpdk-dev] [PATCH v4 4/5] dma/dpaa: support DMA operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch support copy, submit, completed and completed status functionality of DMA driver. Signed-off-by: Gagandeep Singh --- doc/guides/dmadevs/dpaa.rst | 11 ++ drivers/dma/dpaa/dpaa_qdma.c | 334 +++++++++++++++++++++++++++++++++++ drivers/dma/dpaa/dpaa_qdma.h | 4 + 3 files changed, 349 insertions(+) diff --git a/doc/guides/dmadevs/dpaa.rst b/doc/guides/dmadevs/dpaa.rst index 885a8bb8aa..4fbd8a25fb 100644 --- a/doc/guides/dmadevs/dpaa.rst +++ b/doc/guides/dmadevs/dpaa.rst @@ -46,6 +46,17 @@ Initialization On EAL initialization, DPAA DMA devices will be detected on DPAA bus and will be probed and populated into their device list. +Features +-------- + +The DPAA DMA implements following features in the dmadev API: + +- Supports 1 virtual channel. +- Supports all 4 DMA transfers: MEM_TO_MEM, MEM_TO_DEV, + DEV_TO_MEM, DEV_TO_DEV. +- Supports DMA silent mode. +- Supports issuing DMA of data within memory without hogging CPU while + performing DMA operation. Platform Requirement ~~~~~~~~~~~~~~~~~~~~ diff --git a/drivers/dma/dpaa/dpaa_qdma.c b/drivers/dma/dpaa/dpaa_qdma.c index e59cd36872..ebe6211f08 100644 --- a/drivers/dma/dpaa/dpaa_qdma.c +++ b/drivers/dma/dpaa/dpaa_qdma.c @@ -15,12 +15,50 @@ qdma_desc_addr_set64(struct fsl_qdma_format *ccdf, u64 addr) ccdf->addr_lo = rte_cpu_to_le_32(lower_32_bits(addr)); } +static inline u64 +qdma_ccdf_get_queue(const struct fsl_qdma_format *ccdf) +{ + return ccdf->cfg8b_w1 & 0xff; +} + +static inline int +qdma_ccdf_get_offset(const struct fsl_qdma_format *ccdf) +{ + return (rte_le_to_cpu_32(ccdf->cfg) & QDMA_CCDF_MASK) + >> QDMA_CCDF_OFFSET; +} + +static inline void +qdma_ccdf_set_format(struct fsl_qdma_format *ccdf, int offset) +{ + ccdf->cfg = rte_cpu_to_le_32(QDMA_CCDF_FOTMAT | offset); +} + +static inline int +qdma_ccdf_get_status(const struct fsl_qdma_format *ccdf) +{ + return (rte_le_to_cpu_32(ccdf->status) & QDMA_CCDF_MASK) + >> QDMA_CCDF_STATUS; +} + +static inline void +qdma_ccdf_set_ser(struct fsl_qdma_format *ccdf, int status) +{ + ccdf->status = rte_cpu_to_le_32(QDMA_CCDF_SER | status); +} + static inline void qdma_csgf_set_len(struct fsl_qdma_format *csgf, int len) { csgf->cfg = rte_cpu_to_le_32(len & QDMA_SG_LEN_MASK); } +static inline void +qdma_csgf_set_f(struct fsl_qdma_format *csgf, int len) +{ + csgf->cfg = rte_cpu_to_le_32(QDMA_SG_FIN | (len & QDMA_SG_LEN_MASK)); +} + static inline int ilog2(int x) { @@ -47,6 +85,18 @@ qdma_writel(u32 val, void *addr) QDMA_OUT(addr, val); } +static u32 +qdma_readl_be(void *addr) +{ + return QDMA_IN_BE(addr); +} + +static void +qdma_writel_be(u32 val, void *addr) +{ + QDMA_OUT_BE(addr, val); +} + static void *dma_pool_alloc(int size, int aligned, dma_addr_t *phy_addr) { @@ -104,6 +154,32 @@ fsl_qdma_free_chan_resources(struct fsl_qdma_chan *fsl_chan) fsl_qdma->desc_allocated--; } +static void +fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp, + dma_addr_t dst, dma_addr_t src, u32 len) +{ + struct fsl_qdma_format *csgf_src, *csgf_dest; + + /* Note: command table (fsl_comp->virt_addr) is getting filled + * directly in cmd descriptors of queues while enqueuing the descriptor + * please refer fsl_qdma_enqueue_desc + * frame list table (virt_addr) + 1) and source, + * destination descriptor table + * (fsl_comp->desc_virt_addr and fsl_comp->desc_virt_addr+1) move to + * the control path to fsl_qdma_pre_request_enqueue_comp_sd_desc + */ + csgf_src = (struct fsl_qdma_format *)fsl_comp->virt_addr + 2; + csgf_dest = (struct fsl_qdma_format *)fsl_comp->virt_addr + 3; + + /* Status notification is enqueued to status queue. */ + qdma_desc_addr_set64(csgf_src, src); + qdma_csgf_set_len(csgf_src, len); + qdma_desc_addr_set64(csgf_dest, dst); + qdma_csgf_set_len(csgf_dest, len); + /* This entry is the last entry. */ + qdma_csgf_set_f(csgf_dest, len); +} + /* * Pre-request command descriptor and compound S/G for enqueue. */ @@ -175,6 +251,26 @@ fsl_qdma_pre_request_enqueue_comp_sd_desc( return -ENOMEM; } +/* + * Request a command descriptor for enqueue. + */ +static struct fsl_qdma_comp * +fsl_qdma_request_enqueue_desc(struct fsl_qdma_chan *fsl_chan) +{ + struct fsl_qdma_queue *queue = fsl_chan->queue; + struct fsl_qdma_comp *comp_temp; + + if (!list_empty(&queue->comp_free)) { + comp_temp = list_first_entry(&queue->comp_free, + struct fsl_qdma_comp, + list); + list_del(&comp_temp->list); + return comp_temp; + } + + return NULL; +} + static struct fsl_qdma_queue *fsl_qdma_alloc_queue_resources(struct fsl_qdma_engine *fsl_qdma) { @@ -324,6 +420,54 @@ fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma) return 0; } +static int +fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma, + void *block, int id, const uint16_t nb_cpls, + uint16_t *last_idx, + enum rte_dma_status_code *status) +{ + struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue; + struct fsl_qdma_queue *fsl_status = fsl_qdma->status[id]; + struct fsl_qdma_queue *temp_queue; + struct fsl_qdma_format *status_addr; + struct fsl_qdma_comp *fsl_comp = NULL; + u32 reg, i; + int count = 0; + + while (count < nb_cpls) { + reg = qdma_readl_be(block + FSL_QDMA_BSQSR); + if (reg & FSL_QDMA_BSQSR_QE_BE) + return count; + + status_addr = fsl_status->virt_head; + + i = qdma_ccdf_get_queue(status_addr) + + id * fsl_qdma->n_queues; + temp_queue = fsl_queue + i; + fsl_comp = list_first_entry(&temp_queue->comp_used, + struct fsl_qdma_comp, + list); + list_del(&fsl_comp->list); + + reg = qdma_readl_be(block + FSL_QDMA_BSQMR); + reg |= FSL_QDMA_BSQMR_DI_BE; + + qdma_desc_addr_set64(status_addr, 0x0); + fsl_status->virt_head++; + if (fsl_status->virt_head == fsl_status->cq + fsl_status->n_cq) + fsl_status->virt_head = fsl_status->cq; + qdma_writel_be(reg, block + FSL_QDMA_BSQMR); + *last_idx = fsl_comp->index; + if (status != NULL) + status[count] = RTE_DMA_STATUS_SUCCESSFUL; + + list_add_tail(&fsl_comp->list, &temp_queue->comp_free); + count++; + + } + return count; +} + static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma) { @@ -419,6 +563,66 @@ fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma) return 0; } +static void * +fsl_qdma_prep_memcpy(void *fsl_chan, dma_addr_t dst, + dma_addr_t src, size_t len, + void *call_back, + void *param) +{ + struct fsl_qdma_comp *fsl_comp; + + fsl_comp = + fsl_qdma_request_enqueue_desc((struct fsl_qdma_chan *)fsl_chan); + if (!fsl_comp) + return NULL; + + fsl_comp->qchan = fsl_chan; + fsl_comp->call_back_func = call_back; + fsl_comp->params = param; + + fsl_qdma_comp_fill_memcpy(fsl_comp, dst, src, len); + return (void *)fsl_comp; +} + +static int +fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan, + struct fsl_qdma_comp *fsl_comp, + uint64_t flags) +{ + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue; + void *block = fsl_queue->block_base; + struct fsl_qdma_format *ccdf; + u32 reg; + + /* retrieve and store the register value in big endian + * to avoid bits swap + */ + reg = qdma_readl_be(block + + FSL_QDMA_BCQSR(fsl_queue->id)); + if (reg & (FSL_QDMA_BCQSR_QF_XOFF_BE)) + return -1; + + /* filling descriptor command table */ + ccdf = (struct fsl_qdma_format *)fsl_queue->virt_head; + qdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16); + qdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(fsl_comp->virt_addr)); + qdma_ccdf_set_ser(ccdf, qdma_ccdf_get_status(fsl_comp->virt_addr)); + fsl_comp->index = fsl_queue->virt_head - fsl_queue->cq; + fsl_queue->virt_head++; + + if (fsl_queue->virt_head == fsl_queue->cq + fsl_queue->n_cq) + fsl_queue->virt_head = fsl_queue->cq; + + list_add_tail(&fsl_comp->list, &fsl_queue->comp_used); + + if (flags == RTE_DMA_OP_FLAG_SUBMIT) { + reg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id)); + reg |= FSL_QDMA_BCQMR_EI_BE; + qdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id)); + } + return fsl_comp->index; +} + static int fsl_qdma_alloc_chan_resources(struct fsl_qdma_chan *fsl_chan) { @@ -535,6 +739,132 @@ dpaa_qdma_queue_setup(struct rte_dma_dev *dmadev, return dpaa_get_channel(fsl_qdma, vchan); } +static int +dpaa_qdma_submit(void *dev_private, uint16_t vchan) +{ + struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private; + struct fsl_qdma_chan *fsl_chan = + &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]]; + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue; + void *block = fsl_queue->block_base; + u32 reg; + + while (fsl_queue->pending) { + reg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id)); + reg |= FSL_QDMA_BCQMR_EI_BE; + qdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id)); + fsl_queue->pending--; + } + + return 0; +} + +static int +dpaa_qdma_enqueue(void *dev_private, uint16_t vchan, + rte_iova_t src, rte_iova_t dst, + uint32_t length, uint64_t flags) +{ + struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private; + struct fsl_qdma_chan *fsl_chan = + &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]]; + int ret; + + void *fsl_comp = NULL; + + fsl_comp = fsl_qdma_prep_memcpy(fsl_chan, + (dma_addr_t)dst, (dma_addr_t)src, + length, NULL, NULL); + if (!fsl_comp) { + DPAA_QDMA_DP_DEBUG("fsl_comp is NULL\n"); + return -1; + } + ret = fsl_qdma_enqueue_desc(fsl_chan, fsl_comp, flags); + + return ret; +} + +static uint16_t +dpaa_qdma_dequeue_status(void *dev_private, uint16_t vchan, + const uint16_t nb_cpls, uint16_t *last_idx, + enum rte_dma_status_code *st) +{ + struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private; + int id = (int)((fsl_qdma->vchan_map[vchan]) / QDMA_QUEUES); + void *block; + int intr; + void *status = fsl_qdma->status_base; + + intr = qdma_readl_be(status + FSL_QDMA_DEDR); + if (intr) { + DPAA_QDMA_ERR("DMA transaction error! %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW0R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW0R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW1R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW1R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW2R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW2R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW3R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW3R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFQIDR); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFQIDR %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECBR); + DPAA_QDMA_INFO("reg FSL_QDMA_DECBR %x\n", intr); + qdma_writel(0xffffffff, + status + FSL_QDMA_DEDR); + intr = qdma_readl(status + FSL_QDMA_DEDR); + } + + block = fsl_qdma->block_base + + FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id); + + intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id, nb_cpls, + last_idx, st); + + return intr; +} + + +static uint16_t +dpaa_qdma_dequeue(void *dev_private, + uint16_t vchan, const uint16_t nb_cpls, + uint16_t *last_idx, bool *has_error) +{ + struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private; + int id = (int)((fsl_qdma->vchan_map[vchan]) / QDMA_QUEUES); + void *block; + int intr; + void *status = fsl_qdma->status_base; + + intr = qdma_readl_be(status + FSL_QDMA_DEDR); + if (intr) { + DPAA_QDMA_ERR("DMA transaction error! %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW0R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW0R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW1R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW1R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW2R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW2R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW3R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW3R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFQIDR); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFQIDR %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECBR); + DPAA_QDMA_INFO("reg FSL_QDMA_DECBR %x\n", intr); + qdma_writel(0xffffffff, + status + FSL_QDMA_DEDR); + intr = qdma_readl(status + FSL_QDMA_DEDR); + *has_error = true; + } + + block = fsl_qdma->block_base + + FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id); + + intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id, nb_cpls, + last_idx, NULL); + + return intr; +} + static struct rte_dma_dev_ops dpaa_qdma_ops = { .dev_info_get = dpaa_info_get, .dev_configure = dpaa_qdma_configure, @@ -652,6 +982,10 @@ dpaa_qdma_probe(__rte_unused struct rte_dpaa_driver *dpaa_drv, dmadev->dev_ops = &dpaa_qdma_ops; dmadev->device = &dpaa_dev->device; dmadev->fp_obj->dev_private = dmadev->data->dev_private; + dmadev->fp_obj->copy = dpaa_qdma_enqueue; + dmadev->fp_obj->submit = dpaa_qdma_submit; + dmadev->fp_obj->completed = dpaa_qdma_dequeue; + dmadev->fp_obj->completed_status = dpaa_qdma_dequeue_status; /* Invoke PMD device initialization function */ ret = dpaa_qdma_init(dmadev); diff --git a/drivers/dma/dpaa/dpaa_qdma.h b/drivers/dma/dpaa/dpaa_qdma.h index f046167108..6d0ac58317 100644 --- a/drivers/dma/dpaa/dpaa_qdma.h +++ b/drivers/dma/dpaa/dpaa_qdma.h @@ -7,6 +7,10 @@ #include +#ifndef BIT +#define BIT(nr) (1UL << (nr)) +#endif + #define CORE_NUMBER 4 #define RETRIES 5 -- 2.25.1