From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8557FA0C4B; Mon, 8 Nov 2021 22:39:46 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 76EFF4111C; Mon, 8 Nov 2021 22:39:46 +0100 (CET) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2045.outbound.protection.outlook.com [40.107.244.45]) by mails.dpdk.org (Postfix) with ESMTP id BFA334111B for ; Mon, 8 Nov 2021 22:39:44 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=NvmD7Z4ybiDegCQKZMrNojKWOFKF1E40wG7syIuufuxGJggkURFDx7HuoazLTyWHo/7q495bljSjefS/7NqX6qFtSeg/BXyyR08XB9FwBqgdkb2fAZtExKiB1jCXq1s2LEzjEOlvdDRlGAMPTahG22BzsbHurOc7uu9xYmQG5sQdeB6KcYQ2VjSDbsv/REmmc/P6b1K4Ml4ZCmKYZiTyQ7yJ0wuhv5b17jccV4KLU58yYv6LLaRlofPGgnJbP0ixKD0brIR6leqsnCHEn3mEZUVaV9eEQ6a9TqPdhjgkYfDtkg+XdO3uMCDCBeqmoEu7DAewcvW+D1XQ/qKkyItIEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3k3AgeBq2rmSkKUYR+wrmG9APouvpYI46D/OOeLaHaU=; b=Ug8krs0YGoETA4d6RsC6C+OEn2o/dGVllqDAuBOe+x1QNmHL/EtGvzCzZ0AUSiosC02S8wzRR0CmjPh6/mI6dA/jhhl75odsVsXRmemZjymWwG6u7jk14MQwh+eg2QITAtRVNGFqy93JFRzQZI8zq5U8+zSw80cAWpVLsse5YW8z2Lri17t8CV1ZiNHUrzMUOhu0gW7hZKxu/jOgfGz7MXrESzGp7MNYlaHH1js24CfGe2NYaghaaS9G44ZUb28aKa25FTWm7Y/Jg9kGXxY8tWD9HiKoBU0l5E2R0kzSPYIH1BnSfcsShVaoW0zvx555KLSkkKIdJokC2K47Q5ZfAA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3k3AgeBq2rmSkKUYR+wrmG9APouvpYI46D/OOeLaHaU=; b=BAhSjcFU5rqjrULjXSUlSkr7fgsCLMWDItU/G0gXu/xWNCWVKi7X4uusnuwkQ5n3i4XlAuqQepQta4H4xehVeU3auxEehlpbXqecaFA/2CQoOcTJnqccvNq7w40qL2FHxAfSpTWFbxHZWhq+C3kde7+yxvQaLzELQ7YBHCr3cDz6OHQ/wbIZxbb0KUcxP6FdILnJEkcxgL0H0/4KMTTLYAQuXD5pSfZ/CcmQQ4L0QiZ7ijKSvj9oFggy60POqv5fCTXfaHunxm79q7cs31Zw2gHCjxWhApjLiYgeGK55ARKgCZRzS457tBLMaM/RGj1yjEhs29/0WEFgq6EubkEiNQ== Received: from BN9PR03CA0665.namprd03.prod.outlook.com (2603:10b6:408:10e::10) by BN6PR1201MB0196.namprd12.prod.outlook.com (2603:10b6:405:4d::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.11; Mon, 8 Nov 2021 21:39:41 +0000 Received: from BN8NAM11FT067.eop-nam11.prod.protection.outlook.com (2603:10b6:408:10e::4) by BN9PR03CA0665.outlook.office365.com (2603:10b6:408:10e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.11 via Frontend Transport; Mon, 8 Nov 2021 21:39:41 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT067.mail.protection.outlook.com (10.13.177.159) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Mon, 8 Nov 2021 21:39:40 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 8 Nov 2021 21:39:36 +0000 From: To: CC: Elena Agostini Date: Tue, 9 Nov 2021 05:50:41 +0000 Message-ID: <20211109055041.942-2-eagostini@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211109055041.942-1-eagostini@nvidia.com> References: <20211005224905.13505-1-eagostini@nvidia.com> <20211109055041.942-1-eagostini@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ef8d033f-0450-4a2d-faec-08d9a3004579 X-MS-TrafficTypeDiagnostic: BN6PR1201MB0196: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:185; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /ZEhQM/vh17jjAm1HeC5td7iU4lOr1pZPvTjO0IAIuDbZrRzJWExjdwS8YXFGKHUCkYhIMQntf5wT8MwI5E7J6V6DquYW2OhEd+mdrAzN/gt/S5k0Yuwx36QcGUf3FH6mnLVBx6Ww8ERDrAzrm8GD73pEqfdkDelx4roQAfF3L8XY5UfTCo1gPEeJFe2qm0jiE9IMrC2F+OkD3ZPhZAsuRmNm/kfKPqCB6c9CUEn2o+mA4nVJMwNcoL+W5m01mA8quZrsIU9N78ySdaDg6/RDykPcf/JvhX8OqazpiK07I110Qds9kN21RDJzpCzoGWuuG1SaCgi/5UlDGn9CRm+7tTCo9kFQKJT8YL+gJ3wPgAgDa4p8RSUpMQ1PmZ/lz3oQU6e1rj4MbDcmu/pPobb3bGNR97jUMNGhf2oV3njpjQW50XcVvXeIaI70qZ3r3/JdKgpZjCxdNVihOrBAfIKyzHAoQiEdqBPcTnLRz4ML3hRQsFekBE875VsDJqMK2XGDicAUxzyzRykqnCIi9/txyUSN0wBR/weqzTbKMF+l2DSWDSe6TSiMQ5vzSP8JrsvuGE0cpvccjADYncw11tlgA4ql8wAFUbtesiUtT7LfPmcYOVd92aJNuNwGypNKz9l++zqHjoRNXx6xvl0rVuveiI1TTikWN84x7cFfldVUJf0sIGyqKNUPJgAhLVhBK6+UewVNDGDobyluxoGVmuc3MT9+UzCOJhYh62zhBRpXfe/HriHmWWOUukkcY0/2YMQzie6zW1y4Tf+r4FcA3zwv4bRiARWcaTZs1QOaq/BCfXuP3q7cysIL9rqCuFB0PSx X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(36756003)(8676002)(70586007)(8936002)(83380400001)(82310400003)(4326008)(6286002)(6666004)(2616005)(2906002)(5660300002)(2876002)(36860700001)(426003)(86362001)(7696005)(30864003)(47076005)(356005)(508600001)(186003)(55016002)(336012)(70206006)(107886003)(316002)(36906005)(1076003)(7636003)(6916009)(26005)(16526019); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Nov 2021 21:39:40.6837 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef8d033f-0450-4a2d-faec-08d9a3004579 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT067.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0196 Subject: [dpdk-dev] [PATCH v4 1/1] gpu/cuda: introduce CUDA driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Elena Agostini This is the CUDA implementation of the gpudev library. Funcitonalities implemented through CUDA Driver API are: - Device probe and remove - Manage device memory allocations - Register/unregister external CPU memory in the device memory area Signed-off-by: Elena Agostini --- doc/guides/gpus/cuda.rst | 110 +++++ doc/guides/gpus/index.rst | 1 + drivers/gpu/cuda/cuda.c | 813 +++++++++++++++++++++++++++++++++++ drivers/gpu/cuda/meson.build | 20 + drivers/gpu/cuda/version.map | 3 + drivers/gpu/meson.build | 2 +- 6 files changed, 948 insertions(+), 1 deletion(-) create mode 100644 doc/guides/gpus/cuda.rst create mode 100644 drivers/gpu/cuda/cuda.c create mode 100644 drivers/gpu/cuda/meson.build create mode 100644 drivers/gpu/cuda/version.map diff --git a/doc/guides/gpus/cuda.rst b/doc/guides/gpus/cuda.rst new file mode 100644 index 0000000000..64a78bf1e1 --- /dev/null +++ b/doc/guides/gpus/cuda.rst @@ -0,0 +1,110 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright (c) 2021 NVIDIA Corporation & Affiliates + +CUDA GPU driver +=============== + +The CUDA GPU driver library (**librte_gpu_cuda**) provides support for NVIDIA GPUs. +Information and documentation about these devices can be found on the +`NVIDIA website `__. Help is also provided by the +`NVIDIA CUDA Toolkit developer zone `__. + +Design +------ + +**librte_gpu_cuda** relies on CUDA Driver API (no need for CUDA Runtime API). + +Goal of this driver library is not to provide a wrapper for the whole CUDA Driver API. +Instead, the scope is to implement the generic features of gpudev API. +For a CUDA application, integrating the gpudev library functions using the CUDA driver library +is quite straightforward and doesn't create any compatibility problem. + +Initialization +~~~~~~~~~~~~~~ + +During initialization, CUDA driver library detects NVIDIA physical GPUs on the +system or specified via EAL device options (e.g. ``-a b6:00.0``). +The driver initializes the CUDA driver environment through ``cuInit(0)`` function. +For this reason, it's required to set any CUDA environment configuration before +calling ``rte_eal_init`` function in the DPDK application. + +If the CUDA driver environment has been already initialized, the ``cuInit(0)`` +in CUDA driver library has no effect. + +CUDA Driver sub-contexts +~~~~~~~~~~~~~~~~~~~~~~~~ + +After initialization, a CUDA application can create multiple sub-contexts on GPU +physical devices. Through gpudev library, is possible to register these sub-contexts +in the CUDA driver library as child devices having as parent a GPU physical device. + +CUDA driver library also supports `MPS `__. + +GPU memory management +~~~~~~~~~~~~~~~~~~~~~ + +The CUDA driver library maintains a table of GPU memory addresses allocated +and CPU memory addresses registered associated to the input CUDA context. +Whenever the application tried to deallocate or deregister a memory address, +if the address is not in the table the CUDA driver library will return an error. + +Features +-------- + +- Register new child devices aka new CUDA Driver contexts +- Allocate memory on the GPU +- Register CPU memory to make it visible from GPU + +Minimal requirements +-------------------- + +Minimal requirements to enable the CUDA driver library are: + +- NVIDIA GPU Ampere or Volta +- CUDA 11.4 Driver API or newer + +`GPUDirect RDMA Technology `__ +allows compatible network cards (e.g. Mellanox) to directly send and receive packets +using GPU memory instead of additional memory copies through the CPU system memory. +To enable this technology, system requirements are: + +- `nvidia-peermem `__ module running on the system +- Mellanox Network card ConnectX-5 or newer (BlueField models included) +- DPDK mlx5 PMD enabled +- To reach the best performance, a PCIe switch between GPU and NIC is recommended + +Limitations +----------- + +Supported only on Linux. + +Supported GPUs +-------------- + +The following NVIDIA GPU devices are supported by this CUDA driver: + +- NVIDIA A100 80GB PCIe +- NVIDIA A100 40GB PCIe +- NVIDIA A30 24GB +- NVIDIA A10 24GB +- NVIDIA V100 32GB PCIe +- NVIDIA V100 16GB PCIe + +External references +------------------- + +A good example of how to use the GPU CUDA driver through the gpudev library +is the l2fwd-nv application that can be found `here `__. + +The application is based on vanilla DPDK example l2fwd and it's enhanced with GPU memory +managed through gpudev library and CUDA to launch the swap of packets' MAC addresses workload +on the GPU. + +l2fwd-nv is not intended to be used for performance (testpmd is the good candidate for this). +The goal is to show different use-cases about how a CUDA application can use DPDK to: + +- allocate memory on GPU device using gpudev library +- use that memory to create an external GPU memory mempool +- receive packets directly in GPU memory +- coordinate the workload on the GPU with the network and CPU activity to receive packets +- send modified packets directly from the GPU memory diff --git a/doc/guides/gpus/index.rst b/doc/guides/gpus/index.rst index 1878423239..4b7a420556 100644 --- a/doc/guides/gpus/index.rst +++ b/doc/guides/gpus/index.rst @@ -9,3 +9,4 @@ General-Purpose Graphics Processing Unit Drivers :numbered: overview + cuda diff --git a/drivers/gpu/cuda/cuda.c b/drivers/gpu/cuda/cuda.c new file mode 100644 index 0000000000..5108785bb7 --- /dev/null +++ b/drivers/gpu/cuda/cuda.c @@ -0,0 +1,813 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2021 NVIDIA Corporation & Affiliates + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* NVIDIA GPU vendor */ +#define NVIDIA_GPU_VENDOR_ID (0x10de) + +/* NVIDIA GPU device IDs */ +#define NVIDIA_GPU_A100_40GB_DEVICE_ID (0x20f1) +#define NVIDIA_GPU_A100_80GB_DEVICE_ID (0x20b5) + +#define NVIDIA_GPU_A30_24GB_DEVICE_ID (0x20b7) +#define NVIDIA_GPU_A10_24GB_DEVICE_ID (0x2236) + +#define NVIDIA_GPU_V100_32GB_DEVICE_ID (0x1db6) +#define NVIDIA_GPU_V100_16GB_DEVICE_ID (0x1db4) + +#define CUDA_MAX_ALLOCATION_NUM 512 + +#define GPU_PAGE_SHIFT 16 +#define GPU_PAGE_SIZE (1UL << GPU_PAGE_SHIFT) + +static RTE_LOG_REGISTER_DEFAULT(cuda_logtype, NOTICE); + +/** Helper macro for logging */ +#define rte_gpu_cuda_log(level, fmt, ...) \ + rte_log(RTE_LOG_ ## level, cuda_logtype, fmt "\n", ##__VA_ARGS__) + +#define rte_gpu_cuda_log_debug(fmt, ...) \ + rte_gpu_cuda_log(DEBUG, RTE_STR(__LINE__) ":%s() " fmt, __func__, \ + ##__VA_ARGS__) + +/* NVIDIA GPU address map */ +static struct rte_pci_id pci_id_cuda_map[] = { + { + RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID, + NVIDIA_GPU_A100_40GB_DEVICE_ID) + }, + { + RTE_PCI_DEVICE(NVIDIA_GPU_VENDOR_ID, + NVIDIA_GPU_V100_32GB_DEVICE_ID) + }, + /* {.device_id = 0}, ?? */ +}; + +/* Device private info */ +struct cuda_info { + char gpu_name[RTE_DEV_NAME_MAX_LEN]; + CUdevice cu_dev; +}; + +/* Type of memory allocated by CUDA driver */ +enum mem_type { + GPU_MEM = 0, + CPU_REGISTERED, + GPU_REGISTERED /* Not used yet */ +}; + +/* key associated to a memory address */ +typedef uintptr_t cuda_ptr_key; + +/* Single entry of the memory list */ +struct mem_entry { + CUdeviceptr ptr_d; + void *ptr_h; + size_t size; + struct rte_gpu *dev; + CUcontext ctx; + cuda_ptr_key pkey; + enum mem_type mtype; + struct mem_entry *prev; + struct mem_entry *next; +}; + +static struct mem_entry *mem_alloc_list_head; +static struct mem_entry *mem_alloc_list_tail; +static uint32_t mem_alloc_list_last_elem; + +/* Generate a key from a memory pointer */ +static cuda_ptr_key +get_hash_from_ptr(void *ptr) +{ + return (uintptr_t) ptr; +} + +static uint32_t +mem_list_count_item(void) +{ + return mem_alloc_list_last_elem; +} + +/* Initiate list of memory allocations if not done yet */ +static struct mem_entry * +mem_list_add_item(void) +{ + /* Initiate list of memory allocations if not done yet */ + if (mem_alloc_list_head == NULL) { + mem_alloc_list_head = rte_zmalloc(NULL, + sizeof(struct mem_entry), + RTE_CACHE_LINE_SIZE); + if (mem_alloc_list_head == NULL) { + rte_gpu_cuda_log(ERR, "Failed to allocate memory for memory list.\n"); + return NULL; + } + + mem_alloc_list_head->next = NULL; + mem_alloc_list_head->prev = NULL; + mem_alloc_list_tail = mem_alloc_list_head; + } else { + struct mem_entry *mem_alloc_list_cur = rte_zmalloc(NULL, + sizeof(struct mem_entry), + RTE_CACHE_LINE_SIZE); + + if (mem_alloc_list_cur == NULL) { + rte_gpu_cuda_log(ERR, "Failed to allocate memory for memory list.\n"); + return NULL; + } + + mem_alloc_list_tail->next = mem_alloc_list_cur; + mem_alloc_list_cur->prev = mem_alloc_list_tail; + mem_alloc_list_tail = mem_alloc_list_tail->next; + mem_alloc_list_tail->next = NULL; + } + + mem_alloc_list_last_elem++; + + return mem_alloc_list_tail; +} + +static struct mem_entry * +mem_list_find_item(cuda_ptr_key pk) +{ + struct mem_entry *mem_alloc_list_cur = NULL; + + if (mem_alloc_list_head == NULL) { + rte_gpu_cuda_log(ERR, "Memory list doesn't exist\n"); + return NULL; + } + + if (mem_list_count_item() == 0) { + rte_gpu_cuda_log(ERR, "No items in memory list\n"); + return NULL; + } + + mem_alloc_list_cur = mem_alloc_list_head; + + while (mem_alloc_list_cur != NULL) { + if (mem_alloc_list_cur->pkey == pk) + return mem_alloc_list_cur; + mem_alloc_list_cur = mem_alloc_list_cur->next; + } + + return mem_alloc_list_cur; +} + +static int +mem_list_del_item(cuda_ptr_key pk) +{ + struct mem_entry *mem_alloc_list_cur = NULL; + + mem_alloc_list_cur = mem_list_find_item(pk); + if (mem_alloc_list_cur == NULL) + return -EINVAL; + + /* if key is in head */ + if (mem_alloc_list_cur->prev == NULL) + mem_alloc_list_head = mem_alloc_list_cur->next; + else { + mem_alloc_list_cur->prev->next = mem_alloc_list_cur->next; + if (mem_alloc_list_cur->next != NULL) + mem_alloc_list_cur->next->prev = mem_alloc_list_cur->prev; + } + + rte_free(mem_alloc_list_cur); + + mem_alloc_list_last_elem--; + + return 0; +} + +static int +cuda_dev_info_get(struct rte_gpu *dev, struct rte_gpu_info *info) +{ + int ret = 0; + CUresult res; + struct rte_gpu_info parent_info; + CUexecAffinityParam affinityPrm; + const char *err_string; + struct cuda_info *private; + CUcontext current_ctx; + CUcontext input_ctx; + + if (dev == NULL) + return -EINVAL; + + /* Child initialization time probably called by rte_gpu_add_child() */ + if (dev->mpshared->info.parent != RTE_GPU_ID_NONE && dev->mpshared->dev_private == NULL) { + /* Store current ctx */ + res = cuCtxGetCurrent(¤t_ctx); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, "cuCtxGetCurrent failed with %s.\n", err_string); + + return -1; + } + + /* Set child ctx as current ctx */ + input_ctx = (CUcontext)dev->mpshared->info.context; + res = cuCtxSetCurrent(input_ctx); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, + "cuCtxSetCurrent input failed with %s.\n", + err_string); + + return -1; + } + + /* + * Ctx capacity info + */ + + /* MPS compatible */ + res = cuCtxGetExecAffinity(&affinityPrm, CU_EXEC_AFFINITY_TYPE_SM_COUNT); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, "cuCtxGetExecAffinity failed with %s.\n", err_string); + } + dev->mpshared->info.processor_count = (uint32_t)affinityPrm.param.smCount.val; + + ret = rte_gpu_info_get(dev->mpshared->info.parent, &parent_info); + if (ret) + return -ENODEV; + dev->mpshared->info.total_memory = parent_info.total_memory; + + /* + * GPU Device private info + */ + dev->mpshared->dev_private = rte_zmalloc(NULL, + sizeof(struct cuda_info), + RTE_CACHE_LINE_SIZE); + if (dev->mpshared->dev_private == NULL) { + rte_gpu_cuda_log(ERR, "Failed to allocate memory for GPU process private.\n"); + + return -1; + } + + private = (struct cuda_info *)dev->mpshared->dev_private; + + res = cuCtxGetDevice(&(private->cu_dev)); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, "cuCtxGetDevice failed with %s.\n", err_string); + + return -1; + } + + res = cuDeviceGetName(private->gpu_name, RTE_DEV_NAME_MAX_LEN, private->cu_dev); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, "cuDeviceGetName failed with %s.\n", err_string); + + return -1; + } + + /* Restore original ctx as current ctx */ + res = cuCtxSetCurrent(current_ctx); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, + "cuCtxSetCurrent current failed with %s.\n", + err_string); + + return -1; + } + } + + *info = dev->mpshared->info; + + return 0; +} + +/* + * GPU Memory + */ + +static int +cuda_mem_alloc(struct rte_gpu *dev, size_t size, void **ptr) +{ + CUresult res; + const char *err_string; + CUcontext current_ctx; + CUcontext input_ctx; + unsigned int flag = 1; + + if (dev == NULL || size == 0) + return -EINVAL; + + /* Store current ctx */ + res = cuCtxGetCurrent(¤t_ctx); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, "cuCtxGetCurrent failed with %s.\n", err_string); + + return -1; + } + + /* Set child ctx as current ctx */ + input_ctx = (CUcontext)dev->mpshared->info.context; + res = cuCtxSetCurrent(input_ctx); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, "cuCtxSetCurrent input failed with %s.\n", err_string); + + return -1; + } + + /* Get next memory list item */ + mem_alloc_list_tail = mem_list_add_item(); + if (mem_alloc_list_tail == NULL) + return -ENOMEM; + + /* Allocate memory */ + mem_alloc_list_tail->size = size; + res = cuMemAlloc(&(mem_alloc_list_tail->ptr_d), mem_alloc_list_tail->size); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, + "cuCtxSetCurrent current failed with %s.\n", + err_string); + + return -1; + } + + /* GPUDirect RDMA attribute required */ + res = cuPointerSetAttribute(&flag, + CU_POINTER_ATTRIBUTE_SYNC_MEMOPS, + mem_alloc_list_tail->ptr_d); + if (res != CUDA_SUCCESS) { + rte_gpu_cuda_log(ERR, + "Could not set SYNC MEMOP attribute for GPU memory at %"PRIu32", err %d\n", + (uint32_t) mem_alloc_list_tail->ptr_d, res); + return -1; + } + + mem_alloc_list_tail->pkey = get_hash_from_ptr((void *) mem_alloc_list_tail->ptr_d); + mem_alloc_list_tail->ptr_h = NULL; + mem_alloc_list_tail->size = size; + mem_alloc_list_tail->dev = dev; + mem_alloc_list_tail->ctx = (CUcontext)dev->mpshared->info.context; + mem_alloc_list_tail->mtype = GPU_MEM; + + /* Restore original ctx as current ctx */ + res = cuCtxSetCurrent(current_ctx); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, "cuCtxSetCurrent current failed with %s.\n", err_string); + + return -1; + } + + *ptr = (void *) mem_alloc_list_tail->ptr_d; + + return 0; +} + +static int +cuda_mem_register(struct rte_gpu *dev, size_t size, void *ptr) +{ + CUresult res; + const char *err_string; + CUcontext current_ctx; + CUcontext input_ctx; + unsigned int flag = 1; + int use_ptr_h = 0; + + if (dev == NULL || size == 0 || ptr == NULL) + return -EINVAL; + + /* Store current ctx */ + res = cuCtxGetCurrent(¤t_ctx); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, "cuCtxGetCurrent failed with %s.\n", err_string); + + return -1; + } + + /* Set child ctx as current ctx */ + input_ctx = (CUcontext)dev->mpshared->info.context; + res = cuCtxSetCurrent(input_ctx); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, "cuCtxSetCurrent input failed with %s.\n", err_string); + + return -1; + } + + /* Get next memory list item */ + mem_alloc_list_tail = mem_list_add_item(); + if (mem_alloc_list_tail == NULL) + return -ENOMEM; + + /* Allocate memory */ + mem_alloc_list_tail->size = size; + mem_alloc_list_tail->ptr_h = ptr; + + res = cuMemHostRegister(mem_alloc_list_tail->ptr_h, + mem_alloc_list_tail->size, + CU_MEMHOSTREGISTER_PORTABLE | CU_MEMHOSTREGISTER_DEVICEMAP); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, + "cuMemHostRegister failed with %s ptr %p size %zd.\n", + err_string, mem_alloc_list_tail->ptr_h, mem_alloc_list_tail->size); + + return -1; + } + + res = cuDeviceGetAttribute(&(use_ptr_h), + CU_DEVICE_ATTRIBUTE_CAN_USE_HOST_POINTER_FOR_REGISTERED_MEM, + ((struct cuda_info *)(dev->mpshared->dev_private))->cu_dev); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, "cuDeviceGetAttribute failed with %s.\n", + err_string + ); + + return -1; + } + + if (use_ptr_h == 0) { + res = cuMemHostGetDevicePointer(&(mem_alloc_list_tail->ptr_d), + mem_alloc_list_tail->ptr_h, + 0); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, + "cuMemHostGetDevicePointer failed with %s.\n", + err_string); + + return -1; + } + + if ((uintptr_t) mem_alloc_list_tail->ptr_d != (uintptr_t) mem_alloc_list_tail->ptr_h) { + rte_gpu_cuda_log(ERR, + "Host input pointer is different wrt GPU registered pointer\n"); + return -1; + } + } else { + mem_alloc_list_tail->ptr_d = (CUdeviceptr) mem_alloc_list_tail->ptr_h; + } + + /* GPUDirect RDMA attribute required */ + res = cuPointerSetAttribute(&flag, + CU_POINTER_ATTRIBUTE_SYNC_MEMOPS, + mem_alloc_list_tail->ptr_d); + if (res != CUDA_SUCCESS) { + rte_gpu_cuda_log(ERR, + "Could not set SYNC MEMOP attribute for GPU memory at %"PRIu32", err %d\n", + (uint32_t) mem_alloc_list_tail->ptr_d, res); + return -1; + } + + mem_alloc_list_tail->pkey = get_hash_from_ptr((void *) mem_alloc_list_tail->ptr_h); + mem_alloc_list_tail->size = size; + mem_alloc_list_tail->dev = dev; + mem_alloc_list_tail->ctx = (CUcontext)dev->mpshared->info.context; + mem_alloc_list_tail->mtype = CPU_REGISTERED; + + /* Restore original ctx as current ctx */ + res = cuCtxSetCurrent(current_ctx); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, + "cuCtxSetCurrent current failed with %s.\n", + err_string); + + return -1; + } + + return 0; +} + +static int +cuda_mem_free(struct rte_gpu *dev, void *ptr) +{ + CUresult res; + struct mem_entry *mem_item; + const char *err_string; + cuda_ptr_key hk; + + if (dev == NULL || ptr == NULL) + return -EINVAL; + + hk = get_hash_from_ptr((void *) ptr); + + mem_item = mem_list_find_item(hk); + if (mem_item == NULL) { + rte_gpu_cuda_log(ERR, "Memory address 0x%p not found in driver memory\n", ptr); + return -1; + } + + if (mem_item->mtype == GPU_MEM) { + res = cuMemFree(mem_item->ptr_d); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, "cuMemFree current failed with %s.\n", err_string); + + return -1; + } + + return mem_list_del_item(hk); + } + + rte_gpu_cuda_log(ERR, "Memory type %d not supported\n", mem_item->mtype); + return -1; +} + +static int +cuda_mem_unregister(struct rte_gpu *dev, void *ptr) +{ + CUresult res; + struct mem_entry *mem_item; + const char *err_string; + cuda_ptr_key hk; + + if (dev == NULL || ptr == NULL) + return -EINVAL; + + hk = get_hash_from_ptr((void *) ptr); + + mem_item = mem_list_find_item(hk); + if (mem_item == NULL) { + rte_gpu_cuda_log(ERR, "Memory address 0x%p not nd in driver memory\n", ptr); + return -1; + } + + if (mem_item->mtype == CPU_REGISTERED) { + res = cuMemHostUnregister(ptr); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, + "cuMemHostUnregister current failed with %s.\n", + err_string); + + return -1; + } + + return mem_list_del_item(hk); + } + + rte_gpu_cuda_log(ERR, "Memory type %d not supported\n", mem_item->mtype); + return -1; +} + +static int +cuda_dev_close(struct rte_gpu *dev) +{ + if (dev == NULL) + return -EINVAL; + + rte_free(dev->mpshared->dev_private); + + return 0; +} + +static int +cuda_wmb(struct rte_gpu *dev) +{ + CUresult res; + const char *err_string; + CUcontext current_ctx; + CUcontext input_ctx; + + if (dev == NULL) + return -EINVAL; + + /* Store current ctx */ + res = cuCtxGetCurrent(¤t_ctx); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, "cuCtxGetCurrent failed with %s.\n", err_string); + + return -1; + } + + /* Set child ctx as current ctx */ + input_ctx = (CUcontext)dev->mpshared->info.context; + res = cuCtxSetCurrent(input_ctx); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, "cuCtxSetCurrent input failed with %s.\n", err_string); + + return -1; + } + + res = cuFlushGPUDirectRDMAWrites(CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TARGET_CURRENT_CTX, + CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_ALL_DEVICES); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, + "cuFlushGPUDirectRDMAWrites current failed with %s.\n", + err_string); + + return -1; + } + + /* Restore original ctx as current ctx */ + res = cuCtxSetCurrent(current_ctx); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, + "cuCtxSetCurrent current failed with %s.\n", + err_string); + + return -1; + } + + return 0; +} + +static int +cuda_gpu_probe(__rte_unused struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) +{ + struct rte_gpu *dev = NULL; + CUresult res; + CUdevice cu_dev_id; + CUcontext pctx; + char dev_name[RTE_DEV_NAME_MAX_LEN]; + const char *err_string; + int processor_count = 0; + struct cuda_info *private; + + if (pci_dev == NULL) { + rte_gpu_cuda_log(ERR, "NULL PCI device"); + return -EINVAL; + } + + rte_pci_device_name(&pci_dev->addr, dev_name, sizeof(dev_name)); + + /* Allocate memory to be used privately by drivers */ + dev = rte_gpu_allocate(pci_dev->device.name); + if (dev == NULL) + return -ENODEV; + + /* Initialize values only for the first CUDA driver call */ + if (dev->mpshared->info.dev_id == 0) { + mem_alloc_list_head = NULL; + mem_alloc_list_tail = NULL; + mem_alloc_list_last_elem = 0; + } + + /* Fill HW specific part of device structure */ + dev->device = &pci_dev->device; + dev->mpshared->info.numa_node = pci_dev->device.numa_node; + + /* + * GPU Device init + */ + + /* + * Required to initialize the CUDA Driver. + * Multiple calls of cuInit() will return immediately + * without making any relevant change + */ + cuInit(0); + + /* Get NVIDIA GPU Device descriptor */ + res = cuDeviceGetByPCIBusId(&cu_dev_id, dev->device->name); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, + "cuDeviceGetByPCIBusId name %s failed with %d: %s.\n", + dev->device->name, res, err_string); + + return -1; + } + + res = cuDevicePrimaryCtxRetain(&pctx, cu_dev_id); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, + "cuDevicePrimaryCtxRetain name %s failed with %d: %s.\n", + dev->device->name, res, err_string); + + return -1; + } + + dev->mpshared->info.context = (uint64_t) pctx; + + /* + * GPU Device generic info + */ + + /* Processor count */ + res = cuDeviceGetAttribute(&(processor_count), + CU_DEVICE_ATTRIBUTE_MULTIPROCESSOR_COUNT, + cu_dev_id); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, + "cuDeviceGetAttribute failed with %s.\n", + err_string); + + return -1; + } + dev->mpshared->info.processor_count = (uint32_t)processor_count; + + /* Total memory */ + res = cuDeviceTotalMem(&dev->mpshared->info.total_memory, cu_dev_id); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, + "cuDeviceTotalMem failed with %s.\n", + err_string); + + return -1; + } + + /* + * GPU Device private info + */ + dev->mpshared->dev_private = rte_zmalloc(NULL, + sizeof(struct cuda_info), + RTE_CACHE_LINE_SIZE); + if (dev->mpshared->dev_private == NULL) { + rte_gpu_cuda_log(ERR, + "Failed to allocate memory for GPU process private.\n"); + + return -1; + } + + private = (struct cuda_info *)dev->mpshared->dev_private; + private->cu_dev = cu_dev_id; + res = cuDeviceGetName(private->gpu_name, + RTE_DEV_NAME_MAX_LEN, + cu_dev_id); + if (res != CUDA_SUCCESS) { + cuGetErrorString(res, &(err_string)); + rte_gpu_cuda_log(ERR, + "cuDeviceGetName failed with %s.\n", + err_string); + + return -1; + } + + dev->ops.dev_info_get = cuda_dev_info_get; + dev->ops.dev_close = cuda_dev_close; + dev->ops.mem_alloc = cuda_mem_alloc; + dev->ops.mem_free = cuda_mem_free; + dev->ops.mem_register = cuda_mem_register; + dev->ops.mem_unregister = cuda_mem_unregister; + dev->ops.wmb = cuda_wmb; + + rte_gpu_complete_new(dev); + + rte_gpu_cuda_log_debug("dev id = %u name = %s\n", dev->mpshared->info.dev_id, private->gpu_name); + + return 0; +} + +static int +cuda_gpu_remove(struct rte_pci_device *pci_dev) +{ + struct rte_gpu *dev; + int ret; + uint8_t gpu_id; + + if (pci_dev == NULL) + return -EINVAL; + + dev = rte_gpu_get_by_name(pci_dev->device.name); + if (dev == NULL) { + rte_gpu_cuda_log(ERR, + "Couldn't find HW dev \"%s\" to uninitialise it", + pci_dev->device.name); + return -ENODEV; + } + gpu_id = dev->mpshared->info.dev_id; + + /* release dev from library */ + ret = rte_gpu_release(dev); + if (ret) + rte_gpu_cuda_log(ERR, "Device %i failed to uninit: %i", gpu_id, ret); + + rte_gpu_cuda_log_debug("Destroyed dev = %u", gpu_id); + + return 0; +} + +static struct rte_pci_driver rte_cuda_driver = { + .id_table = pci_id_cuda_map, + .drv_flags = RTE_PCI_DRV_WC_ACTIVATE, + .probe = cuda_gpu_probe, + .remove = cuda_gpu_remove, +}; + +RTE_PMD_REGISTER_PCI(gpu_cuda, rte_cuda_driver); +RTE_PMD_REGISTER_PCI_TABLE(gpu_cuda, pci_id_cuda_map); +RTE_PMD_REGISTER_KMOD_DEP(gpu_cuda, "* nvidia & (nv_peer_mem | nvpeer_mem)"); diff --git a/drivers/gpu/cuda/meson.build b/drivers/gpu/cuda/meson.build new file mode 100644 index 0000000000..f084bbcf83 --- /dev/null +++ b/drivers/gpu/cuda/meson.build @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (c) 2021 NVIDIA Corporation & Affiliates + +if not is_linux + build = false + reason = 'only supported on Linux' +endif + +cuda_dep = dependency('cuda', version : '>=11.4', modules: ['cuda'], required: false) + +if not cuda_dep.found() + build = false + reason = 'missing dependency, "cuda >= 11.4"' + subdir_done() +endif + +ext_deps += cuda_dep + +deps += ['gpudev','pci','bus_pci', 'hash'] +sources = files('cuda.c') diff --git a/drivers/gpu/cuda/version.map b/drivers/gpu/cuda/version.map new file mode 100644 index 0000000000..4a76d1d52d --- /dev/null +++ b/drivers/gpu/cuda/version.map @@ -0,0 +1,3 @@ +DPDK_21 { + local: *; +}; diff --git a/drivers/gpu/meson.build b/drivers/gpu/meson.build index e51ad3381b..601bedcd61 100644 --- a/drivers/gpu/meson.build +++ b/drivers/gpu/meson.build @@ -1,4 +1,4 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright (c) 2021 NVIDIA Corporation & Affiliates -drivers = [] +drivers = [ 'cuda' ] -- 2.17.1