From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 465E0A0C4B; Tue, 9 Nov 2021 10:42:13 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 35BD940E03; Tue, 9 Nov 2021 10:42:13 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 404C34068B for ; Tue, 9 Nov 2021 10:42:12 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A93ClBC014217 for ; Tue, 9 Nov 2021 01:42:11 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=LW7HFwC5rLR/Cw8duAIF0pPF4WXBD0MUG2bHhJwPmfs=; b=Z76KhtlC7z1I/bm9qoIEKm6zc3NlH1hn2gVYb7prK1QXLJFp/VAP6gGFAQ1+8/9Ts7B0 6Ra4ysav8nunufseLFBeGCBZ4Rbw+4PDXoKsjgJ/5d/bIinI7E8HMQ1/cauwBNomdeUN gYrBa4YUsV0yjsfFxOTTAEfP1YBLM9kzda4SlezUByb5djhQVMsOl5Be9d0iWLv2p843 hfyjZSdv1fo+CBgpJkxSBsVXLOpLofv62MTvH1wisde/F16BRzLgadh8IYLwSv3pEipf lPbUMHawRILug6ZBI8QQq0XneBC+pnvA5kHfBiiwXTHis32bqW5ZHGZyasspnVMQo6Mr QQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3c7gvg1j5d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 09 Nov 2021 01:42:11 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 9 Nov 2021 01:42:09 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 9 Nov 2021 01:42:09 -0800 Received: from satheeshpaullabpc.marvell.com (unknown [10.28.34.33]) by maili.marvell.com (Postfix) with ESMTP id DC06B3F7074; Tue, 9 Nov 2021 01:42:07 -0800 (PST) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Satheesh Paul Date: Tue, 9 Nov 2021 15:12:03 +0530 Message-ID: <20211109094204.2343402-1-psatheesh@marvell.com> X-Mailer: git-send-email 2.25.4 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: e5ya442JYa1sBGQrA6ve-eVMg5l-eUqa X-Proofpoint-ORIG-GUID: e5ya442JYa1sBGQrA6ve-eVMg5l-eUqa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-09_03,2021-11-08_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH 22.02 1/2] common/cnxk: support to set channel mask for SDP interfaces X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satheesh Paul ROC changes to support setting channel mask for SDP interfaces. Signed-off-by: Satheesh Paul --- drivers/common/cnxk/roc_npc.c | 13 +++++++++++++ drivers/common/cnxk/roc_npc.h | 3 +++ drivers/common/cnxk/roc_npc_mcam.c | 10 ++++++++++ drivers/common/cnxk/roc_npc_priv.h | 3 +++ 4 files changed, 29 insertions(+) diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c index 503c74748f..d18dfd4259 100644 --- a/drivers/common/cnxk/roc_npc.c +++ b/drivers/common/cnxk/roc_npc.c @@ -1152,6 +1152,19 @@ roc_npc_flow_create(struct roc_npc *roc_npc, const struct roc_npc_attr *attr, int rc; npc->channel = roc_npc->channel; + npc->is_sdp_link = roc_nix_is_sdp(roc_npc->roc_nix); + if (npc->is_sdp_link) { + if (roc_npc->is_sdp_mask_set) { + npc->sdp_channel = roc_npc->sdp_channel; + npc->sdp_channel_mask = roc_npc->sdp_channel_mask; + } else { + /* By default set the channel and mask to cover + * the whole SDP channel range. + */ + npc->sdp_channel = (uint16_t)NIX_CHAN_SDP_CH_START; + npc->sdp_channel_mask = (uint16_t)NIX_CHAN_SDP_CH_START; + } + } flow = plt_zmalloc(sizeof(*flow), 0); if (flow == NULL) { diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h index e13d557136..8c24126ae8 100644 --- a/drivers/common/cnxk/roc_npc.h +++ b/drivers/common/cnxk/roc_npc.h @@ -195,6 +195,9 @@ struct roc_npc { uint64_t rx_parse_nibble; /* Parsed RSS Flowkey cfg for current flow being created */ uint32_t flowkey_cfg_state; + bool is_sdp_mask_set; + uint16_t sdp_channel; + uint16_t sdp_channel_mask; #define ROC_NPC_MEM_SZ (5 * 1024) uint8_t reserved[ROC_NPC_MEM_SZ]; diff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c index ba7f89b45b..80851d6f9f 100644 --- a/drivers/common/cnxk/roc_npc_mcam.c +++ b/drivers/common/cnxk/roc_npc_mcam.c @@ -575,6 +575,16 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow, flow->npc_action |= (uint64_t)pf_func << 4; flow->mcam_data[0] |= (uint64_t)inl_dev->channel; flow->mcam_mask[0] |= (uint64_t)inl_dev->chan_mask; + } else if (npc->is_sdp_link) { + req->entry_data.kw[0] &= ~(GENMASK(11, 0)); + req->entry_data.kw_mask[0] &= ~(GENMASK(11, 0)); + req->entry_data.kw[0] |= (uint64_t)npc->sdp_channel; + req->entry_data.kw_mask[0] |= + (uint64_t)npc->sdp_channel_mask; + flow->mcam_data[0] &= ~(GENMASK(11, 0)); + flow->mcam_mask[0] &= ~(GENMASK(11, 0)); + flow->mcam_data[0] |= (uint64_t)npc->sdp_channel; + flow->mcam_mask[0] |= (uint64_t)npc->sdp_channel_mask; } else { req->entry_data.kw[0] |= (uint64_t)npc->channel; req->entry_data.kw_mask[0] |= (BIT_ULL(12) - 1); diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h index 712302bc5c..86c10ea082 100644 --- a/drivers/common/cnxk/roc_npc_priv.h +++ b/drivers/common/cnxk/roc_npc_priv.h @@ -360,6 +360,9 @@ struct npc { uint32_t keyw[NPC_MAX_INTF]; /* max key + data len bits */ uint32_t mcam_entries; /* mcam entries supported */ uint16_t channel; /* RX Channel number */ + bool is_sdp_link; + uint16_t sdp_channel; + uint16_t sdp_channel_mask; uint32_t rss_grps; /* rss groups supported */ uint16_t flow_prealloc_size; /* Pre allocated mcam size */ uint16_t flow_max_priority; /* Max priority for flow */ -- 2.25.4