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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT046.mail.protection.outlook.com (10.13.172.121) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4690.15 via Frontend Transport; Thu, 11 Nov 2021 16:16:51 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 11 Nov 2021 16:16:49 +0000 From: Gregory Etelson To: , , CC: , Matan Azrad Subject: [PATCH] net/mlx5: fix integrity conversion scheme Date: Thu, 11 Nov 2021 18:16:26 +0200 Message-ID: <20211111161627.10436-1-getelson@nvidia.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c7faf09d-0fb8-4e5f-00c7-08d9a52eab6d X-MS-TrafficTypeDiagnostic: CH2PR12MB3701: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4714; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(54906003)(110136005)(8936002)(6636002)(508600001)(5660300002)(36756003)(316002)(7696005)(7636003)(70586007)(356005)(70206006)(2906002)(336012)(83380400001)(1076003)(55016002)(6286002)(2616005)(8676002)(47076005)(82310400003)(4326008)(450100002)(86362001)(6666004)(26005)(107886003)(426003)(36860700001)(186003)(16526019)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2021 16:16:51.1582 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c7faf09d-0fb8-4e5f-00c7-08d9a52eab6d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB3701 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org RTE flow integrity API provides top-level packet validations. RTE integrity bits are not always translated one-to-one to hardware integrity bits. For example RTE l3_ok and l4_ok integrity bits require 2 hardware integrity bits each. The patch fixes RTE l3_ok and l4_ok bits translation to match ConnectX-6 hardware. Cc: stable@dpdk.org Fixes: 79f8952783d0 ("net/mlx5: support integrity flow item") Signed-off-by: Gregory Etelson --- drivers/net/mlx5/mlx5_flow_dv.c | 79 +++++++++++++++------------------ 1 file changed, 37 insertions(+), 42 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 28911d6f0f..1b4e15dff1 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -12106,34 +12106,24 @@ flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask, void *headers_m, void *headers_v) { if (mask->l4_ok) { - /* application l4_ok filter aggregates all hardware l4 filters - * therefore hw l4_checksum_ok must be implicitly added here. + /* RTE l4_ok filter aggregates hardware l4_ok and + * l4_checksum_ok filters. + * Positive RTE l4_ok match requires hardware match on both L4 + * hardware integrity bits. + * For negative match, check hardware l4_checksum_ok bit only, + * because hardware sets that bit to 0 for all packets + * with bad L4. */ - struct rte_flow_item_integrity local_item; - - local_item.l4_csum_ok = 1; - MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, - local_item.l4_csum_ok); if (value->l4_ok) { - /* application l4_ok = 1 matches sets both hw flags - * l4_ok and l4_checksum_ok flags to 1. - */ - MLX5_SET(fte_match_set_lyr_2_4, headers_v, - l4_checksum_ok, local_item.l4_csum_ok); - MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, - mask->l4_ok); - MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, - value->l4_ok); - } else { - /* application l4_ok = 0 matches on hw flag - * l4_checksum_ok = 0 only. - */ - MLX5_SET(fte_match_set_lyr_2_4, headers_v, - l4_checksum_ok, 0); + MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, 1); + MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, 1); } - } else if (mask->l4_csum_ok) { - MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, - mask->l4_csum_ok); + MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1); + MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok, + !!value->l4_ok); + } + if (mask->l4_csum_ok) { + MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1); MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok, value->l4_csum_ok); } @@ -12145,28 +12135,33 @@ flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask, void *headers_m, void *headers_v, bool is_ipv4) { if (mask->l3_ok) { - /* application l3_ok filter aggregates all hardware l3 filters - * therefore hw ipv4_checksum_ok must be implicitly added here. + /* RTE l3_ok filter aggregates for IPv4 hardware l3_ok and + * ipv4_csum_ok filters. + * Positive RTE l3_ok match requires hardware match on both L3 + * hardware integrity bits. + * For negative match, check hardware l3_csum_ok bit only, + * because hardware sets that bit to 0 for all packets + * with bad L3. */ - struct rte_flow_item_integrity local_item; - - local_item.ipv4_csum_ok = !!is_ipv4; - MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, - local_item.ipv4_csum_ok); - if (value->l3_ok) { + if (is_ipv4) { + if (value->l3_ok) { + MLX5_SET(fte_match_set_lyr_2_4, headers_m, + l3_ok, 1); + MLX5_SET(fte_match_set_lyr_2_4, headers_v, + l3_ok, 1); + } + MLX5_SET(fte_match_set_lyr_2_4, headers_m, + ipv4_checksum_ok, 1); MLX5_SET(fte_match_set_lyr_2_4, headers_v, - ipv4_checksum_ok, local_item.ipv4_csum_ok); - MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, - mask->l3_ok); + ipv4_checksum_ok, !!value->l3_ok); + } else { + MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, 1); MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok, value->l3_ok); - } else { - MLX5_SET(fte_match_set_lyr_2_4, headers_v, - ipv4_checksum_ok, 0); } - } else if (mask->ipv4_csum_ok) { - MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, - mask->ipv4_csum_ok); + } + if (mask->ipv4_csum_ok) { + MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, 1); MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok, value->ipv4_csum_ok); } -- 2.33.1