From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6E0EDA0C47; Wed, 17 Nov 2021 01:23:13 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D0A9B41161; Wed, 17 Nov 2021 01:22:55 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 4780641155 for ; Wed, 17 Nov 2021 01:22:52 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1AGLwcGk008411 for ; Tue, 16 Nov 2021 16:22:51 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=QotEOaZQG2ChvN+vW+KkzXs9G1ZLoyfYlYVwxcYKaqo=; b=R19r0RlpKPmZR3hD9sQNfyalOrbivTILPgQ1LpkthYT3Uv6yckipmT6awrxxLdRcw/RY G9PyyFzn1XdsskR9bXu5elT5YvfJ7wKBcf7OteNAn4gkB2Z6gPxI1n3sONts3jMoETzE kmHihYWf6R65BZSjBtLPV4gazDUDUbbruPL3HP+AwgxzCDmEaL+1+zo3XNxnd5CGD0+s kq6/TskF70LdWu8jYGqnvXFeJCyBWP6bBhlMcYN9KhhCOF1dK9sKFPooA8Bn5SJQy5EN VTEAyxsbnJ7lO9pNllhV1awwO/OGLm0WCzpyKkv8kriShVWtHGFqIXoJ4LuL9rp78HDT yw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3cc85xc9v4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 16 Nov 2021 16:22:51 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 16 Nov 2021 16:22:49 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 16 Nov 2021 16:22:49 -0800 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id A15C63F705B; Tue, 16 Nov 2021 16:22:48 -0800 (PST) From: Tomasz Duszynski To: CC: , Tomasz Duszynski Subject: [PATCH 04/10] raw/cnxk_gpio: support queue setup Date: Wed, 17 Nov 2021 01:21:49 +0100 Message-ID: <20211117002155.293267-5-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211117002155.293267-1-tduszynski@marvell.com> References: <20211117002155.293267-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: CUM7hSzeC-v3INQx2ddZmOwYDhWj-Omq X-Proofpoint-ORIG-GUID: CUM7hSzeC-v3INQx2ddZmOwYDhWj-Omq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-16_07,2021-11-16_01,2020-04-07_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for queue setup. Signed-off-by: Tomasz Duszynski --- drivers/raw/cnxk_gpio/cnxk_gpio.c | 80 +++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/raw/cnxk_gpio/cnxk_gpio.c b/drivers/raw/cnxk_gpio/cnxk_gpio.c index 84be7f861e..98b5dd9cd8 100644 --- a/drivers/raw/cnxk_gpio/cnxk_gpio.c +++ b/drivers/raw/cnxk_gpio/cnxk_gpio.c @@ -134,6 +134,85 @@ cnxk_gpio_read_attr_int(char *attr, int *val) return 0; } +static int +cnxk_gpio_write_attr(const char *attr, const char *val) +{ + FILE *fp; + int ret; + + if (!val) + return -EINVAL; + + fp = fopen(attr, "w"); + if (!fp) + return -errno; + + ret = fprintf(fp, "%s", val); + if (ret < 0) { + fclose(fp); + return ret; + } + + ret = fclose(fp); + if (ret) + return -errno; + + return 0; +} + +static int +cnxk_gpio_write_attr_int(const char *attr, int val) +{ + char buf[CNXK_GPIO_BUFSZ]; + + snprintf(buf, sizeof(buf), "%d", val); + + return cnxk_gpio_write_attr(attr, buf); +} + +static struct cnxk_gpio * +cnxk_gpio_lookup(struct cnxk_gpiochip *gpiochip, uint16_t queue) +{ + if (queue >= gpiochip->num_gpios) + return NULL; + + return gpiochip->gpios[queue]; +} + +static int +cnxk_gpio_queue_setup(struct rte_rawdev *dev, uint16_t queue_id, + rte_rawdev_obj_t queue_conf, size_t queue_conf_size) +{ + struct cnxk_gpiochip *gpiochip = dev->dev_private; + char buf[CNXK_GPIO_BUFSZ]; + struct cnxk_gpio *gpio; + int ret; + + RTE_SET_USED(queue_conf); + RTE_SET_USED(queue_conf_size); + + gpio = cnxk_gpio_lookup(gpiochip, queue_id); + if (gpio) + return -EEXIST; + + gpio = rte_zmalloc(NULL, sizeof(*gpio), 0); + if (!gpio) + return -ENOMEM; + gpio->num = queue_id + gpiochip->base; + gpio->gpiochip = gpiochip; + + snprintf(buf, sizeof(buf), "%s/export", CNXK_GPIO_CLASS_PATH); + ret = cnxk_gpio_write_attr_int(buf, gpio->num); + if (ret) { + rte_free(gpio); + return ret; + } + + gpiochip->gpios[queue_id] = gpio; + + return 0; +} + static int cnxk_gpio_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id, rte_rawdev_obj_t queue_conf, size_t queue_conf_size) @@ -163,6 +242,7 @@ cnxk_gpio_queue_count(struct rte_rawdev *dev) static const struct rte_rawdev_ops cnxk_gpio_rawdev_ops = { .queue_def_conf = cnxk_gpio_queue_def_conf, .queue_count = cnxk_gpio_queue_count, + .queue_setup = cnxk_gpio_queue_setup, }; static int -- 2.25.1