From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7D25A0C47; Wed, 17 Nov 2021 01:23:24 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C56274117A; Wed, 17 Nov 2021 01:22:58 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 9C8BE4115F for ; Wed, 17 Nov 2021 01:22:55 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1AGJnS4V008504 for ; Tue, 16 Nov 2021 16:22:54 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=s3Ae8ZAYexJkQow3+yjvoK4hDQORdpuCqSMxaEKodNo=; b=Y3v21J3wo/lebN0MBsT06wDt6NCFs+flOVsTTdvZYiMnVZts5BU+BXW9Bayn7UM03klt mytYPnqHTbm3Gvd6eZte9NQMCF+jxILLYNVEGGLG2BikFYMKwKVI/L/YZkdrSc4w/iBm ql2WlIqbRFVK5NOzqXi8VpY0VqByoztQ/Apzhd4Ekv2wqJxmF8jtLdbdNBRGIouffTJG 7ufjITbjqL+HTtaf3Bus3UcHT1NIwV6hD66ziJab9kYn9NJDov60Y7yqt+nDtVMXH4WA K9rEa5Gps4FaFJI0AxHe6OX8LntUrK3fCjK3mVrJAm19B+GWg1OUJh5q/tGaChhb8X8K OA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3cck4h8yh6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 16 Nov 2021 16:22:54 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 16 Nov 2021 16:22:53 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 16 Nov 2021 16:22:53 -0800 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 103893F705B; Tue, 16 Nov 2021 16:22:51 -0800 (PST) From: Tomasz Duszynski To: CC: , Tomasz Duszynski Subject: [PATCH 06/10] raw/cnxk_gpio: support enqueuing buffers Date: Wed, 17 Nov 2021 01:21:51 +0100 Message-ID: <20211117002155.293267-7-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211117002155.293267-1-tduszynski@marvell.com> References: <20211117002155.293267-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: VslG-WqFpvw2gHf5FwgjG4iRg-wShK4d X-Proofpoint-GUID: VslG-WqFpvw2gHf5FwgjG4iRg-wShK4d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-16_07,2021-11-16_01,2020-04-07_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add dummy support for enqueuing buffers. Signed-off-by: Tomasz Duszynski --- drivers/raw/cnxk_gpio/cnxk_gpio.c | 46 +++++++++++++++++++++++ drivers/raw/cnxk_gpio/cnxk_gpio.h | 1 + drivers/raw/cnxk_gpio/meson.build | 1 + drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h | 38 +++++++++++++++++++ 4 files changed, 86 insertions(+) create mode 100644 drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h diff --git a/drivers/raw/cnxk_gpio/cnxk_gpio.c b/drivers/raw/cnxk_gpio/cnxk_gpio.c index 8ac3c5e1be..c08ccdfbb8 100644 --- a/drivers/raw/cnxk_gpio/cnxk_gpio.c +++ b/drivers/raw/cnxk_gpio/cnxk_gpio.c @@ -14,6 +14,7 @@ #include #include "cnxk_gpio.h" +#include "rte_pmd_cnxk_gpio.h" #define CNXK_GPIO_BUFSZ 128 #define CNXK_GPIO_CLASS_PATH "/sys/class/gpio" @@ -262,7 +263,52 @@ cnxk_gpio_queue_count(struct rte_rawdev *dev) return gpiochip->num_gpios; } +static int +cnxk_gpio_process_buf(struct cnxk_gpio *gpio, struct rte_rawdev_buf *rbuf) +{ + struct cnxk_gpio_msg *msg = rbuf->buf_addr; + void *rsp = NULL; + + switch (msg->type) { + default: + return -EINVAL; + } + + /* get rid of last response if any */ + if (gpio->rsp) { + RTE_LOG(WARNING, PMD, "previous response got overwritten\n"); + rte_free(gpio->rsp); + } + gpio->rsp = rsp; + + return 0; +} + +static int +cnxk_gpio_enqueue_bufs(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers, + unsigned int count, rte_rawdev_obj_t context) +{ + struct cnxk_gpiochip *gpiochip = dev->dev_private; + unsigned int queue = (size_t)context; + struct cnxk_gpio *gpio; + int ret; + + if (count == 0) + return 0; + + gpio = cnxk_gpio_lookup(gpiochip, queue); + if (!gpio) + return -ENODEV; + + ret = cnxk_gpio_process_buf(gpio, buffers[0]); + if (ret) + return ret; + + return 1; +} + static const struct rte_rawdev_ops cnxk_gpio_rawdev_ops = { + .enqueue_bufs = cnxk_gpio_enqueue_bufs, .queue_def_conf = cnxk_gpio_queue_def_conf, .queue_count = cnxk_gpio_queue_count, .queue_setup = cnxk_gpio_queue_setup, diff --git a/drivers/raw/cnxk_gpio/cnxk_gpio.h b/drivers/raw/cnxk_gpio/cnxk_gpio.h index 0ee9789a01..1eadde965e 100644 --- a/drivers/raw/cnxk_gpio/cnxk_gpio.h +++ b/drivers/raw/cnxk_gpio/cnxk_gpio.h @@ -7,6 +7,7 @@ struct cnxk_gpio { struct cnxk_gpiochip *gpiochip; + void *rsp; int num; }; diff --git a/drivers/raw/cnxk_gpio/meson.build b/drivers/raw/cnxk_gpio/meson.build index 9a7e716c1e..3fbfdd838c 100644 --- a/drivers/raw/cnxk_gpio/meson.build +++ b/drivers/raw/cnxk_gpio/meson.build @@ -6,3 +6,4 @@ deps += ['bus_vdev', 'common_cnxk', 'rawdev', 'kvargs'] sources = files( 'cnxk_gpio.c', ) +headers = files('rte_pmd_cnxk_gpio.h') diff --git a/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h b/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h new file mode 100644 index 0000000000..c71065e10c --- /dev/null +++ b/drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _RTE_PMD_CNXK_GPIO_H_ +#define _RTE_PMD_CNXK_GPIO_H_ + +/** + * @file rte_pmd_cnxk_gpio.h + * + * Marvell GPIO PMD specific structures and interface + * + * This API allows applications to manage GPIOs in user space along with + * installing interrupt handlers for low latency signal processing. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Available message types */ +enum cnxk_gpio_msg_type { + /** Invalid message type */ + CNXK_GPIO_MSG_TYPE_INVALID, +}; + +struct cnxk_gpio_msg { + /** Message type */ + enum cnxk_gpio_msg_type type; + /** Message data passed to PMD or received from PMD */ + void *data; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_PMD_CNXK_GPIO_H_ */ -- 2.25.1