From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A08ECA0548; Sun, 28 Nov 2021 16:46:08 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EE3364068E; Sun, 28 Nov 2021 16:46:07 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 5C58C4068A for ; Sun, 28 Nov 2021 16:46:06 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1ASEIsI4014713; Sun, 28 Nov 2021 07:46:05 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=snrDgh3yEwI4XcpDHf63fNew4He6v8pE49VauoXZeY4=; b=gLJ5bHyt73QgTIJPeJG60YxuKJkxC/TuvBOJ7npjkDYFMION0Gc/EzIuedmLDZf5Iqk8 aH0HLMQQ/kq0Mk/JhkGMcMah8G6sJBUnxXU0AFko3+SrrE0PVuvfd5YR0bcdOIlQoAQP QnKy0DDaBX1b6+GJ+slXwwx3biXg9p9IVJamredSZwS0IRMiRGMpF+JncD+TBq4Pzgk8 4e6ZeVzw3p4zPhVBmFCGcci8StMLXOSMTvFPdcH9Y5Lf8RqrA/d+0cRjeBYjJ6bZUd6q f6fxWt4nBVzC+H/8dOJfj4m79p4Fs/pTMXbrB7VqU54Ozi7T7ogODSWzNLKxh/2cY0hl sw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ckn2satkj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 28 Nov 2021 07:46:05 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 28 Nov 2021 07:46:03 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 28 Nov 2021 07:46:03 -0800 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 319303F70B8; Sun, 28 Nov 2021 07:46:01 -0800 (PST) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski Subject: [DPDK 22.02 PATCH v2 00/10] Add cnxk_gpio PMD Date: Sun, 28 Nov 2021 16:44:32 +0100 Message-ID: <20211128154442.4029049-1-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211117002155.293267-1-tduszynski@marvell.com> References: <20211117002155.293267-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: p_m7CwETA5fgDk0fhCWrn7w6xuQp5gFE X-Proofpoint-ORIG-GUID: p_m7CwETA5fgDk0fhCWrn7w6xuQp5gFE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-28_06,2021-11-28_01,2020-04-07_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This series introduces a new rawdevice PMD which allows to manage userspace GPIOs and install custom GPIO interrupt handlers which bypass kernel. This is especially useful for applications that, besides providing standard dataplane functionality, want to have fast and low latency access to GPIO pin state. It'd be great to have that merged during 22.02 merge window. v2: - do not trigger irq by writing to /dev/mem, use ioctl() instead Tomasz Duszynski (10): raw/cnxk_gpio: add GPIO driver skeleton raw/cnxk_gpio: support reading default queue conf raw/cnxk_gpio: support reading queue count raw/cnxk_gpio: support queue setup raw/cnxk_gpio: support queue release raw/cnxk_gpio: support enqueuing buffers raw/cnxk_gpio: support dequeuing buffers raw/cnxk_gpio: support standard GPIO operations raw/cnxk_gpio: support custom irq handlers raw/cnxk_gpio: support selftest doc/guides/rawdevs/cnxk_gpio.rst | 195 +++++++ doc/guides/rawdevs/index.rst | 1 + drivers/raw/cnxk_gpio/cnxk_gpio.c | 633 +++++++++++++++++++++ drivers/raw/cnxk_gpio/cnxk_gpio.h | 33 ++ drivers/raw/cnxk_gpio/cnxk_gpio_irq.c | 216 +++++++ drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c | 386 +++++++++++++ drivers/raw/cnxk_gpio/meson.build | 11 + drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h | 429 ++++++++++++++ drivers/raw/cnxk_gpio/version.map | 3 + drivers/raw/meson.build | 1 + 10 files changed, 1908 insertions(+) create mode 100644 doc/guides/rawdevs/cnxk_gpio.rst create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio.c create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio.h create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio_irq.c create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c create mode 100644 drivers/raw/cnxk_gpio/meson.build create mode 100644 drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h create mode 100644 drivers/raw/cnxk_gpio/version.map -- 2.25.1