From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 34279A0032; Mon, 13 Dec 2021 09:18:22 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9D3F840140; Mon, 13 Dec 2021 09:18:21 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id F157E40042 for ; Mon, 13 Dec 2021 09:18:19 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1BD7iF7F026887; Mon, 13 Dec 2021 00:18:17 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=+rdiidzqDYOdtiDqhYq3wZw8iYjwtnwInsRQiGHdGZ4=; b=Nl/1BCZcQRZ2KnshinaP+6T1BinXPQ1vH2mxgnR8S4hjtz91Jox5WTdau2PwZzXWTwAm cO5YBft4MKSqoPEVuNVFt5OWL0RGX+CNbXIJYm0HSIshZxOPQDI35Q9yxI2eRRmw8ifM OIX+xpZDHngvo133wMmscxKvCzo1VGILjuDVPtSDhEmCNA+MkKcCtNmi2mpRG4R4IkFR akNvDSgzTTz95/OpaVdq3OdhUJA0wkxhhtbVJAg6snckQzLK6ptlVBXc0aecdjRCXfvu cC1ffVfUcQArVViC6j3CxaVSy9NPcYuFqqKIV8gNvOcX9sku9l9yaBtq/nXTqahnSKHa yQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3cx21kg39w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 13 Dec 2021 00:18:17 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 13 Dec 2021 00:18:16 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Dec 2021 00:18:16 -0800 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 1FDE83F7050; Mon, 13 Dec 2021 00:18:14 -0800 (PST) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski Subject: [PATCH v3 00/10] Add cnxk_gpio PMD Date: Mon, 13 Dec 2021 09:17:22 +0100 Message-ID: <20211213081732.2096334-1-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211128154442.4029049-1-tduszynski@marvell.com> References: <20211128154442.4029049-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: DR4mV1bZq-mvLSZ67evNV5cLd56j2pJq X-Proofpoint-ORIG-GUID: DR4mV1bZq-mvLSZ67evNV5cLd56j2pJq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-13_03,2021-12-10_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This series introduces a new rawdevice PMD which allows to manage userspace GPIOs and install custom GPIO interrupt handlers which bypass kernel. This is especially useful for applications that, besides providing standard dataplane functionality, want to have fast and low latency access to GPIO pin state. It'd be great to have that merged during 22.02 merge window. v3: - fix meson formatting - fix cnxk_gpio_process_buf() return value v2: - do not trigger irq by writing to /dev/mem, use ioctl() instead Tomasz Duszynski (10): raw/cnxk_gpio: add GPIO driver skeleton raw/cnxk_gpio: support reading default queue conf raw/cnxk_gpio: support reading queue count raw/cnxk_gpio: support queue setup raw/cnxk_gpio: support queue release raw/cnxk_gpio: support enqueuing buffers raw/cnxk_gpio: support dequeuing buffers raw/cnxk_gpio: support standard GPIO operations raw/cnxk_gpio: support custom irq handlers raw/cnxk_gpio: support selftest doc/guides/rawdevs/cnxk_gpio.rst | 195 +++++++ doc/guides/rawdevs/index.rst | 1 + drivers/raw/cnxk_gpio/cnxk_gpio.c | 633 +++++++++++++++++++++ drivers/raw/cnxk_gpio/cnxk_gpio.h | 33 ++ drivers/raw/cnxk_gpio/cnxk_gpio_irq.c | 216 +++++++ drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c | 386 +++++++++++++ drivers/raw/cnxk_gpio/meson.build | 11 + drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h | 429 ++++++++++++++ drivers/raw/cnxk_gpio/version.map | 3 + drivers/raw/meson.build | 1 + 10 files changed, 1908 insertions(+) create mode 100644 doc/guides/rawdevs/cnxk_gpio.rst create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio.c create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio.h create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio_irq.c create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c create mode 100644 drivers/raw/cnxk_gpio/meson.build create mode 100644 drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h create mode 100644 drivers/raw/cnxk_gpio/version.map -- 2.25.1