From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3BD7BA0032; Mon, 13 Dec 2021 12:06:29 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C22E5406A2; Mon, 13 Dec 2021 12:06:28 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id ACE3C40042 for ; Mon, 13 Dec 2021 12:06:26 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1BD1Z2Ld027182; Mon, 13 Dec 2021 03:06:21 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=LjFNvIp9blYjLG0sLy5BuHfFZrWye0GD0Cbz2GGpmvQ=; b=cRMOC0TCy6EWjQglistmiq2jvqA67rhtJfmq7ics/iytGmvND5GKSFcs6rdGbbTDDG31 ql400jQ2q/puVya16PtEkw/FzIfMttMWE5xEchTk7OBSXSgwJoraT+EcYR+MGA5eKXRZ RcCeiq9KgSjm6S+/FGaTJ8z1ScxkOYLyQ8NlvI1J7Jfm/BDuUEt+rl/N5NZXDrw/Mi6T 0AGB74R3ZZralaoiCsQnAEfQV2/ffdXeWuL0LiO+kr7qI9HTRNDQ+LVv5MTl8heKXbov vRUQN6L4OnwYHxPCnANH78yASF8Q3uzfKqXqg+6VfeoGNfVe+akzalDlS4buEMcm+wFy Uw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3cwvmysnjp-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 13 Dec 2021 03:06:21 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 13 Dec 2021 03:06:21 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 13 Dec 2021 03:06:21 -0800 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 3B2443F7068; Mon, 13 Dec 2021 03:06:18 -0800 (PST) From: To: , Jan Viktorin , Ruifeng Wang , Bruce Richardson CC: , Pavan Nikhilesh Subject: [PATCH] config/cn10k: align mempool elements to 128 bytes Date: Mon, 13 Dec 2021 16:36:14 +0530 Message-ID: <20211213110615.4458-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: zco-T0oig4SpPZmMw477NmGKsmyknwVU X-Proofpoint-ORIG-GUID: zco-T0oig4SpPZmMw477NmGKsmyknwVU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-13_04,2021-12-13_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Mempool elements are by default aligned to CACHELINE_SIZE. In CN10K cacheline size is 64B but the RoC requires buffers to be aligned to 128B. Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned 128 bytes. Signed-off-by: Pavan Nikhilesh --- config/arm/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 213324d262..33afe1a9ad 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -276,7 +276,8 @@ soc_cn10k = { 'implementer' : '0x41', 'flags': [ ['RTE_MAX_LCORE', 24], - ['RTE_MAX_NUMA_NODES', 1] + ['RTE_MAX_NUMA_NODES', 1], + ['RTE_MEMPOOL_ALIGN', 128] ], 'part_number': '0xd49', 'extra_march_features': ['crypto'], -- 2.17.1