From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A9BEAA00C3; Mon, 13 Dec 2021 21:54:33 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 76D81406A2; Mon, 13 Dec 2021 21:54:33 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id AD43D40042 for ; Mon, 13 Dec 2021 21:54:31 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1BDElW0a030174 for ; Mon, 13 Dec 2021 12:54:30 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=7jWCKZb4ivwx8ewTvgepVsOo32+fnF1M2LxcCGbs/0A=; b=Qi2SwWLNojTZZKYNQkm9xfm7KYWILA/OttzQBlarg1EFPkLD8wzvu4o8Z7PRt1hM7UId vwi//M3dz41izLcP0ILKjN2fUAt6y1SUUmQo+kNwTohHaHtpecrPeQ2NGiOexspAMIKs FSzcGxEqIOxNIehNvJDs7y1kfLhG+Qc1XdvyHgG12RVbPiw3H5pYJMePnmrWOHxBhVnl EKzamppquCNkRE2oRX8IjjtHErXgYlxMSBUidg+iouF6d325qDIxRbBpcP974oLJGXrM EYOZjD/memH32MQfJ1ARC6+LlOD4UEZu8WB+Q8UPKBN0TgLslO7pfYurVvY4HRcV/Kw/ 3w== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3cx88ahjw9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 13 Dec 2021 12:54:30 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 13 Dec 2021 12:54:29 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Dec 2021 12:54:29 -0800 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id DF64A3F7078; Mon, 13 Dec 2021 12:54:26 -0800 (PST) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Pavan Nikhilesh Subject: [PATCH] common/cnxk: add workaround for vWQE flush Date: Tue, 14 Dec 2021 02:24:23 +0530 Message-ID: <20211213205424.5588-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: f5hKsq0vUHR7kKOlSr_teyt3_jVip11B X-Proofpoint-ORIG-GUID: f5hKsq0vUHR7kKOlSr_teyt3_jVip11B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-13_10,2021-12-13_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Due to an errata writing to vWQE flush register might hang NIX. Add workaround for vWQE flush hang by waiting for the max coalescing timeout to flush out any pending vWQEs. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/roc_nix_inl.c | 3 +-- drivers/common/cnxk/roc_nix_inl_dev.c | 12 ++++++++++++ drivers/common/cnxk/roc_nix_inl_priv.h | 1 + drivers/common/cnxk/roc_nix_priv.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 19 +++++++++++++++++-- 5 files changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index f0fc690417..e8981c4aa4 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -595,8 +595,7 @@ roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq) plt_err("Failed to disable inline device rq, rc=%d", rc); /* Flush NIX LF for CN10K */ - if (roc_model_is_cn10k()) - plt_write64(0, inl_dev->nix_base + NIX_LF_OP_VWQE_FLUSH); + nix_rq_vwqe_flush(rq, inl_dev->vwqe_interval); return rc; } diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index a0fe6ecd82..10912a6c93 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -346,6 +346,7 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev) struct mbox *mbox = dev->mbox; struct nix_lf_alloc_rsp *rsp; struct nix_lf_alloc_req *req; + struct nix_hw_info *hw_info; size_t inb_sa_sz; int i, rc = -ENOSPC; void *sa; @@ -382,6 +383,17 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev) inl_dev->qints = rsp->qints; inl_dev->cints = rsp->cints; + /* Get VWQE info if supported */ + if (roc_model_is_cn10k()) { + mbox_alloc_msg_nix_get_hw_info(mbox); + rc = mbox_process_msg(mbox, (void *)&hw_info); + if (rc) { + plt_err("Failed to get HW info, rc=%d", rc); + goto lf_free; + } + inl_dev->vwqe_interval = hw_info->vwqe_delay; + } + /* Register nix interrupts */ rc = nix_inl_nix_register_irqs(inl_dev); if (rc) { diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h index 3dc526f929..be53a3fa81 100644 --- a/drivers/common/cnxk/roc_nix_inl_priv.h +++ b/drivers/common/cnxk/roc_nix_inl_priv.h @@ -35,6 +35,7 @@ struct nix_inl_dev { /* NIX data */ uint8_t lf_tx_stats; uint8_t lf_rx_stats; + uint16_t vwqe_interval; uint16_t cints; uint16_t qints; struct roc_nix_rq rq; diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 04575af295..deb2a6ba11 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -377,6 +377,7 @@ int nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg, int nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable); int nix_tm_bp_config_get(struct roc_nix *roc_nix, bool *is_enabled); int nix_tm_bp_config_set(struct roc_nix *roc_nix, bool enable); +void nix_rq_vwqe_flush(struct roc_nix_rq *rq, uint16_t vwqe_interval); /* * TM priv utils. diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index c8c8401d81..d5f6813e69 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -28,6 +28,22 @@ nix_qsize_clampup(uint32_t val) return i; } +void +nix_rq_vwqe_flush(struct roc_nix_rq *rq, uint16_t vwqe_interval) +{ + uint64_t wait_ns; + + if (!roc_model_is_cn10k()) + return; + /* Due to HW errata writes to VWQE_FLUSH might hang, so instead + * wait for max vwqe timeout interval. + */ + if (rq->vwqe_ena) { + wait_ns = rq->vwqe_wait_tmo * (vwqe_interval + 1) * 100; + plt_delay_us((wait_ns / 1E3) + 1); + } +} + int nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable) { @@ -66,9 +82,8 @@ roc_nix_rq_ena_dis(struct roc_nix_rq *rq, bool enable) int rc; rc = nix_rq_ena_dis(&nix->dev, rq, enable); + nix_rq_vwqe_flush(rq, nix->vwqe_interval); - if (roc_model_is_cn10k()) - plt_write64(rq->qid, nix->base + NIX_LF_OP_VWQE_FLUSH); return rc; } -- 2.17.1