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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.236) by DM6NAM11FT005.mail.protection.outlook.com (10.13.172.238) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4867.7 via Frontend Transport; Fri, 7 Jan 2022 16:10:15 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 7 Jan 2022 16:10:14 +0000 Received: from nvidia.com (172.20.187.5) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.986.9; Fri, 7 Jan 2022 08:10:14 -0800 From: To: CC: Elena Agostini Subject: [PATCH v2 1/3] gpudev: mem alloc aligned memory Date: Sat, 8 Jan 2022 00:20:01 +0000 Message-ID: <20220108002003.21153-1-eagostini@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220104014721.1799-1-eagostini@nvidia.com> References: <20220104014721.1799-1-eagostini@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0516ab2b-ec21-42be-027e-08d9d1f83144 X-MS-TrafficTypeDiagnostic: BY5PR12MB4258:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; 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SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(36840700001)(40470700002)(46966006)(5660300002)(8936002)(81166007)(26005)(2876002)(6916009)(82310400004)(1076003)(55016003)(47076005)(356005)(8676002)(40460700001)(86362001)(4326008)(107886003)(6286002)(36756003)(70586007)(70206006)(426003)(336012)(7696005)(2616005)(316002)(36860700001)(6666004)(2906002)(16526019)(186003)(508600001)(83380400001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2022 16:10:15.6552 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0516ab2b-ec21-42be-027e-08d9d1f83144 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4258 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Elena Agostini Similarly to rte_malloc, rte_gpu_mem_alloc accept as input the memory alignment size. GPU driver should return GPU memory address aligned with the input value. Changelog: - rte_gpu_mem_alloc parameters order Signed-off-by: Elena Agostini --- lib/gpudev/gpudev.c | 10 ++++++++-- lib/gpudev/gpudev_driver.h | 2 +- lib/gpudev/rte_gpudev.h | 10 +++++++--- 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/lib/gpudev/gpudev.c b/lib/gpudev/gpudev.c index 9ae36dbae9..59e2169292 100644 --- a/lib/gpudev/gpudev.c +++ b/lib/gpudev/gpudev.c @@ -527,7 +527,7 @@ rte_gpu_info_get(int16_t dev_id, struct rte_gpu_info *info) } void * -rte_gpu_mem_alloc(int16_t dev_id, size_t size) +rte_gpu_mem_alloc(int16_t dev_id, size_t size, unsigned int align) { struct rte_gpu *dev; void *ptr; @@ -549,7 +549,13 @@ rte_gpu_mem_alloc(int16_t dev_id, size_t size) if (size == 0) /* dry-run */ return NULL; - ret = dev->ops.mem_alloc(dev, size, &ptr); + if (align && !rte_is_power_of_2(align)) { + GPU_LOG(ERR, "requested alignment is not a power of two %u", align); + rte_errno = EINVAL; + return NULL; + } + + ret = dev->ops.mem_alloc(dev, size, align, &ptr); switch (ret) { case 0: diff --git a/lib/gpudev/gpudev_driver.h b/lib/gpudev/gpudev_driver.h index cb7b101f2f..0ed7478e9b 100644 --- a/lib/gpudev/gpudev_driver.h +++ b/lib/gpudev/gpudev_driver.h @@ -27,7 +27,7 @@ enum rte_gpu_state { struct rte_gpu; typedef int (rte_gpu_close_t)(struct rte_gpu *dev); typedef int (rte_gpu_info_get_t)(struct rte_gpu *dev, struct rte_gpu_info *info); -typedef int (rte_gpu_mem_alloc_t)(struct rte_gpu *dev, size_t size, void **ptr); +typedef int (rte_gpu_mem_alloc_t)(struct rte_gpu *dev, size_t size, unsigned int align, void **ptr); typedef int (rte_gpu_mem_free_t)(struct rte_gpu *dev, void *ptr); typedef int (rte_gpu_mem_register_t)(struct rte_gpu *dev, size_t size, void *ptr); typedef int (rte_gpu_mem_unregister_t)(struct rte_gpu *dev, void *ptr); diff --git a/lib/gpudev/rte_gpudev.h b/lib/gpudev/rte_gpudev.h index fa3f3aad4f..9e2e2c5dce 100644 --- a/lib/gpudev/rte_gpudev.h +++ b/lib/gpudev/rte_gpudev.h @@ -364,18 +364,22 @@ int rte_gpu_info_get(int16_t dev_id, struct rte_gpu_info *info); * @param size * Number of bytes to allocate. * Requesting 0 will do nothing. - * + * @param align + * If 0, the return is a pointer that is suitably aligned for any kind of + * variable (in the same manner as malloc()). + * Otherwise, the return is a pointer that is a multiple of *align*. In + * this case, it must obviously be a power of two. * @return * A pointer to the allocated memory, otherwise NULL and rte_errno is set: * - ENODEV if invalid dev_id - * - EINVAL if reserved flags + * - EINVAL if align is not a power of two * - ENOTSUP if operation not supported by the driver * - E2BIG if size is higher than limit * - ENOMEM if out of space * - EPERM if driver error */ __rte_experimental -void *rte_gpu_mem_alloc(int16_t dev_id, size_t size) +void *rte_gpu_mem_alloc(int16_t dev_id, size_t size, unsigned int align) __rte_alloc_size(2); /** -- 2.17.1