From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 15BECA0350; Sat, 22 Jan 2022 02:51:57 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BF3694279F; Sat, 22 Jan 2022 02:51:33 +0100 (CET) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id A113F4277F for ; Sat, 22 Jan 2022 02:51:27 +0100 (CET) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.55]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4JgfMz0MNjzbkJK; Sat, 22 Jan 2022 09:50:39 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.21; Sat, 22 Jan 2022 09:51:25 +0800 From: "Min Hu (Connor)" To: CC: , , Subject: [PATCH v2 06/15] net/hns3: extract a function to handle reset fail Date: Sat, 22 Jan 2022 09:51:33 +0800 Message-ID: <20220122015142.9516-7-humin29@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220122015142.9516-1-humin29@huawei.com> References: <20220107101558.39219-1-humin29@huawei.com> <20220122015142.9516-1-humin29@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Huisong Li Extract a function to handle reset fail for clearer code logic. Signed-off-by: Huisong Li --- drivers/net/hns3/hns3_intr.c | 54 +++++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 22 deletions(-) diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 66dc509086..3ca2e1e338 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -2770,6 +2770,37 @@ hns3_reset_post(struct hns3_adapter *hns) return -EIO; } +static void +hns3_reset_fail_handle(struct hns3_adapter *hns) +{ + struct hns3_hw *hw = &hns->hw; + struct timeval tv_delta; + struct timeval tv; + + hns3_clear_reset_level(hw, &hw->reset.pending); + if (hns3_reset_err_handle(hns)) { + hw->reset.stage = RESET_STAGE_PREWAIT; + hns3_schedule_reset(hns); + return; + } + + rte_spinlock_lock(&hw->lock); + if (hw->reset.mbuf_deferred_free) { + hns3_dev_release_mbufs(hns); + hw->reset.mbuf_deferred_free = false; + } + rte_spinlock_unlock(&hw->lock); + __atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED); + hw->reset.stage = RESET_STAGE_NONE; + hns3_clock_gettime(&tv); + timersub(&tv, &hw->reset.start_time, &tv_delta); + hns3_warn(hw, "%s reset fail delta %" PRIu64 " ms time=%ld.%.6ld", + reset_string[hw->reset.level], + hns3_clock_calctime_ms(&tv_delta), + tv.tv_sec, tv.tv_usec); + hw->reset.level = HNS3_NONE_RESET; +} + /* * There are three scenarios as follows: * When the reset is not in progress, the reset process starts. @@ -2784,7 +2815,6 @@ int hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) { struct hns3_hw *hw = &hns->hw; - struct timeval tv_delta; struct timeval tv; int ret; @@ -2843,27 +2873,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) if (ret == -EAGAIN) return ret; err: - hns3_clear_reset_level(hw, &hw->reset.pending); - if (hns3_reset_err_handle(hns)) { - hw->reset.stage = RESET_STAGE_PREWAIT; - hns3_schedule_reset(hns); - } else { - rte_spinlock_lock(&hw->lock); - if (hw->reset.mbuf_deferred_free) { - hns3_dev_release_mbufs(hns); - hw->reset.mbuf_deferred_free = false; - } - rte_spinlock_unlock(&hw->lock); - __atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED); - hw->reset.stage = RESET_STAGE_NONE; - hns3_clock_gettime(&tv); - timersub(&tv, &hw->reset.start_time, &tv_delta); - hns3_warn(hw, "%s reset fail delta %" PRIu64 " ms time=%ld.%.6ld", - reset_string[hw->reset.level], - hns3_clock_calctime_ms(&tv_delta), - tv.tv_sec, tv.tv_usec); - hw->reset.level = HNS3_NONE_RESET; - } + hns3_reset_fail_handle(hns); return -EIO; } -- 2.33.0