From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9D61FA034E; Sun, 6 Feb 2022 15:30:39 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 33AC2410E8; Sun, 6 Feb 2022 15:30:36 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 8530E410E8 for ; Sun, 6 Feb 2022 15:30:34 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 2167mxTD015079; Sun, 6 Feb 2022 06:30:33 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=yZfj3Vtk792Zm4TNE9BdBLuNTr/2T2e8oLMTTURCUpc=; b=DbRUFTUHR4cyFtT9CPd01mPw/AIyq+fGlXcZSUOKHTWxvseiw7J/bEj9RhSH6oIeXh0i hZjCsaDYojBzZT4doXevzhm4KZ2N7Nuc2sj/Ut2f3Ajabr4r3DVRezSoTtCUlk0A7kuY AImOuLTvzKqijD4Rtg9rterYhW4HHByviDSL9JGPShLzVbSWhVVyviPzXN3pJdnPECnF N31Zti1VyDTLjUKklsWLEZjDc4UALXLgEjDXhdPttxgBhdz9p4GqWk0kUhroF/LpFPY1 ZQ4ouH+A7cOcUkahhngXwrAs/pL8ycbKAcqORV+mbZIbocT/ZcZp6rUNhWwuOgLzz4fV VQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3e1smr2kwf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 06 Feb 2022 06:30:33 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 6 Feb 2022 06:30:31 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 6 Feb 2022 06:30:31 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 16E753F7065; Sun, 6 Feb 2022 06:30:29 -0800 (PST) From: Nithin Dabilpuram To: , Radu Nicolau , Akhil Goyal CC: , Nithin Dabilpuram Subject: [PATCH 2/4] examples/ipsec-secgw: disable Tx chksum offload for inline Date: Sun, 6 Feb 2022 20:00:20 +0530 Message-ID: <20220206143022.13098-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220206143022.13098-1-ndabilpuram@marvell.com> References: <20220206143022.13098-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: wlc2bRVoIfS9rQiUXqbefqKx-onEoOwU X-Proofpoint-ORIG-GUID: wlc2bRVoIfS9rQiUXqbefqKx-onEoOwU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-06_04,2022-02-03_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable Tx IPv4 checksum offload only when Tx inline crypto is needed. In other cases such as Tx Inline protocol offload, checksum computation is implicitly taken care by HW. The advantage of having only necessary offloads enabled is that Tx burst function can be as light as possible. Signed-off-by: Nithin Dabilpuram --- examples/ipsec-secgw/ipsec-secgw.c | 3 --- examples/ipsec-secgw/sa.c | 9 +++++++++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/examples/ipsec-secgw/ipsec-secgw.c b/examples/ipsec-secgw/ipsec-secgw.c index 21abc0d..d8a9bfa 100644 --- a/examples/ipsec-secgw/ipsec-secgw.c +++ b/examples/ipsec-secgw/ipsec-secgw.c @@ -2314,9 +2314,6 @@ port_init(uint16_t portid, uint64_t req_rx_offloads, uint64_t req_tx_offloads) local_port_conf.txmode.offloads |= RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; - if (dev_info.tx_offload_capa & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) - local_port_conf.txmode.offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM; - printf("port %u configuring rx_offloads=0x%" PRIx64 ", tx_offloads=0x%" PRIx64 "\n", portid, local_port_conf.rxmode.offloads, diff --git a/examples/ipsec-secgw/sa.c b/examples/ipsec-secgw/sa.c index 1839ac7..b878a48 100644 --- a/examples/ipsec-secgw/sa.c +++ b/examples/ipsec-secgw/sa.c @@ -1790,6 +1790,15 @@ sa_check_offloads(uint16_t port_id, uint64_t *rx_offloads, RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL) && rule->portid == port_id) { *tx_offloads |= RTE_ETH_TX_OFFLOAD_SECURITY; + + /* Checksum offload is not needed for inline protocol as + * all processing for Outbound IPSec packets will be + * implicitly taken care and for non-IPSec packets, + * there is no need of IPv4 Checksum offload. + */ + if (rule_type == RTE_SECURITY_ACTION_TYPE_INLINE_CRYPTO) + *tx_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM; + if (rule->mss) *tx_offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO; } -- 2.8.4