From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B7B5EA034F; Mon, 7 Feb 2022 08:32:05 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1F64A4122E; Mon, 7 Feb 2022 08:30:41 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B7B5D4122E for ; Mon, 7 Feb 2022 08:30:39 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 216NOarY004938 for ; Sun, 6 Feb 2022 23:30:39 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=E0Y80ZP1kj7SKhl6dMHcaOkR4257hh64ZBw8tKWQS50=; b=J9YiX95E88x9ps0PuMdx7jbdRDmqFP7Ra8FBWLeDkT5RuacNYVmLfueiREzpCMmf5NzO IuAybB3RKD8AYMR2BB7UFsbvZmgU26F1yuzQM1sOYZMPIu/OXeivK6V9BXUukx+ChzOI SSkY755v969SVbK0X3gjs/xkLK/8vSAJ8lm6WFVSREtsDHGWciQGPES49Iuji0IpjuvC 9PwMavm9Tv0/04RnG63pnLKB0dcbbIAaLiCiytEoj8aGramqAg1GZ6qcu16Yr/9YCktW BLv/ez6SWmQWyd9ZUQLy12BO2wes5TBvw3wvUTbkO8kTlJH43N5seHoTXI2syi/AN3on gg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3e1smr4p6f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 06 Feb 2022 23:30:38 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 6 Feb 2022 23:30:36 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 6 Feb 2022 23:30:36 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id E91113F7063; Sun, 6 Feb 2022 23:30:34 -0800 (PST) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Subject: [PATCH 18/20] net/cnxk: enable flow control by default on device configure Date: Mon, 7 Feb 2022 12:59:30 +0530 Message-ID: <20220207072932.22409-18-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220207072932.22409-1-ndabilpuram@marvell.com> References: <20220207072932.22409-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: PYafvVjB7KZFAicyY9NpyaVDN2GQWcnN X-Proofpoint-ORIG-GUID: PYafvVjB7KZFAicyY9NpyaVDN2GQWcnN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-07_02,2022-02-03_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable flow control by default on device configuration instead of basing it on Kernel behaviour. Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cnxk_ethdev.c | 24 +++++++----------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index aa76d87..e4fbb09 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -306,25 +306,15 @@ static int nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev) { struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); - struct cnxk_fc_cfg *fc = &dev->fc_cfg; - struct rte_eth_fc_conf fc_conf = {0}; - int rc; + enum roc_nix_fc_mode fc_mode = ROC_NIX_FC_FULL; - /* Both Rx & Tx flow ctrl get enabled(RTE_ETH_FC_FULL) in HW - * by AF driver, update those info in PMD structure. - */ - rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf); - if (rc) - goto exit; + /* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */ + if (roc_model_is_cn96_ax() && + dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG) + fc_mode = ROC_NIX_FC_TX; - fc->mode = fc_conf.mode; - fc->rx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) || - (fc_conf.mode == RTE_ETH_FC_RX_PAUSE); - fc->tx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) || - (fc_conf.mode == RTE_ETH_FC_TX_PAUSE); - -exit: - return rc; + /* By default enable flow control */ + return roc_nix_fc_mode_set(&dev->nix, fc_mode); } static int -- 2.8.4