From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 70EF1A034F; Mon, 7 Feb 2022 08:30:31 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D0FF64114B; Mon, 7 Feb 2022 08:30:16 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 23F4B410F3 for ; Mon, 7 Feb 2022 08:30:14 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 216LsOhF030467 for ; Sun, 6 Feb 2022 23:30:13 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=bu5HS1JSE+XM5WcbEyJErWNflbOWJS0AVF+fG7HjK5c=; b=Db/Q0OaUmH4mvG4VmlL8qP9aGpWv4GwjauFtKdnfsKu1CokYFkqcIJgbApMlEzCmyRRW JwOnK5yF8/G5c5/CSOItME8AioQTGgXVZvlzW43lWXhIe4tOfFppBp0MukhxlLxvbdqn aXvnPCMh3WY4cZRpTzok4qHAa/7AbXY8QWM9MCMxuzBejlcU7drLgBP7GBi8Uhk7SOnS sbXXg207dgYnqJ7blQa1Jq4fZ2SQwEO82NWGGHqJDDfZTNrCWJbaLoJZJZbzxRTYK9Re 3F1N7wbEMncz5ER0w9Gh71LzCn7NDr8xPlt/CGOkJ7hS/mzDYP7Hob8yIoN4z4nD1HVq Aw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3e1smr4p28-9 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 06 Feb 2022 23:30:13 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 6 Feb 2022 23:30:06 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 6 Feb 2022 23:30:06 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 173DC3F70C8; Sun, 6 Feb 2022 23:30:01 -0800 (PST) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Vidya Sagar Velumuri Subject: [PATCH 06/20] common/cnxk: enable l3hdr write back in SA Date: Mon, 7 Feb 2022 12:59:18 +0530 Message-ID: <20220207072932.22409-6-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220207072932.22409-1-ndabilpuram@marvell.com> References: <20220207072932.22409-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: Y81A-uuMwnZzsAqu_c3-crb2MxbooXHx X-Proofpoint-ORIG-GUID: Y81A-uuMwnZzsAqu_c3-crb2MxbooXHx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-07_02,2022-02-03_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Enable the field in SA to write back l2, l3 hdrs in case of errors during inline processing. Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_ie_ot.c | 1 + drivers/common/cnxk/roc_ie_ot.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_ie_ot.c b/drivers/common/cnxk/roc_ie_ot.c index 1ea7bfd..d0b7ad3 100644 --- a/drivers/common/cnxk/roc_ie_ot.c +++ b/drivers/common/cnxk/roc_ie_ot.c @@ -17,6 +17,7 @@ roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa, bool is_inline) sa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META; sa->w0.s.pkind = ROC_IE_OT_CPT_PKIND; sa->w0.s.et_ovrwr = 1; + sa->w2.s.l3hdr_on_err = 1; } offset = offsetof(struct roc_ot_ipsec_inb_sa, ctx); diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h index 2b4f5d3..1029d1e 100644 --- a/drivers/common/cnxk/roc_ie_ot.h +++ b/drivers/common/cnxk/roc_ie_ot.h @@ -336,7 +336,8 @@ struct roc_ot_ipsec_inb_sa { uint64_t ip_hdr_verify : 2; uint64_t udp_ports_verify : 1; - uint64_t rsvd6 : 7; + uint64_t l3hdr_on_err : 1; + uint64_t rsvd6 : 6; uint64_t async_mode : 1; uint64_t spi : 32; -- 2.8.4