From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4205AA0352; Tue, 8 Feb 2022 19:15:04 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D0F3F4115E; Tue, 8 Feb 2022 19:15:00 +0100 (CET) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 5A01C41140 for ; Tue, 8 Feb 2022 19:14:59 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644344099; x=1675880099; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=im17znONqyAYV4gqnlLZWxQi8+T98SQApnpdgr8++Uk=; b=hLiOPqoKk0GEbWnCCVn7qIzb0Fh8vb8YQb/eqLI941WRlWdrRlALICWj 5rb2odRyMXlFFENGGi6kbxTfXQr3zjFNfmWAkO/lZPdkKJ8g2LPp93PY7 zIXo0ah4tMfb1XKzUr9YKuar2WtYBqS9p6yafLuEaVxSIZoKK8RoqHZ05 N12e5ZcSWtrs7lzvsF5QvUvVhMzlctnRzzO7/rWG4xFc1rfe9IWM53L8A 3IjFEZKhqROO8KIjXjY9/RI7Q4Y146PN2c8nVLTmtTndvDN1y4Jtgq0bn f9xJ0z4ljRw6aQruaogA2CzPQpwjdtS6dIJ3TSiJa+JEYMbKkEiH09GJM w==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="248962983" X-IronPort-AV: E=Sophos;i="5.88,353,1635231600"; d="scan'208";a="248962983" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 10:14:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,353,1635231600"; d="scan'208";a="540720097" Received: from silpixa00400465.ir.intel.com ([10.55.129.31]) by orsmga008.jf.intel.com with ESMTP; 08 Feb 2022 10:14:57 -0800 From: Kai Ji To: dev@dpdk.org Cc: gakhil@marvell.com, Kai Ji Subject: [dpdk-dev v7 01/10] common/qat: define build op request and dequeue op Date: Wed, 9 Feb 2022 02:14:45 +0800 Message-Id: <20220208181454.69121-2-kai.ji@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220208181454.69121-1-kai.ji@intel.com> References: <20220204185057.29893-11-kai.ji@intel.com> <20220208181454.69121-1-kai.ji@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch introduce build request op and dequeue op function pointers to qat queue pair implementation. Those two functions are used to be assigned during qat session generation based on crypto operation Signed-off-by: Kai Ji --- drivers/common/qat/qat_qp.c | 10 ++++-- drivers/common/qat/qat_qp.h | 54 ++++++++++++++++++++++++++-- drivers/compress/qat/qat_comp_pmd.c | 4 +-- drivers/crypto/qat/qat_asym_pmd.c | 4 +-- drivers/crypto/qat/qat_sym_pmd.c | 4 +-- drivers/crypto/qat/qat_sym_session.h | 13 ++++++- 6 files changed, 76 insertions(+), 13 deletions(-) diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c index cde421eb77..ed632b5ebe 100644 --- a/drivers/common/qat/qat_qp.c +++ b/drivers/common/qat/qat_qp.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2015-2018 Intel Corporation + * Copyright(c) 2015-2022 Intel Corporation */ #include @@ -550,7 +550,9 @@ adf_modulo(uint32_t data, uint32_t modulo_mask) } uint16_t -qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops) +qat_enqueue_op_burst(void *qp, + __rte_unused qat_op_build_request_t op_build_request, + void **ops, uint16_t nb_ops) { register struct qat_queue *queue; struct qat_qp *tmp_qp = (struct qat_qp *)qp; @@ -817,7 +819,9 @@ qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops) } uint16_t -qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops) +qat_dequeue_op_burst(void *qp, void **ops, + __rte_unused qat_op_dequeue_t qat_dequeue_process_response, + uint16_t nb_ops) { struct qat_queue *rx_queue; struct qat_qp *tmp_qp = (struct qat_qp *)qp; diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h index deafb407b3..66f00943a5 100644 --- a/drivers/common/qat/qat_qp.h +++ b/drivers/common/qat/qat_qp.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2018 Intel Corporation + * Copyright(c) 2018-2022 Intel Corporation */ #ifndef _QAT_QP_H_ #define _QAT_QP_H_ @@ -36,6 +36,51 @@ struct qat_queue { /* number of responses processed since last CSR head write */ }; +/** + * Type define qat_op_build_request_t function pointer, passed in as argument + * in enqueue op burst, where a build request assigned base on the type of + * crypto op. + * + * @param in_op + * An input op pointer + * @param out_msg + * out_meg pointer + * @param op_cookie + * op cookie pointer + * @param opaque + * an opaque data may be used to store context may be useful between + * 2 enqueue operations. + * @param dev_gen + * qat device gen id + * @return + * - 0 if the crypto request is build successfully, + * - EINVAL if error + **/ +typedef int (*qat_op_build_request_t)(void *in_op, uint8_t *out_msg, + void *op_cookie, uint64_t *opaque, enum qat_device_gen dev_gen); + +/** + * Type define qat_op_dequeue_t function pointer, passed in as argument + * in dequeue op burst, where a dequeue op assigned base on the type of + * crypto op. + * + * @param op + * An input op pointer + * @param resp + * qat response msg pointer + * @param op_cookie + * op cookie pointer + * @param dequeue_err_count + * dequeue error counter + * @return + * - 0 if dequeue OP is successful + * - EINVAL if error + **/ +typedef int (*qat_op_dequeue_t)(void **op, uint8_t *resp, void *op_cookie, + uint64_t *dequeue_err_count __rte_unused); + +#define QAT_BUILD_REQUEST_MAX_OPAQUE_SIZE 2 + struct qat_qp { void *mmap_bar_addr; struct qat_queue tx_q; @@ -44,6 +89,7 @@ struct qat_qp { struct rte_mempool *op_cookie_pool; void **op_cookies; uint32_t nb_descriptors; + uint64_t opaque[QAT_BUILD_REQUEST_MAX_OPAQUE_SIZE]; enum qat_device_gen qat_dev_gen; enum qat_service_type service_type; struct qat_pci_device *qat_dev; @@ -78,13 +124,15 @@ struct qat_qp_config { }; uint16_t -qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops); +qat_enqueue_op_burst(void *qp, qat_op_build_request_t op_build_request, + void **ops, uint16_t nb_ops); uint16_t qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops); uint16_t -qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops); +qat_dequeue_op_burst(void *qp, void **ops, + qat_op_dequeue_t qat_dequeue_process_response, uint16_t nb_ops); int qat_qp_release(enum qat_device_gen qat_dev_gen, struct qat_qp **qp_addr); diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c index da6404c017..8e497e7a09 100644 --- a/drivers/compress/qat/qat_comp_pmd.c +++ b/drivers/compress/qat/qat_comp_pmd.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2015-2019 Intel Corporation + * Copyright(c) 2015-2022 Intel Corporation */ #include @@ -620,7 +620,7 @@ static uint16_t qat_comp_pmd_dequeue_first_op_burst(void *qp, struct rte_comp_op **ops, uint16_t nb_ops) { - uint16_t ret = qat_dequeue_op_burst(qp, (void **)ops, nb_ops); + uint16_t ret = qat_dequeue_op_burst(qp, (void **)ops, NULL, nb_ops); struct qat_qp *tmp_qp = (struct qat_qp *)qp; if (ret) { diff --git a/drivers/crypto/qat/qat_asym_pmd.c b/drivers/crypto/qat/qat_asym_pmd.c index addee384e3..9a7596b227 100644 --- a/drivers/crypto/qat/qat_asym_pmd.c +++ b/drivers/crypto/qat/qat_asym_pmd.c @@ -62,13 +62,13 @@ static struct rte_cryptodev_ops crypto_qat_ops = { uint16_t qat_asym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops) { - return qat_enqueue_op_burst(qp, (void **)ops, nb_ops); + return qat_enqueue_op_burst(qp, NULL, (void **)ops, nb_ops); } uint16_t qat_asym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops) { - return qat_dequeue_op_burst(qp, (void **)ops, nb_ops); + return qat_dequeue_op_burst(qp, (void **)ops, NULL, nb_ops); } /* An rte_driver is needed in the registration of both the device and the driver diff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c index b835245f17..28a26260fb 100644 --- a/drivers/crypto/qat/qat_sym_pmd.c +++ b/drivers/crypto/qat/qat_sym_pmd.c @@ -49,14 +49,14 @@ static uint16_t qat_sym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops) { - return qat_enqueue_op_burst(qp, (void **)ops, nb_ops); + return qat_enqueue_op_burst(qp, NULL, (void **)ops, nb_ops); } static uint16_t qat_sym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops) { - return qat_dequeue_op_burst(qp, (void **)ops, nb_ops); + return qat_dequeue_op_burst(qp, (void **)ops, NULL, nb_ops); } /* An rte_driver is needed in the registration of both the device and the driver diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h index 6ebc176729..fe875a7fd0 100644 --- a/drivers/crypto/qat/qat_sym_session.h +++ b/drivers/crypto/qat/qat_sym_session.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2015-2019 Intel Corporation + * Copyright(c) 2015-2022 Intel Corporation */ #ifndef _QAT_SYM_SESSION_H_ #define _QAT_SYM_SESSION_H_ @@ -63,6 +63,16 @@ enum qat_sym_proto_flag { QAT_CRYPTO_PROTO_FLAG_ZUC = 4 }; +struct qat_sym_session; + +/* + * typedef qat_op_build_request_t function pointer, passed in as argument + * in enqueue op burst, where a build request assigned base on the type of + * crypto op. + */ +typedef int (*qat_sym_build_request_t)(void *in_op, struct qat_sym_session *ctx, + uint8_t *out_msg, void *op_cookie); + /* Common content descriptor */ struct qat_sym_cd { struct icp_qat_hw_cipher_algo_blk cipher; @@ -107,6 +117,7 @@ struct qat_sym_session { /* Some generations need different setup of counter */ uint32_t slice_types; enum qat_sym_proto_flag qat_proto_flag; + qat_sym_build_request_t build_request[2]; }; int -- 2.17.1