From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8441FA00BE; Thu, 17 Feb 2022 04:04:31 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DB8A940150; Thu, 17 Feb 2022 04:04:30 +0100 (CET) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id 9882440150 for ; Thu, 17 Feb 2022 04:04:29 +0100 (CET) Received: from dggpeml500024.china.huawei.com (unknown [172.30.72.53]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4Jzflr4qT8zbkBj; Thu, 17 Feb 2022 11:03:20 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Thu, 17 Feb 2022 11:04:27 +0800 From: Chengwen Feng To: CC: Subject: [PATCH 4/5] dma/hisilicon: add queue full statistics Date: Thu, 17 Feb 2022 10:59:10 +0800 Message-ID: <20220217025911.35822-5-fengchengwen@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220217025911.35822-1-fengchengwen@huawei.com> References: <20220217025911.35822-1-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds queue full statistics for HiSilicon DMA PMD. Signed-off-by: Chengwen Feng --- drivers/dma/hisilicon/hisi_dmadev.c | 12 ++++++++---- drivers/dma/hisilicon/hisi_dmadev.h | 1 + 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c index 3917db38b7..c36acf01be 100644 --- a/drivers/dma/hisilicon/hisi_dmadev.c +++ b/drivers/dma/hisilicon/hisi_dmadev.c @@ -407,6 +407,7 @@ hisi_dma_start(struct rte_dma_dev *dev) hw->submitted = 0; hw->completed = 0; hw->errors = 0; + hw->qfulls = 0; hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG, HISI_DMA_QUEUE_CTRL0_EN_B, true); @@ -455,6 +456,7 @@ hisi_dma_stats_reset(struct rte_dma_dev *dev, uint16_t vchan) hw->submitted = 0; hw->completed = 0; hw->errors = 0; + hw->qfulls = 0; return 0; } @@ -566,14 +568,14 @@ hisi_dma_dump(const struct rte_dma_dev *dev, FILE *f) " ridx: %u cridx: %u\n" " sq_head: %u sq_tail: %u cq_sq_head: %u\n" " cq_head: %u cqs_completed: %u cqe_vld: %u\n" - " submitted: %" PRIu64 " completed: %" PRIu64 " errors %" - PRIu64"\n", + " submitted: %" PRIu64 " completed: %" PRIu64 " errors: %" + PRIu64 " qfulls: %" PRIu64 "\n", hw->revision, hw->queue_id, hw->sq_depth_mask > 0 ? hw->sq_depth_mask + 1 : 0, hw->ridx, hw->cridx, hw->sq_head, hw->sq_tail, hw->cq_sq_head, hw->cq_head, hw->cqs_completed, hw->cqe_vld, - hw->submitted, hw->completed, hw->errors); + hw->submitted, hw->completed, hw->errors, hw->qfulls); hisi_dma_dump_queue(hw, f); hisi_dma_dump_common(hw, f); @@ -590,8 +592,10 @@ hisi_dma_copy(void *dev_private, uint16_t vchan, RTE_SET_USED(vchan); - if (((hw->sq_tail + 1) & hw->sq_depth_mask) == hw->sq_head) + if (((hw->sq_tail + 1) & hw->sq_depth_mask) == hw->sq_head) { + hw->qfulls++; return -ENOSPC; + } sqe->dw0 = rte_cpu_to_le_32(SQE_OPCODE_M2M); sqe->dw1 = 0; diff --git a/drivers/dma/hisilicon/hisi_dmadev.h b/drivers/dma/hisilicon/hisi_dmadev.h index 1eaa822db1..90b85322ca 100644 --- a/drivers/dma/hisilicon/hisi_dmadev.h +++ b/drivers/dma/hisilicon/hisi_dmadev.h @@ -241,6 +241,7 @@ struct hisi_dma_dev { uint64_t submitted; uint64_t completed; uint64_t errors; + uint64_t qfulls; /** * The following fields are not accessed in the I/O path, so they are -- 2.33.0