[RFC 0/3] Add support for GRE optional fields matching

[RFC 0/3] Add support for GRE optional fields matching

[Sean Zhang]

This patch set adds support for matching optional fields of GRE header.
The optional fields are checksum, key and sequence number. Currently, key
field is supported with pattern gre_key item '.. / gre / gre_key value is
xx / ..' with field gre_key in misc, but misc does not support matching of
checksum and sequence number of GRE.
To support matching of checksum and sequence number fields in GRE,
rdma-core needs the capbility of misc5 and support tunnel_header 0-3. Since
tunnel_header1 is used to match checksum, tunnel_header2 for key and
tunnel_header3 for sequence by hardware. If checksum and sequence number
not present in the pattern, use misc as before for the matching.
Application can still use gre_key item 'gre_key value is xx' for key
matching, the effect is the same if use 'gre_option key is xx'.
If using gre_option item, the flags in gre item should be correspondingly
set. For example, if using gre_option to match checksum, the c_bit should
be set '1' (.. / gre c_bit is 1 / gre_option checksum is xx / ..).

Sean Zhang (3):
  ethdev: support GRE optional fields
  app/testpmd: add gre_option item command
  net/mlx5: support matching on optional fields of GRE

 app/test-pmd/cmdline_flow.c                 |  57 ++++++++++++
 doc/guides/prog_guide/rte_flow.rst          |  16 ++++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |   6 ++
 drivers/common/mlx5/mlx5_devx_cmds.c        |   3 +
 drivers/net/mlx5/linux/mlx5_os.c            |   2 +
 drivers/net/mlx5/mlx5.h                     |   1 +
 drivers/net/mlx5/mlx5_flow.c                |  94 ++++++++++++++++++++
 drivers/net/mlx5/mlx5_flow.h                |   6 ++
 drivers/net/mlx5/mlx5_flow_dv.c             | 133 ++++++++++++++++++++++++++++
 lib/ethdev/rte_flow.c                       |   1 +
 lib/ethdev/rte_flow.h                       |  18 ++++
 11 files changed, 337 insertions(+)

-- 
1.8.3.1

[RFC 1/3] ethdev: support GRE optional fields

[Sean Zhang]

Add flow pattern items and header format for matching optional fields
(checksum/key/sequence) in GRE header. And the flags in gre item should
be correspondingly set with the new added items.

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
---
 doc/guides/prog_guide/rte_flow.rst | 16 ++++++++++++++++
 lib/ethdev/rte_flow.c              |  1 +
 lib/ethdev/rte_flow.h              | 18 ++++++++++++++++++
 3 files changed, 35 insertions(+)

diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
index c51ed88..48d5685 100644
--- a/doc/guides/prog_guide/rte_flow.rst
+++ b/doc/guides/prog_guide/rte_flow.rst
@@ -1113,6 +1113,22 @@ This should be preceded by item ``GRE``.
 - Value to be matched is a big-endian 32 bit integer.
 - When this item present it implicitly match K bit in default mask as "1"
 
+Item: ``GRE_OPTION``
+^^^^^^^^^^^^^^^^^^^^
+
+Matches a GRE optional fields (checksum/key/sequence).
+This should be preceded by item ``GRE``.
+
+- ``checksum``: checksum.
+- ``key``: key.
+- ``sequence``: sequence.
+- The items in GRE_OPTION do not change bit flags(c_bit/k_bit/s_bit) in GRE
+  item. The bit flags need be set with GRE item by application. When the items
+  present, the corresponding bits in GRE spec and mask should be set "1" by
+  application, it means to match specified value of the fields. When the items
+  no present, but the corresponding bits in GRE spec and mask is "1", it means
+  to match any value of the fields.
+
 Item: ``FUZZY``
 ^^^^^^^^^^^^^^^
 
diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c
index a93f68a..03bd1df 100644
--- a/lib/ethdev/rte_flow.c
+++ b/lib/ethdev/rte_flow.c
@@ -139,6 +139,7 @@ struct rte_flow_desc_data {
 	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
 	MK_FLOW_ITEM(TAG, sizeof(struct rte_flow_item_tag)),
 	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
+	MK_FLOW_ITEM(GRE_OPTION, sizeof(struct rte_gre_hdr_option)),
 	MK_FLOW_ITEM(GTP_PSC, sizeof(struct rte_flow_item_gtp_psc)),
 	MK_FLOW_ITEM(PPPOES, sizeof(struct rte_flow_item_pppoe)),
 	MK_FLOW_ITEM(PPPOED, sizeof(struct rte_flow_item_pppoe)),
diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h
index 1031fb2..27b4140 100644
--- a/lib/ethdev/rte_flow.h
+++ b/lib/ethdev/rte_flow.h
@@ -660,6 +660,13 @@ enum rte_flow_item_type {
 	 * See struct rte_flow_item_ppp.
 	 */
 	RTE_FLOW_ITEM_TYPE_PPP,
+
+	/**
+	 * Matches GRE optional fields.
+	 *
+	 * See struct rte_gre_hdr_option.
+	 */
+	RTE_FLOW_ITEM_TYPE_GRE_OPTION,
 };
 
 /**
@@ -1196,6 +1203,17 @@ struct rte_flow_item_gre {
 #endif
 
 /**
+ * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
+ *
+ * Matches GRE optional fields in header.
+ */
+struct rte_gre_hdr_option {
+	rte_be16_t checksum;
+	rte_be32_t key;
+	rte_be32_t sequence;
+};
+
+/**
  * RTE_FLOW_ITEM_TYPE_FUZZY
  *
  * Fuzzy pattern match, expect faster than default.
-- 
1.8.3.1

RE: [RFC 1/3] ethdev: support GRE optional fields

[Ori Kam]

Hi Sean,


> -----Original Message-----
> From: Sean Zhang <xiazhang@nvidia.com>
> Subject: [RFC 1/3] ethdev: support GRE optional fields
> 
> Add flow pattern items and header format for matching optional fields
> (checksum/key/sequence) in GRE header. And the flags in gre item should
> be correspondingly set with the new added items.
> 
> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> ---
>  doc/guides/prog_guide/rte_flow.rst | 16 ++++++++++++++++
>  lib/ethdev/rte_flow.c              |  1 +
>  lib/ethdev/rte_flow.h              | 18 ++++++++++++++++++
>  3 files changed, 35 insertions(+)
> 
> diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
> index c51ed88..48d5685 100644
> --- a/doc/guides/prog_guide/rte_flow.rst
> +++ b/doc/guides/prog_guide/rte_flow.rst
> @@ -1113,6 +1113,22 @@ This should be preceded by item ``GRE``.
>  - Value to be matched is a big-endian 32 bit integer.
>  - When this item present it implicitly match K bit in default mask as "1"
> 
> +Item: ``GRE_OPTION``
> +^^^^^^^^^^^^^^^^^^^^
> +
> +Matches a GRE optional fields (checksum/key/sequence).
> +This should be preceded by item ``GRE``.
> +
> +- ``checksum``: checksum.
> +- ``key``: key.
> +- ``sequence``: sequence.
> +- The items in GRE_OPTION do not change bit flags(c_bit/k_bit/s_bit) in GRE
> +  item. The bit flags need be set with GRE item by application. When the items
> +  present, the corresponding bits in GRE spec and mask should be set "1" by
> +  application, it means to match specified value of the fields. When the items
> +  no present, but the corresponding bits in GRE spec and mask is "1", it means
> +  to match any value of the fields.
> +
>  Item: ``FUZZY``
>  ^^^^^^^^^^^^^^^
> 
> diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c
> index a93f68a..03bd1df 100644
> --- a/lib/ethdev/rte_flow.c
> +++ b/lib/ethdev/rte_flow.c
> @@ -139,6 +139,7 @@ struct rte_flow_desc_data {
>  	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
>  	MK_FLOW_ITEM(TAG, sizeof(struct rte_flow_item_tag)),
>  	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
> +	MK_FLOW_ITEM(GRE_OPTION, sizeof(struct rte_gre_hdr_option)),

I think that this new item is making the gre_key redundant,
why not deprecate it?

>  	MK_FLOW_ITEM(GTP_PSC, sizeof(struct rte_flow_item_gtp_psc)),
>  	MK_FLOW_ITEM(PPPOES, sizeof(struct rte_flow_item_pppoe)),
>  	MK_FLOW_ITEM(PPPOED, sizeof(struct rte_flow_item_pppoe)),
> diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h
> index 1031fb2..27b4140 100644
> --- a/lib/ethdev/rte_flow.h
> +++ b/lib/ethdev/rte_flow.h
> @@ -660,6 +660,13 @@ enum rte_flow_item_type {
>  	 * See struct rte_flow_item_ppp.
>  	 */
>  	RTE_FLOW_ITEM_TYPE_PPP,
> +
> +	/**
> +	 * Matches GRE optional fields.
> +	 *
> +	 * See struct rte_gre_hdr_option.
> +	 */
> +	RTE_FLOW_ITEM_TYPE_GRE_OPTION,
>  };
> 
>  /**
> @@ -1196,6 +1203,17 @@ struct rte_flow_item_gre {
>  #endif
> 
>  /**
> + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
> + *
> + * Matches GRE optional fields in header.
> + */
> +struct rte_gre_hdr_option {
> +	rte_be16_t checksum;
> +	rte_be32_t key;
> +	rte_be32_t sequence;
> +};
> +
> +/**
>   * RTE_FLOW_ITEM_TYPE_FUZZY
>   *
>   * Fuzzy pattern match, expect faster than default.
> --
> 1.8.3.1

Best,
Ori

RE: [RFC 1/3] ethdev: support GRE optional fields

[Sean Zhang (Networking SW)]

Hi Ori,

> -----Original Message-----
> From: Ori Kam <orika@nvidia.com>
> Sent: Sunday, January 9, 2022 8:30 PM
> To: Sean Zhang (Networking SW) <xiazhang@nvidia.com>; Matan Azrad
> <matan@nvidia.com>; NBU-Contact-Thomas Monjalon (EXTERNAL)
> <thomas@monjalon.net>; Ferruh Yigit <ferruh.yigit@intel.com>; Andrew
> Rybchenko <andrew.rybchenko@oktetlabs.ru>
> Cc: dev@dpdk.org
> Subject: RE: [RFC 1/3] ethdev: support GRE optional fields
> 
> Hi Sean,
> 
> 
> > -----Original Message-----
> > From: Sean Zhang <xiazhang@nvidia.com>
> > Subject: [RFC 1/3] ethdev: support GRE optional fields
> >
> > Add flow pattern items and header format for matching optional fields
> > (checksum/key/sequence) in GRE header. And the flags in gre item
> > should be correspondingly set with the new added items.
> >
> > Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> > ---
> >  doc/guides/prog_guide/rte_flow.rst | 16 ++++++++++++++++
> >  lib/ethdev/rte_flow.c              |  1 +
> >  lib/ethdev/rte_flow.h              | 18 ++++++++++++++++++
> >  3 files changed, 35 insertions(+)
> >
> > diff --git a/doc/guides/prog_guide/rte_flow.rst
> > b/doc/guides/prog_guide/rte_flow.rst
> > index c51ed88..48d5685 100644
> > --- a/doc/guides/prog_guide/rte_flow.rst
> > +++ b/doc/guides/prog_guide/rte_flow.rst
> > @@ -1113,6 +1113,22 @@ This should be preceded by item ``GRE``.
> >  - Value to be matched is a big-endian 32 bit integer.
> >  - When this item present it implicitly match K bit in default mask as "1"
> >
> > +Item: ``GRE_OPTION``
> > +^^^^^^^^^^^^^^^^^^^^
> > +
> > +Matches a GRE optional fields (checksum/key/sequence).
> > +This should be preceded by item ``GRE``.
> > +
> > +- ``checksum``: checksum.
> > +- ``key``: key.
> > +- ``sequence``: sequence.
> > +- The items in GRE_OPTION do not change bit flags(c_bit/k_bit/s_bit)
> > +in GRE
> > +  item. The bit flags need be set with GRE item by application. When
> > +the items
> > +  present, the corresponding bits in GRE spec and mask should be set
> > +"1" by
> > +  application, it means to match specified value of the fields. When
> > +the items
> > +  no present, but the corresponding bits in GRE spec and mask is "1",
> > +it means
> > +  to match any value of the fields.
> > +
> >  Item: ``FUZZY``
> >  ^^^^^^^^^^^^^^^
> >
> > diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c index
> > a93f68a..03bd1df 100644
> > --- a/lib/ethdev/rte_flow.c
> > +++ b/lib/ethdev/rte_flow.c
> > @@ -139,6 +139,7 @@ struct rte_flow_desc_data {
> >  	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
> >  	MK_FLOW_ITEM(TAG, sizeof(struct rte_flow_item_tag)),
> >  	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
> > +	MK_FLOW_ITEM(GRE_OPTION, sizeof(struct rte_gre_hdr_option)),
> 
> I think that this new item is making the gre_key redundant, why not
> deprecate it?

Do you mean to add description like bellow?

  Item: ``GRE_KEY``
  ^^^^^^^^^^^^^^^
 +This action is deprecated. Consider `Item: GRE_OPTION`.

> 
> >  	MK_FLOW_ITEM(GTP_PSC, sizeof(struct rte_flow_item_gtp_psc)),
> >  	MK_FLOW_ITEM(PPPOES, sizeof(struct rte_flow_item_pppoe)),
> >  	MK_FLOW_ITEM(PPPOED, sizeof(struct rte_flow_item_pppoe)), diff -
> -git
> > a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h index 1031fb2..27b4140
> > 100644
> > --- a/lib/ethdev/rte_flow.h
> > +++ b/lib/ethdev/rte_flow.h
> > @@ -660,6 +660,13 @@ enum rte_flow_item_type {
> >  	 * See struct rte_flow_item_ppp.
> >  	 */
> >  	RTE_FLOW_ITEM_TYPE_PPP,
> > +
> > +	/**
> > +	 * Matches GRE optional fields.
> > +	 *
> > +	 * See struct rte_gre_hdr_option.
> > +	 */
> > +	RTE_FLOW_ITEM_TYPE_GRE_OPTION,
> >  };
> >
> >  /**
> > @@ -1196,6 +1203,17 @@ struct rte_flow_item_gre {  #endif
> >
> >  /**
> > + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
> > + *
> > + * Matches GRE optional fields in header.
> > + */
> > +struct rte_gre_hdr_option {
> > +	rte_be16_t checksum;
> > +	rte_be32_t key;
> > +	rte_be32_t sequence;
> > +};
> > +
> > +/**
> >   * RTE_FLOW_ITEM_TYPE_FUZZY
> >   *
> >   * Fuzzy pattern match, expect faster than default.
> > --
> > 1.8.3.1
> 
> Best,
> Ori

Thanks,
Sean

RE: [RFC 1/3] ethdev: support GRE optional fields

[Ori Kam]

Hi Sean,

> -----Original Message-----
> From: Sean Zhang (Networking SW) <xiazhang@nvidia.com>
> Sent: Tuesday, January 11, 2022 5:45 AM
> Subject: RE: [RFC 1/3] ethdev: support GRE optional fields
> 
> Hi Ori,
> 
> > -----Original Message-----
> > From: Ori Kam <orika@nvidia.com>
> > Sent: Sunday, January 9, 2022 8:30 PM
> > To: Sean Zhang (Networking SW) <xiazhang@nvidia.com>; Matan Azrad
> > <matan@nvidia.com>; NBU-Contact-Thomas Monjalon (EXTERNAL)
> > <thomas@monjalon.net>; Ferruh Yigit <ferruh.yigit@intel.com>; Andrew
> > Rybchenko <andrew.rybchenko@oktetlabs.ru>
> > Cc: dev@dpdk.org
> > Subject: RE: [RFC 1/3] ethdev: support GRE optional fields
> >
> > Hi Sean,
> >
> >
> > > -----Original Message-----
> > > From: Sean Zhang <xiazhang@nvidia.com>
> > > Subject: [RFC 1/3] ethdev: support GRE optional fields
> > >
> > > Add flow pattern items and header format for matching optional fields
> > > (checksum/key/sequence) in GRE header. And the flags in gre item
> > > should be correspondingly set with the new added items.
> > >
> > > Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> > > ---
> > >  doc/guides/prog_guide/rte_flow.rst | 16 ++++++++++++++++
> > >  lib/ethdev/rte_flow.c              |  1 +
> > >  lib/ethdev/rte_flow.h              | 18 ++++++++++++++++++
> > >  3 files changed, 35 insertions(+)
> > >
> > > diff --git a/doc/guides/prog_guide/rte_flow.rst
> > > b/doc/guides/prog_guide/rte_flow.rst
> > > index c51ed88..48d5685 100644
> > > --- a/doc/guides/prog_guide/rte_flow.rst
> > > +++ b/doc/guides/prog_guide/rte_flow.rst
> > > @@ -1113,6 +1113,22 @@ This should be preceded by item ``GRE``.
> > >  - Value to be matched is a big-endian 32 bit integer.
> > >  - When this item present it implicitly match K bit in default mask as "1"
> > >
> > > +Item: ``GRE_OPTION``
> > > +^^^^^^^^^^^^^^^^^^^^
> > > +
> > > +Matches a GRE optional fields (checksum/key/sequence).
> > > +This should be preceded by item ``GRE``.
> > > +
> > > +- ``checksum``: checksum.
> > > +- ``key``: key.
> > > +- ``sequence``: sequence.
> > > +- The items in GRE_OPTION do not change bit flags(c_bit/k_bit/s_bit)
> > > +in GRE
> > > +  item. The bit flags need be set with GRE item by application. When
> > > +the items
> > > +  present, the corresponding bits in GRE spec and mask should be set
> > > +"1" by
> > > +  application, it means to match specified value of the fields. When
> > > +the items
> > > +  no present, but the corresponding bits in GRE spec and mask is "1",
> > > +it means
> > > +  to match any value of the fields.
> > > +
> > >  Item: ``FUZZY``
> > >  ^^^^^^^^^^^^^^^
> > >
> > > diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c index
> > > a93f68a..03bd1df 100644
> > > --- a/lib/ethdev/rte_flow.c
> > > +++ b/lib/ethdev/rte_flow.c
> > > @@ -139,6 +139,7 @@ struct rte_flow_desc_data {
> > >  	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
> > >  	MK_FLOW_ITEM(TAG, sizeof(struct rte_flow_item_tag)),
> > >  	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
> > > +	MK_FLOW_ITEM(GRE_OPTION, sizeof(struct rte_gre_hdr_option)),
> >
> > I think that this new item is making the gre_key redundant, why not
> > deprecate it?
> 
> Do you mean to add description like bellow?
> 
>   Item: ``GRE_KEY``
>   ^^^^^^^^^^^^^^^
>  +This action is deprecated. Consider `Item: GRE_OPTION`.

Yes and also add the depreciation notice in the release notes,
there is also need to see if other PMD are using the GRE_KEY.
But to be clear do not remove this support now just send notice that it should
be removed.

> 
> >
> > >  	MK_FLOW_ITEM(GTP_PSC, sizeof(struct rte_flow_item_gtp_psc)),
> > >  	MK_FLOW_ITEM(PPPOES, sizeof(struct rte_flow_item_pppoe)),
> > >  	MK_FLOW_ITEM(PPPOED, sizeof(struct rte_flow_item_pppoe)), diff -
> > -git
> > > a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h index 1031fb2..27b4140
> > > 100644
> > > --- a/lib/ethdev/rte_flow.h
> > > +++ b/lib/ethdev/rte_flow.h
> > > @@ -660,6 +660,13 @@ enum rte_flow_item_type {
> > >  	 * See struct rte_flow_item_ppp.
> > >  	 */
> > >  	RTE_FLOW_ITEM_TYPE_PPP,
> > > +
> > > +	/**
> > > +	 * Matches GRE optional fields.
> > > +	 *
> > > +	 * See struct rte_gre_hdr_option.
> > > +	 */
> > > +	RTE_FLOW_ITEM_TYPE_GRE_OPTION,
> > >  };
> > >
> > >  /**
> > > @@ -1196,6 +1203,17 @@ struct rte_flow_item_gre {  #endif
> > >
> > >  /**
> > > + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
> > > + *
> > > + * Matches GRE optional fields in header.
> > > + */
> > > +struct rte_gre_hdr_option {
> > > +	rte_be16_t checksum;
> > > +	rte_be32_t key;
> > > +	rte_be32_t sequence;
> > > +};
> > > +
> > > +/**
> > >   * RTE_FLOW_ITEM_TYPE_FUZZY
> > >   *
> > >   * Fuzzy pattern match, expect faster than default.
> > > --
> > > 1.8.3.1
> >
> > Best,
> > Ori
> 
> Thanks,
> Sean

RE: [RFC 1/3] ethdev: support GRE optional fields

[Sean Zhang (Networking SW)]

Hi Ori,

> -----Original Message-----
> From: Ori Kam <orika@nvidia.com>
> Sent: Tuesday, January 11, 2022 3:24 PM
> To: Sean Zhang (Networking SW) <xiazhang@nvidia.com>; Matan Azrad
> <matan@nvidia.com>; NBU-Contact-Thomas Monjalon (EXTERNAL)
> <thomas@monjalon.net>; Ferruh Yigit <ferruh.yigit@intel.com>; Andrew
> Rybchenko <andrew.rybchenko@oktetlabs.ru>
> Cc: dev@dpdk.org
> Subject: RE: [RFC 1/3] ethdev: support GRE optional fields
> 
> Hi Sean,
> 
> > -----Original Message-----
> > From: Sean Zhang (Networking SW) <xiazhang@nvidia.com>
> > Sent: Tuesday, January 11, 2022 5:45 AM
> > Subject: RE: [RFC 1/3] ethdev: support GRE optional fields
> >
> > Hi Ori,
> >
> > > -----Original Message-----
> > > From: Ori Kam <orika@nvidia.com>
> > > Sent: Sunday, January 9, 2022 8:30 PM
> > > To: Sean Zhang (Networking SW) <xiazhang@nvidia.com>; Matan Azrad
> > > <matan@nvidia.com>; NBU-Contact-Thomas Monjalon (EXTERNAL)
> > > <thomas@monjalon.net>; Ferruh Yigit <ferruh.yigit@intel.com>; Andrew
> > > Rybchenko <andrew.rybchenko@oktetlabs.ru>
> > > Cc: dev@dpdk.org
> > > Subject: RE: [RFC 1/3] ethdev: support GRE optional fields
> > >
> > > Hi Sean,
> > >
> > >
> > > > -----Original Message-----
> > > > From: Sean Zhang <xiazhang@nvidia.com>
> > > > Subject: [RFC 1/3] ethdev: support GRE optional fields
> > > >
> > > > Add flow pattern items and header format for matching optional
> > > > fields
> > > > (checksum/key/sequence) in GRE header. And the flags in gre item
> > > > should be correspondingly set with the new added items.
> > > >
> > > > Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> > > > ---
> > > >  doc/guides/prog_guide/rte_flow.rst | 16 ++++++++++++++++
> > > >  lib/ethdev/rte_flow.c              |  1 +
> > > >  lib/ethdev/rte_flow.h              | 18 ++++++++++++++++++
> > > >  3 files changed, 35 insertions(+)
> > > >
> > > > diff --git a/doc/guides/prog_guide/rte_flow.rst
> > > > b/doc/guides/prog_guide/rte_flow.rst
> > > > index c51ed88..48d5685 100644
> > > > --- a/doc/guides/prog_guide/rte_flow.rst
> > > > +++ b/doc/guides/prog_guide/rte_flow.rst
> > > > @@ -1113,6 +1113,22 @@ This should be preceded by item ``GRE``.
> > > >  - Value to be matched is a big-endian 32 bit integer.
> > > >  - When this item present it implicitly match K bit in default mask as "1"
> > > >
> > > > +Item: ``GRE_OPTION``
> > > > +^^^^^^^^^^^^^^^^^^^^
> > > > +
> > > > +Matches a GRE optional fields (checksum/key/sequence).
> > > > +This should be preceded by item ``GRE``.
> > > > +
> > > > +- ``checksum``: checksum.
> > > > +- ``key``: key.
> > > > +- ``sequence``: sequence.
> > > > +- The items in GRE_OPTION do not change bit
> > > > +flags(c_bit/k_bit/s_bit) in GRE
> > > > +  item. The bit flags need be set with GRE item by application.
> > > > +When the items
> > > > +  present, the corresponding bits in GRE spec and mask should be
> > > > +set "1" by
> > > > +  application, it means to match specified value of the fields.
> > > > +When the items
> > > > +  no present, but the corresponding bits in GRE spec and mask is
> > > > +"1", it means
> > > > +  to match any value of the fields.
> > > > +
> > > >  Item: ``FUZZY``
> > > >  ^^^^^^^^^^^^^^^
> > > >
> > > > diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c index
> > > > a93f68a..03bd1df 100644
> > > > --- a/lib/ethdev/rte_flow.c
> > > > +++ b/lib/ethdev/rte_flow.c
> > > > @@ -139,6 +139,7 @@ struct rte_flow_desc_data {
> > > >  	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
> > > >  	MK_FLOW_ITEM(TAG, sizeof(struct rte_flow_item_tag)),
> > > >  	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
> > > > +	MK_FLOW_ITEM(GRE_OPTION, sizeof(struct rte_gre_hdr_option)),
> > >
> > > I think that this new item is making the gre_key redundant, why not
> > > deprecate it?
> >
> > Do you mean to add description like bellow?
> >
> >   Item: ``GRE_KEY``
> >   ^^^^^^^^^^^^^^^
> >  +This action is deprecated. Consider `Item: GRE_OPTION`.
> 
> Yes and also add the depreciation notice in the release notes, there is also
> need to see if other PMD are using the GRE_KEY.
> But to be clear do not remove this support now just send notice that it
> should be removed.

Got it, and will update in v2 patch.

Thanks,
Sean
> 
> >
> > >
> > > >  	MK_FLOW_ITEM(GTP_PSC, sizeof(struct rte_flow_item_gtp_psc)),
> > > >  	MK_FLOW_ITEM(PPPOES, sizeof(struct rte_flow_item_pppoe)),
> > > >  	MK_FLOW_ITEM(PPPOED, sizeof(struct rte_flow_item_pppoe)), diff -
> > > -git
> > > > a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h index
> > > > 1031fb2..27b4140
> > > > 100644
> > > > --- a/lib/ethdev/rte_flow.h
> > > > +++ b/lib/ethdev/rte_flow.h
> > > > @@ -660,6 +660,13 @@ enum rte_flow_item_type {
> > > >  	 * See struct rte_flow_item_ppp.
> > > >  	 */
> > > >  	RTE_FLOW_ITEM_TYPE_PPP,
> > > > +
> > > > +	/**
> > > > +	 * Matches GRE optional fields.
> > > > +	 *
> > > > +	 * See struct rte_gre_hdr_option.
> > > > +	 */
> > > > +	RTE_FLOW_ITEM_TYPE_GRE_OPTION,
> > > >  };
> > > >
> > > >  /**
> > > > @@ -1196,6 +1203,17 @@ struct rte_flow_item_gre {  #endif
> > > >
> > > >  /**
> > > > + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
> > > > + *
> > > > + * Matches GRE optional fields in header.
> > > > + */
> > > > +struct rte_gre_hdr_option {
> > > > +	rte_be16_t checksum;
> > > > +	rte_be32_t key;
> > > > +	rte_be32_t sequence;
> > > > +};
> > > > +
> > > > +/**
> > > >   * RTE_FLOW_ITEM_TYPE_FUZZY
> > > >   *
> > > >   * Fuzzy pattern match, expect faster than default.
> > > > --
> > > > 1.8.3.1
> > >
> > > Best,
> > > Ori
> >
> > Thanks,
> > Sean

Re: [RFC 1/3] ethdev: support GRE optional fields

[Ferruh Yigit]

On 12/30/2021 3:08 AM, Sean Zhang wrote:
> Add flow pattern items and header format for matching optional fields
> (checksum/key/sequence) in GRE header. And the flags in gre item should
> be correspondingly set with the new added items.
> 
> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> ---
>   doc/guides/prog_guide/rte_flow.rst | 16 ++++++++++++++++
>   lib/ethdev/rte_flow.c              |  1 +
>   lib/ethdev/rte_flow.h              | 18 ++++++++++++++++++
>   3 files changed, 35 insertions(+)
> 
> diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
> index c51ed88..48d5685 100644
> --- a/doc/guides/prog_guide/rte_flow.rst
> +++ b/doc/guides/prog_guide/rte_flow.rst
> @@ -1113,6 +1113,22 @@ This should be preceded by item ``GRE``.
>   - Value to be matched is a big-endian 32 bit integer.
>   - When this item present it implicitly match K bit in default mask as "1"
>   
> +Item: ``GRE_OPTION``
> +^^^^^^^^^^^^^^^^^^^^
> +
> +Matches a GRE optional fields (checksum/key/sequence).
> +This should be preceded by item ``GRE``.
> +
> +- ``checksum``: checksum.
> +- ``key``: key.
> +- ``sequence``: sequence.
> +- The items in GRE_OPTION do not change bit flags(c_bit/k_bit/s_bit) in GRE
> +  item. The bit flags need be set with GRE item by application. When the items
> +  present, the corresponding bits in GRE spec and mask should be set "1" by
> +  application, it means to match specified value of the fields. When the items
> +  no present, but the corresponding bits in GRE spec and mask is "1", it means
> +  to match any value of the fields.
> +
>   Item: ``FUZZY``
>   ^^^^^^^^^^^^^^^
>   
> diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c
> index a93f68a..03bd1df 100644
> --- a/lib/ethdev/rte_flow.c
> +++ b/lib/ethdev/rte_flow.c
> @@ -139,6 +139,7 @@ struct rte_flow_desc_data {
>   	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
>   	MK_FLOW_ITEM(TAG, sizeof(struct rte_flow_item_tag)),
>   	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
> +	MK_FLOW_ITEM(GRE_OPTION, sizeof(struct rte_gre_hdr_option)),
>   	MK_FLOW_ITEM(GTP_PSC, sizeof(struct rte_flow_item_gtp_psc)),
>   	MK_FLOW_ITEM(PPPOES, sizeof(struct rte_flow_item_pppoe)),
>   	MK_FLOW_ITEM(PPPOED, sizeof(struct rte_flow_item_pppoe)),
> diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h
> index 1031fb2..27b4140 100644
> --- a/lib/ethdev/rte_flow.h
> +++ b/lib/ethdev/rte_flow.h
> @@ -660,6 +660,13 @@ enum rte_flow_item_type {
>   	 * See struct rte_flow_item_ppp.
>   	 */
>   	RTE_FLOW_ITEM_TYPE_PPP,
> +
> +	/**
> +	 * Matches GRE optional fields.
> +	 *
> +	 * See struct rte_gre_hdr_option.
> +	 */
> +	RTE_FLOW_ITEM_TYPE_GRE_OPTION,
>   };
>   
>   /**
> @@ -1196,6 +1203,17 @@ struct rte_flow_item_gre {
>   #endif
>   
>   /**
> + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
> + *
> + * Matches GRE optional fields in header.
> + */
> +struct rte_gre_hdr_option {
> +	rte_be16_t checksum;
> +	rte_be32_t key;
> +	rte_be32_t sequence;
> +};
> +

Hi Ori, Andrew,

The decision was to have protocol structs in the net library and flow structs
use from there, wasn't it?
(Btw, a deprecation notice is still pending to clear some existing ones)

So for the GRE optional fields, what about having a struct in the 'rte_gre.h'?
(Also perhaps an GRE extended protocol header can be defined combining
'rte_gre_hdr' and optional fields struct.)
Later flow API struct can embed that struct.

Re: [RFC 1/3] ethdev: support GRE optional fields

[Thomas Monjalon]

19/01/2022 10:53, Ferruh Yigit:
> On 12/30/2021 3:08 AM, Sean Zhang wrote:
> > --- a/lib/ethdev/rte_flow.h
> > +++ b/lib/ethdev/rte_flow.h
> >   /**
> > + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
> > + *
> > + * Matches GRE optional fields in header.
> > + */
> > +struct rte_gre_hdr_option {
> > +	rte_be16_t checksum;
> > +	rte_be32_t key;
> > +	rte_be32_t sequence;
> > +};
> > +
> 
> Hi Ori, Andrew,
> 
> The decision was to have protocol structs in the net library and flow structs
> use from there, wasn't it?
> (Btw, a deprecation notice is still pending to clear some existing ones)
> 
> So for the GRE optional fields, what about having a struct in the 'rte_gre.h'?
> (Also perhaps an GRE extended protocol header can be defined combining
> 'rte_gre_hdr' and optional fields struct.)
> Later flow API struct can embed that struct.

+1 for using librte_net.
This addition in rte_flow looks to be a mistake.
Please fix in the next version.

RE: [RFC 1/3] ethdev: support GRE optional fields

[Ori Kam]

Hi,

> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Subject: Re: [RFC 1/3] ethdev: support GRE optional fields
> 
> 19/01/2022 10:53, Ferruh Yigit:
> > On 12/30/2021 3:08 AM, Sean Zhang wrote:
> > > --- a/lib/ethdev/rte_flow.h
> > > +++ b/lib/ethdev/rte_flow.h
> > >   /**
> > > + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
> > > + *
> > > + * Matches GRE optional fields in header.
> > > + */
> > > +struct rte_gre_hdr_option {
> > > +	rte_be16_t checksum;
> > > +	rte_be32_t key;
> > > +	rte_be32_t sequence;
> > > +};
> > > +
> >
> > Hi Ori, Andrew,
> >
> > The decision was to have protocol structs in the net library and flow structs
> > use from there, wasn't it?
> > (Btw, a deprecation notice is still pending to clear some existing ones)
> >
> > So for the GRE optional fields, what about having a struct in the 'rte_gre.h'?
> > (Also perhaps an GRE extended protocol header can be defined combining
> > 'rte_gre_hdr' and optional fields struct.)
> > Later flow API struct can embed that struct.
> 
> +1 for using librte_net.
> This addition in rte_flow looks to be a mistake.
> Please fix the next version.
> 
Nice idea,
but my main concern is that the header should have the header is defined.
Since some of the fields are optional this will look something like this:
gre_hdr_option_checksum {
rte_be_16_t checksum;
}

gre_hdr_option_key {
rte_be_32_t key;
}

gre_hdr_option_ sequence {
rte_be_32_t sequence;
}

I don't want to have so many rte_flow_items,
Has more and more protocols have optional data it doesn't make sense to create the item for each.

If I'm looking at it from an ideal place, I would like that the optional fields will be part of the original item.
For example in test pmd I would like to write:
Eth / ipv4 / udp / gre flags is key & checksum checksum is yyy key is xxx / end
And not 
Eth / ipv4 / udp / gre flags is key & checksum / gre_option checksum is yyy key is xxx / end
This means that the structure will look like this:
struct rte_flow_item_gre {
	union {
		struct {
			/**
		 	* Checksum (1b), reserved 0 (12b), version (3b).
			 * Refer to RFC 2784.
			 */
			rte_be16_t c_rsvd0_ver;
			rte_be16_t protocol; /**< Protocol type. */
		}
		struct rte_gre_hdr hdr
	}
	rte_be_16_t checksum;
	rte_be_32_t key;
	rte_be_32_t sequence;
};
The main issue with this is that it breaks ABI,
Maybe to solve this we can create a new structure gre_ext?

In any way I think we should think how we allow adding members to structures without 
ABI breakage.

Best,
Ori

RE: [RFC 1/3] ethdev: support GRE optional fields

[Sean Zhang (Networking SW)]

Hi,

> -----Original Message-----
> From: Ori Kam <orika@nvidia.com>
> Sent: Wednesday, January 19, 2022 6:57 PM
> To: NBU-Contact-Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>;
> Sean Zhang (Networking SW) <xiazhang@nvidia.com>; Matan Azrad
> <matan@nvidia.com>; Ferruh Yigit <ferruh.yigit@intel.com>
> Cc: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>; dev@dpdk.org
> Subject: RE: [RFC 1/3] ethdev: support GRE optional fields
> 
> Hi,
> 
> > -----Original Message-----
> > From: Thomas Monjalon <thomas@monjalon.net>
> > Subject: Re: [RFC 1/3] ethdev: support GRE optional fields
> >
> > 19/01/2022 10:53, Ferruh Yigit:
> > > On 12/30/2021 3:08 AM, Sean Zhang wrote:
> > > > --- a/lib/ethdev/rte_flow.h
> > > > +++ b/lib/ethdev/rte_flow.h
> > > >   /**
> > > > + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
> > > > + *
> > > > + * Matches GRE optional fields in header.
> > > > + */
> > > > +struct rte_gre_hdr_option {
> > > > +	rte_be16_t checksum;
> > > > +	rte_be32_t key;
> > > > +	rte_be32_t sequence;
> > > > +};
> > > > +
> > >
> > > Hi Ori, Andrew,
> > >
> > > The decision was to have protocol structs in the net library and
> > > flow structs use from there, wasn't it?
> > > (Btw, a deprecation notice is still pending to clear some existing
> > > ones)
> > >
> > > So for the GRE optional fields, what about having a struct in the
> 'rte_gre.h'?
> > > (Also perhaps an GRE extended protocol header can be defined
> > > combining 'rte_gre_hdr' and optional fields struct.) Later flow API
> > > struct can embed that struct.
> >
> > +1 for using librte_net.
> > This addition in rte_flow looks to be a mistake.
> > Please fix the next version.
> >
> Nice idea,
> but my main concern is that the header should have the header is defined.
> Since some of the fields are optional this will look something like this:
> gre_hdr_option_checksum {
> rte_be_16_t checksum;
> }
> 
> gre_hdr_option_key {
> rte_be_32_t key;
> }
> 
> gre_hdr_option_ sequence {
> rte_be_32_t sequence;
> }
> 
> I don't want to have so many rte_flow_items, Has more and more protocols
> have optional data it doesn't make sense to create the item for each.
> 
> If I'm looking at it from an ideal place, I would like that the optional fields will
> be part of the original item.
> For example in test pmd I would like to write:
> Eth / ipv4 / udp / gre flags is key & checksum checksum is yyy key is xxx / end
> And not Eth / ipv4 / udp / gre flags is key & checksum / gre_option checksum
> is yyy key is xxx / end This means that the structure will look like this:
> struct rte_flow_item_gre {
> 	union {
> 		struct {
> 			/**
> 		 	* Checksum (1b), reserved 0 (12b), version (3b).
> 			 * Refer to RFC 2784.
> 			 */
> 			rte_be16_t c_rsvd0_ver;
> 			rte_be16_t protocol; /**< Protocol type. */
> 		}
> 		struct rte_gre_hdr hdr
> 	}
> 	rte_be_16_t checksum;
> 	rte_be_32_t key;
> 	rte_be_32_t sequence;
> };
> The main issue with this is that it breaks ABI, Maybe to solve this we can
> create a new structure gre_ext?
> 
> In any way I think we should think how we allow adding members to
> structures without ABI breakage.
> 
> Best,
> Ori

Thanks for the comments and suggestion.
So the acceptable solution is to have new structs define in rte_gre.h?
struct gre_hdr_opt_checksum {
	rte_be_16_t checksum;
}
 
struct gre_hdr_opt_key {
	rte_be_32_t key;
}
 
struct gre_hdr_opt_ sequence {
	rte_be_32_t sequence;
}

And to add new struct gre_ext defined in rte_flow.h:
struct gre_ext {
	struct rte_gre_hdr hdr;
	struct gre_hdr_opt_checkum checksum;
	struct rte_hdr_opt_key key;
	struct rte_hdr_opt_seq seq;
};

And we use struct gre_ext for this new added flow item gre_option.

Correct me if my understanding is not right.

Thanks,
Sean

Re: [RFC 1/3] ethdev: support GRE optional fields

[Ferruh Yigit]

On 1/25/2022 9:49 AM, Sean Zhang (Networking SW) wrote:
> Hi,
> 
>> -----Original Message-----
>> From: Ori Kam <orika@nvidia.com>
>> Sent: Wednesday, January 19, 2022 6:57 PM
>> To: NBU-Contact-Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>;
>> Sean Zhang (Networking SW) <xiazhang@nvidia.com>; Matan Azrad
>> <matan@nvidia.com>; Ferruh Yigit <ferruh.yigit@intel.com>
>> Cc: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>; dev@dpdk.org
>> Subject: RE: [RFC 1/3] ethdev: support GRE optional fields
>>
>> Hi,
>>
>>> -----Original Message-----
>>> From: Thomas Monjalon <thomas@monjalon.net>
>>> Subject: Re: [RFC 1/3] ethdev: support GRE optional fields
>>>
>>> 19/01/2022 10:53, Ferruh Yigit:
>>>> On 12/30/2021 3:08 AM, Sean Zhang wrote:
>>>>> --- a/lib/ethdev/rte_flow.h
>>>>> +++ b/lib/ethdev/rte_flow.h
>>>>>    /**
>>>>> + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
>>>>> + *
>>>>> + * Matches GRE optional fields in header.
>>>>> + */
>>>>> +struct rte_gre_hdr_option {
>>>>> +	rte_be16_t checksum;
>>>>> +	rte_be32_t key;
>>>>> +	rte_be32_t sequence;
>>>>> +};
>>>>> +
>>>>
>>>> Hi Ori, Andrew,
>>>>
>>>> The decision was to have protocol structs in the net library and
>>>> flow structs use from there, wasn't it?
>>>> (Btw, a deprecation notice is still pending to clear some existing
>>>> ones)
>>>>
>>>> So for the GRE optional fields, what about having a struct in the
>> 'rte_gre.h'?
>>>> (Also perhaps an GRE extended protocol header can be defined
>>>> combining 'rte_gre_hdr' and optional fields struct.) Later flow API
>>>> struct can embed that struct.
>>>
>>> +1 for using librte_net.
>>> This addition in rte_flow looks to be a mistake.
>>> Please fix the next version.
>>>
>> Nice idea,
>> but my main concern is that the header should have the header is defined.
>> Since some of the fields are optional this will look something like this:
>> gre_hdr_option_checksum {
>> rte_be_16_t checksum;
>> }
>>
>> gre_hdr_option_key {
>> rte_be_32_t key;
>> }
>>
>> gre_hdr_option_ sequence {
>> rte_be_32_t sequence;
>> }
>>
>> I don't want to have so many rte_flow_items, Has more and more protocols
>> have optional data it doesn't make sense to create the item for each.
>>
>> If I'm looking at it from an ideal place, I would like that the optional fields will
>> be part of the original item.
>> For example in test pmd I would like to write:
>> Eth / ipv4 / udp / gre flags is key & checksum checksum is yyy key is xxx / end
>> And not Eth / ipv4 / udp / gre flags is key & checksum / gre_option checksum
>> is yyy key is xxx / end This means that the structure will look like this:
>> struct rte_flow_item_gre {
>> 	union {
>> 		struct {
>> 			/**
>> 		 	* Checksum (1b), reserved 0 (12b), version (3b).
>> 			 * Refer to RFC 2784.
>> 			 */
>> 			rte_be16_t c_rsvd0_ver;
>> 			rte_be16_t protocol; /**< Protocol type. */
>> 		}
>> 		struct rte_gre_hdr hdr
>> 	}
>> 	rte_be_16_t checksum;
>> 	rte_be_32_t key;
>> 	rte_be_32_t sequence;
>> };
>> The main issue with this is that it breaks ABI, Maybe to solve this we can
>> create a new structure gre_ext?
>>
>> In any way I think we should think how we allow adding members to
>> structures without ABI breakage.
>>
>> Best,
>> Ori
> 
> Thanks for the comments and suggestion.
> So the acceptable solution is to have new structs define in rte_gre.h?
> struct gre_hdr_opt_checksum {
> 	rte_be_16_t checksum;
> }
>   
> struct gre_hdr_opt_key {
> 	rte_be_32_t key;
> }
>   
> struct gre_hdr_opt_ sequence {
> 	rte_be_32_t sequence;
> }
> 
> And to add new struct gre_ext defined in rte_flow.h:
> struct gre_ext {
> 	struct rte_gre_hdr hdr;
> 	struct gre_hdr_opt_checkum checksum;
> 	struct rte_hdr_opt_key key;
> 	struct rte_hdr_opt_seq seq;
> };
> 
> And we use struct gre_ext for this new added flow item gre_option.
> 

What about having a struct for 'options' and use in in flow item for options,
like:

struct gre_hdr_opt {
   struct gre_hdr_opt_checkum checksum;
   struct rte_hdr_opt_key key;
   struct rte_hdr_opt_seq seq;
}

struct gre_hdr_ext {
   struct rte_gre_hdr hdr;
   struct gre_hdr_opt;
}

struct rte_flow_item_gre_opt {
   struct gre_hdr_opt hdr;
}

> Correct me if my understanding is not right.
> 
> Thanks,
> Sean
> 
> 

RE: [RFC 1/3] ethdev: support GRE optional fields

[Ori Kam]

Hi Ferruh,

> -----Original Message-----
> From: Ferruh Yigit <ferruh.yigit@intel.com>
> Subject: Re: [RFC 1/3] ethdev: support GRE optional fields
> 
> On 1/25/2022 9:49 AM, Sean Zhang (Networking SW) wrote:
> > Hi,
> >
> >> -----Original Message-----
> >> From: Ori Kam <orika@nvidia.com>
> >> Sent: Wednesday, January 19, 2022 6:57 PM
> >> To: NBU-Contact-Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>;
> >> Sean Zhang (Networking SW) <xiazhang@nvidia.com>; Matan Azrad
> >> <matan@nvidia.com>; Ferruh Yigit <ferruh.yigit@intel.com>
> >> Cc: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>; dev@dpdk.org
> >> Subject: RE: [RFC 1/3] ethdev: support GRE optional fields
> >>
> >> Hi,
> >>
> >>> -----Original Message-----
> >>> From: Thomas Monjalon <thomas@monjalon.net>
> >>> Subject: Re: [RFC 1/3] ethdev: support GRE optional fields
> >>>
> >>> 19/01/2022 10:53, Ferruh Yigit:
> >>>> On 12/30/2021 3:08 AM, Sean Zhang wrote:
> >>>>> --- a/lib/ethdev/rte_flow.h
> >>>>> +++ b/lib/ethdev/rte_flow.h
> >>>>>    /**
> >>>>> + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
> >>>>> + *
> >>>>> + * Matches GRE optional fields in header.
> >>>>> + */
> >>>>> +struct rte_gre_hdr_option {
> >>>>> +	rte_be16_t checksum;
> >>>>> +	rte_be32_t key;
> >>>>> +	rte_be32_t sequence;
> >>>>> +};
> >>>>> +
> >>>>
> >>>> Hi Ori, Andrew,
> >>>>
> >>>> The decision was to have protocol structs in the net library and
> >>>> flow structs use from there, wasn't it?
> >>>> (Btw, a deprecation notice is still pending to clear some existing
> >>>> ones)
> >>>>
> >>>> So for the GRE optional fields, what about having a struct in the
> >> 'rte_gre.h'?
> >>>> (Also perhaps an GRE extended protocol header can be defined
> >>>> combining 'rte_gre_hdr' and optional fields struct.) Later flow API
> >>>> struct can embed that struct.
> >>>
> >>> +1 for using librte_net.
> >>> This addition in rte_flow looks to be a mistake.
> >>> Please fix the next version.
> >>>
> >> Nice idea,
> >> but my main concern is that the header should have the header is defined.
> >> Since some of the fields are optional this will look something like this:
> >> gre_hdr_option_checksum {
> >> rte_be_16_t checksum;
> >> }
> >>
> >> gre_hdr_option_key {
> >> rte_be_32_t key;
> >> }
> >>
> >> gre_hdr_option_ sequence {
> >> rte_be_32_t sequence;
> >> }
> >>
> >> I don't want to have so many rte_flow_items, Has more and more protocols
> >> have optional data it doesn't make sense to create the item for each.
> >>
> >> If I'm looking at it from an ideal place, I would like that the optional fields will
> >> be part of the original item.
> >> For example in test pmd I would like to write:
> >> Eth / ipv4 / udp / gre flags is key & checksum checksum is yyy key is xxx / end
> >> And not Eth / ipv4 / udp / gre flags is key & checksum / gre_option checksum
> >> is yyy key is xxx / end This means that the structure will look like this:
> >> struct rte_flow_item_gre {
> >> 	union {
> >> 		struct {
> >> 			/**
> >> 		 	* Checksum (1b), reserved 0 (12b), version (3b).
> >> 			 * Refer to RFC 2784.
> >> 			 */
> >> 			rte_be16_t c_rsvd0_ver;
> >> 			rte_be16_t protocol; /**< Protocol type. */
> >> 		}
> >> 		struct rte_gre_hdr hdr
> >> 	}
> >> 	rte_be_16_t checksum;
> >> 	rte_be_32_t key;
> >> 	rte_be_32_t sequence;
> >> };
> >> The main issue with this is that it breaks ABI, Maybe to solve this we can
> >> create a new structure gre_ext?
> >>
> >> In any way I think we should think how we allow adding members to
> >> structures without ABI breakage.
> >>
> >> Best,
> >> Ori
> >
> > Thanks for the comments and suggestion.
> > So the acceptable solution is to have new structs define in rte_gre.h?
> > struct gre_hdr_opt_checksum {
> > 	rte_be_16_t checksum;
> > }
> >
> > struct gre_hdr_opt_key {
> > 	rte_be_32_t key;
> > }
> >
> > struct gre_hdr_opt_ sequence {
> > 	rte_be_32_t sequence;
> > }
> >
> > And to add new struct gre_ext defined in rte_flow.h:
> > struct gre_ext {
> > 	struct rte_gre_hdr hdr;
> > 	struct gre_hdr_opt_checkum checksum;
> > 	struct rte_hdr_opt_key key;
> > 	struct rte_hdr_opt_seq seq;
> > };
> >
> > And we use struct gre_ext for this new added flow item gre_option.
> >
> 
> What about having a struct for 'options' and use in in flow item for options,
> like:
> 
> struct gre_hdr_opt {
>    struct gre_hdr_opt_checkum checksum;
>    struct rte_hdr_opt_key key;
>    struct rte_hdr_opt_seq seq;
> }
> 
> struct gre_hdr_ext {
>    struct rte_gre_hdr hdr;
>    struct gre_hdr_opt;
> }
> 
> struct rte_flow_item_gre_opt {
>    struct gre_hdr_opt hdr;
> }

Fom my understanding the header should reflect structures
as they appear in the spec.

If we look at the spec, from my understanding each of those items is stand-alone.
It is possible to have just key or key and seq or any other combination.
So the struct you suggested is not valid struct in gre header.

If you are O.K with adding such a struct to the gre file I will also be O.K with it.

Best,
Ori
> 
> > Correct me if my understanding is not right.
> >
> > Thanks,
> > Sean
> >
> >

Re: [RFC 1/3] ethdev: support GRE optional fields

[Ferruh Yigit]

On 1/25/2022 1:06 PM, Ori Kam wrote:
> Hi Ferruh,
> 
>> -----Original Message-----
>> From: Ferruh Yigit <ferruh.yigit@intel.com>
>> Subject: Re: [RFC 1/3] ethdev: support GRE optional fields
>>
>> On 1/25/2022 9:49 AM, Sean Zhang (Networking SW) wrote:
>>> Hi,
>>>
>>>> -----Original Message-----
>>>> From: Ori Kam <orika@nvidia.com>
>>>> Sent: Wednesday, January 19, 2022 6:57 PM
>>>> To: NBU-Contact-Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>;
>>>> Sean Zhang (Networking SW) <xiazhang@nvidia.com>; Matan Azrad
>>>> <matan@nvidia.com>; Ferruh Yigit <ferruh.yigit@intel.com>
>>>> Cc: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>; dev@dpdk.org
>>>> Subject: RE: [RFC 1/3] ethdev: support GRE optional fields
>>>>
>>>> Hi,
>>>>
>>>>> -----Original Message-----
>>>>> From: Thomas Monjalon <thomas@monjalon.net>
>>>>> Subject: Re: [RFC 1/3] ethdev: support GRE optional fields
>>>>>
>>>>> 19/01/2022 10:53, Ferruh Yigit:
>>>>>> On 12/30/2021 3:08 AM, Sean Zhang wrote:
>>>>>>> --- a/lib/ethdev/rte_flow.h
>>>>>>> +++ b/lib/ethdev/rte_flow.h
>>>>>>>     /**
>>>>>>> + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
>>>>>>> + *
>>>>>>> + * Matches GRE optional fields in header.
>>>>>>> + */
>>>>>>> +struct rte_gre_hdr_option {
>>>>>>> +	rte_be16_t checksum;
>>>>>>> +	rte_be32_t key;
>>>>>>> +	rte_be32_t sequence;
>>>>>>> +};
>>>>>>> +
>>>>>>
>>>>>> Hi Ori, Andrew,
>>>>>>
>>>>>> The decision was to have protocol structs in the net library and
>>>>>> flow structs use from there, wasn't it?
>>>>>> (Btw, a deprecation notice is still pending to clear some existing
>>>>>> ones)
>>>>>>
>>>>>> So for the GRE optional fields, what about having a struct in the
>>>> 'rte_gre.h'?
>>>>>> (Also perhaps an GRE extended protocol header can be defined
>>>>>> combining 'rte_gre_hdr' and optional fields struct.) Later flow API
>>>>>> struct can embed that struct.
>>>>>
>>>>> +1 for using librte_net.
>>>>> This addition in rte_flow looks to be a mistake.
>>>>> Please fix the next version.
>>>>>
>>>> Nice idea,
>>>> but my main concern is that the header should have the header is defined.
>>>> Since some of the fields are optional this will look something like this:
>>>> gre_hdr_option_checksum {
>>>> rte_be_16_t checksum;
>>>> }
>>>>
>>>> gre_hdr_option_key {
>>>> rte_be_32_t key;
>>>> }
>>>>
>>>> gre_hdr_option_ sequence {
>>>> rte_be_32_t sequence;
>>>> }
>>>>
>>>> I don't want to have so many rte_flow_items, Has more and more protocols
>>>> have optional data it doesn't make sense to create the item for each.
>>>>
>>>> If I'm looking at it from an ideal place, I would like that the optional fields will
>>>> be part of the original item.
>>>> For example in test pmd I would like to write:
>>>> Eth / ipv4 / udp / gre flags is key & checksum checksum is yyy key is xxx / end
>>>> And not Eth / ipv4 / udp / gre flags is key & checksum / gre_option checksum
>>>> is yyy key is xxx / end This means that the structure will look like this:
>>>> struct rte_flow_item_gre {
>>>> 	union {
>>>> 		struct {
>>>> 			/**
>>>> 		 	* Checksum (1b), reserved 0 (12b), version (3b).
>>>> 			 * Refer to RFC 2784.
>>>> 			 */
>>>> 			rte_be16_t c_rsvd0_ver;
>>>> 			rte_be16_t protocol; /**< Protocol type. */
>>>> 		}
>>>> 		struct rte_gre_hdr hdr
>>>> 	}
>>>> 	rte_be_16_t checksum;
>>>> 	rte_be_32_t key;
>>>> 	rte_be_32_t sequence;
>>>> };
>>>> The main issue with this is that it breaks ABI, Maybe to solve this we can
>>>> create a new structure gre_ext?
>>>>
>>>> In any way I think we should think how we allow adding members to
>>>> structures without ABI breakage.
>>>>
>>>> Best,
>>>> Ori
>>>
>>> Thanks for the comments and suggestion.
>>> So the acceptable solution is to have new structs define in rte_gre.h?
>>> struct gre_hdr_opt_checksum {
>>> 	rte_be_16_t checksum;
>>> }
>>>
>>> struct gre_hdr_opt_key {
>>> 	rte_be_32_t key;
>>> }
>>>
>>> struct gre_hdr_opt_ sequence {
>>> 	rte_be_32_t sequence;
>>> }
>>>
>>> And to add new struct gre_ext defined in rte_flow.h:
>>> struct gre_ext {
>>> 	struct rte_gre_hdr hdr;
>>> 	struct gre_hdr_opt_checkum checksum;
>>> 	struct rte_hdr_opt_key key;
>>> 	struct rte_hdr_opt_seq seq;
>>> };
>>>
>>> And we use struct gre_ext for this new added flow item gre_option.
>>>
>>
>> What about having a struct for 'options' and use in in flow item for options,
>> like:
>>
>> struct gre_hdr_opt {
>>     struct gre_hdr_opt_checkum checksum;
>>     struct rte_hdr_opt_key key;
>>     struct rte_hdr_opt_seq seq;
>> }
>>
>> struct gre_hdr_ext {
>>     struct rte_gre_hdr hdr;
>>     struct gre_hdr_opt;
>> }
>>
>> struct rte_flow_item_gre_opt {
>>     struct gre_hdr_opt hdr;
>> }
> 
> Fom my understanding the header should reflect structures
> as they appear in the spec.
> 
> If we look at the spec, from my understanding each of those items is stand-alone.
> It is possible to have just key or key and seq or any other combination.
> So the struct you suggested is not valid struct in gre header.
> 

If it is not valid header representation, please forget about it.

But this means initially suggested 'struct gre_ext' is wrong, right?

So should 'rte_flow_item_gre_opt' use separate structs, like:

struct rte_flow_item_gre_opt {
   struct gre_hdr_opt_checkum checksum;
   struct rte_hdr_opt_key key;
   struct rte_hdr_opt_seq seq;
}


> If you are O.K with adding such a struct to the gre file I will also be O.K with it.
> 
> Best,
> Ori
>>
>>> Correct me if my understanding is not right.
>>>
>>> Thanks,
>>> Sean
>>>
>>>
> 

RE: [RFC 1/3] ethdev: support GRE optional fields

[Ori Kam]

Hi Ferruh,

> -----Original Message-----
> From: Ferruh Yigit <ferruh.yigit@intel.com>
> Sent: Tuesday, January 25, 2022 4:29 PM
> Subject: Re: [RFC 1/3] ethdev: support GRE optional fields
> 
> On 1/25/2022 1:06 PM, Ori Kam wrote:
> > Hi Ferruh,
> >
> >> -----Original Message-----
> >> From: Ferruh Yigit <ferruh.yigit@intel.com>
> >> Subject: Re: [RFC 1/3] ethdev: support GRE optional fields
> >>
> >> On 1/25/2022 9:49 AM, Sean Zhang (Networking SW) wrote:
> >>> Hi,
> >>>
> >>>> -----Original Message-----
> >>>> From: Ori Kam <orika@nvidia.com>
> >>>> Sent: Wednesday, January 19, 2022 6:57 PM
> >>>> To: NBU-Contact-Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>;
> >>>> Sean Zhang (Networking SW) <xiazhang@nvidia.com>; Matan Azrad
> >>>> <matan@nvidia.com>; Ferruh Yigit <ferruh.yigit@intel.com>
> >>>> Cc: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>; dev@dpdk.org
> >>>> Subject: RE: [RFC 1/3] ethdev: support GRE optional fields
> >>>>
> >>>> Hi,
> >>>>
> >>>>> -----Original Message-----
> >>>>> From: Thomas Monjalon <thomas@monjalon.net>
> >>>>> Subject: Re: [RFC 1/3] ethdev: support GRE optional fields
> >>>>>
> >>>>> 19/01/2022 10:53, Ferruh Yigit:
> >>>>>> On 12/30/2021 3:08 AM, Sean Zhang wrote:
> >>>>>>> --- a/lib/ethdev/rte_flow.h
> >>>>>>> +++ b/lib/ethdev/rte_flow.h
> >>>>>>>     /**
> >>>>>>> + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
> >>>>>>> + *
> >>>>>>> + * Matches GRE optional fields in header.
> >>>>>>> + */
> >>>>>>> +struct rte_gre_hdr_option {
> >>>>>>> +	rte_be16_t checksum;
> >>>>>>> +	rte_be32_t key;
> >>>>>>> +	rte_be32_t sequence;
> >>>>>>> +};
> >>>>>>> +
> >>>>>>
> >>>>>> Hi Ori, Andrew,
> >>>>>>
> >>>>>> The decision was to have protocol structs in the net library and
> >>>>>> flow structs use from there, wasn't it?
> >>>>>> (Btw, a deprecation notice is still pending to clear some existing
> >>>>>> ones)
> >>>>>>
> >>>>>> So for the GRE optional fields, what about having a struct in the
> >>>> 'rte_gre.h'?
> >>>>>> (Also perhaps an GRE extended protocol header can be defined
> >>>>>> combining 'rte_gre_hdr' and optional fields struct.) Later flow API
> >>>>>> struct can embed that struct.
> >>>>>
> >>>>> +1 for using librte_net.
> >>>>> This addition in rte_flow looks to be a mistake.
> >>>>> Please fix the next version.
> >>>>>
> >>>> Nice idea,
> >>>> but my main concern is that the header should have the header is defined.
> >>>> Since some of the fields are optional this will look something like this:
> >>>> gre_hdr_option_checksum {
> >>>> rte_be_16_t checksum;
> >>>> }
> >>>>
> >>>> gre_hdr_option_key {
> >>>> rte_be_32_t key;
> >>>> }
> >>>>
> >>>> gre_hdr_option_ sequence {
> >>>> rte_be_32_t sequence;
> >>>> }
> >>>>
> >>>> I don't want to have so many rte_flow_items, Has more and more protocols
> >>>> have optional data it doesn't make sense to create the item for each.
> >>>>
> >>>> If I'm looking at it from an ideal place, I would like that the optional fields will
> >>>> be part of the original item.
> >>>> For example in test pmd I would like to write:
> >>>> Eth / ipv4 / udp / gre flags is key & checksum checksum is yyy key is xxx / end
> >>>> And not Eth / ipv4 / udp / gre flags is key & checksum / gre_option checksum
> >>>> is yyy key is xxx / end This means that the structure will look like this:
> >>>> struct rte_flow_item_gre {
> >>>> 	union {
> >>>> 		struct {
> >>>> 			/**
> >>>> 		 	* Checksum (1b), reserved 0 (12b), version (3b).
> >>>> 			 * Refer to RFC 2784.
> >>>> 			 */
> >>>> 			rte_be16_t c_rsvd0_ver;
> >>>> 			rte_be16_t protocol; /**< Protocol type. */
> >>>> 		}
> >>>> 		struct rte_gre_hdr hdr
> >>>> 	}
> >>>> 	rte_be_16_t checksum;
> >>>> 	rte_be_32_t key;
> >>>> 	rte_be_32_t sequence;
> >>>> };
> >>>> The main issue with this is that it breaks ABI, Maybe to solve this we can
> >>>> create a new structure gre_ext?
> >>>>
> >>>> In any way I think we should think how we allow adding members to
> >>>> structures without ABI breakage.
> >>>>
> >>>> Best,
> >>>> Ori
> >>>
> >>> Thanks for the comments and suggestion.
> >>> So the acceptable solution is to have new structs define in rte_gre.h?
> >>> struct gre_hdr_opt_checksum {
> >>> 	rte_be_16_t checksum;
> >>> }
> >>>
> >>> struct gre_hdr_opt_key {
> >>> 	rte_be_32_t key;
> >>> }
> >>>
> >>> struct gre_hdr_opt_ sequence {
> >>> 	rte_be_32_t sequence;
> >>> }
> >>>
> >>> And to add new struct gre_ext defined in rte_flow.h:
> >>> struct gre_ext {
> >>> 	struct rte_gre_hdr hdr;
> >>> 	struct gre_hdr_opt_checkum checksum;
> >>> 	struct rte_hdr_opt_key key;
> >>> 	struct rte_hdr_opt_seq seq;
> >>> };
> >>>
> >>> And we use struct gre_ext for this new added flow item gre_option.
> >>>
> >>
> >> What about having a struct for 'options' and use in in flow item for options,
> >> like:
> >>
> >> struct gre_hdr_opt {
> >>     struct gre_hdr_opt_checkum checksum;
> >>     struct rte_hdr_opt_key key;
> >>     struct rte_hdr_opt_seq seq;
> >> }
> >>
> >> struct gre_hdr_ext {
> >>     struct rte_gre_hdr hdr;
> >>     struct gre_hdr_opt;
> >> }
> >>
> >> struct rte_flow_item_gre_opt {
> >>     struct gre_hdr_opt hdr;
> >> }
> >
> > Fom my understanding the header should reflect structures
> > as they appear in the spec.
> >
> > If we look at the spec, from my understanding each of those items is stand-alone.
> > It is possible to have just key or key and seq or any other combination.
> > So the struct you suggested is not valid struct in gre header.
> >
> 
> If it is not valid header representation, please forget about it.
> 
> But this means initially suggested 'struct gre_ext' is wrong, right?
> 
> So should 'rte_flow_item_gre_opt' use separate structs, like:
> 
> struct rte_flow_item_gre_opt {
>    struct gre_hdr_opt_checkum checksum;
>    struct rte_hdr_opt_key key;
>    struct rte_hdr_opt_seq seq;
> }
> 
Yes this is the last suggestion from Sean, the only difference is that
he created a new item gre_ext that holds the struct that you listed above
and added the gre header. This means that from rte_flow thre is only one GRE item
(the old one can be deprecated) 

Ori
> 
> > If you are O.K with adding such a struct to the gre file I will also be O.K with it.
> >
> > Best,
> > Ori
> >>
> >>> Correct me if my understanding is not right.
> >>>
> >>> Thanks,
> >>> Sean
> >>>
> >>>
> >

[v1 0/4] Add support for GRE optional fields matching

[Sean Zhang]

This patch set adds support for matching optional fields of GRE header.
The optional fields are checksum, key and sequence number. Currently, key
field is supported with pattern gre_key item '.. / gre / gre_key value is
xx / ..' with field gre_key in misc, but misc does not support matching of
checksum and sequence number of GRE.
To support matching of checksum and sequence number fields in GRE,
rdma-core needs the capbility of misc5 and support tunnel_header 0-3. Since
tunnel_header1 is used to match checksum, tunnel_header2 for key and
tunnel_header3 for sequence by hardware. If checksum and sequence number
not present in the pattern, use misc as before for the matching.
Application can still use gre_key item 'gre_key value is xx' for key
matching, the effect is the same if use 'gre_option key is xx'.
If using gre_option item, the flags in gre item should be correspondingly
set. For example, if using gre_option to match checksum, the c_bit should
be set '1' (.. / gre c_bit is 1 / gre_option checksum is xx / ..).

Sean Zhang (4):
  lib: add optional fields in GRE header
  ethdev: support GRE optional fields
  app/testpmd: add gre_option item command
  net/mlx5: support matching optional fields of GRE

 app/test-pmd/cmdline_flow.c                 |  59 +++++++++++
 doc/guides/prog_guide/rte_flow.rst          |  17 ++++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |   6 ++
 drivers/common/mlx5/mlx5_devx_cmds.c        |   3 +
 drivers/net/mlx5/linux/mlx5_os.c            |   2 +
 drivers/net/mlx5/mlx5.h                     |   1 +
 drivers/net/mlx5/mlx5_flow.c                | 106 ++++++++++++++++++++
 drivers/net/mlx5/mlx5_flow.h                |   6 ++
 drivers/net/mlx5/mlx5_flow_dv.c             | 146 ++++++++++++++++++++++++++++
 lib/ethdev/rte_flow.c                       |   1 +
 lib/ethdev/rte_flow.h                       |  19 ++++
 lib/net/rte_gre.h                           |  21 ++++
 12 files changed, 387 insertions(+)

-- 
1.8.3.1

[v1 1/4] lib: add optional fields in GRE header

[Sean Zhang]

There are optional fields in GRE header(checksum/key/sequence), this
patch adds definition of structures of the optional fields.

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
---
 lib/net/rte_gre.h | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/lib/net/rte_gre.h b/lib/net/rte_gre.h
index 5897756..5113e79 100644
--- a/lib/net/rte_gre.h
+++ b/lib/net/rte_gre.h
@@ -48,6 +48,27 @@ struct rte_gre_hdr {
 	uint16_t proto;  /**< Protocol Type */
 } __rte_packed;
 
+/**
+ * Optional field checksum in GRE header
+ */
+struct rte_gre_hdr_opt_checksum {
+	rte_be16_t checksum;
+} __rte_packed;
+
+/**
+ * Optional field key in GRE header
+ */
+struct rte_gre_hdr_opt_key {
+	rte_be32_t key;
+} __rte_packed;
+
+/**
+ * Optional field sequence in GRE header
+ */
+struct rte_gre_hdr_opt_sequence {
+	rte_be32_t sequence;
+} __rte_packed;
+
 #ifdef __cplusplus
 }
 #endif
-- 
1.8.3.1

RE: [v1 1/4] lib: add optional fields in GRE header

[Ori Kam]

Hi Sean,

> -----Original Message-----
> From: Sean Zhang <xiazhang@nvidia.com>
> Subject: [v1 1/4] lib: add optional fields in GRE header
> 
> There are optional fields in GRE header(checksum/key/sequence), this
> patch adds definition of structures of the optional fields.
> 
> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> ---
>  lib/net/rte_gre.h | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/lib/net/rte_gre.h b/lib/net/rte_gre.h
> index 5897756..5113e79 100644
> --- a/lib/net/rte_gre.h
> +++ b/lib/net/rte_gre.h
> @@ -48,6 +48,27 @@ struct rte_gre_hdr {
>  	uint16_t proto;  /**< Protocol Type */
>  } __rte_packed;
> 
> +/**
> + * Optional field checksum in GRE header
> + */
> +struct rte_gre_hdr_opt_checksum {
> +	rte_be16_t checksum;
> +} __rte_packed;
> +
> +/**
> + * Optional field key in GRE header
> + */
> +struct rte_gre_hdr_opt_key {
> +	rte_be32_t key;
> +} __rte_packed;
> +
> +/**
> + * Optional field sequence in GRE header
> + */
> +struct rte_gre_hdr_opt_sequence {
> +	rte_be32_t sequence;
> +} __rte_packed;
> +
>  #ifdef __cplusplus
>  }
>  #endif
> --
> 1.8.3.1

Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori

[v1 2/4] ethdev: support GRE optional fields

[Sean Zhang]

Add flow pattern items and header format for matching optional fields
(checksum/key/sequence) in GRE header. And the flags in gre item should
be correspondingly set with the new added items.

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
---
 doc/guides/prog_guide/rte_flow.rst | 17 +++++++++++++++++
 lib/ethdev/rte_flow.c              |  1 +
 lib/ethdev/rte_flow.h              | 19 +++++++++++++++++++
 3 files changed, 37 insertions(+)

diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
index b4aa9c4..0e47501 100644
--- a/doc/guides/prog_guide/rte_flow.rst
+++ b/doc/guides/prog_guide/rte_flow.rst
@@ -1106,6 +1106,7 @@ Matches a GRE header.
 
 Item: ``GRE_KEY``
 ^^^^^^^^^^^^^^^^^
+This action is deprecated. Consider `Item: GRE_OPTION`.
 
 Matches a GRE key field.
 This should be preceded by item ``GRE``.
@@ -1113,6 +1114,22 @@ This should be preceded by item ``GRE``.
 - Value to be matched is a big-endian 32 bit integer.
 - When this item present it implicitly match K bit in default mask as "1"
 
+Item: ``GRE_OPTION``
+^^^^^^^^^^^^^^^^^^^^
+
+Matches a GRE optional fields (checksum/key/sequence).
+This should be preceded by item ``GRE``.
+
+- ``checksum``: checksum.
+- ``key``: key.
+- ``sequence``: sequence.
+- The items in GRE_OPTION do not change bit flags(c_bit/k_bit/s_bit) in GRE
+  item. The bit flags need be set with GRE item by application. When the items
+  present, the corresponding bits in GRE spec and mask should be set "1" by
+  application, it means to match specified value of the fields. When the items
+  no present, but the corresponding bits in GRE spec and mask is "1", it means
+  to match any value of the fields.
+
 Item: ``FUZZY``
 ^^^^^^^^^^^^^^^
 
diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c
index a93f68a..7f93900 100644
--- a/lib/ethdev/rte_flow.c
+++ b/lib/ethdev/rte_flow.c
@@ -139,6 +139,7 @@ struct rte_flow_desc_data {
 	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
 	MK_FLOW_ITEM(TAG, sizeof(struct rte_flow_item_tag)),
 	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
+	MK_FLOW_ITEM(GRE_OPTION, sizeof(struct rte_flow_item_gre_opt)),
 	MK_FLOW_ITEM(GTP_PSC, sizeof(struct rte_flow_item_gtp_psc)),
 	MK_FLOW_ITEM(PPPOES, sizeof(struct rte_flow_item_pppoe)),
 	MK_FLOW_ITEM(PPPOED, sizeof(struct rte_flow_item_pppoe)),
diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h
index 1031fb2..db58b47 100644
--- a/lib/ethdev/rte_flow.h
+++ b/lib/ethdev/rte_flow.h
@@ -37,6 +37,7 @@
 #include <rte_gtp.h>
 #include <rte_l2tpv2.h>
 #include <rte_ppp.h>
+#include <rte_gre.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -660,6 +661,13 @@ enum rte_flow_item_type {
 	 * See struct rte_flow_item_ppp.
 	 */
 	RTE_FLOW_ITEM_TYPE_PPP,
+
+	/**
+	 * Matches GRE optional fields.
+	 *
+	 * See struct rte_flow_item_gre_opt.
+	 */
+	RTE_FLOW_ITEM_TYPE_GRE_OPTION,
 };
 
 /**
@@ -1196,6 +1204,17 @@ struct rte_flow_item_gre {
 #endif
 
 /**
+ * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
+ *
+ * Matches GRE optional fields in header.
+ */
+struct rte_flow_item_gre_opt {
+	struct rte_gre_hdr_opt_checksum checksum;
+	struct rte_gre_hdr_opt_key key;
+	struct rte_gre_hdr_opt_sequence sequence;
+};
+
+/**
  * RTE_FLOW_ITEM_TYPE_FUZZY
  *
  * Fuzzy pattern match, expect faster than default.
-- 
1.8.3.1

RE: [v1 2/4] ethdev: support GRE optional fields

[Ori Kam]

Hi Sean,

Please add this feature to the release note.

> -----Original Message-----
> From: Sean Zhang (Networking SW) <xiazhang@nvidia.com>
> Sent: Wednesday, January 26, 2022 10:44 AM
> Subject: [v1 2/4] ethdev: support GRE optional fields
> 
> Add flow pattern items and header format for matching optional fields
> (checksum/key/sequence) in GRE header. And the flags in gre item should
> be correspondingly set with the new added items.
> 
> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> ---
>  doc/guides/prog_guide/rte_flow.rst | 17 +++++++++++++++++
>  lib/ethdev/rte_flow.c              |  1 +
>  lib/ethdev/rte_flow.h              | 19 +++++++++++++++++++
>  3 files changed, 37 insertions(+)
> 
> diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
> index b4aa9c4..0e47501 100644
> --- a/doc/guides/prog_guide/rte_flow.rst
> +++ b/doc/guides/prog_guide/rte_flow.rst
> @@ -1106,6 +1106,7 @@ Matches a GRE header.
> 
>  Item: ``GRE_KEY``
>  ^^^^^^^^^^^^^^^^^
> +This action is deprecated. Consider `Item: GRE_OPTION`.
> 
>  Matches a GRE key field.
>  This should be preceded by item ``GRE``.
> @@ -1113,6 +1114,22 @@ This should be preceded by item ``GRE``.
>  - Value to be matched is a big-endian 32 bit integer.
>  - When this item present it implicitly match K bit in default mask as "1"
> 
> +Item: ``GRE_OPTION``
> +^^^^^^^^^^^^^^^^^^^^
> +
> +Matches a GRE optional fields (checksum/key/sequence).
> +This should be preceded by item ``GRE``.
> +
> +- ``checksum``: checksum.
> +- ``key``: key.
> +- ``sequence``: sequence.
> +- The items in GRE_OPTION do not change bit flags(c_bit/k_bit/s_bit) in GRE
> +  item. The bit flags need be set with GRE item by application. When the items
> +  present, the corresponding bits in GRE spec and mask should be set "1" by
> +  application, it means to match specified value of the fields. When the items
> +  no present, but the corresponding bits in GRE spec and mask is "1", it means
> +  to match any value of the fields.
> +
>  Item: ``FUZZY``
>  ^^^^^^^^^^^^^^^
> 
> diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c
> index a93f68a..7f93900 100644
> --- a/lib/ethdev/rte_flow.c
> +++ b/lib/ethdev/rte_flow.c
> @@ -139,6 +139,7 @@ struct rte_flow_desc_data {
>  	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
>  	MK_FLOW_ITEM(TAG, sizeof(struct rte_flow_item_tag)),
>  	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
> +	MK_FLOW_ITEM(GRE_OPTION, sizeof(struct rte_flow_item_gre_opt)),
>  	MK_FLOW_ITEM(GTP_PSC, sizeof(struct rte_flow_item_gtp_psc)),
>  	MK_FLOW_ITEM(PPPOES, sizeof(struct rte_flow_item_pppoe)),
>  	MK_FLOW_ITEM(PPPOED, sizeof(struct rte_flow_item_pppoe)),
> diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h
> index 1031fb2..db58b47 100644
> --- a/lib/ethdev/rte_flow.h
> +++ b/lib/ethdev/rte_flow.h
> @@ -37,6 +37,7 @@
>  #include <rte_gtp.h>
>  #include <rte_l2tpv2.h>
>  #include <rte_ppp.h>
> +#include <rte_gre.h>
> 
>  #ifdef __cplusplus
>  extern "C" {
> @@ -660,6 +661,13 @@ enum rte_flow_item_type {
>  	 * See struct rte_flow_item_ppp.
>  	 */
>  	RTE_FLOW_ITEM_TYPE_PPP,
> +
> +	/**
> +	 * Matches GRE optional fields.
> +	 *
> +	 * See struct rte_flow_item_gre_opt.
> +	 */
> +	RTE_FLOW_ITEM_TYPE_GRE_OPTION,
>  };
> 
>  /**
> @@ -1196,6 +1204,17 @@ struct rte_flow_item_gre {
>  #endif
> 
>  /**
> + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
> + *
> + * Matches GRE optional fields in header.
> + */
> +struct rte_flow_item_gre_opt {
> +	struct rte_gre_hdr_opt_checksum checksum;
> +	struct rte_gre_hdr_opt_key key;
> +	struct rte_gre_hdr_opt_sequence sequence;
> +};
> +
> +/**
>   * RTE_FLOW_ITEM_TYPE_FUZZY
>   *
>   * Fuzzy pattern match, expect faster than default.
> --
> 1.8.3.1

Best,
Ori

Re: [v1 2/4] ethdev: support GRE optional fields

[Ferruh Yigit]

On 2/1/2022 12:57 PM, Ori Kam wrote:
> Hi Sean,
> 
> Please add this feature to the release note.
> 

Hi Sean,

Reminder of this change request, waiting for new version.

Also please remember to add the missing doc in mlx patch (4/4) in next version.

Thanks,
ferruh


>> -----Original Message-----
>> From: Sean Zhang (Networking SW) <xiazhang@nvidia.com>
>> Sent: Wednesday, January 26, 2022 10:44 AM
>> Subject: [v1 2/4] ethdev: support GRE optional fields
>>
>> Add flow pattern items and header format for matching optional fields
>> (checksum/key/sequence) in GRE header. And the flags in gre item should
>> be correspondingly set with the new added items.
>>
>> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
>> ---
>>   doc/guides/prog_guide/rte_flow.rst | 17 +++++++++++++++++
>>   lib/ethdev/rte_flow.c              |  1 +
>>   lib/ethdev/rte_flow.h              | 19 +++++++++++++++++++
>>   3 files changed, 37 insertions(+)
>>
>> diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
>> index b4aa9c4..0e47501 100644
>> --- a/doc/guides/prog_guide/rte_flow.rst
>> +++ b/doc/guides/prog_guide/rte_flow.rst
>> @@ -1106,6 +1106,7 @@ Matches a GRE header.
>>
>>   Item: ``GRE_KEY``
>>   ^^^^^^^^^^^^^^^^^
>> +This action is deprecated. Consider `Item: GRE_OPTION`.
>>
>>   Matches a GRE key field.
>>   This should be preceded by item ``GRE``.
>> @@ -1113,6 +1114,22 @@ This should be preceded by item ``GRE``.
>>   - Value to be matched is a big-endian 32 bit integer.
>>   - When this item present it implicitly match K bit in default mask as "1"
>>
>> +Item: ``GRE_OPTION``
>> +^^^^^^^^^^^^^^^^^^^^
>> +
>> +Matches a GRE optional fields (checksum/key/sequence).
>> +This should be preceded by item ``GRE``.
>> +
>> +- ``checksum``: checksum.
>> +- ``key``: key.
>> +- ``sequence``: sequence.
>> +- The items in GRE_OPTION do not change bit flags(c_bit/k_bit/s_bit) in GRE
>> +  item. The bit flags need be set with GRE item by application. When the items
>> +  present, the corresponding bits in GRE spec and mask should be set "1" by
>> +  application, it means to match specified value of the fields. When the items
>> +  no present, but the corresponding bits in GRE spec and mask is "1", it means
>> +  to match any value of the fields.
>> +
>>   Item: ``FUZZY``
>>   ^^^^^^^^^^^^^^^
>>
>> diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c
>> index a93f68a..7f93900 100644
>> --- a/lib/ethdev/rte_flow.c
>> +++ b/lib/ethdev/rte_flow.c
>> @@ -139,6 +139,7 @@ struct rte_flow_desc_data {
>>   	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
>>   	MK_FLOW_ITEM(TAG, sizeof(struct rte_flow_item_tag)),
>>   	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
>> +	MK_FLOW_ITEM(GRE_OPTION, sizeof(struct rte_flow_item_gre_opt)),
>>   	MK_FLOW_ITEM(GTP_PSC, sizeof(struct rte_flow_item_gtp_psc)),
>>   	MK_FLOW_ITEM(PPPOES, sizeof(struct rte_flow_item_pppoe)),
>>   	MK_FLOW_ITEM(PPPOED, sizeof(struct rte_flow_item_pppoe)),
>> diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h
>> index 1031fb2..db58b47 100644
>> --- a/lib/ethdev/rte_flow.h
>> +++ b/lib/ethdev/rte_flow.h
>> @@ -37,6 +37,7 @@
>>   #include <rte_gtp.h>
>>   #include <rte_l2tpv2.h>
>>   #include <rte_ppp.h>
>> +#include <rte_gre.h>
>>
>>   #ifdef __cplusplus
>>   extern "C" {
>> @@ -660,6 +661,13 @@ enum rte_flow_item_type {
>>   	 * See struct rte_flow_item_ppp.
>>   	 */
>>   	RTE_FLOW_ITEM_TYPE_PPP,
>> +
>> +	/**
>> +	 * Matches GRE optional fields.
>> +	 *
>> +	 * See struct rte_flow_item_gre_opt.
>> +	 */
>> +	RTE_FLOW_ITEM_TYPE_GRE_OPTION,
>>   };
>>
>>   /**
>> @@ -1196,6 +1204,17 @@ struct rte_flow_item_gre {
>>   #endif
>>
>>   /**
>> + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
>> + *
>> + * Matches GRE optional fields in header.
>> + */
>> +struct rte_flow_item_gre_opt {
>> +	struct rte_gre_hdr_opt_checksum checksum;
>> +	struct rte_gre_hdr_opt_key key;
>> +	struct rte_gre_hdr_opt_sequence sequence;
>> +};
>> +
>> +/**
>>    * RTE_FLOW_ITEM_TYPE_FUZZY
>>    *
>>    * Fuzzy pattern match, expect faster than default.
>> --
>> 1.8.3.1
> 
> Best,
> Ori
> 

[v1 3/4] app/testpmd: add gre_option item command

[Sean Zhang]

Add gre_option command for matching optional fields(checksum/key/sequence)
in GRE header. The item must follow gre item, and the item does not
change the flags in gre item, the application should set the flags in
gre item correspondingly.
Application can still use gre_key item 'gre_key value is xx' for key
matching, the effect is the same with using 'gre_option key is xx'.

The examples for gre_option are as follows:

To match on checksum field with value 0x11:
testpmd> ... pattern / eth / gre c_bit is 1 / gre_option checksum is
		0x11 / end ..

To match on checksum field with value 0x11 and any value of key:
testpmd> ... pattern / eth / gre c_bit is 1 k_bit is 1 / gre_option
		checksum is 0x11 / end ..

To match on checksum field with value 0x11 and no key field in packet:
testpmd> ... pattern / eth / gre c_bit is 1 k_bit is 0 / gre_option
		checksum is 0x11 / end ..

The invalid patterns for gre_option are as follows:

testpmd> ... pattern / eth / gre / gre_option checksum is 0x11 / end ..
		(c_bit in gre item not present)
testpmd> ... pattern / eth / gre c_bit is 0 / gre_option checksum is 0x11 /
		end .. (c_bit is unset for gre item, but checksum is
		specified by gre_option item)

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
---
 app/test-pmd/cmdline_flow.c                 | 59 +++++++++++++++++++++++++++++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  6 +++
 2 files changed, 65 insertions(+)

diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
index 5c2bba4..b7aacac 100644
--- a/app/test-pmd/cmdline_flow.c
+++ b/app/test-pmd/cmdline_flow.c
@@ -271,6 +271,10 @@ enum index {
 	ITEM_META_DATA,
 	ITEM_GRE_KEY,
 	ITEM_GRE_KEY_VALUE,
+	ITEM_GRE_OPTION,
+	ITEM_GRE_OPTION_CHECKSUM,
+	ITEM_GRE_OPTION_KEY,
+	ITEM_GRE_OPTION_SEQUENCE,
 	ITEM_GTP_PSC,
 	ITEM_GTP_PSC_QFI,
 	ITEM_GTP_PSC_PDU_T,
@@ -1042,6 +1046,7 @@ struct parse_action_priv {
 	ITEM_ICMP6_ND_OPT_TLA_ETH,
 	ITEM_META,
 	ITEM_GRE_KEY,
+	ITEM_GRE_OPTION,
 	ITEM_GTP_PSC,
 	ITEM_PPPOES,
 	ITEM_PPPOED,
@@ -1232,6 +1237,14 @@ struct parse_action_priv {
 	ZERO,
 };
 
+static const enum index item_gre_option[] = {
+	ITEM_GRE_OPTION_CHECKSUM,
+	ITEM_GRE_OPTION_KEY,
+	ITEM_GRE_OPTION_SEQUENCE,
+	ITEM_NEXT,
+	ZERO,
+};
+
 static const enum index item_gtp[] = {
 	ITEM_GTP_FLAGS,
 	ITEM_GTP_MSG_TYPE,
@@ -3479,6 +3492,38 @@ static int comp_set_modify_field_id(struct context *, const struct token *,
 			     item_param),
 		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
 	},
+	[ITEM_GRE_OPTION] = {
+		.name = "gre_option",
+		.help = "match GRE optional fields",
+		.priv = PRIV_ITEM(GRE_OPTION,
+				  sizeof(struct rte_flow_item_gre_opt)),
+		.next = NEXT(item_gre_option),
+		.call = parse_vc,
+	},
+	[ITEM_GRE_OPTION_CHECKSUM] = {
+		.name = "checksum",
+		.help = "match GRE checksum",
+		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
+			     item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt,
+					     checksum)),
+	},
+	[ITEM_GRE_OPTION_KEY] = {
+		.name = "key",
+		.help = "match GRE key",
+		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
+			     item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt,
+					     key)),
+	},
+	[ITEM_GRE_OPTION_SEQUENCE] = {
+		.name = "sequence",
+		.help = "match GRE sequence",
+		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
+			     item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt,
+					     sequence)),
+	},
 	[ITEM_GTP_PSC] = {
 		.name = "gtp_psc",
 		.help = "match GTP extension header with type 0x85",
@@ -9235,6 +9280,20 @@ static int comp_set_modify_field_id(struct context *, const struct token *,
 				((const struct rte_flow_item_flex *)
 				item->spec)->length : 0;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
+			size = 0;
+			if (item->spec) {
+				const struct rte_flow_item_gre_opt
+					*opt = item->spec;
+				if (opt->checksum.checksum)
+					size += 4;
+				if (opt->key.key)
+					size += 4;
+				if (opt->sequence.sequence)
+					size += 4;
+			}
+			proto = 0x2F;
+			break;
 		default:
 			fprintf(stderr, "Error - Not supported item\n");
 			goto error;
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index 94792d8..751503e 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -3714,6 +3714,12 @@ This section lists supported pattern items and their attributes, if any.
 
   - ``value {unsigned}``: key value.
 
+- ``gre_option``: match GRE optional fields(checksum/key/sequence).
+
+  - ``checksum {unsigned}``: checksum value.
+  - ``key {unsigned}``: key value.
+  - ``sequence {unsigned}``: sequence number value.
+
 - ``fuzzy``: fuzzy pattern match, expect faster than default.
 
   - ``thresh {unsigned}``: accuracy threshold.
-- 
1.8.3.1

RE: [v1 3/4] app/testpmd: add gre_option item command

[Ori Kam]

Hi Sean,


> -----Original Message-----
> From: Sean Zhang (Networking SW) <xiazhang@nvidia.com>
> Sent: Wednesday, January 26, 2022 10:44 AM
> Subject: [v1 3/4] app/testpmd: add gre_option item command
> 
> Add gre_option command for matching optional fields(checksum/key/sequence)
> in GRE header. The item must follow gre item, and the item does not
> change the flags in gre item, the application should set the flags in
> gre item correspondingly.
> Application can still use gre_key item 'gre_key value is xx' for key
> matching, the effect is the same with using 'gre_option key is xx'.
> 
> The examples for gre_option are as follows:
> 
> To match on checksum field with value 0x11:
> testpmd> ... pattern / eth / gre c_bit is 1 / gre_option checksum is
> 		0x11 / end ..
> 
> To match on checksum field with value 0x11 and any value of key:
> testpmd> ... pattern / eth / gre c_bit is 1 k_bit is 1 / gre_option
> 		checksum is 0x11 / end ..
> 
> To match on checksum field with value 0x11 and no key field in packet:
> testpmd> ... pattern / eth / gre c_bit is 1 k_bit is 0 / gre_option
> 		checksum is 0x11 / end ..
> 
> The invalid patterns for gre_option are as follows:
> 
> testpmd> ... pattern / eth / gre / gre_option checksum is 0x11 / end ..
> 		(c_bit in gre item not present)
> testpmd> ... pattern / eth / gre c_bit is 0 / gre_option checksum is 0x11 /
> 		end .. (c_bit is unset for gre item, but checksum is
> 		specified by gre_option item)
> 
> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> ---
>  app/test-pmd/cmdline_flow.c                 | 59 +++++++++++++++++++++++++++++
>  doc/guides/testpmd_app_ug/testpmd_funcs.rst |  6 +++
>  2 files changed, 65 insertions(+)
> 
> diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
> index 5c2bba4..b7aacac 100644
> --- a/app/test-pmd/cmdline_flow.c
> +++ b/app/test-pmd/cmdline_flow.c
> @@ -271,6 +271,10 @@ enum index {
>  	ITEM_META_DATA,
>  	ITEM_GRE_KEY,
>  	ITEM_GRE_KEY_VALUE,
> +	ITEM_GRE_OPTION,
> +	ITEM_GRE_OPTION_CHECKSUM,
> +	ITEM_GRE_OPTION_KEY,
> +	ITEM_GRE_OPTION_SEQUENCE,
>  	ITEM_GTP_PSC,
>  	ITEM_GTP_PSC_QFI,
>  	ITEM_GTP_PSC_PDU_T,
> @@ -1042,6 +1046,7 @@ struct parse_action_priv {
>  	ITEM_ICMP6_ND_OPT_TLA_ETH,
>  	ITEM_META,
>  	ITEM_GRE_KEY,
> +	ITEM_GRE_OPTION,
>  	ITEM_GTP_PSC,
>  	ITEM_PPPOES,
>  	ITEM_PPPOED,
> @@ -1232,6 +1237,14 @@ struct parse_action_priv {
>  	ZERO,
>  };
> 
> +static const enum index item_gre_option[] = {
> +	ITEM_GRE_OPTION_CHECKSUM,
> +	ITEM_GRE_OPTION_KEY,
> +	ITEM_GRE_OPTION_SEQUENCE,
> +	ITEM_NEXT,
> +	ZERO,
> +};
> +
>  static const enum index item_gtp[] = {
>  	ITEM_GTP_FLAGS,
>  	ITEM_GTP_MSG_TYPE,
> @@ -3479,6 +3492,38 @@ static int comp_set_modify_field_id(struct context *, const struct token *,
>  			     item_param),
>  		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
>  	},
> +	[ITEM_GRE_OPTION] = {
> +		.name = "gre_option",
> +		.help = "match GRE optional fields",
> +		.priv = PRIV_ITEM(GRE_OPTION,
> +				  sizeof(struct rte_flow_item_gre_opt)),
> +		.next = NEXT(item_gre_option),
> +		.call = parse_vc,
> +	},
> +	[ITEM_GRE_OPTION_CHECKSUM] = {
> +		.name = "checksum",
> +		.help = "match GRE checksum",
> +		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
> +			     item_param),
> +		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt,
> +					     checksum)),
> +	},
> +	[ITEM_GRE_OPTION_KEY] = {
> +		.name = "key",
> +		.help = "match GRE key",
> +		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
> +			     item_param),
> +		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt,
> +					     key)),
> +	},
> +	[ITEM_GRE_OPTION_SEQUENCE] = {
> +		.name = "sequence",
> +		.help = "match GRE sequence",
> +		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
> +			     item_param),
> +		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt,
> +					     sequence)),
> +	},
>  	[ITEM_GTP_PSC] = {
>  		.name = "gtp_psc",
>  		.help = "match GTP extension header with type 0x85",
> @@ -9235,6 +9280,20 @@ static int comp_set_modify_field_id(struct context *, const struct token *,
>  				((const struct rte_flow_item_flex *)
>  				item->spec)->length : 0;
>  			break;
> +		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
> +			size = 0;
> +			if (item->spec) {
> +				const struct rte_flow_item_gre_opt
> +					*opt = item->spec;
> +				if (opt->checksum.checksum)
> +					size += 4;
> +				if (opt->key.key)
> +					size += 4;
> +				if (opt->sequence.sequence)
> +					size += 4;
> +			}
> +			proto = 0x2F;
> +			break;
>  		default:
>  			fprintf(stderr, "Error - Not supported item\n");
>  			goto error;
> diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> index 94792d8..751503e 100644
> --- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> +++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> @@ -3714,6 +3714,12 @@ This section lists supported pattern items and their attributes, if any.
> 
>    - ``value {unsigned}``: key value.
> 
> +- ``gre_option``: match GRE optional fields(checksum/key/sequence).
> +
> +  - ``checksum {unsigned}``: checksum value.
> +  - ``key {unsigned}``: key value.
> +  - ``sequence {unsigned}``: sequence number value.
> +
>  - ``fuzzy``: fuzzy pattern match, expect faster than default.
> 
>    - ``thresh {unsigned}``: accuracy threshold.
> --
> 1.8.3.1

Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori

[v1 4/4] net/mlx5: support matching optional fields of GRE

[Sean Zhang]

This patch adds matching on the optional fields (checksum/key/sequence)
of GRE header. The matching of checksum and sequence fields requests
support from rdma-core with capability of misc5 and tunner_header 0-3.

For patterns without checksum and sequence specified, keep using misc for
matching as before, but for patterns with checksum or sequence, validate
capability first and then use misc5 for the matching.

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
---
 drivers/common/mlx5/mlx5_devx_cmds.c |   3 +
 drivers/net/mlx5/linux/mlx5_os.c     |   2 +
 drivers/net/mlx5/mlx5.h              |   1 +
 drivers/net/mlx5/mlx5_flow.c         | 106 +++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_flow.h         |   6 ++
 drivers/net/mlx5/mlx5_flow_dv.c      | 146 +++++++++++++++++++++++++++++++++++
 6 files changed, 264 insertions(+)

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 7cd3d4f..5d21480 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1027,6 +1027,9 @@ struct mlx5_devx_obj *
 	attr->flow.tunnel_header_0_1 = MLX5_GET
 		(flow_table_nic_cap, hcattr,
 		 ft_field_support_2_nic_receive.tunnel_header_0_1);
+	attr->flow.tunnel_header_2_3 = MLX5_GET
+		(flow_table_nic_cap, hcattr,
+		 ft_field_support_2_nic_receive.tunnel_header_2_3);
 	attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
 	attr->inner_ipv4_ihl = MLX5_GET
 		(flow_table_nic_cap, hcattr,
diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index 36f0fbf..6dbbb1f 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -1385,6 +1385,8 @@
 		}
 		if (config->hca_attr.flow.tunnel_header_0_1)
 			sh->tunnel_header_0_1 = 1;
+		if (config->hca_attr.flow.tunnel_header_2_3)
+			sh->tunnel_header_2_3 = 1;
 #endif
 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 		if (config->hca_attr.flow_hit_aso &&
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index b55f581..32b1c7b 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1150,6 +1150,7 @@ struct mlx5_dev_ctx_shared {
 	uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
 	uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
 	uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */
+	uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */
 	uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
 	uint32_t reclaim_mode:1; /* Reclaim memory. */
 	uint32_t dr_drop_action_en:1; /* Use DR drop action. */
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index b7cf414..9e608ba 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -2802,6 +2802,112 @@ struct mlx5_flow_tunnel_info {
 }
 
 /**
+ * Validate GRE optional item.
+ *
+ * @param[in] dev
+ *   Pointer to the Ethernet device structure.
+ * @param[in] item
+ *   Item specification.
+ * @param[in] item_flags
+ *   Bit flags to mark detected items.
+ * @param[in] attr
+ *   Flow rule attributes.
+ * @param[in] gre_item
+ *   Pointer to gre_item
+ * @param[out] error
+ *   Pointer to error structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
+				   const struct rte_flow_item *item,
+				   uint64_t item_flags,
+				   const struct rte_flow_attr *attr,
+				   const struct rte_flow_item *gre_item,
+				   struct rte_flow_error *error)
+{
+	const struct rte_flow_item_gre *gre_spec = gre_item->spec;
+	const struct rte_flow_item_gre *gre_mask = gre_item->mask;
+	const struct rte_flow_item_gre_opt *spec = item->spec;
+	const struct rte_flow_item_gre_opt *mask = item->mask;
+	struct mlx5_priv *priv = dev->data->dev_private;
+	int ret = 0;
+
+	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "No preceding GRE header");
+	if (item_flags & MLX5_FLOW_LAYER_INNER)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "GRE option following a wrong item");
+	if (!gre_mask)
+		gre_mask = &rte_flow_item_gre_mask;
+
+	struct rte_flow_item_gre_opt gre_option_default_mask = {
+		.checksum = {
+			.checksum = 0xffff,
+		},
+		.key = {
+			.key = 0xffffffff,
+		},
+		.sequence = {
+			.sequence = 0xffffffff,
+		},
+	};
+
+	if (!mask)
+		mask = &gre_option_default_mask;
+
+	if (spec && mask->checksum.checksum)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x8000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x8000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item,
+						  "Checksum bit must be on");
+
+	if (spec && mask->key.key)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item, "Key bit must be on");
+
+	if (spec && mask->sequence.sequence)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x1000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x1000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item,
+						  "Sequence bit must be on");
+
+	if (spec && (mask->checksum.checksum || mask->sequence.sequence)) {
+		if (priv->sh->steering_format_version ==
+		    MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 ||
+		    ((attr->group || attr->transfer) &&
+		     !priv->sh->misc5_cap) ||
+		    (!(priv->sh->tunnel_header_0_1 &&
+		       priv->sh->tunnel_header_2_3) &&
+		    !attr->group && !attr->transfer))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item,
+						  "Checksum/Sequence not supported");
+	}
+
+	ret = mlx5_flow_item_acceptable
+		(item, (const uint8_t *)mask,
+		 (const uint8_t *)&gre_option_default_mask,
+		 sizeof(struct rte_flow_item_gre_opt),
+		 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
+
+	return ret;
+}
+
+/**
  * Validate GRE item.
  *
  * @param[in] item
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 8c131d6..210cc26 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -1523,6 +1523,12 @@ int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
 				    uint64_t item_flags,
 				    const struct rte_flow_item *gre_item,
 				    struct rte_flow_error *error);
+int mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
+				const struct rte_flow_item *item,
+				uint64_t item_flags,
+				const struct rte_flow_attr *attr,
+				const struct rte_flow_item *gre_item,
+				struct rte_flow_error *error);
 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
 				 uint64_t item_flags,
 				 uint64_t last_item,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 8022d7d..4536ddb 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -7112,6 +7112,13 @@ struct mlx5_list_entry *
 			gre_item = items;
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
+			ret = mlx5_flow_validate_item_gre_option(dev, items, item_flags,
+							  attr, gre_item, error);
+			if (ret < 0)
+				return ret;
+			last_item = MLX5_FLOW_LAYER_GRE;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			ret = mlx5_flow_validate_item_nvgre(items, item_flags,
 							    next_protocol,
@@ -8833,6 +8840,135 @@ struct mlx5_list_entry *
 }
 
 /**
+ * Add GRE optional items to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] gre_item
+ *   Pointer to gre_item.
+ * @param[in] pattern_flags
+ *   Accumulated pattern flags.
+ */
+static void
+flow_dv_translate_item_gre_option(void *matcher, void *key,
+				  const struct rte_flow_item *item,
+				  const struct rte_flow_item *gre_item,
+				  uint64_t pattern_flags)
+{
+	const struct rte_flow_item_gre_opt *option_m = item->mask;
+	const struct rte_flow_item_gre_opt *option_v = item->spec;
+	const struct rte_flow_item_gre *gre_m = gre_item->mask;
+	const struct rte_flow_item_gre *gre_v = gre_item->spec;
+	static const struct rte_flow_item_gre empty_gre = {0};
+	struct rte_flow_item gre_key_item;
+	uint16_t c_rsvd0_ver_m, c_rsvd0_ver_v;
+	uint16_t protocol_m, protocol_v;
+	uint32_t *tunnel_header_v[4];
+	uint32_t *tunnel_header_m[4];
+	void *misc5_m;
+	void *misc5_v;
+
+	struct rte_flow_item_gre_opt gre_option_default_mask = {
+		.checksum = {
+			.checksum = 0xffff,
+		},
+		.key = {
+			.key = 0xffffffff,
+		},
+		.sequence = {
+			.sequence = 0xffffffff,
+		},
+	};
+
+	if (!option_v)
+		return;
+	if (!option_m)
+		option_m = &gre_option_default_mask;
+
+	if (!(option_m->sequence.sequence || option_m->checksum.checksum)) {
+		flow_dv_translate_item_gre(matcher, key, gre_item,
+					   pattern_flags);
+		gre_key_item.spec = &option_v->key.key;
+		gre_key_item.mask = &option_m->key.key;
+		flow_dv_translate_item_gre_key(matcher, key, &gre_key_item);
+		return;
+	}
+
+	if (!gre_v) {
+		gre_v = &empty_gre;
+		gre_m = &empty_gre;
+	} else {
+		if (!gre_m)
+			gre_m = &rte_flow_item_gre_mask;
+	}
+
+	misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
+	misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
+	tunnel_header_v[0] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_v, tunnel_header_0);
+	tunnel_header_m[0] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_m, tunnel_header_0);
+	tunnel_header_v[1] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_v, tunnel_header_1);
+	tunnel_header_m[1] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_m, tunnel_header_1);
+	tunnel_header_v[2] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_v, tunnel_header_2);
+	tunnel_header_m[2] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_m, tunnel_header_2);
+	tunnel_header_v[3] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_v, tunnel_header_3);
+	tunnel_header_m[3] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_m, tunnel_header_3);
+
+	protocol_v = gre_v->protocol;
+	protocol_m = gre_m->protocol;
+	if (!protocol_m) {
+		/* Force next protocol to prevent matchers duplication */
+		uint16_t ether_type =
+			mlx5_translate_tunnel_etypes(pattern_flags);
+		if (ether_type) {
+			protocol_v = rte_be_to_cpu_16(ether_type);
+			protocol_m = 0xFFFF;
+		}
+	}
+	c_rsvd0_ver_v = gre_v->c_rsvd0_ver;
+	c_rsvd0_ver_m = gre_m->c_rsvd0_ver;
+
+
+	if (option_m->sequence.sequence) {
+		c_rsvd0_ver_v |= RTE_BE16(0x1000);
+		c_rsvd0_ver_m |= RTE_BE16(0x1000);
+	}
+
+	if (option_m->key.key) {
+		c_rsvd0_ver_v |= RTE_BE16(0x2000);
+		c_rsvd0_ver_m |= RTE_BE16(0x2000);
+	}
+
+	if (option_m->checksum.checksum) {
+		c_rsvd0_ver_v |= RTE_BE16(0x8000);
+		c_rsvd0_ver_m |= RTE_BE16(0x8000);
+	}
+
+	*tunnel_header_v[0] = (c_rsvd0_ver_v | protocol_v << 16) &
+			(c_rsvd0_ver_m | protocol_m << 16);
+	*tunnel_header_m[0] = c_rsvd0_ver_m | protocol_m << 16;
+	*tunnel_header_v[1] = option_v->checksum.checksum &
+		option_m->checksum.checksum;
+	*tunnel_header_m[1] = option_m->checksum.checksum;
+	*tunnel_header_v[2] = option_v->key.key & option_m->key.key;
+	*tunnel_header_m[2] = option_m->key.key;
+	*tunnel_header_v[3] = option_v->sequence.sequence &
+		option_m->sequence.sequence;
+	*tunnel_header_m[3] = option_m->sequence.sequence;
+}
+
+/**
  * Add NVGRE item to matcher and to the value.
  *
  * @param[in, out] matcher
@@ -12708,6 +12844,7 @@ struct mlx5_list_entry *
 	};
 	const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
 	const struct rte_flow_item *tunnel_item = NULL;
+	const struct rte_flow_item *gre_item = NULL;
 
 	if (!wks)
 		return rte_flow_error_set(error, ENOMEM,
@@ -13480,12 +13617,18 @@ struct mlx5_list_entry *
 			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
 			last_item = MLX5_FLOW_LAYER_GRE;
 			tunnel_item = items;
+			gre_item = items;
 			break;
 		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
 			flow_dv_translate_item_gre_key(match_mask,
 						       match_value, items);
 			last_item = MLX5_FLOW_LAYER_GRE_KEY;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
+			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
+			last_item = MLX5_FLOW_LAYER_GRE;
+			tunnel_item = items;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
 			last_item = MLX5_FLOW_LAYER_GRE;
@@ -13645,6 +13788,9 @@ struct mlx5_list_entry *
 		else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
 			flow_dv_translate_item_nvgre(match_mask, match_value,
 						     tunnel_item, item_flags);
+		else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION)
+			flow_dv_translate_item_gre_option(match_mask, match_value,
+					tunnel_item, gre_item, item_flags);
 		else
 			MLX5_ASSERT(false);
 	}
-- 
1.8.3.1

Re: [v1 4/4] net/mlx5: support matching optional fields of GRE

[Ferruh Yigit]

On 1/26/2022 8:44 AM, Sean Zhang wrote:
> This patch adds matching on the optional fields (checksum/key/sequence)
> of GRE header. The matching of checksum and sequence fields requests
> support from rdma-core with capability of misc5 and tunner_header 0-3.
> 
> For patterns without checksum and sequence specified, keep using misc for
> matching as before, but for patterns with checksum or sequence, validate
> capability first and then use misc5 for the matching.
> 
> Signed-off-by: Sean Zhang<xiazhang@nvidia.com>
> ---
>   drivers/common/mlx5/mlx5_devx_cmds.c |   3 +
>   drivers/net/mlx5/linux/mlx5_os.c     |   2 +
>   drivers/net/mlx5/mlx5.h              |   1 +
>   drivers/net/mlx5/mlx5_flow.c         | 106 +++++++++++++++++++++++++
>   drivers/net/mlx5/mlx5_flow.h         |   6 ++
>   drivers/net/mlx5/mlx5_flow_dv.c      | 146 +++++++++++++++++++++++++++++++++++
>   6 files changed, 264 insertions(+)

Documentation seems missing:

$ ./devtools/check-doc-vs-code.sh
rte_flow doc out of sync for mlx5
         item gre_option

Re: [v1 0/4] Add support for GRE optional fields matching

[Ferruh Yigit]

On 1/26/2022 8:44 AM, Sean Zhang wrote:
> This patch set adds support for matching optional fields of GRE header.
> The optional fields are checksum, key and sequence number. Currently, key
> field is supported with pattern gre_key item '.. / gre / gre_key value is
> xx / ..' with field gre_key in misc, but misc does not support matching of
> checksum and sequence number of GRE.
> To support matching of checksum and sequence number fields in GRE,
> rdma-core needs the capbility of misc5 and support tunnel_header 0-3. Since
> tunnel_header1 is used to match checksum, tunnel_header2 for key and
> tunnel_header3 for sequence by hardware. If checksum and sequence number
> not present in the pattern, use misc as before for the matching.
> Application can still use gre_key item 'gre_key value is xx' for key
> matching, the effect is the same if use 'gre_option key is xx'.
> If using gre_option item, the flags in gre item should be correspondingly
> set. For example, if using gre_option to match checksum, the c_bit should
> be set '1' (.. / gre c_bit is 1 / gre_option checksum is xx / ..).
> 
> Sean Zhang (4):
>    lib: add optional fields in GRE header
>    ethdev: support GRE optional fields
>    app/testpmd: add gre_option item command
>    net/mlx5: support matching optional fields of GRE
> 

Look good to me (except that missing doc in mlx5 patch), but waiting for
Ori's review to proceed.

[v2 0/4] Add support for GRE optional fields matching

[Sean Zhang]

This patch set adds support for matching optional fields of GRE header.
The optional fields are checksum, key and sequence number. Currently, key
field is supported with pattern gre_key item '.. / gre / gre_key value is
xx / ..' with field gre_key in misc, but misc does not support matching of
checksum and sequence number of GRE.
To support matching of checksum and sequence number fields in GRE,
rdma-core needs the capbility of misc5 and support tunnel_header 0-3. Since
tunnel_header1 is used to match checksum, tunnel_header2 for key and
tunnel_header3 for sequence by hardware. If checksum and sequence number
not present in the pattern, use misc as before for the matching.
Application can still use gre_key item 'gre_key value is xx' for key
matching, the effect is the same if use 'gre_option key is xx'.
If using gre_option item, the flags in gre item should be correspondingly
set. For example, if using gre_option to match checksum, the c_bit should
be set '1' (.. / gre c_bit is 1 / gre_option checksum is xx / ..).

change in v2:
-changed the struct defined in rte_flow for gre_option item.
-fixed raw encap issue.

Sean Zhang (4):
  lib: add optional fields in GRE header
  ethdev: support GRE optional fields
  app/testpmd: add gre_option item command
  net/mlx5: support matching optional fields of GRE

 app/test-pmd/cmdline_flow.c                 |  72 +++++++++++++++
 doc/guides/nics/mlx5.rst                    |   8 ++
 doc/guides/prog_guide/rte_flow.rst          |  17 ++++
 doc/guides/rel_notes/release_22_03.rst      |   5 ++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |   6 ++
 drivers/common/mlx5/mlx5_devx_cmds.c        |   3 +
 drivers/net/mlx5/linux/mlx5_os.c            |   2 +
 drivers/net/mlx5/mlx5.h                     |   1 +
 drivers/net/mlx5/mlx5_flow.c                | 108 +++++++++++++++++++++++
 drivers/net/mlx5/mlx5_flow.h                |   6 ++
 drivers/net/mlx5/mlx5_flow_dv.c             | 130 ++++++++++++++++++++++++++++
 lib/ethdev/rte_flow.c                       |   1 +
 lib/ethdev/rte_flow.h                       |  19 ++++
 lib/net/rte_gre.h                           |  22 +++++
 14 files changed, 400 insertions(+)

-- 
1.8.3.1

[v2 1/4] lib: add optional fields in GRE header

[Sean Zhang]

There are optional fields in GRE header(checksum/key/sequence), this
patch adds definition of structures of the optional fields.

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
---
 lib/net/rte_gre.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/lib/net/rte_gre.h b/lib/net/rte_gre.h
index 5897756..6c6aef6 100644
--- a/lib/net/rte_gre.h
+++ b/lib/net/rte_gre.h
@@ -48,6 +48,28 @@ struct rte_gre_hdr {
 	uint16_t proto;  /**< Protocol Type */
 } __rte_packed;
 
+/**
+ * Optional field checksum in GRE header
+ */
+struct rte_gre_hdr_opt_checksum_rsvd {
+	rte_be16_t checksum;
+	rte_be16_t reserved1;
+} __rte_packed;
+
+/**
+ * Optional field key in GRE header
+ */
+struct rte_gre_hdr_opt_key {
+	rte_be32_t key;
+} __rte_packed;
+
+/**
+ * Optional field sequence in GRE header
+ */
+struct rte_gre_hdr_opt_sequence {
+	rte_be32_t sequence;
+} __rte_packed;
+
 #ifdef __cplusplus
 }
 #endif
-- 
1.8.3.1

Re: [v2 1/4] lib: add optional fields in GRE header

[Ferruh Yigit]

On 2/11/2022 1:45 AM, Sean Zhang wrote:
> There are optional fields in GRE header(checksum/key/sequence), this
> patch adds definition of structures of the optional fields.
> 
> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> ---
>   lib/net/rte_gre.h | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 
> diff --git a/lib/net/rte_gre.h b/lib/net/rte_gre.h
> index 5897756..6c6aef6 100644
> --- a/lib/net/rte_gre.h
> +++ b/lib/net/rte_gre.h
> @@ -48,6 +48,28 @@ struct rte_gre_hdr {
>   	uint16_t proto;  /**< Protocol Type */
>   } __rte_packed;
>   
> +/**
> + * Optional field checksum in GRE header
> + */
> +struct rte_gre_hdr_opt_checksum_rsvd {
> +	rte_be16_t checksum;
> +	rte_be16_t reserved1;

Can you please explain why this reserved field is added,
I guess it i not part of the GRE spec, but added for mlx driver?

Since these struts will be public, we can't update them later easily,
so we should be careful on them.

> +} __rte_packed;
> +
> +/**
> + * Optional field key in GRE header
> + */
> +struct rte_gre_hdr_opt_key {
> +	rte_be32_t key;
> +} __rte_packed;
> +
> +/**
> + * Optional field sequence in GRE header
> + */
> +struct rte_gre_hdr_opt_sequence {
> +	rte_be32_t sequence;
> +} __rte_packed;
> +
>   #ifdef __cplusplus
>   }
>   #endif

RE: [v2 1/4] lib: add optional fields in GRE header

[Sean Zhang (Networking SW)]

Hi Ferruh,

> -----Original Message-----
> From: Ferruh Yigit <ferruh.yigit@intel.com>
> Sent: Friday, February 11, 2022 5:38 PM
> To: Sean Zhang (Networking SW) <xiazhang@nvidia.com>; NBU-Contact-
> Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>; Olivier Matz
> <olivier.matz@6wind.com>
> Cc: dev@dpdk.org; Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>;
> Ori Kam <orika@nvidia.com>
> Subject: Re: [v2 1/4] lib: add optional fields in GRE header
> 
> External email: Use caution opening links or attachments
> 
> 
> On 2/11/2022 1:45 AM, Sean Zhang wrote:
> > There are optional fields in GRE header(checksum/key/sequence), this
> > patch adds definition of structures of the optional fields.
> >
> > Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> > ---
> >   lib/net/rte_gre.h | 22 ++++++++++++++++++++++
> >   1 file changed, 22 insertions(+)
> >
> > diff --git a/lib/net/rte_gre.h b/lib/net/rte_gre.h index
> > 5897756..6c6aef6 100644
> > --- a/lib/net/rte_gre.h
> > +++ b/lib/net/rte_gre.h
> > @@ -48,6 +48,28 @@ struct rte_gre_hdr {
> >       uint16_t proto;  /**< Protocol Type */
> >   } __rte_packed;
> >
> > +/**
> > + * Optional field checksum in GRE header  */ struct
> > +rte_gre_hdr_opt_checksum_rsvd {
> > +     rte_be16_t checksum;
> > +     rte_be16_t reserved1;
> 
> Can you please explain why this reserved field is added, I guess it i not part of
> the GRE spec, but added for mlx driver?
> 

Yes, the reserverd1 field is part of GRE spec, and the field go together with checksum field, so I add the reserverd1 field here.

You can refer to section 2.6 of https://datatracker.ietf.org/doc/rfc2784/ 

> Since these struts will be public, we can't update them later easily, so we
> should be careful on them.
> 
> > +} __rte_packed;
> > +
> > +/**
> > + * Optional field key in GRE header
> > + */
> > +struct rte_gre_hdr_opt_key {
> > +     rte_be32_t key;
> > +} __rte_packed;
> > +
> > +/**
> > + * Optional field sequence in GRE header  */ struct
> > +rte_gre_hdr_opt_sequence {
> > +     rte_be32_t sequence;
> > +} __rte_packed;
> > +
> >   #ifdef __cplusplus
> >   }
> >   #endif

Re: [v2 1/4] lib: add optional fields in GRE header

[Ferruh Yigit]

On 2/11/2022 10:23 AM, Sean Zhang (Networking SW) wrote:
> Hi Ferruh,
> 
>> -----Original Message-----
>> From: Ferruh Yigit <ferruh.yigit@intel.com>
>> Sent: Friday, February 11, 2022 5:38 PM
>> To: Sean Zhang (Networking SW) <xiazhang@nvidia.com>; NBU-Contact-
>> Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>; Olivier Matz
>> <olivier.matz@6wind.com>
>> Cc: dev@dpdk.org; Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>;
>> Ori Kam <orika@nvidia.com>
>> Subject: Re: [v2 1/4] lib: add optional fields in GRE header
>>
>> External email: Use caution opening links or attachments
>>
>>
>> On 2/11/2022 1:45 AM, Sean Zhang wrote:
>>> There are optional fields in GRE header(checksum/key/sequence), this
>>> patch adds definition of structures of the optional fields.
>>>
>>> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
>>> ---
>>>    lib/net/rte_gre.h | 22 ++++++++++++++++++++++
>>>    1 file changed, 22 insertions(+)
>>>
>>> diff --git a/lib/net/rte_gre.h b/lib/net/rte_gre.h index
>>> 5897756..6c6aef6 100644
>>> --- a/lib/net/rte_gre.h
>>> +++ b/lib/net/rte_gre.h
>>> @@ -48,6 +48,28 @@ struct rte_gre_hdr {
>>>        uint16_t proto;  /**< Protocol Type */
>>>    } __rte_packed;
>>>
>>> +/**
>>> + * Optional field checksum in GRE header  */ struct
>>> +rte_gre_hdr_opt_checksum_rsvd {
>>> +     rte_be16_t checksum;
>>> +     rte_be16_t reserved1;
>>
>> Can you please explain why this reserved field is added, I guess it i not part of
>> the GRE spec, but added for mlx driver?
>>
> 
> Yes, the reserverd1 field is part of GRE spec, and the field go together with checksum field, so I add the reserverd1 field here.
> 
> You can refer to section 2.6 of https://datatracker.ietf.org/doc/rfc2784/
> 

ack, thanks.

>> Since these struts will be public, we can't update them later easily, so we
>> should be careful on them.
>>
>>> +} __rte_packed;
>>> +
>>> +/**
>>> + * Optional field key in GRE header
>>> + */
>>> +struct rte_gre_hdr_opt_key {
>>> +     rte_be32_t key;
>>> +} __rte_packed;
>>> +
>>> +/**
>>> + * Optional field sequence in GRE header  */ struct
>>> +rte_gre_hdr_opt_sequence {
>>> +     rte_be32_t sequence;
>>> +} __rte_packed;
>>> +
>>>    #ifdef __cplusplus
>>>    }
>>>    #endif
> 

RE: [v2 1/4] lib: add optional fields in GRE header

[Ori Kam]

Hi Sean,

> -----Original Message-----
> From: Sean Zhang <xiazhang@nvidia.com>
> Subject: [v2 1/4] lib: add optional fields in GRE header
> 
> There are optional fields in GRE header(checksum/key/sequence), this
> patch adds definition of structures of the optional fields.
> 
> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> ---
>  lib/net/rte_gre.h | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/lib/net/rte_gre.h b/lib/net/rte_gre.h
> index 5897756..6c6aef6 100644
> --- a/lib/net/rte_gre.h
> +++ b/lib/net/rte_gre.h
> @@ -48,6 +48,28 @@ struct rte_gre_hdr {
>  	uint16_t proto;  /**< Protocol Type */
>  } __rte_packed;
> 
> +/**
> + * Optional field checksum in GRE header
> + */
> +struct rte_gre_hdr_opt_checksum_rsvd {
> +	rte_be16_t checksum;
> +	rte_be16_t reserved1;
> +} __rte_packed;
> +
> +/**
> + * Optional field key in GRE header
> + */
> +struct rte_gre_hdr_opt_key {
> +	rte_be32_t key;
> +} __rte_packed;
> +
> +/**
> + * Optional field sequence in GRE header
> + */
> +struct rte_gre_hdr_opt_sequence {
> +	rte_be32_t sequence;
> +} __rte_packed;
> +
>  #ifdef __cplusplus
>  }
>  #endif
> --
> 1.8.3.1

Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori

[v2 2/4] ethdev: support GRE optional fields

[Sean Zhang]

Add flow pattern items and header format for matching optional fields
(checksum/key/sequence) in GRE header. And the flags in gre item should
be correspondingly set with the new added items.

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
---
 doc/guides/prog_guide/rte_flow.rst     | 17 +++++++++++++++++
 doc/guides/rel_notes/release_22_03.rst |  5 +++++
 lib/ethdev/rte_flow.c                  |  1 +
 lib/ethdev/rte_flow.h                  | 19 +++++++++++++++++++
 4 files changed, 42 insertions(+)

diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
index b4aa9c4..0e47501 100644
--- a/doc/guides/prog_guide/rte_flow.rst
+++ b/doc/guides/prog_guide/rte_flow.rst
@@ -1106,6 +1106,7 @@ Matches a GRE header.
 
 Item: ``GRE_KEY``
 ^^^^^^^^^^^^^^^^^
+This action is deprecated. Consider `Item: GRE_OPTION`.
 
 Matches a GRE key field.
 This should be preceded by item ``GRE``.
@@ -1113,6 +1114,22 @@ This should be preceded by item ``GRE``.
 - Value to be matched is a big-endian 32 bit integer.
 - When this item present it implicitly match K bit in default mask as "1"
 
+Item: ``GRE_OPTION``
+^^^^^^^^^^^^^^^^^^^^
+
+Matches a GRE optional fields (checksum/key/sequence).
+This should be preceded by item ``GRE``.
+
+- ``checksum``: checksum.
+- ``key``: key.
+- ``sequence``: sequence.
+- The items in GRE_OPTION do not change bit flags(c_bit/k_bit/s_bit) in GRE
+  item. The bit flags need be set with GRE item by application. When the items
+  present, the corresponding bits in GRE spec and mask should be set "1" by
+  application, it means to match specified value of the fields. When the items
+  no present, but the corresponding bits in GRE spec and mask is "1", it means
+  to match any value of the fields.
+
 Item: ``FUZZY``
 ^^^^^^^^^^^^^^^
 
diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst
index b20716c..721ce16 100644
--- a/doc/guides/rel_notes/release_22_03.rst
+++ b/doc/guides/rel_notes/release_22_03.rst
@@ -87,6 +87,11 @@ New Features
 
   The new API ``rte_event_eth_rx_adapter_event_port_get()`` was added.
 
+* **Added rte_flow support for matching GRE optional fields.**
+
+  * Added ``gre_option`` item in rte_flow to support checksum/key/sequence
+    matching in GRE packets.
+
 * **Updated testpmd.**
 
   * Called ``rte_ipv4/6_udptcp_cksum_mbuf()`` functions in testpmd csum mode
diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c
index a93f68a..7f93900 100644
--- a/lib/ethdev/rte_flow.c
+++ b/lib/ethdev/rte_flow.c
@@ -139,6 +139,7 @@ struct rte_flow_desc_data {
 	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
 	MK_FLOW_ITEM(TAG, sizeof(struct rte_flow_item_tag)),
 	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
+	MK_FLOW_ITEM(GRE_OPTION, sizeof(struct rte_flow_item_gre_opt)),
 	MK_FLOW_ITEM(GTP_PSC, sizeof(struct rte_flow_item_gtp_psc)),
 	MK_FLOW_ITEM(PPPOES, sizeof(struct rte_flow_item_pppoe)),
 	MK_FLOW_ITEM(PPPOED, sizeof(struct rte_flow_item_pppoe)),
diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h
index 1031fb2..765beb3 100644
--- a/lib/ethdev/rte_flow.h
+++ b/lib/ethdev/rte_flow.h
@@ -37,6 +37,7 @@
 #include <rte_gtp.h>
 #include <rte_l2tpv2.h>
 #include <rte_ppp.h>
+#include <rte_gre.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -660,6 +661,13 @@ enum rte_flow_item_type {
 	 * See struct rte_flow_item_ppp.
 	 */
 	RTE_FLOW_ITEM_TYPE_PPP,
+
+	/**
+	 * Matches GRE optional fields.
+	 *
+	 * See struct rte_flow_item_gre_opt.
+	 */
+	RTE_FLOW_ITEM_TYPE_GRE_OPTION,
 };
 
 /**
@@ -1196,6 +1204,17 @@ struct rte_flow_item_gre {
 #endif
 
 /**
+ * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
+ *
+ * Matches GRE optional fields in header.
+ */
+struct rte_flow_item_gre_opt {
+	struct rte_gre_hdr_opt_checksum_rsvd checksum_rsvd;
+	struct rte_gre_hdr_opt_key key;
+	struct rte_gre_hdr_opt_sequence sequence;
+};
+
+/**
  * RTE_FLOW_ITEM_TYPE_FUZZY
  *
  * Fuzzy pattern match, expect faster than default.
-- 
1.8.3.1

RE: [v2 2/4] ethdev: support GRE optional fields

[Ori Kam]

Hi Sean,

> -----Original Message-----
> From: Sean Zhang (Networking SW) <xiazhang@nvidia.com>
> Subject: [v2 2/4] ethdev: support GRE optional fields
> 
> Add flow pattern items and header format for matching optional fields
> (checksum/key/sequence) in GRE header. And the flags in gre item should
> be correspondingly set with the new added items.
> 
> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> ---
>  doc/guides/prog_guide/rte_flow.rst     | 17 +++++++++++++++++
>  doc/guides/rel_notes/release_22_03.rst |  5 +++++
>  lib/ethdev/rte_flow.c                  |  1 +
>  lib/ethdev/rte_flow.h                  | 19 +++++++++++++++++++
>  4 files changed, 42 insertions(+)
> 
> diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
> index b4aa9c4..0e47501 100644
> --- a/doc/guides/prog_guide/rte_flow.rst
> +++ b/doc/guides/prog_guide/rte_flow.rst
> @@ -1106,6 +1106,7 @@ Matches a GRE header.
> 
>  Item: ``GRE_KEY``
>  ^^^^^^^^^^^^^^^^^
> +This action is deprecated. Consider `Item: GRE_OPTION`.
> 
>  Matches a GRE key field.
>  This should be preceded by item ``GRE``.
> @@ -1113,6 +1114,22 @@ This should be preceded by item ``GRE``.
>  - Value to be matched is a big-endian 32 bit integer.
>  - When this item present it implicitly match K bit in default mask as "1"
> 
> +Item: ``GRE_OPTION``
> +^^^^^^^^^^^^^^^^^^^^
> +
> +Matches a GRE optional fields (checksum/key/sequence).
> +This should be preceded by item ``GRE``.
> +
> +- ``checksum``: checksum.
> +- ``key``: key.
> +- ``sequence``: sequence.
> +- The items in GRE_OPTION do not change bit flags(c_bit/k_bit/s_bit) in GRE
> +  item. The bit flags need be set with GRE item by application. When the items
> +  present, the corresponding bits in GRE spec and mask should be set "1" by
> +  application, it means to match specified value of the fields. When the items
> +  no present, but the corresponding bits in GRE spec and mask is "1", it means
> +  to match any value of the fields.
> +
>  Item: ``FUZZY``
>  ^^^^^^^^^^^^^^^
> 
> diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst
> index b20716c..721ce16 100644
> --- a/doc/guides/rel_notes/release_22_03.rst
> +++ b/doc/guides/rel_notes/release_22_03.rst
> @@ -87,6 +87,11 @@ New Features
> 
>    The new API ``rte_event_eth_rx_adapter_event_port_get()`` was added.
> 
> +* **Added rte_flow support for matching GRE optional fields.**
> +
> +  * Added ``gre_option`` item in rte_flow to support checksum/key/sequence
> +    matching in GRE packets.
> +
>  * **Updated testpmd.**
> 
>    * Called ``rte_ipv4/6_udptcp_cksum_mbuf()`` functions in testpmd csum mode
> diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c
> index a93f68a..7f93900 100644
> --- a/lib/ethdev/rte_flow.c
> +++ b/lib/ethdev/rte_flow.c
> @@ -139,6 +139,7 @@ struct rte_flow_desc_data {
>  	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
>  	MK_FLOW_ITEM(TAG, sizeof(struct rte_flow_item_tag)),
>  	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
> +	MK_FLOW_ITEM(GRE_OPTION, sizeof(struct rte_flow_item_gre_opt)),
>  	MK_FLOW_ITEM(GTP_PSC, sizeof(struct rte_flow_item_gtp_psc)),
>  	MK_FLOW_ITEM(PPPOES, sizeof(struct rte_flow_item_pppoe)),
>  	MK_FLOW_ITEM(PPPOED, sizeof(struct rte_flow_item_pppoe)),
> diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h
> index 1031fb2..765beb3 100644
> --- a/lib/ethdev/rte_flow.h
> +++ b/lib/ethdev/rte_flow.h
> @@ -37,6 +37,7 @@
>  #include <rte_gtp.h>
>  #include <rte_l2tpv2.h>
>  #include <rte_ppp.h>
> +#include <rte_gre.h>
> 
>  #ifdef __cplusplus
>  extern "C" {
> @@ -660,6 +661,13 @@ enum rte_flow_item_type {
>  	 * See struct rte_flow_item_ppp.
>  	 */
>  	RTE_FLOW_ITEM_TYPE_PPP,
> +
> +	/**
> +	 * Matches GRE optional fields.
> +	 *
> +	 * See struct rte_flow_item_gre_opt.
> +	 */
> +	RTE_FLOW_ITEM_TYPE_GRE_OPTION,
>  };
> 
>  /**
> @@ -1196,6 +1204,17 @@ struct rte_flow_item_gre {
>  #endif
> 
>  /**
> + * RTE_FLOW_ITEM_TYPE_GRE_OPTION.
> + *
> + * Matches GRE optional fields in header.
> + */
> +struct rte_flow_item_gre_opt {
> +	struct rte_gre_hdr_opt_checksum_rsvd checksum_rsvd;
> +	struct rte_gre_hdr_opt_key key;
> +	struct rte_gre_hdr_opt_sequence sequence;
> +};
> +
> +/**
>   * RTE_FLOW_ITEM_TYPE_FUZZY
>   *
>   * Fuzzy pattern match, expect faster than default.
> --
> 1.8.3.1

Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori

[v2 3/4] app/testpmd: add gre_option item command

[Sean Zhang]

Add gre_option command for matching optional fields(checksum/key/sequence)
in GRE header. The item must follow gre item, and the item does not
change the flags in gre item, the application should set the flags in
gre item correspondingly.
Application can still use gre_key item 'gre_key value is xx' for key
matching, the effect is the same with using 'gre_option key is xx'.

The examples for gre_option are as follows:

To match on checksum field with value 0x11:
testpmd> ... pattern / eth / gre c_bit is 1 / gre_option checksum is
		0x11 / end ..

To match on checksum field with value 0x11 and any value of key:
testpmd> ... pattern / eth / gre c_bit is 1 k_bit is 1 / gre_option
		checksum is 0x11 / end ..

To match on checksum field with value 0x11 and no key field in packet:
testpmd> ... pattern / eth / gre c_bit is 1 k_bit is 0 / gre_option
		checksum is 0x11 / end ..

The invalid patterns for gre_option are as follows:

testpmd> ... pattern / eth / gre / gre_option checksum is 0x11 / end ..
		(c_bit in gre item not present)
testpmd> ... pattern / eth / gre c_bit is 0 / gre_option checksum is 0x11 /
		end .. (c_bit is unset for gre item, but checksum is
		specified by gre_option item)

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
---
 app/test-pmd/cmdline_flow.c                 | 72 +++++++++++++++++++++++++++++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  6 +++
 2 files changed, 78 insertions(+)

diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
index 7b56b1b..b977480 100644
--- a/app/test-pmd/cmdline_flow.c
+++ b/app/test-pmd/cmdline_flow.c
@@ -272,6 +272,10 @@ enum index {
 	ITEM_META_DATA,
 	ITEM_GRE_KEY,
 	ITEM_GRE_KEY_VALUE,
+	ITEM_GRE_OPTION,
+	ITEM_GRE_OPTION_CHECKSUM,
+	ITEM_GRE_OPTION_KEY,
+	ITEM_GRE_OPTION_SEQUENCE,
 	ITEM_GTP_PSC,
 	ITEM_GTP_PSC_QFI,
 	ITEM_GTP_PSC_PDU_T,
@@ -1043,6 +1047,7 @@ struct parse_action_priv {
 	ITEM_ICMP6_ND_OPT_TLA_ETH,
 	ITEM_META,
 	ITEM_GRE_KEY,
+	ITEM_GRE_OPTION,
 	ITEM_GTP_PSC,
 	ITEM_PPPOES,
 	ITEM_PPPOED,
@@ -1234,6 +1239,14 @@ struct parse_action_priv {
 	ZERO,
 };
 
+static const enum index item_gre_option[] = {
+	ITEM_GRE_OPTION_CHECKSUM,
+	ITEM_GRE_OPTION_KEY,
+	ITEM_GRE_OPTION_SEQUENCE,
+	ITEM_NEXT,
+	ZERO,
+};
+
 static const enum index item_gtp[] = {
 	ITEM_GTP_FLAGS,
 	ITEM_GTP_MSG_TYPE,
@@ -3494,6 +3507,38 @@ static int comp_set_modify_field_id(struct context *, const struct token *,
 			     item_param),
 		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
 	},
+	[ITEM_GRE_OPTION] = {
+		.name = "gre_option",
+		.help = "match GRE optional fields",
+		.priv = PRIV_ITEM(GRE_OPTION,
+				  sizeof(struct rte_flow_item_gre_opt)),
+		.next = NEXT(item_gre_option),
+		.call = parse_vc,
+	},
+	[ITEM_GRE_OPTION_CHECKSUM] = {
+		.name = "checksum",
+		.help = "match GRE checksum",
+		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
+			     item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt,
+					     checksum_rsvd.checksum)),
+	},
+	[ITEM_GRE_OPTION_KEY] = {
+		.name = "key",
+		.help = "match GRE key",
+		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
+			     item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt,
+					     key.key)),
+	},
+	[ITEM_GRE_OPTION_SEQUENCE] = {
+		.name = "sequence",
+		.help = "match GRE sequence",
+		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
+			     item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt,
+					     sequence.sequence)),
+	},
 	[ITEM_GTP_PSC] = {
 		.name = "gtp_psc",
 		.help = "match GTP extension header with type 0x85",
@@ -9252,6 +9297,33 @@ static int comp_set_modify_field_id(struct context *, const struct token *,
 				((const struct rte_flow_item_flex *)
 				item->spec)->length : 0;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
+			size = 0;
+			if (item->spec) {
+				const struct rte_flow_item_gre_opt
+					*opt = item->spec;
+				if (opt->checksum_rsvd.checksum) {
+					*total_size +=
+						sizeof(opt->checksum_rsvd);
+					rte_memcpy(data_tail - (*total_size),
+						   &opt->checksum_rsvd,
+						   sizeof(opt->checksum_rsvd));
+				}
+				if (opt->key.key) {
+					*total_size += sizeof(opt->key.key);
+					rte_memcpy(data_tail - (*total_size),
+						   &opt->key.key,
+						   sizeof(opt->key.key));
+				}
+				if (opt->sequence.sequence) {
+					*total_size += sizeof(opt->sequence.sequence);
+					rte_memcpy(data_tail - (*total_size),
+						   &opt->sequence.sequence,
+						   sizeof(opt->sequence.sequence));
+				}
+			}
+			proto = 0x2F;
+			break;
 		default:
 			fprintf(stderr, "Error - Not supported item\n");
 			goto error;
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index 0551121..09cd1f4 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -3715,6 +3715,12 @@ This section lists supported pattern items and their attributes, if any.
 
   - ``value {unsigned}``: key value.
 
+- ``gre_option``: match GRE optional fields(checksum/key/sequence).
+
+  - ``checksum {unsigned}``: checksum value.
+  - ``key {unsigned}``: key value.
+  - ``sequence {unsigned}``: sequence number value.
+
 - ``fuzzy``: fuzzy pattern match, expect faster than default.
 
   - ``thresh {unsigned}``: accuracy threshold.
-- 
1.8.3.1

RE: [v2 3/4] app/testpmd: add gre_option item command

[Ori Kam]

Hi Sean,

> -----Original Message-----
> From: Sean Zhang (Networking SW) <xiazhang@nvidia.com>
> Subject: [v2 3/4] app/testpmd: add gre_option item command
> 
> Add gre_option command for matching optional fields(checksum/key/sequence)
> in GRE header. The item must follow gre item, and the item does not
> change the flags in gre item, the application should set the flags in
> gre item correspondingly.
> Application can still use gre_key item 'gre_key value is xx' for key
> matching, the effect is the same with using 'gre_option key is xx'.
> 
> The examples for gre_option are as follows:
> 
> To match on checksum field with value 0x11:
> testpmd> ... pattern / eth / gre c_bit is 1 / gre_option checksum is
> 		0x11 / end ..
> 
> To match on checksum field with value 0x11 and any value of key:
> testpmd> ... pattern / eth / gre c_bit is 1 k_bit is 1 / gre_option
> 		checksum is 0x11 / end ..
> 
> To match on checksum field with value 0x11 and no key field in packet:
> testpmd> ... pattern / eth / gre c_bit is 1 k_bit is 0 / gre_option
> 		checksum is 0x11 / end ..
> 
> The invalid patterns for gre_option are as follows:
> 
> testpmd> ... pattern / eth / gre / gre_option checksum is 0x11 / end ..
> 		(c_bit in gre item not present)
> testpmd> ... pattern / eth / gre c_bit is 0 / gre_option checksum is 0x11 /
> 		end .. (c_bit is unset for gre item, but checksum is
> 		specified by gre_option item)
> 
> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> ---
>  app/test-pmd/cmdline_flow.c                 | 72 +++++++++++++++++++++++++++++
>  doc/guides/testpmd_app_ug/testpmd_funcs.rst |  6 +++
>  2 files changed, 78 insertions(+)
> 
> diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
> index 7b56b1b..b977480 100644
> --- a/app/test-pmd/cmdline_flow.c
> +++ b/app/test-pmd/cmdline_flow.c
> @@ -272,6 +272,10 @@ enum index {
>  	ITEM_META_DATA,
>  	ITEM_GRE_KEY,
>  	ITEM_GRE_KEY_VALUE,
> +	ITEM_GRE_OPTION,
> +	ITEM_GRE_OPTION_CHECKSUM,
> +	ITEM_GRE_OPTION_KEY,
> +	ITEM_GRE_OPTION_SEQUENCE,
>  	ITEM_GTP_PSC,
>  	ITEM_GTP_PSC_QFI,
>  	ITEM_GTP_PSC_PDU_T,
> @@ -1043,6 +1047,7 @@ struct parse_action_priv {
>  	ITEM_ICMP6_ND_OPT_TLA_ETH,
>  	ITEM_META,
>  	ITEM_GRE_KEY,
> +	ITEM_GRE_OPTION,
>  	ITEM_GTP_PSC,
>  	ITEM_PPPOES,
>  	ITEM_PPPOED,
> @@ -1234,6 +1239,14 @@ struct parse_action_priv {
>  	ZERO,
>  };
> 
> +static const enum index item_gre_option[] = {
> +	ITEM_GRE_OPTION_CHECKSUM,
> +	ITEM_GRE_OPTION_KEY,
> +	ITEM_GRE_OPTION_SEQUENCE,
> +	ITEM_NEXT,
> +	ZERO,
> +};
> +
>  static const enum index item_gtp[] = {
>  	ITEM_GTP_FLAGS,
>  	ITEM_GTP_MSG_TYPE,
> @@ -3494,6 +3507,38 @@ static int comp_set_modify_field_id(struct context *, const struct token *,
>  			     item_param),
>  		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
>  	},
> +	[ITEM_GRE_OPTION] = {
> +		.name = "gre_option",
> +		.help = "match GRE optional fields",
> +		.priv = PRIV_ITEM(GRE_OPTION,
> +				  sizeof(struct rte_flow_item_gre_opt)),
> +		.next = NEXT(item_gre_option),
> +		.call = parse_vc,
> +	},
> +	[ITEM_GRE_OPTION_CHECKSUM] = {
> +		.name = "checksum",
> +		.help = "match GRE checksum",
> +		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
> +			     item_param),
> +		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt,
> +					     checksum_rsvd.checksum)),
> +	},
> +	[ITEM_GRE_OPTION_KEY] = {
> +		.name = "key",
> +		.help = "match GRE key",
> +		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
> +			     item_param),
> +		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt,
> +					     key.key)),
> +	},
> +	[ITEM_GRE_OPTION_SEQUENCE] = {
> +		.name = "sequence",
> +		.help = "match GRE sequence",
> +		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
> +			     item_param),
> +		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt,
> +					     sequence.sequence)),
> +	},
>  	[ITEM_GTP_PSC] = {
>  		.name = "gtp_psc",
>  		.help = "match GTP extension header with type 0x85",
> @@ -9252,6 +9297,33 @@ static int comp_set_modify_field_id(struct context *, const struct token *,
>  				((const struct rte_flow_item_flex *)
>  				item->spec)->length : 0;
>  			break;
> +		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
> +			size = 0;
> +			if (item->spec) {
> +				const struct rte_flow_item_gre_opt
> +					*opt = item->spec;
> +				if (opt->checksum_rsvd.checksum) {
> +					*total_size +=
> +						sizeof(opt->checksum_rsvd);
> +					rte_memcpy(data_tail - (*total_size),
> +						   &opt->checksum_rsvd,
> +						   sizeof(opt->checksum_rsvd));
> +				}
> +				if (opt->key.key) {
> +					*total_size += sizeof(opt->key.key);
> +					rte_memcpy(data_tail - (*total_size),
> +						   &opt->key.key,
> +						   sizeof(opt->key.key));
> +				}
> +				if (opt->sequence.sequence) {
> +					*total_size += sizeof(opt->sequence.sequence);
> +					rte_memcpy(data_tail - (*total_size),
> +						   &opt->sequence.sequence,
> +						   sizeof(opt->sequence.sequence));
> +				}
> +			}
> +			proto = 0x2F;
> +			break;
>  		default:
>  			fprintf(stderr, "Error - Not supported item\n");
>  			goto error;
> diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> index 0551121..09cd1f4 100644
> --- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> +++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> @@ -3715,6 +3715,12 @@ This section lists supported pattern items and their attributes, if any.
> 
>    - ``value {unsigned}``: key value.
> 
> +- ``gre_option``: match GRE optional fields(checksum/key/sequence).
> +
> +  - ``checksum {unsigned}``: checksum value.
> +  - ``key {unsigned}``: key value.
> +  - ``sequence {unsigned}``: sequence number value.
> +
>  - ``fuzzy``: fuzzy pattern match, expect faster than default.
> 
>    - ``thresh {unsigned}``: accuracy threshold.
> --
> 1.8.3.1

Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori

[v2 4/4] net/mlx5: support matching optional fields of GRE

[Sean Zhang]

This patch adds matching on the optional fields (checksum/key/sequence)
of GRE header. The matching of checksum and sequence fields requests
support from rdma-core with capability of misc5 and tunner_header 0-3.

For patterns without checksum and sequence specified, keep using misc for
matching as before, but for patterns with checksum or sequence, validate
capability first and then use misc5 for the matching.

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
---
 doc/guides/nics/mlx5.rst             |   8 +++
 drivers/common/mlx5/mlx5_devx_cmds.c |   3 +
 drivers/net/mlx5/linux/mlx5_os.c     |   2 +
 drivers/net/mlx5/mlx5.h              |   1 +
 drivers/net/mlx5/mlx5_flow.c         | 108 +++++++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_flow.h         |   6 ++
 drivers/net/mlx5/mlx5_flow_dv.c      | 130 +++++++++++++++++++++++++++++++++++
 7 files changed, 258 insertions(+)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index daa7f2a..abd6b8b 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -508,6 +508,14 @@ Limitations
     from the reference "Clock Queue" completions,
     the scheduled send timestamps should not be specified with non-zero MSB.
 
+- Match on GRE header supports the following fields:
+
+  - c_rsvd0_v: C bit, K bit, S bit
+  - protocol type
+  - Checksum
+  - Key
+  - Sequence
+
 Statistics
 ----------
 
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 2e807a0..77436ed 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1043,6 +1043,9 @@ struct mlx5_devx_obj *
 	attr->flow.tunnel_header_0_1 = MLX5_GET
 		(flow_table_nic_cap, hcattr,
 		 ft_field_support_2_nic_receive.tunnel_header_0_1);
+	attr->flow.tunnel_header_2_3 = MLX5_GET
+		(flow_table_nic_cap, hcattr,
+		 ft_field_support_2_nic_receive.tunnel_header_2_3);
 	attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
 	attr->inner_ipv4_ihl = MLX5_GET
 		(flow_table_nic_cap, hcattr,
diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index aecdc5a..7f59cfb 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -1383,6 +1383,8 @@
 		}
 		if (config->hca_attr.flow.tunnel_header_0_1)
 			sh->tunnel_header_0_1 = 1;
+		if (config->hca_attr.flow.tunnel_header_2_3)
+			sh->tunnel_header_2_3 = 1;
 #endif
 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 		if (config->hca_attr.flow_hit_aso &&
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 737ad68..5faca7a 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1154,6 +1154,7 @@ struct mlx5_dev_ctx_shared {
 	uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
 	uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
 	uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */
+	uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */
 	uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
 	uint32_t reclaim_mode:1; /* Reclaim memory. */
 	uint32_t dr_drop_action_en:1; /* Use DR drop action. */
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index d7cb1eb..7f0af38 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -2815,6 +2815,114 @@ struct mlx5_flow_tunnel_info {
 }
 
 /**
+ * Validate GRE optional item.
+ *
+ * @param[in] dev
+ *   Pointer to the Ethernet device structure.
+ * @param[in] item
+ *   Item specification.
+ * @param[in] item_flags
+ *   Bit flags to mark detected items.
+ * @param[in] attr
+ *   Flow rule attributes.
+ * @param[in] gre_item
+ *   Pointer to gre_item
+ * @param[out] error
+ *   Pointer to error structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
+				   const struct rte_flow_item *item,
+				   uint64_t item_flags,
+				   const struct rte_flow_attr *attr,
+				   const struct rte_flow_item *gre_item,
+				   struct rte_flow_error *error)
+{
+	const struct rte_flow_item_gre *gre_spec = gre_item->spec;
+	const struct rte_flow_item_gre *gre_mask = gre_item->mask;
+	const struct rte_flow_item_gre_opt *spec = item->spec;
+	const struct rte_flow_item_gre_opt *mask = item->mask;
+	struct mlx5_priv *priv = dev->data->dev_private;
+	int ret = 0;
+
+	struct rte_flow_item_gre_opt nic_mask = {
+		.checksum_rsvd = {
+			.checksum = RTE_BE16(UINT16_MAX),
+			.reserved1 = 0x0,
+		},
+		.key = {
+			.key = RTE_BE32(UINT32_MAX),
+		},
+		.sequence = {
+			.sequence = RTE_BE32(UINT32_MAX),
+		},
+	};
+
+	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "No preceding GRE header");
+	if (item_flags & MLX5_FLOW_LAYER_INNER)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "GRE option following a wrong item");
+	if (!spec || !mask)
+		return rte_flow_error_set(error, EINVAL,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "At least one field gre_option(checksum/key/sequence) must be specified");
+	if (!gre_mask)
+		gre_mask = &rte_flow_item_gre_mask;
+
+	if (mask->checksum_rsvd.checksum)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x8000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x8000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item,
+						  "Checksum bit must be on");
+
+	if (mask->key.key)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item, "Key bit must be on");
+
+	if (mask->sequence.sequence)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x1000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x1000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item,
+						  "Sequence bit must be on");
+
+	if (mask->checksum_rsvd.checksum || mask->sequence.sequence) {
+		if (priv->sh->steering_format_version ==
+		    MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 ||
+		    ((attr->group || attr->transfer) &&
+		     !priv->sh->misc5_cap) ||
+		    (!(priv->sh->tunnel_header_0_1 &&
+		       priv->sh->tunnel_header_2_3) &&
+		    !attr->group && !attr->transfer))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item,
+						  "Checksum/Sequence not supported");
+	}
+
+	ret = mlx5_flow_item_acceptable
+		(item, (const uint8_t *)mask,
+		 (const uint8_t *)&nic_mask,
+		 sizeof(struct rte_flow_item_gre_opt),
+		 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
+
+	return ret;
+}
+
+/**
  * Validate GRE item.
  *
  * @param[in] item
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 7fec79a..667b241 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -1537,6 +1537,12 @@ int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
 				    uint64_t item_flags,
 				    const struct rte_flow_item *gre_item,
 				    struct rte_flow_error *error);
+int mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
+				const struct rte_flow_item *item,
+				uint64_t item_flags,
+				const struct rte_flow_attr *attr,
+				const struct rte_flow_item *gre_item,
+				struct rte_flow_error *error);
 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
 				 uint64_t item_flags,
 				 uint64_t last_item,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index ef9c66e..bd3fcdc 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -7101,6 +7101,13 @@ struct mlx5_list_entry *
 			gre_item = items;
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
+			ret = mlx5_flow_validate_item_gre_option(dev, items, item_flags,
+							  attr, gre_item, error);
+			if (ret < 0)
+				return ret;
+			last_item = MLX5_FLOW_LAYER_GRE;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			ret = mlx5_flow_validate_item_nvgre(items, item_flags,
 							    next_protocol,
@@ -8822,6 +8829,119 @@ struct mlx5_list_entry *
 }
 
 /**
+ * Add GRE optional items to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] gre_item
+ *   Pointer to gre_item.
+ * @param[in] pattern_flags
+ *   Accumulated pattern flags.
+ */
+static void
+flow_dv_translate_item_gre_option(void *matcher, void *key,
+				  const struct rte_flow_item *item,
+				  const struct rte_flow_item *gre_item,
+				  uint64_t pattern_flags)
+{
+	const struct rte_flow_item_gre_opt *option_m = item->mask;
+	const struct rte_flow_item_gre_opt *option_v = item->spec;
+	const struct rte_flow_item_gre *gre_m = gre_item->mask;
+	const struct rte_flow_item_gre *gre_v = gre_item->spec;
+	static const struct rte_flow_item_gre empty_gre = {0};
+	struct rte_flow_item gre_key_item;
+	uint16_t c_rsvd0_ver_m, c_rsvd0_ver_v;
+	uint16_t protocol_m, protocol_v;
+	uint32_t *tunnel_header_v[4];
+	uint32_t *tunnel_header_m[4];
+	void *misc5_m;
+	void *misc5_v;
+
+	if (!(option_m->sequence.sequence ||
+	      option_m->checksum_rsvd.checksum)) {
+		flow_dv_translate_item_gre(matcher, key, gre_item,
+					   pattern_flags);
+		gre_key_item.spec = &option_v->key.key;
+		gre_key_item.mask = &option_m->key.key;
+		flow_dv_translate_item_gre_key(matcher, key, &gre_key_item);
+		return;
+	}
+
+	if (!gre_v) {
+		gre_v = &empty_gre;
+		gre_m = &empty_gre;
+	} else {
+		if (!gre_m)
+			gre_m = &rte_flow_item_gre_mask;
+	}
+
+	misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
+	misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
+	tunnel_header_v[0] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_v, tunnel_header_0);
+	tunnel_header_m[0] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_m, tunnel_header_0);
+	tunnel_header_v[1] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_v, tunnel_header_1);
+	tunnel_header_m[1] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_m, tunnel_header_1);
+	tunnel_header_v[2] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_v, tunnel_header_2);
+	tunnel_header_m[2] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_m, tunnel_header_2);
+	tunnel_header_v[3] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_v, tunnel_header_3);
+	tunnel_header_m[3] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_m, tunnel_header_3);
+
+	protocol_v = gre_v->protocol;
+	protocol_m = gre_m->protocol;
+	if (!protocol_m) {
+		/* Force next protocol to prevent matchers duplication */
+		uint16_t ether_type =
+			mlx5_translate_tunnel_etypes(pattern_flags);
+		if (ether_type) {
+			protocol_v = rte_be_to_cpu_16(ether_type);
+			protocol_m = UINT16_MAX;
+		}
+	}
+	c_rsvd0_ver_v = gre_v->c_rsvd0_ver;
+	c_rsvd0_ver_m = gre_m->c_rsvd0_ver;
+
+
+	if (option_m->sequence.sequence) {
+		c_rsvd0_ver_v |= RTE_BE16(0x1000);
+		c_rsvd0_ver_m |= RTE_BE16(0x1000);
+	}
+
+	if (option_m->key.key) {
+		c_rsvd0_ver_v |= RTE_BE16(0x2000);
+		c_rsvd0_ver_m |= RTE_BE16(0x2000);
+	}
+
+	if (option_m->checksum_rsvd.checksum) {
+		c_rsvd0_ver_v |= RTE_BE16(0x8000);
+		c_rsvd0_ver_m |= RTE_BE16(0x8000);
+	}
+
+	*tunnel_header_v[0] = (c_rsvd0_ver_v | protocol_v << 16) &
+			(c_rsvd0_ver_m | protocol_m << 16);
+	*tunnel_header_m[0] = c_rsvd0_ver_m | protocol_m << 16;
+	*tunnel_header_v[1] = option_v->checksum_rsvd.checksum &
+		option_m->checksum_rsvd.checksum;
+	*tunnel_header_m[1] = option_m->checksum_rsvd.checksum;
+	*tunnel_header_v[2] = option_v->key.key & option_m->key.key;
+	*tunnel_header_m[2] = option_m->key.key;
+	*tunnel_header_v[3] = option_v->sequence.sequence &
+		option_m->sequence.sequence;
+	*tunnel_header_m[3] = option_m->sequence.sequence;
+}
+
+/**
  * Add NVGRE item to matcher and to the value.
  *
  * @param[in, out] matcher
@@ -12697,6 +12817,7 @@ struct mlx5_list_entry *
 	};
 	const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
 	const struct rte_flow_item *tunnel_item = NULL;
+	const struct rte_flow_item *gre_item = NULL;
 
 	if (!wks)
 		return rte_flow_error_set(error, ENOMEM,
@@ -13469,12 +13590,18 @@ struct mlx5_list_entry *
 			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
 			last_item = MLX5_FLOW_LAYER_GRE;
 			tunnel_item = items;
+			gre_item = items;
 			break;
 		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
 			flow_dv_translate_item_gre_key(match_mask,
 						       match_value, items);
 			last_item = MLX5_FLOW_LAYER_GRE_KEY;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
+			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
+			last_item = MLX5_FLOW_LAYER_GRE;
+			tunnel_item = items;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
 			last_item = MLX5_FLOW_LAYER_GRE;
@@ -13634,6 +13761,9 @@ struct mlx5_list_entry *
 		else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
 			flow_dv_translate_item_nvgre(match_mask, match_value,
 						     tunnel_item, item_flags);
+		else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION)
+			flow_dv_translate_item_gre_option(match_mask, match_value,
+					tunnel_item, gre_item, item_flags);
 		else
 			MLX5_ASSERT(false);
 	}
-- 
1.8.3.1

[PATCH] net/mlx5: support matching optional fields of GRE

[Sean Zhang]

This patch adds matching on the optional fields (checksum/key/sequence)
of GRE header. The matching on checksum and sequence fields requests
support from rdma-core with the capability of misc5 and tunnel_header 0-3.

For patterns without checksum and sequence specified, keep using misc for
matching as before, but for patterns with checksum or sequence, validate
capability first and then use misc5 for the matching.

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
Acked-by: Slava Ovsiienko <viacheslavo@nvidia.com>

---
v3 - some code style change
v2 - replace default mask with nic mask
---
 doc/guides/nics/mlx5.rst             |  10 +++
 drivers/common/mlx5/mlx5_devx_cmds.c |   3 +
 drivers/net/mlx5/linux/mlx5_os.c     |   2 +
 drivers/net/mlx5/mlx5.h              |   1 +
 drivers/net/mlx5/mlx5_flow.c         | 101 +++++++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_flow.h         |   6 ++
 drivers/net/mlx5/mlx5_flow_dv.c      | 121 +++++++++++++++++++++++++++++++++++
 7 files changed, 244 insertions(+)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index c3cc0c0..4611f0f 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -511,6 +511,16 @@ Limitations
     from the reference "Clock Queue" completions,
     the scheduled send timestamps should not be specified with non-zero MSB.
 
+- Match on GRE header supports the following fields:
+
+  - c_rsvd0_v: C bit, K bit, S bit
+  - protocol type
+  - Checksum
+  - Key
+  - Sequence
+
+  Matching on checksum and sequence needs OFED 5.6+.
+
 Statistics
 ----------
 
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 2e807a0..77436ed 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1043,6 +1043,9 @@ struct mlx5_devx_obj *
 	attr->flow.tunnel_header_0_1 = MLX5_GET
 		(flow_table_nic_cap, hcattr,
 		 ft_field_support_2_nic_receive.tunnel_header_0_1);
+	attr->flow.tunnel_header_2_3 = MLX5_GET
+		(flow_table_nic_cap, hcattr,
+		 ft_field_support_2_nic_receive.tunnel_header_2_3);
 	attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
 	attr->inner_ipv4_ihl = MLX5_GET
 		(flow_table_nic_cap, hcattr,
diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index bbe05bb..b8a9dea 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -1383,6 +1383,8 @@
 		}
 		if (config->hca_attr.flow.tunnel_header_0_1)
 			sh->tunnel_header_0_1 = 1;
+		if (config->hca_attr.flow.tunnel_header_2_3)
+			sh->tunnel_header_2_3 = 1;
 #endif
 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 		if (config->hca_attr.flow_hit_aso &&
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 737ad68..5faca7a 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1154,6 +1154,7 @@ struct mlx5_dev_ctx_shared {
 	uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
 	uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
 	uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */
+	uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */
 	uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
 	uint32_t reclaim_mode:1; /* Reclaim memory. */
 	uint32_t dr_drop_action_en:1; /* Use DR drop action. */
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 179cc3b..fc1249d 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -2815,6 +2815,107 @@ struct mlx5_flow_tunnel_info {
 }
 
 /**
+ * Validate GRE optional item.
+ *
+ * @param[in] dev
+ *   Pointer to the Ethernet device structure.
+ * @param[in] item
+ *   Item specification.
+ * @param[in] item_flags
+ *   Bit flags to mark detected items.
+ * @param[in] attr
+ *   Flow rule attributes.
+ * @param[in] gre_item
+ *   Pointer to gre_item
+ * @param[out] error
+ *   Pointer to error structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
+				   const struct rte_flow_item *item,
+				   uint64_t item_flags,
+				   const struct rte_flow_attr *attr,
+				   const struct rte_flow_item *gre_item,
+				   struct rte_flow_error *error)
+{
+	const struct rte_flow_item_gre *gre_spec = gre_item->spec;
+	const struct rte_flow_item_gre *gre_mask = gre_item->mask;
+	const struct rte_flow_item_gre_opt *spec = item->spec;
+	const struct rte_flow_item_gre_opt *mask = item->mask;
+	struct mlx5_priv *priv = dev->data->dev_private;
+	int ret = 0;
+	struct rte_flow_item_gre_opt nic_mask = {
+		.checksum_rsvd = {
+			.checksum = RTE_BE16(UINT16_MAX),
+			.reserved1 = 0x0,
+		},
+		.key = {
+			.key = RTE_BE32(UINT32_MAX),
+		},
+		.sequence = {
+			.sequence = RTE_BE32(UINT32_MAX),
+		},
+	};
+
+	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "No preceding GRE header");
+	if (item_flags & MLX5_FLOW_LAYER_INNER)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "GRE option following a wrong item");
+	if (!spec || !mask)
+		return rte_flow_error_set(error, EINVAL,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "At least one field gre_option(checksum/key/sequence) must be specified");
+	if (!gre_mask)
+		gre_mask = &rte_flow_item_gre_mask;
+	if (mask->checksum_rsvd.checksum)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x8000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x8000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item,
+						  "Checksum bit must be on");
+	if (mask->key.key)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item, "Key bit must be on");
+	if (mask->sequence.sequence)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x1000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x1000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item,
+						  "Sequence bit must be on");
+	if (mask->checksum_rsvd.checksum || mask->sequence.sequence) {
+		if (priv->sh->steering_format_version ==
+		    MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 ||
+		    ((attr->group || attr->transfer) &&
+		     !priv->sh->misc5_cap) ||
+		    (!(priv->sh->tunnel_header_0_1 &&
+		       priv->sh->tunnel_header_2_3) &&
+		    !attr->group && !attr->transfer))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item,
+						  "Checksum/Sequence not supported");
+	}
+	ret = mlx5_flow_item_acceptable
+		(item, (const uint8_t *)mask,
+		 (const uint8_t *)&nic_mask,
+		 sizeof(struct rte_flow_item_gre_opt),
+		 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
+	return ret;
+}
+
+/**
  * Validate GRE item.
  *
  * @param[in] item
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 7fec79a..667b241 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -1537,6 +1537,12 @@ int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
 				    uint64_t item_flags,
 				    const struct rte_flow_item *gre_item,
 				    struct rte_flow_error *error);
+int mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
+				const struct rte_flow_item *item,
+				uint64_t item_flags,
+				const struct rte_flow_attr *attr,
+				const struct rte_flow_item *gre_item,
+				struct rte_flow_error *error);
 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
 				 uint64_t item_flags,
 				 uint64_t last_item,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index ef9c66e..ba61a33 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -7101,6 +7101,13 @@ struct mlx5_list_entry *
 			gre_item = items;
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
+			ret = mlx5_flow_validate_item_gre_option(dev, items, item_flags,
+							  attr, gre_item, error);
+			if (ret < 0)
+				return ret;
+			last_item = MLX5_FLOW_LAYER_GRE;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			ret = mlx5_flow_validate_item_nvgre(items, item_flags,
 							    next_protocol,
@@ -8822,6 +8829,110 @@ struct mlx5_list_entry *
 }
 
 /**
+ * Add GRE optional items to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] gre_item
+ *   Pointer to gre_item.
+ * @param[in] pattern_flags
+ *   Accumulated pattern flags.
+ */
+static void
+flow_dv_translate_item_gre_option(void *matcher, void *key,
+				  const struct rte_flow_item *item,
+				  const struct rte_flow_item *gre_item,
+				  uint64_t pattern_flags)
+{
+	const struct rte_flow_item_gre_opt *option_m = item->mask;
+	const struct rte_flow_item_gre_opt *option_v = item->spec;
+	const struct rte_flow_item_gre *gre_m = gre_item->mask;
+	const struct rte_flow_item_gre *gre_v = gre_item->spec;
+	static const struct rte_flow_item_gre empty_gre = {0};
+	struct rte_flow_item gre_key_item;
+	uint16_t c_rsvd0_ver_m, c_rsvd0_ver_v;
+	uint16_t protocol_m, protocol_v;
+	void *misc5_m;
+	void *misc5_v;
+
+	/*
+	 * If only match key field, keep using misc for matching.
+	 * If need to match checksum or sequence, using misc5 and do
+	 * not need using misc.
+	 */
+	if (!(option_m->sequence.sequence ||
+	      option_m->checksum_rsvd.checksum)) {
+		flow_dv_translate_item_gre(matcher, key, gre_item,
+					   pattern_flags);
+		gre_key_item.spec = &option_v->key.key;
+		gre_key_item.mask = &option_m->key.key;
+		flow_dv_translate_item_gre_key(matcher, key, &gre_key_item);
+		return;
+	}
+	if (!gre_v) {
+		gre_v = &empty_gre;
+		gre_m = &empty_gre;
+	} else {
+		if (!gre_m)
+			gre_m = &rte_flow_item_gre_mask;
+	}
+	protocol_v = gre_v->protocol;
+	protocol_m = gre_m->protocol;
+	if (!protocol_m) {
+		/* Force next protocol to prevent matchers duplication */
+		uint16_t ether_type =
+			mlx5_translate_tunnel_etypes(pattern_flags);
+		if (ether_type) {
+			protocol_v = rte_be_to_cpu_16(ether_type);
+			protocol_m = UINT16_MAX;
+		}
+	}
+	c_rsvd0_ver_v = gre_v->c_rsvd0_ver;
+	c_rsvd0_ver_m = gre_m->c_rsvd0_ver;
+	if (option_m->sequence.sequence) {
+		c_rsvd0_ver_v |= RTE_BE16(0x1000);
+		c_rsvd0_ver_m |= RTE_BE16(0x1000);
+	}
+	if (option_m->key.key) {
+		c_rsvd0_ver_v |= RTE_BE16(0x2000);
+		c_rsvd0_ver_m |= RTE_BE16(0x2000);
+	}
+	if (option_m->checksum_rsvd.checksum) {
+		c_rsvd0_ver_v |= RTE_BE16(0x8000);
+		c_rsvd0_ver_m |= RTE_BE16(0x8000);
+	}
+	/*
+	 * Hardware parses GRE optional field into the fixed location,
+	 * do not need to adjust the tunnel dword indices.
+	 */
+	misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
+	misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
+	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_0,
+		 rte_be_to_cpu_32((c_rsvd0_ver_v | protocol_v << 16) &
+				  (c_rsvd0_ver_m | protocol_m << 16)));
+	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_0,
+		 rte_be_to_cpu_32(c_rsvd0_ver_m | protocol_m << 16));
+	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_1,
+		 rte_be_to_cpu_32(option_v->checksum_rsvd.checksum &
+				  option_m->checksum_rsvd.checksum));
+	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_1,
+		 rte_be_to_cpu_32(option_m->checksum_rsvd.checksum));
+	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_2,
+		 rte_be_to_cpu_32(option_v->key.key & option_m->key.key));
+	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_2,
+		 rte_be_to_cpu_32(option_m->key.key));
+	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_3,
+		 rte_be_to_cpu_32(option_v->sequence.sequence &
+				  option_m->sequence.sequence));
+	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_3,
+		 rte_be_to_cpu_32(option_m->sequence.sequence));
+}
+
+/**
  * Add NVGRE item to matcher and to the value.
  *
  * @param[in, out] matcher
@@ -12697,6 +12808,7 @@ struct mlx5_list_entry *
 	};
 	const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
 	const struct rte_flow_item *tunnel_item = NULL;
+	const struct rte_flow_item *gre_item = NULL;
 
 	if (!wks)
 		return rte_flow_error_set(error, ENOMEM,
@@ -13469,12 +13581,18 @@ struct mlx5_list_entry *
 			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
 			last_item = MLX5_FLOW_LAYER_GRE;
 			tunnel_item = items;
+			gre_item = items;
 			break;
 		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
 			flow_dv_translate_item_gre_key(match_mask,
 						       match_value, items);
 			last_item = MLX5_FLOW_LAYER_GRE_KEY;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
+			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
+			last_item = MLX5_FLOW_LAYER_GRE;
+			tunnel_item = items;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
 			last_item = MLX5_FLOW_LAYER_GRE;
@@ -13634,6 +13752,9 @@ struct mlx5_list_entry *
 		else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
 			flow_dv_translate_item_nvgre(match_mask, match_value,
 						     tunnel_item, item_flags);
+		else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION)
+			flow_dv_translate_item_gre_option(match_mask, match_value,
+					tunnel_item, gre_item, item_flags);
 		else
 			MLX5_ASSERT(false);
 	}
-- 
1.8.3.1

Re: [PATCH] net/mlx5: support matching optional fields of GRE

[Thomas Monjalon]

17/02/2022 07:27, Sean Zhang:
> This patch adds matching on the optional fields (checksum/key/sequence)
> of GRE header. The matching on checksum and sequence fields requests
> support from rdma-core with the capability of misc5 and tunnel_header 0-3.
> 
> For patterns without checksum and sequence specified, keep using misc for
> matching as before, but for patterns with checksum or sequence, validate
> capability first and then use misc5 for the matching.
> 
> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> Acked-by: Slava Ovsiienko <viacheslavo@nvidia.com>
> 
> ---
> v3 - some code style change
> v2 - replace default mask with nic mask
> ---
>  doc/guides/nics/mlx5.rst             |  10 +++
>  drivers/common/mlx5/mlx5_devx_cmds.c |   3 +
>  drivers/net/mlx5/linux/mlx5_os.c     |   2 +
>  drivers/net/mlx5/mlx5.h              |   1 +
>  drivers/net/mlx5/mlx5_flow.c         | 101 +++++++++++++++++++++++++++++
>  drivers/net/mlx5/mlx5_flow.h         |   6 ++
>  drivers/net/mlx5/mlx5_flow_dv.c      | 121 +++++++++++++++++++++++++++++++++++
>  7 files changed, 244 insertions(+)

Should we add a line in the release notes?

RE: [PATCH] net/mlx5: support matching optional fields of GRE

[Sean Zhang (Networking SW)]

Hi Thomas,

> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Thursday, February 17, 2022 4:34 PM
> To: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; Sean Zhang (Networking SW)
> <xiazhang@nvidia.com>
> Cc: dev@dpdk.org
> Subject: Re: [PATCH] net/mlx5: support matching optional fields of GRE
> 
> External email: Use caution opening links or attachments
> 
> 
> 17/02/2022 07:27, Sean Zhang:
> > This patch adds matching on the optional fields
> > (checksum/key/sequence) of GRE header. The matching on checksum and
> > sequence fields requests support from rdma-core with the capability of
> misc5 and tunnel_header 0-3.
> >
> > For patterns without checksum and sequence specified, keep using misc
> > for matching as before, but for patterns with checksum or sequence,
> > validate capability first and then use misc5 for the matching.
> >
> > Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> > Acked-by: Slava Ovsiienko <viacheslavo@nvidia.com>
> >
> > ---
> > v3 - some code style change
> > v2 - replace default mask with nic mask
> > ---
> >  doc/guides/nics/mlx5.rst             |  10 +++
> >  drivers/common/mlx5/mlx5_devx_cmds.c |   3 +
> >  drivers/net/mlx5/linux/mlx5_os.c     |   2 +
> >  drivers/net/mlx5/mlx5.h              |   1 +
> >  drivers/net/mlx5/mlx5_flow.c         | 101
> +++++++++++++++++++++++++++++
> >  drivers/net/mlx5/mlx5_flow.h         |   6 ++
> >  drivers/net/mlx5/mlx5_flow_dv.c      | 121
> +++++++++++++++++++++++++++++++++++
> >  7 files changed, 244 insertions(+)
> 
> Should we add a line in the release notes?
> 

This patch is v3 of the forth patch of patch set: https://patches.dpdk.org/project/dpdk/cover/20220211014530.77711-1-xiazhang@nvidia.com/
The release notes changed in the second patch of the patch set and applied in v2.

--- a/doc/guides/rel_notes/release_22_03.rst
+++ b/doc/guides/rel_notes/release_22_03.rst
@@ -87,6 +87,11 @@  New Features
 
   The new API ``rte_event_eth_rx_adapter_event_port_get()`` was added.
 
+* **Added rte_flow support for matching GRE optional fields.**
+
+  * Added ``gre_option`` item in rte_flow to support checksum/key/sequence
+    matching in GRE packets.
+
 * **Updated testpmd.**

Sorry the subject-prefix missing v3 information.

Thanks,
Sean

Re: [PATCH] net/mlx5: support matching optional fields of GRE

[Thomas Monjalon]

21/02/2022 04:00, Sean Zhang (Networking SW):
> Hi Thomas,
> 
> > -----Original Message-----
> > From: Thomas Monjalon <thomas@monjalon.net>
> > Sent: Thursday, February 17, 2022 4:34 PM
> > To: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> > <viacheslavo@nvidia.com>; Sean Zhang (Networking SW)
> > <xiazhang@nvidia.com>
> > Cc: dev@dpdk.org
> > Subject: Re: [PATCH] net/mlx5: support matching optional fields of GRE
> > 
> > External email: Use caution opening links or attachments
> > 
> > 
> > 17/02/2022 07:27, Sean Zhang:
> > > This patch adds matching on the optional fields
> > > (checksum/key/sequence) of GRE header. The matching on checksum and
> > > sequence fields requests support from rdma-core with the capability of
> > misc5 and tunnel_header 0-3.
> > >
> > > For patterns without checksum and sequence specified, keep using misc
> > > for matching as before, but for patterns with checksum or sequence,
> > > validate capability first and then use misc5 for the matching.
> > >
> > > Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> > > Acked-by: Slava Ovsiienko <viacheslavo@nvidia.com>
> > >
> > > ---
> > > v3 - some code style change
> > > v2 - replace default mask with nic mask
> > > ---
> > >  doc/guides/nics/mlx5.rst             |  10 +++
> > >  drivers/common/mlx5/mlx5_devx_cmds.c |   3 +
> > >  drivers/net/mlx5/linux/mlx5_os.c     |   2 +
> > >  drivers/net/mlx5/mlx5.h              |   1 +
> > >  drivers/net/mlx5/mlx5_flow.c         | 101
> > +++++++++++++++++++++++++++++
> > >  drivers/net/mlx5/mlx5_flow.h         |   6 ++
> > >  drivers/net/mlx5/mlx5_flow_dv.c      | 121
> > +++++++++++++++++++++++++++++++++++
> > >  7 files changed, 244 insertions(+)
> > 
> > Should we add a line in the release notes?
> > 
> 
> This patch is v3 of the forth patch of patch set: https://patches.dpdk.org/project/dpdk/cover/20220211014530.77711-1-xiazhang@nvidia.com/
> The release notes changed in the second patch of the patch set and applied in v2.
> 
> --- a/doc/guides/rel_notes/release_22_03.rst
> +++ b/doc/guides/rel_notes/release_22_03.rst
> @@ -87,6 +87,11 @@  New Features
>  
>    The new API ``rte_event_eth_rx_adapter_event_port_get()`` was added.
>  
> +* **Added rte_flow support for matching GRE optional fields.**
> +
> +  * Added ``gre_option`` item in rte_flow to support checksum/key/sequence
> +    matching in GRE packets.
> +

OK but it is missing a line for mlx5 features.
I'm adding it while merging.

RE: [PATCH] net/mlx5: support matching optional fields of GRE

[Sean Zhang (Networking SW)]

Thanks Thomas.

> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Friday, February 25, 2022 11:32 PM
> To: Sean Zhang (Networking SW) <xiazhang@nvidia.com>
> Cc: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; dev@dpdk.org; Asaf Penso <asafp@nvidia.com>
> Subject: Re: [PATCH] net/mlx5: support matching optional fields of GRE
> 
> External email: Use caution opening links or attachments
> 
> 
> 21/02/2022 04:00, Sean Zhang (Networking SW):
> > Hi Thomas,
> >
> > > -----Original Message-----
> > > From: Thomas Monjalon <thomas@monjalon.net>
> > > Sent: Thursday, February 17, 2022 4:34 PM
> > > To: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> > > <viacheslavo@nvidia.com>; Sean Zhang (Networking SW)
> > > <xiazhang@nvidia.com>
> > > Cc: dev@dpdk.org
> > > Subject: Re: [PATCH] net/mlx5: support matching optional fields of
> > > GRE
> > >
> > > External email: Use caution opening links or attachments
> > >
> > >
> > > 17/02/2022 07:27, Sean Zhang:
> > > > This patch adds matching on the optional fields
> > > > (checksum/key/sequence) of GRE header. The matching on checksum
> > > > and sequence fields requests support from rdma-core with the
> > > > capability of
> > > misc5 and tunnel_header 0-3.
> > > >
> > > > For patterns without checksum and sequence specified, keep using
> > > > misc for matching as before, but for patterns with checksum or
> > > > sequence, validate capability first and then use misc5 for the matching.
> > > >
> > > > Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> > > > Acked-by: Slava Ovsiienko <viacheslavo@nvidia.com>
> > > >
> > > > ---
> > > > v3 - some code style change
> > > > v2 - replace default mask with nic mask
> > > > ---
> > > >  doc/guides/nics/mlx5.rst             |  10 +++
> > > >  drivers/common/mlx5/mlx5_devx_cmds.c |   3 +
> > > >  drivers/net/mlx5/linux/mlx5_os.c     |   2 +
> > > >  drivers/net/mlx5/mlx5.h              |   1 +
> > > >  drivers/net/mlx5/mlx5_flow.c         | 101
> > > +++++++++++++++++++++++++++++
> > > >  drivers/net/mlx5/mlx5_flow.h         |   6 ++
> > > >  drivers/net/mlx5/mlx5_flow_dv.c      | 121
> > > +++++++++++++++++++++++++++++++++++
> > > >  7 files changed, 244 insertions(+)
> > >
> > > Should we add a line in the release notes?
> > >
> >
> > This patch is v3 of the forth patch of patch set:
> > https://patches.dpdk.org/project/dpdk/cover/20220211014530.77711-1-xia
> > zhang@nvidia.com/ The release notes changed in the second patch of the
> > patch set and applied in v2.
> >
> > --- a/doc/guides/rel_notes/release_22_03.rst
> > +++ b/doc/guides/rel_notes/release_22_03.rst
> > @@ -87,6 +87,11 @@  New Features
> >
> >    The new API ``rte_event_eth_rx_adapter_event_port_get()`` was added.
> >
> > +* **Added rte_flow support for matching GRE optional fields.**
> > +
> > +  * Added ``gre_option`` item in rte_flow to support
> checksum/key/sequence
> > +    matching in GRE packets.
> > +
> 
> OK but it is missing a line for mlx5 features.
> I'm adding it while merging.
> 
> 

RE: [PATCH] net/mlx5: support matching optional fields of GRE

[Raslan Darawsheh]

Hi Sean,

Can you kindly rebase this patch on top of the latest next-net-mlx/main? 
And send a new version?

Kindest regards,
Raslan Darawsheh

> -----Original Message-----
> From: Sean Zhang <xiazhang@nvidia.com>
> Sent: Thursday, February 17, 2022 8:27 AM
> To: NBU-Contact-Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>;
> Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>
> Cc: dev@dpdk.org
> Subject: [PATCH] net/mlx5: support matching optional fields of GRE
> 
> This patch adds matching on the optional fields (checksum/key/sequence) of
> GRE header. The matching on checksum and sequence fields requests
> support from rdma-core with the capability of misc5 and tunnel_header 0-3.
> 
> For patterns without checksum and sequence specified, keep using misc for
> matching as before, but for patterns with checksum or sequence, validate
> capability first and then use misc5 for the matching.
> 
> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> Acked-by: Slava Ovsiienko <viacheslavo@nvidia.com>
> 
> ---
> v3 - some code style change
> v2 - replace default mask with nic mask
> ---
>  doc/guides/nics/mlx5.rst             |  10 +++
>  drivers/common/mlx5/mlx5_devx_cmds.c |   3 +
>  drivers/net/mlx5/linux/mlx5_os.c     |   2 +
>  drivers/net/mlx5/mlx5.h              |   1 +
>  drivers/net/mlx5/mlx5_flow.c         | 101
> +++++++++++++++++++++++++++++
>  drivers/net/mlx5/mlx5_flow.h         |   6 ++
>  drivers/net/mlx5/mlx5_flow_dv.c      | 121
> +++++++++++++++++++++++++++++++++++
>  7 files changed, 244 insertions(+)
> 
> diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index
> c3cc0c0..4611f0f 100644
> --- a/doc/guides/nics/mlx5.rst
> +++ b/doc/guides/nics/mlx5.rst
> @@ -511,6 +511,16 @@ Limitations
>      from the reference "Clock Queue" completions,
>      the scheduled send timestamps should not be specified with non-zero
> MSB.
> 
> +- Match on GRE header supports the following fields:
> +
> +  - c_rsvd0_v: C bit, K bit, S bit
> +  - protocol type
> +  - Checksum
> +  - Key
> +  - Sequence
> +
> +  Matching on checksum and sequence needs OFED 5.6+.
> +
>  Statistics
>  ----------
> 
> diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c
> b/drivers/common/mlx5/mlx5_devx_cmds.c
> index 2e807a0..77436ed 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.c
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.c
> @@ -1043,6 +1043,9 @@ struct mlx5_devx_obj *
>  	attr->flow.tunnel_header_0_1 = MLX5_GET
>  		(flow_table_nic_cap, hcattr,
>  		 ft_field_support_2_nic_receive.tunnel_header_0_1);
> +	attr->flow.tunnel_header_2_3 = MLX5_GET
> +		(flow_table_nic_cap, hcattr,
> +		 ft_field_support_2_nic_receive.tunnel_header_2_3);
>  	attr->pkt_integrity_match =
> mlx5_devx_query_pkt_integrity_match(hcattr);
>  	attr->inner_ipv4_ihl = MLX5_GET
>  		(flow_table_nic_cap, hcattr,
> diff --git a/drivers/net/mlx5/linux/mlx5_os.c
> b/drivers/net/mlx5/linux/mlx5_os.c
> index bbe05bb..b8a9dea 100644
> --- a/drivers/net/mlx5/linux/mlx5_os.c
> +++ b/drivers/net/mlx5/linux/mlx5_os.c
> @@ -1383,6 +1383,8 @@
>  		}
>  		if (config->hca_attr.flow.tunnel_header_0_1)
>  			sh->tunnel_header_0_1 = 1;
> +		if (config->hca_attr.flow.tunnel_header_2_3)
> +			sh->tunnel_header_2_3 = 1;
>  #endif
>  #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
>  		if (config->hca_attr.flow_hit_aso &&
> diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index
> 737ad68..5faca7a 100644
> --- a/drivers/net/mlx5/mlx5.h
> +++ b/drivers/net/mlx5/mlx5.h
> @@ -1154,6 +1154,7 @@ struct mlx5_dev_ctx_shared {
>  	uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
>  	uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
>  	uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported.
> */
> +	uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported.
> */
>  	uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
>  	uint32_t reclaim_mode:1; /* Reclaim memory. */
>  	uint32_t dr_drop_action_en:1; /* Use DR drop action. */ diff --git
> a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index
> 179cc3b..fc1249d 100644
> --- a/drivers/net/mlx5/mlx5_flow.c
> +++ b/drivers/net/mlx5/mlx5_flow.c
> @@ -2815,6 +2815,107 @@ struct mlx5_flow_tunnel_info {  }
> 
>  /**
> + * Validate GRE optional item.
> + *
> + * @param[in] dev
> + *   Pointer to the Ethernet device structure.
> + * @param[in] item
> + *   Item specification.
> + * @param[in] item_flags
> + *   Bit flags to mark detected items.
> + * @param[in] attr
> + *   Flow rule attributes.
> + * @param[in] gre_item
> + *   Pointer to gre_item
> + * @param[out] error
> + *   Pointer to error structure.
> + *
> + * @return
> + *   0 on success, a negative errno value otherwise and rte_errno is set.
> + */
> +int
> +mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
> +				   const struct rte_flow_item *item,
> +				   uint64_t item_flags,
> +				   const struct rte_flow_attr *attr,
> +				   const struct rte_flow_item *gre_item,
> +				   struct rte_flow_error *error)
> +{
> +	const struct rte_flow_item_gre *gre_spec = gre_item->spec;
> +	const struct rte_flow_item_gre *gre_mask = gre_item->mask;
> +	const struct rte_flow_item_gre_opt *spec = item->spec;
> +	const struct rte_flow_item_gre_opt *mask = item->mask;
> +	struct mlx5_priv *priv = dev->data->dev_private;
> +	int ret = 0;
> +	struct rte_flow_item_gre_opt nic_mask = {
> +		.checksum_rsvd = {
> +			.checksum = RTE_BE16(UINT16_MAX),
> +			.reserved1 = 0x0,
> +		},
> +		.key = {
> +			.key = RTE_BE32(UINT32_MAX),
> +		},
> +		.sequence = {
> +			.sequence = RTE_BE32(UINT32_MAX),
> +		},
> +	};
> +
> +	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
> +		return rte_flow_error_set(error, ENOTSUP,
> +					  RTE_FLOW_ERROR_TYPE_ITEM,
> item,
> +					  "No preceding GRE header");
> +	if (item_flags & MLX5_FLOW_LAYER_INNER)
> +		return rte_flow_error_set(error, ENOTSUP,
> +					  RTE_FLOW_ERROR_TYPE_ITEM,
> item,
> +					  "GRE option following a wrong
> item");
> +	if (!spec || !mask)
> +		return rte_flow_error_set(error, EINVAL,
> +					  RTE_FLOW_ERROR_TYPE_ITEM,
> item,
> +					  "At least one field
> gre_option(checksum/key/sequence) must be specified");
> +	if (!gre_mask)
> +		gre_mask = &rte_flow_item_gre_mask;
> +	if (mask->checksum_rsvd.checksum)
> +		if (gre_spec && (gre_mask->c_rsvd0_ver &
> RTE_BE16(0x8000)) &&
> +				 !(gre_spec->c_rsvd0_ver &
> RTE_BE16(0x8000)))
> +			return rte_flow_error_set(error, EINVAL,
> +
> RTE_FLOW_ERROR_TYPE_ITEM,
> +						  item,
> +						  "Checksum bit must be on");
> +	if (mask->key.key)
> +		if (gre_spec && (gre_mask->c_rsvd0_ver &
> RTE_BE16(0x2000)) &&
> +				 !(gre_spec->c_rsvd0_ver &
> RTE_BE16(0x2000)))
> +			return rte_flow_error_set(error, EINVAL,
> +
> RTE_FLOW_ERROR_TYPE_ITEM,
> +						  item, "Key bit must be on");
> +	if (mask->sequence.sequence)
> +		if (gre_spec && (gre_mask->c_rsvd0_ver &
> RTE_BE16(0x1000)) &&
> +				 !(gre_spec->c_rsvd0_ver &
> RTE_BE16(0x1000)))
> +			return rte_flow_error_set(error, EINVAL,
> +
> RTE_FLOW_ERROR_TYPE_ITEM,
> +						  item,
> +						  "Sequence bit must be on");
> +	if (mask->checksum_rsvd.checksum || mask->sequence.sequence)
> {
> +		if (priv->sh->steering_format_version ==
> +		    MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 ||
> +		    ((attr->group || attr->transfer) &&
> +		     !priv->sh->misc5_cap) ||
> +		    (!(priv->sh->tunnel_header_0_1 &&
> +		       priv->sh->tunnel_header_2_3) &&
> +		    !attr->group && !attr->transfer))
> +			return rte_flow_error_set(error, EINVAL,
> +
> RTE_FLOW_ERROR_TYPE_ITEM,
> +						  item,
> +						  "Checksum/Sequence not
> supported");
> +	}
> +	ret = mlx5_flow_item_acceptable
> +		(item, (const uint8_t *)mask,
> +		 (const uint8_t *)&nic_mask,
> +		 sizeof(struct rte_flow_item_gre_opt),
> +		 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
> +	return ret;
> +}
> +
> +/**
>   * Validate GRE item.
>   *
>   * @param[in] item
> diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
> index 7fec79a..667b241 100644
> --- a/drivers/net/mlx5/mlx5_flow.h
> +++ b/drivers/net/mlx5/mlx5_flow.h
> @@ -1537,6 +1537,12 @@ int mlx5_flow_validate_item_gre_key(const
> struct rte_flow_item *item,
>  				    uint64_t item_flags,
>  				    const struct rte_flow_item *gre_item,
>  				    struct rte_flow_error *error);
> +int mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
> +				const struct rte_flow_item *item,
> +				uint64_t item_flags,
> +				const struct rte_flow_attr *attr,
> +				const struct rte_flow_item *gre_item,
> +				struct rte_flow_error *error);
>  int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
>  				 uint64_t item_flags,
>  				 uint64_t last_item,
> diff --git a/drivers/net/mlx5/mlx5_flow_dv.c
> b/drivers/net/mlx5/mlx5_flow_dv.c index ef9c66e..ba61a33 100644
> --- a/drivers/net/mlx5/mlx5_flow_dv.c
> +++ b/drivers/net/mlx5/mlx5_flow_dv.c
> @@ -7101,6 +7101,13 @@ struct mlx5_list_entry *
>  			gre_item = items;
>  			last_item = MLX5_FLOW_LAYER_GRE;
>  			break;
> +		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
> +			ret = mlx5_flow_validate_item_gre_option(dev,
> items, item_flags,
> +							  attr, gre_item,
> error);
> +			if (ret < 0)
> +				return ret;
> +			last_item = MLX5_FLOW_LAYER_GRE;
> +			break;
>  		case RTE_FLOW_ITEM_TYPE_NVGRE:
>  			ret = mlx5_flow_validate_item_nvgre(items,
> item_flags,
>  							    next_protocol,
> @@ -8822,6 +8829,110 @@ struct mlx5_list_entry *  }
> 
>  /**
> + * Add GRE optional items to matcher and to the value.
> + *
> + * @param[in, out] matcher
> + *   Flow matcher.
> + * @param[in, out] key
> + *   Flow matcher value.
> + * @param[in] item
> + *   Flow pattern to translate.
> + * @param[in] gre_item
> + *   Pointer to gre_item.
> + * @param[in] pattern_flags
> + *   Accumulated pattern flags.
> + */
> +static void
> +flow_dv_translate_item_gre_option(void *matcher, void *key,
> +				  const struct rte_flow_item *item,
> +				  const struct rte_flow_item *gre_item,
> +				  uint64_t pattern_flags)
> +{
> +	const struct rte_flow_item_gre_opt *option_m = item->mask;
> +	const struct rte_flow_item_gre_opt *option_v = item->spec;
> +	const struct rte_flow_item_gre *gre_m = gre_item->mask;
> +	const struct rte_flow_item_gre *gre_v = gre_item->spec;
> +	static const struct rte_flow_item_gre empty_gre = {0};
> +	struct rte_flow_item gre_key_item;
> +	uint16_t c_rsvd0_ver_m, c_rsvd0_ver_v;
> +	uint16_t protocol_m, protocol_v;
> +	void *misc5_m;
> +	void *misc5_v;
> +
> +	/*
> +	 * If only match key field, keep using misc for matching.
> +	 * If need to match checksum or sequence, using misc5 and do
> +	 * not need using misc.
> +	 */
> +	if (!(option_m->sequence.sequence ||
> +	      option_m->checksum_rsvd.checksum)) {
> +		flow_dv_translate_item_gre(matcher, key, gre_item,
> +					   pattern_flags);
> +		gre_key_item.spec = &option_v->key.key;
> +		gre_key_item.mask = &option_m->key.key;
> +		flow_dv_translate_item_gre_key(matcher, key,
> &gre_key_item);
> +		return;
> +	}
> +	if (!gre_v) {
> +		gre_v = &empty_gre;
> +		gre_m = &empty_gre;
> +	} else {
> +		if (!gre_m)
> +			gre_m = &rte_flow_item_gre_mask;
> +	}
> +	protocol_v = gre_v->protocol;
> +	protocol_m = gre_m->protocol;
> +	if (!protocol_m) {
> +		/* Force next protocol to prevent matchers duplication */
> +		uint16_t ether_type =
> +			mlx5_translate_tunnel_etypes(pattern_flags);
> +		if (ether_type) {
> +			protocol_v = rte_be_to_cpu_16(ether_type);
> +			protocol_m = UINT16_MAX;
> +		}
> +	}
> +	c_rsvd0_ver_v = gre_v->c_rsvd0_ver;
> +	c_rsvd0_ver_m = gre_m->c_rsvd0_ver;
> +	if (option_m->sequence.sequence) {
> +		c_rsvd0_ver_v |= RTE_BE16(0x1000);
> +		c_rsvd0_ver_m |= RTE_BE16(0x1000);
> +	}
> +	if (option_m->key.key) {
> +		c_rsvd0_ver_v |= RTE_BE16(0x2000);
> +		c_rsvd0_ver_m |= RTE_BE16(0x2000);
> +	}
> +	if (option_m->checksum_rsvd.checksum) {
> +		c_rsvd0_ver_v |= RTE_BE16(0x8000);
> +		c_rsvd0_ver_m |= RTE_BE16(0x8000);
> +	}
> +	/*
> +	 * Hardware parses GRE optional field into the fixed location,
> +	 * do not need to adjust the tunnel dword indices.
> +	 */
> +	misc5_v = MLX5_ADDR_OF(fte_match_param, key,
> misc_parameters_5);
> +	misc5_m = MLX5_ADDR_OF(fte_match_param, matcher,
> misc_parameters_5);
> +	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_0,
> +		 rte_be_to_cpu_32((c_rsvd0_ver_v | protocol_v << 16) &
> +				  (c_rsvd0_ver_m | protocol_m << 16)));
> +	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_0,
> +		 rte_be_to_cpu_32(c_rsvd0_ver_m | protocol_m << 16));
> +	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_1,
> +		 rte_be_to_cpu_32(option_v->checksum_rsvd.checksum &
> +				  option_m->checksum_rsvd.checksum));
> +	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_1,
> +		 rte_be_to_cpu_32(option_m->checksum_rsvd.checksum));
> +	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_2,
> +		 rte_be_to_cpu_32(option_v->key.key & option_m-
> >key.key));
> +	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_2,
> +		 rte_be_to_cpu_32(option_m->key.key));
> +	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_3,
> +		 rte_be_to_cpu_32(option_v->sequence.sequence &
> +				  option_m->sequence.sequence));
> +	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_3,
> +		 rte_be_to_cpu_32(option_m->sequence.sequence));
> +}
> +
> +/**
>   * Add NVGRE item to matcher and to the value.
>   *
>   * @param[in, out] matcher
> @@ -12697,6 +12808,7 @@ struct mlx5_list_entry *
>  	};
>  	const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
>  	const struct rte_flow_item *tunnel_item = NULL;
> +	const struct rte_flow_item *gre_item = NULL;
> 
>  	if (!wks)
>  		return rte_flow_error_set(error, ENOMEM, @@ -13469,12
> +13581,18 @@ struct mlx5_list_entry *
>  			matcher.priority =
> MLX5_TUNNEL_PRIO_GET(rss_desc);
>  			last_item = MLX5_FLOW_LAYER_GRE;
>  			tunnel_item = items;
> +			gre_item = items;
>  			break;
>  		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
>  			flow_dv_translate_item_gre_key(match_mask,
>  						       match_value, items);
>  			last_item = MLX5_FLOW_LAYER_GRE_KEY;
>  			break;
> +		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
> +			matcher.priority =
> MLX5_TUNNEL_PRIO_GET(rss_desc);
> +			last_item = MLX5_FLOW_LAYER_GRE;
> +			tunnel_item = items;
> +			break;
>  		case RTE_FLOW_ITEM_TYPE_NVGRE:
>  			matcher.priority =
> MLX5_TUNNEL_PRIO_GET(rss_desc);
>  			last_item = MLX5_FLOW_LAYER_GRE;
> @@ -13634,6 +13752,9 @@ struct mlx5_list_entry *
>  		else if (tunnel_item->type ==
> RTE_FLOW_ITEM_TYPE_NVGRE)
>  			flow_dv_translate_item_nvgre(match_mask,
> match_value,
>  						     tunnel_item, item_flags);
> +		else if (tunnel_item->type ==
> RTE_FLOW_ITEM_TYPE_GRE_OPTION)
> +			flow_dv_translate_item_gre_option(match_mask,
> match_value,
> +					tunnel_item, gre_item, item_flags);
>  		else
>  			MLX5_ASSERT(false);
>  	}
> --
> 1.8.3.1

RE: [PATCH] net/mlx5: support matching optional fields of GRE

[Sean Zhang (Networking SW)]

Hi Raslan,

Rebased and new version sent out.

Thanks,
Sean

> -----Original Message-----
> From: Raslan Darawsheh <rasland@nvidia.com>
> Sent: Thursday, February 24, 2022 9:18 PM
> To: Sean Zhang (Networking SW) <xiazhang@nvidia.com>; NBU-Contact-
> Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>; Matan Azrad
> <matan@nvidia.com>; Slava Ovsiienko <viacheslavo@nvidia.com>
> Cc: dev@dpdk.org
> Subject: RE: [PATCH] net/mlx5: support matching optional fields of GRE
> 
> Hi Sean,
> 
> Can you kindly rebase this patch on top of the latest next-net-mlx/main?
> And send a new version?
> 
> Kindest regards,
> Raslan Darawsheh
> 
> > -----Original Message-----
> > From: Sean Zhang <xiazhang@nvidia.com>
> > Sent: Thursday, February 17, 2022 8:27 AM
> > To: NBU-Contact-Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>;
> > Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> > <viacheslavo@nvidia.com>
> > Cc: dev@dpdk.org
> > Subject: [PATCH] net/mlx5: support matching optional fields of GRE
> >
> > This patch adds matching on the optional fields
> > (checksum/key/sequence) of GRE header. The matching on checksum and
> > sequence fields requests support from rdma-core with the capability of misc5
> and tunnel_header 0-3.
> >
> > For patterns without checksum and sequence specified, keep using misc
> > for matching as before, but for patterns with checksum or sequence,
> > validate capability first and then use misc5 for the matching.
> >
> > Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> > Acked-by: Slava Ovsiienko <viacheslavo@nvidia.com>
> >
> > ---
> > v3 - some code style change
> > v2 - replace default mask with nic mask
> > ---
> >  doc/guides/nics/mlx5.rst             |  10 +++
> >  drivers/common/mlx5/mlx5_devx_cmds.c |   3 +
> >  drivers/net/mlx5/linux/mlx5_os.c     |   2 +
> >  drivers/net/mlx5/mlx5.h              |   1 +
> >  drivers/net/mlx5/mlx5_flow.c         | 101
> > +++++++++++++++++++++++++++++
> >  drivers/net/mlx5/mlx5_flow.h         |   6 ++
> >  drivers/net/mlx5/mlx5_flow_dv.c      | 121
> > +++++++++++++++++++++++++++++++++++
> >  7 files changed, 244 insertions(+)
> >
> > diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index
> > c3cc0c0..4611f0f 100644
> > --- a/doc/guides/nics/mlx5.rst
> > +++ b/doc/guides/nics/mlx5.rst
> > @@ -511,6 +511,16 @@ Limitations
> >      from the reference "Clock Queue" completions,
> >      the scheduled send timestamps should not be specified with
> > non-zero MSB.
> >
> > +- Match on GRE header supports the following fields:
> > +
> > +  - c_rsvd0_v: C bit, K bit, S bit
> > +  - protocol type
> > +  - Checksum
> > +  - Key
> > +  - Sequence
> > +
> > +  Matching on checksum and sequence needs OFED 5.6+.
> > +
> >  Statistics
> >  ----------
> >
> > diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c
> > b/drivers/common/mlx5/mlx5_devx_cmds.c
> > index 2e807a0..77436ed 100644
> > --- a/drivers/common/mlx5/mlx5_devx_cmds.c
> > +++ b/drivers/common/mlx5/mlx5_devx_cmds.c
> > @@ -1043,6 +1043,9 @@ struct mlx5_devx_obj *
> >  	attr->flow.tunnel_header_0_1 = MLX5_GET
> >  		(flow_table_nic_cap, hcattr,
> >  		 ft_field_support_2_nic_receive.tunnel_header_0_1);
> > +	attr->flow.tunnel_header_2_3 = MLX5_GET
> > +		(flow_table_nic_cap, hcattr,
> > +		 ft_field_support_2_nic_receive.tunnel_header_2_3);
> >  	attr->pkt_integrity_match =
> > mlx5_devx_query_pkt_integrity_match(hcattr);
> >  	attr->inner_ipv4_ihl = MLX5_GET
> >  		(flow_table_nic_cap, hcattr,
> > diff --git a/drivers/net/mlx5/linux/mlx5_os.c
> > b/drivers/net/mlx5/linux/mlx5_os.c
> > index bbe05bb..b8a9dea 100644
> > --- a/drivers/net/mlx5/linux/mlx5_os.c
> > +++ b/drivers/net/mlx5/linux/mlx5_os.c
> > @@ -1383,6 +1383,8 @@
> >  		}
> >  		if (config->hca_attr.flow.tunnel_header_0_1)
> >  			sh->tunnel_header_0_1 = 1;
> > +		if (config->hca_attr.flow.tunnel_header_2_3)
> > +			sh->tunnel_header_2_3 = 1;
> >  #endif
> >  #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
> >  		if (config->hca_attr.flow_hit_aso && diff --git
> > a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index
> > 737ad68..5faca7a 100644
> > --- a/drivers/net/mlx5/mlx5.h
> > +++ b/drivers/net/mlx5/mlx5.h
> > @@ -1154,6 +1154,7 @@ struct mlx5_dev_ctx_shared {
> >  	uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
> >  	uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
> >  	uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported.
> > */
> > +	uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported.
> > */
> >  	uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
> >  	uint32_t reclaim_mode:1; /* Reclaim memory. */
> >  	uint32_t dr_drop_action_en:1; /* Use DR drop action. */ diff --git
> > a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index
> > 179cc3b..fc1249d 100644
> > --- a/drivers/net/mlx5/mlx5_flow.c
> > +++ b/drivers/net/mlx5/mlx5_flow.c
> > @@ -2815,6 +2815,107 @@ struct mlx5_flow_tunnel_info {  }
> >
> >  /**
> > + * Validate GRE optional item.
> > + *
> > + * @param[in] dev
> > + *   Pointer to the Ethernet device structure.
> > + * @param[in] item
> > + *   Item specification.
> > + * @param[in] item_flags
> > + *   Bit flags to mark detected items.
> > + * @param[in] attr
> > + *   Flow rule attributes.
> > + * @param[in] gre_item
> > + *   Pointer to gre_item
> > + * @param[out] error
> > + *   Pointer to error structure.
> > + *
> > + * @return
> > + *   0 on success, a negative errno value otherwise and rte_errno is set.
> > + */
> > +int
> > +mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
> > +				   const struct rte_flow_item *item,
> > +				   uint64_t item_flags,
> > +				   const struct rte_flow_attr *attr,
> > +				   const struct rte_flow_item *gre_item,
> > +				   struct rte_flow_error *error)
> > +{
> > +	const struct rte_flow_item_gre *gre_spec = gre_item->spec;
> > +	const struct rte_flow_item_gre *gre_mask = gre_item->mask;
> > +	const struct rte_flow_item_gre_opt *spec = item->spec;
> > +	const struct rte_flow_item_gre_opt *mask = item->mask;
> > +	struct mlx5_priv *priv = dev->data->dev_private;
> > +	int ret = 0;
> > +	struct rte_flow_item_gre_opt nic_mask = {
> > +		.checksum_rsvd = {
> > +			.checksum = RTE_BE16(UINT16_MAX),
> > +			.reserved1 = 0x0,
> > +		},
> > +		.key = {
> > +			.key = RTE_BE32(UINT32_MAX),
> > +		},
> > +		.sequence = {
> > +			.sequence = RTE_BE32(UINT32_MAX),
> > +		},
> > +	};
> > +
> > +	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
> > +		return rte_flow_error_set(error, ENOTSUP,
> > +					  RTE_FLOW_ERROR_TYPE_ITEM,
> > item,
> > +					  "No preceding GRE header");
> > +	if (item_flags & MLX5_FLOW_LAYER_INNER)
> > +		return rte_flow_error_set(error, ENOTSUP,
> > +					  RTE_FLOW_ERROR_TYPE_ITEM,
> > item,
> > +					  "GRE option following a wrong
> > item");
> > +	if (!spec || !mask)
> > +		return rte_flow_error_set(error, EINVAL,
> > +					  RTE_FLOW_ERROR_TYPE_ITEM,
> > item,
> > +					  "At least one field
> > gre_option(checksum/key/sequence) must be specified");
> > +	if (!gre_mask)
> > +		gre_mask = &rte_flow_item_gre_mask;
> > +	if (mask->checksum_rsvd.checksum)
> > +		if (gre_spec && (gre_mask->c_rsvd0_ver &
> > RTE_BE16(0x8000)) &&
> > +				 !(gre_spec->c_rsvd0_ver &
> > RTE_BE16(0x8000)))
> > +			return rte_flow_error_set(error, EINVAL,
> > +
> > RTE_FLOW_ERROR_TYPE_ITEM,
> > +						  item,
> > +						  "Checksum bit must be on");
> > +	if (mask->key.key)
> > +		if (gre_spec && (gre_mask->c_rsvd0_ver &
> > RTE_BE16(0x2000)) &&
> > +				 !(gre_spec->c_rsvd0_ver &
> > RTE_BE16(0x2000)))
> > +			return rte_flow_error_set(error, EINVAL,
> > +
> > RTE_FLOW_ERROR_TYPE_ITEM,
> > +						  item, "Key bit must be on");
> > +	if (mask->sequence.sequence)
> > +		if (gre_spec && (gre_mask->c_rsvd0_ver &
> > RTE_BE16(0x1000)) &&
> > +				 !(gre_spec->c_rsvd0_ver &
> > RTE_BE16(0x1000)))
> > +			return rte_flow_error_set(error, EINVAL,
> > +
> > RTE_FLOW_ERROR_TYPE_ITEM,
> > +						  item,
> > +						  "Sequence bit must be on");
> > +	if (mask->checksum_rsvd.checksum || mask->sequence.sequence)
> > {
> > +		if (priv->sh->steering_format_version ==
> > +		    MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 ||
> > +		    ((attr->group || attr->transfer) &&
> > +		     !priv->sh->misc5_cap) ||
> > +		    (!(priv->sh->tunnel_header_0_1 &&
> > +		       priv->sh->tunnel_header_2_3) &&
> > +		    !attr->group && !attr->transfer))
> > +			return rte_flow_error_set(error, EINVAL,
> > +
> > RTE_FLOW_ERROR_TYPE_ITEM,
> > +						  item,
> > +						  "Checksum/Sequence not
> > supported");
> > +	}
> > +	ret = mlx5_flow_item_acceptable
> > +		(item, (const uint8_t *)mask,
> > +		 (const uint8_t *)&nic_mask,
> > +		 sizeof(struct rte_flow_item_gre_opt),
> > +		 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
> > +	return ret;
> > +}
> > +
> > +/**
> >   * Validate GRE item.
> >   *
> >   * @param[in] item
> > diff --git a/drivers/net/mlx5/mlx5_flow.h
> > b/drivers/net/mlx5/mlx5_flow.h index 7fec79a..667b241 100644
> > --- a/drivers/net/mlx5/mlx5_flow.h
> > +++ b/drivers/net/mlx5/mlx5_flow.h
> > @@ -1537,6 +1537,12 @@ int mlx5_flow_validate_item_gre_key(const
> > struct rte_flow_item *item,
> >  				    uint64_t item_flags,
> >  				    const struct rte_flow_item *gre_item,
> >  				    struct rte_flow_error *error);
> > +int mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
> > +				const struct rte_flow_item *item,
> > +				uint64_t item_flags,
> > +				const struct rte_flow_attr *attr,
> > +				const struct rte_flow_item *gre_item,
> > +				struct rte_flow_error *error);
> >  int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
> >  				 uint64_t item_flags,
> >  				 uint64_t last_item,
> > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c
> > b/drivers/net/mlx5/mlx5_flow_dv.c index ef9c66e..ba61a33 100644
> > --- a/drivers/net/mlx5/mlx5_flow_dv.c
> > +++ b/drivers/net/mlx5/mlx5_flow_dv.c
> > @@ -7101,6 +7101,13 @@ struct mlx5_list_entry *
> >  			gre_item = items;
> >  			last_item = MLX5_FLOW_LAYER_GRE;
> >  			break;
> > +		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
> > +			ret = mlx5_flow_validate_item_gre_option(dev,
> > items, item_flags,
> > +							  attr, gre_item,
> > error);
> > +			if (ret < 0)
> > +				return ret;
> > +			last_item = MLX5_FLOW_LAYER_GRE;
> > +			break;
> >  		case RTE_FLOW_ITEM_TYPE_NVGRE:
> >  			ret = mlx5_flow_validate_item_nvgre(items,
> > item_flags,
> >  							    next_protocol,
> > @@ -8822,6 +8829,110 @@ struct mlx5_list_entry *  }
> >
> >  /**
> > + * Add GRE optional items to matcher and to the value.
> > + *
> > + * @param[in, out] matcher
> > + *   Flow matcher.
> > + * @param[in, out] key
> > + *   Flow matcher value.
> > + * @param[in] item
> > + *   Flow pattern to translate.
> > + * @param[in] gre_item
> > + *   Pointer to gre_item.
> > + * @param[in] pattern_flags
> > + *   Accumulated pattern flags.
> > + */
> > +static void
> > +flow_dv_translate_item_gre_option(void *matcher, void *key,
> > +				  const struct rte_flow_item *item,
> > +				  const struct rte_flow_item *gre_item,
> > +				  uint64_t pattern_flags)
> > +{
> > +	const struct rte_flow_item_gre_opt *option_m = item->mask;
> > +	const struct rte_flow_item_gre_opt *option_v = item->spec;
> > +	const struct rte_flow_item_gre *gre_m = gre_item->mask;
> > +	const struct rte_flow_item_gre *gre_v = gre_item->spec;
> > +	static const struct rte_flow_item_gre empty_gre = {0};
> > +	struct rte_flow_item gre_key_item;
> > +	uint16_t c_rsvd0_ver_m, c_rsvd0_ver_v;
> > +	uint16_t protocol_m, protocol_v;
> > +	void *misc5_m;
> > +	void *misc5_v;
> > +
> > +	/*
> > +	 * If only match key field, keep using misc for matching.
> > +	 * If need to match checksum or sequence, using misc5 and do
> > +	 * not need using misc.
> > +	 */
> > +	if (!(option_m->sequence.sequence ||
> > +	      option_m->checksum_rsvd.checksum)) {
> > +		flow_dv_translate_item_gre(matcher, key, gre_item,
> > +					   pattern_flags);
> > +		gre_key_item.spec = &option_v->key.key;
> > +		gre_key_item.mask = &option_m->key.key;
> > +		flow_dv_translate_item_gre_key(matcher, key,
> > &gre_key_item);
> > +		return;
> > +	}
> > +	if (!gre_v) {
> > +		gre_v = &empty_gre;
> > +		gre_m = &empty_gre;
> > +	} else {
> > +		if (!gre_m)
> > +			gre_m = &rte_flow_item_gre_mask;
> > +	}
> > +	protocol_v = gre_v->protocol;
> > +	protocol_m = gre_m->protocol;
> > +	if (!protocol_m) {
> > +		/* Force next protocol to prevent matchers duplication */
> > +		uint16_t ether_type =
> > +			mlx5_translate_tunnel_etypes(pattern_flags);
> > +		if (ether_type) {
> > +			protocol_v = rte_be_to_cpu_16(ether_type);
> > +			protocol_m = UINT16_MAX;
> > +		}
> > +	}
> > +	c_rsvd0_ver_v = gre_v->c_rsvd0_ver;
> > +	c_rsvd0_ver_m = gre_m->c_rsvd0_ver;
> > +	if (option_m->sequence.sequence) {
> > +		c_rsvd0_ver_v |= RTE_BE16(0x1000);
> > +		c_rsvd0_ver_m |= RTE_BE16(0x1000);
> > +	}
> > +	if (option_m->key.key) {
> > +		c_rsvd0_ver_v |= RTE_BE16(0x2000);
> > +		c_rsvd0_ver_m |= RTE_BE16(0x2000);
> > +	}
> > +	if (option_m->checksum_rsvd.checksum) {
> > +		c_rsvd0_ver_v |= RTE_BE16(0x8000);
> > +		c_rsvd0_ver_m |= RTE_BE16(0x8000);
> > +	}
> > +	/*
> > +	 * Hardware parses GRE optional field into the fixed location,
> > +	 * do not need to adjust the tunnel dword indices.
> > +	 */
> > +	misc5_v = MLX5_ADDR_OF(fte_match_param, key,
> > misc_parameters_5);
> > +	misc5_m = MLX5_ADDR_OF(fte_match_param, matcher,
> > misc_parameters_5);
> > +	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_0,
> > +		 rte_be_to_cpu_32((c_rsvd0_ver_v | protocol_v << 16) &
> > +				  (c_rsvd0_ver_m | protocol_m << 16)));
> > +	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_0,
> > +		 rte_be_to_cpu_32(c_rsvd0_ver_m | protocol_m << 16));
> > +	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_1,
> > +		 rte_be_to_cpu_32(option_v->checksum_rsvd.checksum &
> > +				  option_m->checksum_rsvd.checksum));
> > +	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_1,
> > +		 rte_be_to_cpu_32(option_m->checksum_rsvd.checksum));
> > +	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_2,
> > +		 rte_be_to_cpu_32(option_v->key.key & option_m-
> > >key.key));
> > +	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_2,
> > +		 rte_be_to_cpu_32(option_m->key.key));
> > +	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_3,
> > +		 rte_be_to_cpu_32(option_v->sequence.sequence &
> > +				  option_m->sequence.sequence));
> > +	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_3,
> > +		 rte_be_to_cpu_32(option_m->sequence.sequence));
> > +}
> > +
> > +/**
> >   * Add NVGRE item to matcher and to the value.
> >   *
> >   * @param[in, out] matcher
> > @@ -12697,6 +12808,7 @@ struct mlx5_list_entry *
> >  	};
> >  	const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
> >  	const struct rte_flow_item *tunnel_item = NULL;
> > +	const struct rte_flow_item *gre_item = NULL;
> >
> >  	if (!wks)
> >  		return rte_flow_error_set(error, ENOMEM, @@ -13469,12
> > +13581,18 @@ struct mlx5_list_entry *
> >  			matcher.priority =
> > MLX5_TUNNEL_PRIO_GET(rss_desc);
> >  			last_item = MLX5_FLOW_LAYER_GRE;
> >  			tunnel_item = items;
> > +			gre_item = items;
> >  			break;
> >  		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
> >  			flow_dv_translate_item_gre_key(match_mask,
> >  						       match_value, items);
> >  			last_item = MLX5_FLOW_LAYER_GRE_KEY;
> >  			break;
> > +		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
> > +			matcher.priority =
> > MLX5_TUNNEL_PRIO_GET(rss_desc);
> > +			last_item = MLX5_FLOW_LAYER_GRE;
> > +			tunnel_item = items;
> > +			break;
> >  		case RTE_FLOW_ITEM_TYPE_NVGRE:
> >  			matcher.priority =
> > MLX5_TUNNEL_PRIO_GET(rss_desc);
> >  			last_item = MLX5_FLOW_LAYER_GRE;
> > @@ -13634,6 +13752,9 @@ struct mlx5_list_entry *
> >  		else if (tunnel_item->type ==
> > RTE_FLOW_ITEM_TYPE_NVGRE)
> >  			flow_dv_translate_item_nvgre(match_mask,
> > match_value,
> >  						     tunnel_item, item_flags);
> > +		else if (tunnel_item->type ==
> > RTE_FLOW_ITEM_TYPE_GRE_OPTION)
> > +			flow_dv_translate_item_gre_option(match_mask,
> > match_value,
> > +					tunnel_item, gre_item, item_flags);
> >  		else
> >  			MLX5_ASSERT(false);
> >  	}
> > --
> > 1.8.3.1

[v4] net/mlx5: support matching optional fields of GRE

[Sean Zhang]

This patch adds matching on the optional fields (checksum/key/sequence)
of GRE header. The matching on checksum and sequence fields requests
support from rdma-core with the capability of misc5 and tunnel_header 0-3.

For patterns without checksum and sequence specified, keep using misc for
matching as before, but for patterns with checksum or sequence, validate
capability first and then use misc5 for the matching.

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

---
v4 - code rebase
v3 - some code style change
v2 - replace default mask with nic mask
---
 doc/guides/nics/mlx5.rst             |  11 +++
 drivers/common/mlx5/mlx5_devx_cmds.c |   3 +
 drivers/net/mlx5/linux/mlx5_os.c     |   2 +
 drivers/net/mlx5/mlx5.h              |   1 +
 drivers/net/mlx5/mlx5_flow.c         | 101 ++++++++++++++++++++++
 drivers/net/mlx5/mlx5_flow.h         |   6 ++
 drivers/net/mlx5/mlx5_flow_dv.c      | 121 +++++++++++++++++++++++++++
 7 files changed, 245 insertions(+)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 7b04e9bac5..e52aa2cb94 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -493,6 +493,17 @@ Limitations
     - Set ``dv_flow_en`` to 2 in order to enable HW steering.
     - Async queue-based ``rte_flow_q`` APIs supported only.
 
+- Match on GRE header supports the following fields:
+
+  - c_rsvd0_v: C bit, K bit, S bit
+  - protocol type
+  - Checksum
+  - Key
+  - Sequence
+
+  Matching on checksum and sequence needs OFED 5.6+.
+
+
 Statistics
 ----------
 
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 9f1419ded8..d02ac2a678 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1044,6 +1044,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
 	attr->flow.tunnel_header_0_1 = MLX5_GET
 		(flow_table_nic_cap, hcattr,
 		 ft_field_support_2_nic_receive.tunnel_header_0_1);
+	attr->flow.tunnel_header_2_3 = MLX5_GET
+		(flow_table_nic_cap, hcattr,
+		 ft_field_support_2_nic_receive.tunnel_header_2_3);
 	attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
 	attr->inner_ipv4_ihl = MLX5_GET
 		(flow_table_nic_cap, hcattr,
diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index 2e1606a733..ac9be14f54 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -1325,6 +1325,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
 		}
 		if (hca_attr->flow.tunnel_header_0_1)
 			sh->tunnel_header_0_1 = 1;
+		if (hca_attr->flow.tunnel_header_2_3)
+			sh->tunnel_header_2_3 = 1;
 #endif
 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 		if (hca_attr->flow_hit_aso && priv->mtr_color_reg == REG_C_3) {
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index bd69aa2334..c5301921c5 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1186,6 +1186,7 @@ struct mlx5_dev_ctx_shared {
 	uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
 	uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
 	uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */
+	uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */
 	uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
 	uint32_t dr_drop_action_en:1; /* Use DR drop action. */
 	uint32_t drop_action_check_flag:1; /* Check Flag for drop action. */
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 5a4e000c12..b792ddb73a 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -2926,6 +2926,107 @@ mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
 	return ret;
 }
 
+/**
+ * Validate GRE optional item.
+ *
+ * @param[in] dev
+ *   Pointer to the Ethernet device structure.
+ * @param[in] item
+ *   Item specification.
+ * @param[in] item_flags
+ *   Bit flags to mark detected items.
+ * @param[in] attr
+ *   Flow rule attributes.
+ * @param[in] gre_item
+ *   Pointer to gre_item
+ * @param[out] error
+ *   Pointer to error structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
+				   const struct rte_flow_item *item,
+				   uint64_t item_flags,
+				   const struct rte_flow_attr *attr,
+				   const struct rte_flow_item *gre_item,
+				   struct rte_flow_error *error)
+{
+	const struct rte_flow_item_gre *gre_spec = gre_item->spec;
+	const struct rte_flow_item_gre *gre_mask = gre_item->mask;
+	const struct rte_flow_item_gre_opt *spec = item->spec;
+	const struct rte_flow_item_gre_opt *mask = item->mask;
+	struct mlx5_priv *priv = dev->data->dev_private;
+	int ret = 0;
+	struct rte_flow_item_gre_opt nic_mask = {
+		.checksum_rsvd = {
+			.checksum = RTE_BE16(UINT16_MAX),
+			.reserved1 = 0x0,
+		},
+		.key = {
+			.key = RTE_BE32(UINT32_MAX),
+		},
+		.sequence = {
+			.sequence = RTE_BE32(UINT32_MAX),
+		},
+	};
+
+	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "No preceding GRE header");
+	if (item_flags & MLX5_FLOW_LAYER_INNER)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "GRE option following a wrong item");
+	if (!spec || !mask)
+		return rte_flow_error_set(error, EINVAL,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "At least one field gre_option(checksum/key/sequence) must be specified");
+	if (!gre_mask)
+		gre_mask = &rte_flow_item_gre_mask;
+	if (mask->checksum_rsvd.checksum)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x8000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x8000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item,
+						  "Checksum bit must be on");
+	if (mask->key.key)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item, "Key bit must be on");
+	if (mask->sequence.sequence)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x1000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x1000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item,
+						  "Sequence bit must be on");
+	if (mask->checksum_rsvd.checksum || mask->sequence.sequence) {
+		if (priv->sh->steering_format_version ==
+		    MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 ||
+		    ((attr->group || attr->transfer) &&
+		     !priv->sh->misc5_cap) ||
+		    (!(priv->sh->tunnel_header_0_1 &&
+		       priv->sh->tunnel_header_2_3) &&
+		    !attr->group && !attr->transfer))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM,
+						  item,
+						  "Checksum/Sequence not supported");
+	}
+	ret = mlx5_flow_item_acceptable
+		(item, (const uint8_t *)mask,
+		 (const uint8_t *)&nic_mask,
+		 sizeof(struct rte_flow_item_gre_opt),
+		 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
+	return ret;
+}
+
 /**
  * Validate GRE item.
  *
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 09f0d7a75d..e510921a3f 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -1783,6 +1783,12 @@ int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
 				    uint64_t item_flags,
 				    const struct rte_flow_item *gre_item,
 				    struct rte_flow_error *error);
+int mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
+				       const struct rte_flow_item *item,
+				       uint64_t item_flags,
+				       const struct rte_flow_attr *attr,
+				       const struct rte_flow_item *gre_item,
+				       struct rte_flow_error *error);
 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
 				 uint64_t item_flags,
 				 uint64_t last_item,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 7a012f7bb9..aca55bbcdb 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -7109,6 +7109,13 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 			gre_item = items;
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
+			ret = mlx5_flow_validate_item_gre_option(dev, items, item_flags,
+							  attr, gre_item, error);
+			if (ret < 0)
+				return ret;
+			last_item = MLX5_FLOW_LAYER_GRE;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			ret = mlx5_flow_validate_item_nvgre(items, item_flags,
 							    next_protocol,
@@ -8829,6 +8836,110 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 		 protocol_m & protocol_v);
 }
 
+/**
+ * Add GRE optional items to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] gre_item
+ *   Pointer to gre_item.
+ * @param[in] pattern_flags
+ *   Accumulated pattern flags.
+ */
+static void
+flow_dv_translate_item_gre_option(void *matcher, void *key,
+				  const struct rte_flow_item *item,
+				  const struct rte_flow_item *gre_item,
+				  uint64_t pattern_flags)
+{
+	const struct rte_flow_item_gre_opt *option_m = item->mask;
+	const struct rte_flow_item_gre_opt *option_v = item->spec;
+	const struct rte_flow_item_gre *gre_m = gre_item->mask;
+	const struct rte_flow_item_gre *gre_v = gre_item->spec;
+	static const struct rte_flow_item_gre empty_gre = {0};
+	struct rte_flow_item gre_key_item;
+	uint16_t c_rsvd0_ver_m, c_rsvd0_ver_v;
+	uint16_t protocol_m, protocol_v;
+	void *misc5_m;
+	void *misc5_v;
+
+	/*
+	 * If only match key field, keep using misc for matching.
+	 * If need to match checksum or sequence, using misc5 and do
+	 * not need using misc.
+	 */
+	if (!(option_m->sequence.sequence ||
+	      option_m->checksum_rsvd.checksum)) {
+		flow_dv_translate_item_gre(matcher, key, gre_item,
+					   pattern_flags);
+		gre_key_item.spec = &option_v->key.key;
+		gre_key_item.mask = &option_m->key.key;
+		flow_dv_translate_item_gre_key(matcher, key, &gre_key_item);
+		return;
+	}
+	if (!gre_v) {
+		gre_v = &empty_gre;
+		gre_m = &empty_gre;
+	} else {
+		if (!gre_m)
+			gre_m = &rte_flow_item_gre_mask;
+	}
+	protocol_v = gre_v->protocol;
+	protocol_m = gre_m->protocol;
+	if (!protocol_m) {
+		/* Force next protocol to prevent matchers duplication */
+		uint16_t ether_type =
+			mlx5_translate_tunnel_etypes(pattern_flags);
+		if (ether_type) {
+			protocol_v = rte_be_to_cpu_16(ether_type);
+			protocol_m = UINT16_MAX;
+		}
+	}
+	c_rsvd0_ver_v = gre_v->c_rsvd0_ver;
+	c_rsvd0_ver_m = gre_m->c_rsvd0_ver;
+	if (option_m->sequence.sequence) {
+		c_rsvd0_ver_v |= RTE_BE16(0x1000);
+		c_rsvd0_ver_m |= RTE_BE16(0x1000);
+	}
+	if (option_m->key.key) {
+		c_rsvd0_ver_v |= RTE_BE16(0x2000);
+		c_rsvd0_ver_m |= RTE_BE16(0x2000);
+	}
+	if (option_m->checksum_rsvd.checksum) {
+		c_rsvd0_ver_v |= RTE_BE16(0x8000);
+		c_rsvd0_ver_m |= RTE_BE16(0x8000);
+	}
+	/*
+	 * Hardware parses GRE optional field into the fixed location,
+	 * do not need to adjust the tunnel dword indices.
+	 */
+	misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
+	misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
+	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_0,
+		 rte_be_to_cpu_32((c_rsvd0_ver_v | protocol_v << 16) &
+				  (c_rsvd0_ver_m | protocol_m << 16)));
+	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_0,
+		 rte_be_to_cpu_32(c_rsvd0_ver_m | protocol_m << 16));
+	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_1,
+		 rte_be_to_cpu_32(option_v->checksum_rsvd.checksum &
+				  option_m->checksum_rsvd.checksum));
+	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_1,
+		 rte_be_to_cpu_32(option_m->checksum_rsvd.checksum));
+	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_2,
+		 rte_be_to_cpu_32(option_v->key.key & option_m->key.key));
+	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_2,
+		 rte_be_to_cpu_32(option_m->key.key));
+	MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_3,
+		 rte_be_to_cpu_32(option_v->sequence.sequence &
+				  option_m->sequence.sequence));
+	MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_3,
+		 rte_be_to_cpu_32(option_m->sequence.sequence));
+}
+
 /**
  * Add NVGRE item to matcher and to the value.
  *
@@ -12709,6 +12820,7 @@ flow_dv_translate(struct rte_eth_dev *dev,
 	};
 	const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
 	const struct rte_flow_item *tunnel_item = NULL;
+	const struct rte_flow_item *gre_item = NULL;
 
 	if (!wks)
 		return rte_flow_error_set(error, ENOMEM,
@@ -13481,12 +13593,18 @@ flow_dv_translate(struct rte_eth_dev *dev,
 			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
 			last_item = MLX5_FLOW_LAYER_GRE;
 			tunnel_item = items;
+			gre_item = items;
 			break;
 		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
 			flow_dv_translate_item_gre_key(match_mask,
 						       match_value, items);
 			last_item = MLX5_FLOW_LAYER_GRE_KEY;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
+			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
+			last_item = MLX5_FLOW_LAYER_GRE;
+			tunnel_item = items;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
 			last_item = MLX5_FLOW_LAYER_GRE;
@@ -13645,6 +13763,9 @@ flow_dv_translate(struct rte_eth_dev *dev,
 		else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
 			flow_dv_translate_item_nvgre(match_mask, match_value,
 						     tunnel_item, item_flags);
+		else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION)
+			flow_dv_translate_item_gre_option(match_mask, match_value,
+					tunnel_item, gre_item, item_flags);
 		else
 			MLX5_ASSERT(false);
 	}
-- 
2.25.1

Re: [v4] net/mlx5: support matching optional fields of GRE

[Thomas Monjalon]

25/02/2022 02:14, Sean Zhang:
> This patch adds matching on the optional fields (checksum/key/sequence)
> of GRE header. The matching on checksum and sequence fields requests
> support from rdma-core with the capability of misc5 and tunnel_header 0-3.
> 
> For patterns without checksum and sequence specified, keep using misc for
> matching as before, but for patterns with checksum or sequence, validate
> capability first and then use misc5 for the matching.
> 
> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

Applied in next-net-mlx with a release notes addition.

Re: [v4] net/mlx5: support matching optional fields of GRE

[Ferruh Yigit]

On 2/25/2022 1:14 AM, Sean Zhang wrote:
> This patch adds matching on the optional fields (checksum/key/sequence)
> of GRE header. The matching on checksum and sequence fields requests
> support from rdma-core with the capability of misc5 and tunnel_header 0-3.
> 
> For patterns without checksum and sequence specified, keep using misc for
> matching as before, but for patterns with checksum or sequence, validate
> capability first and then use misc5 for the matching.
> 
> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> 

doc is missing:

./devtools/check-doc-vs-code.sh
rte_flow doc out of sync for mlx5
         item gre_option

I can add in next-net while merging, if this is the only issue.

Re: [v4] net/mlx5: support matching optional fields of GRE

[Thomas Monjalon]

25/02/2022 18:55, Ferruh Yigit:
> On 2/25/2022 1:14 AM, Sean Zhang wrote:
> > This patch adds matching on the optional fields (checksum/key/sequence)
> > of GRE header. The matching on checksum and sequence fields requests
> > support from rdma-core with the capability of misc5 and tunnel_header 0-3.
> > 
> > For patterns without checksum and sequence specified, keep using misc for
> > matching as before, but for patterns with checksum or sequence, validate
> > capability first and then use misc5 for the matching.
> > 
> > Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
> > Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> > 
> 
> doc is missing:
> 
> ./devtools/check-doc-vs-code.sh
> rte_flow doc out of sync for mlx5
>          item gre_option
> 
> I can add in next-net while merging, if this is the only issue.

Yes please

Re: [v2 0/4] Add support for GRE optional fields matching

[Ferruh Yigit]

On 2/11/2022 1:45 AM, Sean Zhang wrote:
> This patch set adds support for matching optional fields of GRE header.
> The optional fields are checksum, key and sequence number. Currently, key
> field is supported with pattern gre_key item '.. / gre / gre_key value is
> xx / ..' with field gre_key in misc, but misc does not support matching of
> checksum and sequence number of GRE.
> To support matching of checksum and sequence number fields in GRE,
> rdma-core needs the capbility of misc5 and support tunnel_header 0-3. Since
> tunnel_header1 is used to match checksum, tunnel_header2 for key and

Hi Sean,

The GRE optional fields support in flow API should be generic for any vendor,
above description concerns me flow API implementation is done with to match
a specific vendor implementation.

Will it work to get ethdev part as previous version of this patch (v1),
and get the mlx driver patch when rdma-core is ready?

> tunnel_header3 for sequence by hardware. If checksum and sequence number
> not present in the pattern, use misc as before for the matching.
> Application can still use gre_key item 'gre_key value is xx' for key
> matching, the effect is the same if use 'gre_option key is xx'.
> If using gre_option item, the flags in gre item should be correspondingly
> set. For example, if using gre_option to match checksum, the c_bit should
> be set '1' (.. / gre c_bit is 1 / gre_option checksum is xx / ..).
> 
> change in v2:
> -changed the struct defined in rte_flow for gre_option item.
> -fixed raw encap issue.
> 
> Sean Zhang (4):
>    lib: add optional fields in GRE header
>    ethdev: support GRE optional fields
>    app/testpmd: add gre_option item command
>    net/mlx5: support matching optional fields of GRE
> 
>   app/test-pmd/cmdline_flow.c                 |  72 +++++++++++++++
>   doc/guides/nics/mlx5.rst                    |   8 ++
>   doc/guides/prog_guide/rte_flow.rst          |  17 ++++
>   doc/guides/rel_notes/release_22_03.rst      |   5 ++
>   doc/guides/testpmd_app_ug/testpmd_funcs.rst |   6 ++
>   drivers/common/mlx5/mlx5_devx_cmds.c        |   3 +
>   drivers/net/mlx5/linux/mlx5_os.c            |   2 +
>   drivers/net/mlx5/mlx5.h                     |   1 +
>   drivers/net/mlx5/mlx5_flow.c                | 108 +++++++++++++++++++++++
>   drivers/net/mlx5/mlx5_flow.h                |   6 ++
>   drivers/net/mlx5/mlx5_flow_dv.c             | 130 ++++++++++++++++++++++++++++
>   lib/ethdev/rte_flow.c                       |   1 +
>   lib/ethdev/rte_flow.h                       |  19 ++++
>   lib/net/rte_gre.h                           |  22 +++++
>   14 files changed, 400 insertions(+)
> 

RE: [v2 0/4] Add support for GRE optional fields matching

[Sean Zhang (Networking SW)]

> -----Original Message-----
> From: Ferruh Yigit <ferruh.yigit@intel.com>
> Sent: Friday, February 11, 2022 5:37 PM
> To: Sean Zhang (Networking SW) <xiazhang@nvidia.com>; NBU-Contact-
> Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>
> Cc: dev@dpdk.org; Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>;
> Ori Kam <orika@nvidia.com>; Qi Zhang <qi.z.zhang@intel.com>
> Subject: Re: [v2 0/4] Add support for GRE optional fields matching
> 
> External email: Use caution opening links or attachments
> 
> 
> On 2/11/2022 1:45 AM, Sean Zhang wrote:
> > This patch set adds support for matching optional fields of GRE header.
> > The optional fields are checksum, key and sequence number. Currently,
> > key field is supported with pattern gre_key item '.. / gre / gre_key
> > value is xx / ..' with field gre_key in misc, but misc does not
> > support matching of checksum and sequence number of GRE.
> > To support matching of checksum and sequence number fields in GRE,
> > rdma-core needs the capbility of misc5 and support tunnel_header 0-3.
> > Since
> > tunnel_header1 is used to match checksum, tunnel_header2 for key and
> 
> Hi Sean,
> 
> The GRE optional fields support in flow API should be generic for any vendor,
> above description concerns me flow API implementation is done with to
> match a specific vendor implementation.
> 
> Will it work to get ethdev part as previous version of this patch (v1), and get
> the mlx driver patch when rdma-core is ready?

Hi Ferruh,

Sorry about the confuse of the cover letter, and both flow API patches of v1 and v2 are common, not for specific vendor.

Thanks,
Sean
> 
> > tunnel_header3 for sequence by hardware. If checksum and sequence
> > number not present in the pattern, use misc as before for the matching.
> > Application can still use gre_key item 'gre_key value is xx' for key
> > matching, the effect is the same if use 'gre_option key is xx'.
> > If using gre_option item, the flags in gre item should be
> > correspondingly set. For example, if using gre_option to match
> > checksum, the c_bit should be set '1' (.. / gre c_bit is 1 / gre_option
> checksum is xx / ..).
> >
> > change in v2:
> > -changed the struct defined in rte_flow for gre_option item.
> > -fixed raw encap issue.
> >
> > Sean Zhang (4):
> >    lib: add optional fields in GRE header
> >    ethdev: support GRE optional fields
> >    app/testpmd: add gre_option item command
> >    net/mlx5: support matching optional fields of GRE
> >
> >   app/test-pmd/cmdline_flow.c                 |  72 +++++++++++++++
> >   doc/guides/nics/mlx5.rst                    |   8 ++
> >   doc/guides/prog_guide/rte_flow.rst          |  17 ++++
> >   doc/guides/rel_notes/release_22_03.rst      |   5 ++
> >   doc/guides/testpmd_app_ug/testpmd_funcs.rst |   6 ++
> >   drivers/common/mlx5/mlx5_devx_cmds.c        |   3 +
> >   drivers/net/mlx5/linux/mlx5_os.c            |   2 +
> >   drivers/net/mlx5/mlx5.h                     |   1 +
> >   drivers/net/mlx5/mlx5_flow.c                | 108 +++++++++++++++++++++++
> >   drivers/net/mlx5/mlx5_flow.h                |   6 ++
> >   drivers/net/mlx5/mlx5_flow_dv.c             | 130
> ++++++++++++++++++++++++++++
> >   lib/ethdev/rte_flow.c                       |   1 +
> >   lib/ethdev/rte_flow.h                       |  19 ++++
> >   lib/net/rte_gre.h                           |  22 +++++
> >   14 files changed, 400 insertions(+)
> >

Re: [v2 0/4] Add support for GRE optional fields matching

[Ferruh Yigit]

On 2/11/2022 10:33 AM, Sean Zhang (Networking SW) wrote:
> 
> 
>> -----Original Message-----
>> From: Ferruh Yigit <ferruh.yigit@intel.com>
>> Sent: Friday, February 11, 2022 5:37 PM
>> To: Sean Zhang (Networking SW) <xiazhang@nvidia.com>; NBU-Contact-
>> Thomas Monjalon (EXTERNAL) <thomas@monjalon.net>
>> Cc: dev@dpdk.org; Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>;
>> Ori Kam <orika@nvidia.com>; Qi Zhang <qi.z.zhang@intel.com>
>> Subject: Re: [v2 0/4] Add support for GRE optional fields matching
>>
>> External email: Use caution opening links or attachments
>>
>>
>> On 2/11/2022 1:45 AM, Sean Zhang wrote:
>>> This patch set adds support for matching optional fields of GRE header.
>>> The optional fields are checksum, key and sequence number. Currently,
>>> key field is supported with pattern gre_key item '.. / gre / gre_key
>>> value is xx / ..' with field gre_key in misc, but misc does not
>>> support matching of checksum and sequence number of GRE.
>>> To support matching of checksum and sequence number fields in GRE,
>>> rdma-core needs the capbility of misc5 and support tunnel_header 0-3.
>>> Since
>>> tunnel_header1 is used to match checksum, tunnel_header2 for key and
>>
>> Hi Sean,
>>
>> The GRE optional fields support in flow API should be generic for any vendor,
>> above description concerns me flow API implementation is done with to
>> match a specific vendor implementation.
>>
>> Will it work to get ethdev part as previous version of this patch (v1), and get
>> the mlx driver patch when rdma-core is ready?
> 
> Hi Ferruh,
> 
> Sorry about the confuse of the cover letter, and both flow API patches of v1 and v2 are common, not for specific vendor.
> 

OK, thanks for clarification, we don't want any PMD specific implementation.

> Thanks,
> Sean
>>
>>> tunnel_header3 for sequence by hardware. If checksum and sequence
>>> number not present in the pattern, use misc as before for the matching.
>>> Application can still use gre_key item 'gre_key value is xx' for key
>>> matching, the effect is the same if use 'gre_option key is xx'.
>>> If using gre_option item, the flags in gre item should be
>>> correspondingly set. For example, if using gre_option to match
>>> checksum, the c_bit should be set '1' (.. / gre c_bit is 1 / gre_option
>> checksum is xx / ..).
>>>
>>> change in v2:
>>> -changed the struct defined in rte_flow for gre_option item.
>>> -fixed raw encap issue.
>>>
>>> Sean Zhang (4):
>>>     lib: add optional fields in GRE header
>>>     ethdev: support GRE optional fields
>>>     app/testpmd: add gre_option item command
>>>     net/mlx5: support matching optional fields of GRE
>>>
>>>    app/test-pmd/cmdline_flow.c                 |  72 +++++++++++++++
>>>    doc/guides/nics/mlx5.rst                    |   8 ++
>>>    doc/guides/prog_guide/rte_flow.rst          |  17 ++++
>>>    doc/guides/rel_notes/release_22_03.rst      |   5 ++
>>>    doc/guides/testpmd_app_ug/testpmd_funcs.rst |   6 ++
>>>    drivers/common/mlx5/mlx5_devx_cmds.c        |   3 +
>>>    drivers/net/mlx5/linux/mlx5_os.c            |   2 +
>>>    drivers/net/mlx5/mlx5.h                     |   1 +
>>>    drivers/net/mlx5/mlx5_flow.c                | 108 +++++++++++++++++++++++
>>>    drivers/net/mlx5/mlx5_flow.h                |   6 ++
>>>    drivers/net/mlx5/mlx5_flow_dv.c             | 130
>> ++++++++++++++++++++++++++++
>>>    lib/ethdev/rte_flow.c                       |   1 +
>>>    lib/ethdev/rte_flow.h                       |  19 ++++
>>>    lib/net/rte_gre.h                           |  22 +++++
>>>    14 files changed, 400 insertions(+)
>>>
> 

Re: [v2 0/4] Add support for GRE optional fields matching

[Ferruh Yigit]

On 2/11/2022 1:45 AM, Sean Zhang wrote:
> This patch set adds support for matching optional fields of GRE header.
> The optional fields are checksum, key and sequence number. Currently, key
> field is supported with pattern gre_key item '.. / gre / gre_key value is
> xx / ..' with field gre_key in misc, but misc does not support matching of
> checksum and sequence number of GRE.
> To support matching of checksum and sequence number fields in GRE,
> rdma-core needs the capbility of misc5 and support tunnel_header 0-3. Since
> tunnel_header1 is used to match checksum, tunnel_header2 for key and
> tunnel_header3 for sequence by hardware. If checksum and sequence number
> not present in the pattern, use misc as before for the matching.
> Application can still use gre_key item 'gre_key value is xx' for key
> matching, the effect is the same if use 'gre_option key is xx'.
> If using gre_option item, the flags in gre item should be correspondingly
> set. For example, if using gre_option to match checksum, the c_bit should
> be set '1' (.. / gre c_bit is 1 / gre_option checksum is xx / ..).
> 
> change in v2:
> -changed the struct defined in rte_flow for gre_option item.
> -fixed raw encap issue.
> 
> Sean Zhang (4):
>    lib: add optional fields in GRE header
>    ethdev: support GRE optional fields
>    app/testpmd: add gre_option item command
>    net/mlx5: support matching optional fields of GRE

Except from driver patch (4/4),
Series applied to dpdk-next-net/main, thanks.

Set merged partially to be able to get library patches in -rc1,
driver patch can be merged after -rc1 when reviewed.

[RFC 2/3] app/testpmd: add gre_option item command

[Sean Zhang]

Add gre_option command for matching optional fields(checksum/key/sequence)
in GRE header. The item must follow gre item, and the item does not
change the flags in gre item, the application should set the flags in
gre item correspondingly.
Application can still use gre_key item 'gre_key value is xx' for key
matching, the effect is the same with using 'gre_option key is xx'.

The examples for gre_option are as follows:

To match on checksum field with value 0x11:
testpmd> ... pattern / eth / gre c_bit is 1 / gre_option checksum is
		0x11 / end ..

To match on checksum field with value 0x11 and any value of key:
testpmd> ... pattern / eth / gre c_bit is 1 k_bit is 1 / gre_option
		checksum is 0x11 / end ..

To match on checksum field with value 0x11 and no key field in packet:
testpmd> ... pattern / eth / gre c_bit is 1 k_bit is 0 / gre_option
		checksum is 0x11 / end ..

The invalid patterns for gre_option are as follows:

testpmd> ... pattern / eth / gre / gre_option checksum is 0x11 / end ..
		(c_bit in gre item not present)
testpmd> ... pattern / eth / gre c_bit is 0 / gre_option checksum is 0x11 /
		end .. (c_bit is unset for gre item, but checksum is
		specified by gre_option item)

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
---
 app/test-pmd/cmdline_flow.c                 | 57 +++++++++++++++++++++++++++++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  6 +++
 2 files changed, 63 insertions(+)

diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
index bbe3dc0..4e714c2 100644
--- a/app/test-pmd/cmdline_flow.c
+++ b/app/test-pmd/cmdline_flow.c
@@ -271,6 +271,10 @@ enum index {
 	ITEM_META_DATA,
 	ITEM_GRE_KEY,
 	ITEM_GRE_KEY_VALUE,
+	ITEM_GRE_OPTION,
+	ITEM_GRE_OPTION_CHECKSUM,
+	ITEM_GRE_OPTION_KEY,
+	ITEM_GRE_OPTION_SEQUENCE,
 	ITEM_GTP_PSC,
 	ITEM_GTP_PSC_QFI,
 	ITEM_GTP_PSC_PDU_T,
@@ -1042,6 +1046,7 @@ struct parse_action_priv {
 	ITEM_ICMP6_ND_OPT_TLA_ETH,
 	ITEM_META,
 	ITEM_GRE_KEY,
+	ITEM_GRE_OPTION,
 	ITEM_GTP_PSC,
 	ITEM_PPPOES,
 	ITEM_PPPOED,
@@ -1232,6 +1237,14 @@ struct parse_action_priv {
 	ZERO,
 };
 
+static const enum index item_gre_option[] = {
+	ITEM_GRE_OPTION_CHECKSUM,
+	ITEM_GRE_OPTION_KEY,
+	ITEM_GRE_OPTION_SEQUENCE,
+	ITEM_NEXT,
+	ZERO,
+};
+
 static const enum index item_gtp[] = {
 	ITEM_GTP_FLAGS,
 	ITEM_GTP_MSG_TYPE,
@@ -3479,6 +3492,37 @@ static int comp_set_modify_field_id(struct context *, const struct token *,
 			     item_param),
 		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
 	},
+	[ITEM_GRE_OPTION] = {
+		.name = "gre_option",
+		.help = "match GRE optional fields",
+		.priv = PRIV_ITEM(GRE_OPTION, sizeof(struct rte_gre_hdr_option)),
+		.next = NEXT(item_gre_option),
+		.call = parse_vc,
+	},
+	[ITEM_GRE_OPTION_CHECKSUM] = {
+		.name = "checksum",
+		.help = "match GRE checksum",
+		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
+			     item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_gre_hdr_option,
+					     checksum)),
+	},
+	[ITEM_GRE_OPTION_KEY] = {
+		.name = "key",
+		.help = "match GRE key",
+		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
+			     item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_gre_hdr_option,
+					     key)),
+	},
+	[ITEM_GRE_OPTION_SEQUENCE] = {
+		.name = "sequence",
+		.help = "match GRE sequence",
+		.next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED),
+			     item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_gre_hdr_option,
+					     sequence)),
+	},
 	[ITEM_GTP_PSC] = {
 		.name = "gtp_psc",
 		.help = "match GTP extension header with type 0x85",
@@ -9235,6 +9279,19 @@ static int comp_set_modify_field_id(struct context *, const struct token *,
 				((const struct rte_flow_item_flex *)
 				item->spec)->length : 0;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
+			size = 0;
+			if (item->spec) {
+				const struct rte_gre_hdr_option *opt = item->spec;
+				if (opt->checksum)
+					size += 4;
+				if (opt->key)
+					size += 4;
+				if (opt->sequence)
+					size += 4;
+			}
+			proto = 0x2F;
+			break;
 		default:
 			fprintf(stderr, "Error - Not supported item\n");
 			goto error;
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index 44228cd..b49e93c 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -3714,6 +3714,12 @@ This section lists supported pattern items and their attributes, if any.
 
   - ``value {unsigned}``: key value.
 
+- ``gre_option``: match GRE optional fields(checksum/key/sequence).
+
+  - ``checksum {unsigned}``: checksum value.
+  - ``key {unsigned}``: key value.
+  - ``sequence {unsigned}``: sequence number value.
+
 - ``fuzzy``: fuzzy pattern match, expect faster than default.
 
   - ``thresh {unsigned}``: accuracy threshold.
-- 
1.8.3.1

[RFC 3/3] net/mlx5: support matching on optional fields of GRE

[Sean Zhang]

This patch adds matching on the optional fields (checksum/key/sequence)
of GRE header. The matching of checksum and sequence fields requests
support from rdma-core with capability of misc5 and tunner_header 0-3.

For patterns without checksum and sequence specified, keep using misc for
matching as before, but for patterns with checksum or sequence, validate
capability first and then use misc5 for the matching.

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
---
 drivers/common/mlx5/mlx5_devx_cmds.c |   3 +
 drivers/net/mlx5/linux/mlx5_os.c     |   2 +
 drivers/net/mlx5/mlx5.h              |   1 +
 drivers/net/mlx5/mlx5_flow.c         |  94 +++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_flow.h         |   6 ++
 drivers/net/mlx5/mlx5_flow_dv.c      | 133 +++++++++++++++++++++++++++++++++++
 6 files changed, 239 insertions(+)

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index e52b995..3accb7b 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1027,6 +1027,9 @@ struct mlx5_devx_obj *
 	attr->flow.tunnel_header_0_1 = MLX5_GET
 		(flow_table_nic_cap, hcattr,
 		 ft_field_support_2_nic_receive.tunnel_header_0_1);
+	attr->flow.tunnel_header_2_3 = MLX5_GET
+		(flow_table_nic_cap, hcattr,
+		 ft_field_support_2_nic_receive.tunnel_header_2_3);
 	attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
 	attr->inner_ipv4_ihl = MLX5_GET
 		(flow_table_nic_cap, hcattr,
diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index c29fe3d..3bfcb5c 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -1385,6 +1385,8 @@
 		}
 		if (config->hca_attr.flow.tunnel_header_0_1)
 			sh->tunnel_header_0_1 = 1;
+		if (config->hca_attr.flow.tunnel_header_2_3)
+			sh->tunnel_header_2_3 = 1;
 #endif
 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 		if (config->hca_attr.flow_hit_aso &&
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 8466531..9b5685a 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1150,6 +1150,7 @@ struct mlx5_dev_ctx_shared {
 	uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
 	uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
 	uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */
+	uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */
 	uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
 	uint32_t reclaim_mode:1; /* Reclaim memory. */
 	uint32_t dr_drop_action_en:1; /* Use DR drop action. */
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index f34e4b8..ad948c3 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -2802,6 +2802,100 @@ struct mlx5_flow_tunnel_info {
 }
 
 /**
+ * Validate GRE optional item.
+ *
+ * @param[in] dev
+ *   Pointer to the Ethernet device structure.
+ * @param[in] item
+ *   Item specification.
+ * @param[in] item_flags
+ *   Bit flags to mark detected items.
+ * @param[in] attr
+ *   Flow rule attributes.
+ * @param[in] gre_item
+ *   Pointer to gre_item
+ * @param[out] error
+ *   Pointer to error structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
+				const struct rte_flow_item *item,
+				uint64_t item_flags,
+				const struct rte_flow_attr *attr,
+				const struct rte_flow_item *gre_item,
+				struct rte_flow_error *error)
+{
+	const struct rte_flow_item_gre *gre_spec = gre_item->spec;
+	const struct rte_flow_item_gre *gre_mask = gre_item->mask;
+	const struct rte_gre_hdr_option *spec = item->spec;
+	const struct rte_gre_hdr_option *mask = item->mask;
+	struct mlx5_priv *priv = dev->data->dev_private;
+	int ret = 0;
+
+	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "No preceding GRE header");
+	if (item_flags & MLX5_FLOW_LAYER_INNER)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "GRE option following a wrong item");
+	if (!gre_mask)
+		gre_mask = &rte_flow_item_gre_mask;
+
+	struct rte_gre_hdr_option gre_option_default_mask = {
+		.checksum = 0xffff,
+		.key = 0xffffffff,
+		.sequence = 0xffffffff,
+	};
+
+	if (!mask)
+		mask = &gre_option_default_mask;
+
+	if (spec && mask->checksum)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x8000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x8000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM, item,
+						  "Checksum bit must be on");
+
+	if (spec && mask->key)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM, item,
+						  "Key bit must be on");
+
+	if (spec && mask->sequence)
+		if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x1000)) &&
+				 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x1000)))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM, item,
+						  "Sequence bit must be on");
+
+	if (spec && (mask->checksum || mask->sequence)) {
+		if (priv->sh->steering_format_version ==
+			MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 ||
+			((attr->group || attr->transfer) && !priv->sh->misc5_cap) ||
+			(!(priv->sh->tunnel_header_0_1 && priv->sh->tunnel_header_2_3) &&
+			 !attr->group && !attr->transfer))
+			return rte_flow_error_set(error, EINVAL,
+						  RTE_FLOW_ERROR_TYPE_ITEM, item,
+						  "Checksum/Sequence not supported");
+	}
+
+	ret = mlx5_flow_item_acceptable
+		(item, (const uint8_t *)mask,
+		 (const uint8_t *)&gre_option_default_mask,
+		 sizeof(struct rte_gre_hdr_option), MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
+
+	return ret;
+}
+
+/**
  * Validate GRE item.
  *
  * @param[in] item
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 1f54649..59857ec 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -1523,6 +1523,12 @@ int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
 				    uint64_t item_flags,
 				    const struct rte_flow_item *gre_item,
 				    struct rte_flow_error *error);
+int mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev,
+				const struct rte_flow_item *item,
+				uint64_t item_flags,
+				const struct rte_flow_attr *attr,
+				const struct rte_flow_item *gre_item,
+				struct rte_flow_error *error);
 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
 				 uint64_t item_flags,
 				 uint64_t last_item,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 3da122c..28462f8 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -7112,6 +7112,13 @@ struct mlx5_list_entry *
 			gre_item = items;
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
+			ret = mlx5_flow_validate_item_gre_option(dev, items, item_flags,
+							  attr, gre_item, error);
+			if (ret < 0)
+				return ret;
+			last_item = MLX5_FLOW_LAYER_GRE;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			ret = mlx5_flow_validate_item_nvgre(items, item_flags,
 							    next_protocol,
@@ -8833,6 +8840,122 @@ struct mlx5_list_entry *
 }
 
 /**
+ * Add GRE optional items to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] gre_item
+ *   Pointer to gre_item.
+ * @param[in] pattern_flags
+ *   Accumulated pattern flags.
+ */
+static void
+flow_dv_translate_item_gre_option(void *matcher, void *key,
+					const struct rte_flow_item *item,
+					const struct rte_flow_item *gre_item,
+					uint64_t pattern_flags)
+{
+	void *misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
+	void *misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
+	const struct rte_gre_hdr_option *option_m = item->mask;
+	const struct rte_gre_hdr_option *option_v = item->spec;
+	const struct rte_flow_item_gre *gre_m = gre_item->mask;
+	const struct rte_flow_item_gre *gre_v = gre_item->spec;
+	static const struct rte_flow_item_gre empty_gre = {0};
+	struct rte_flow_item gre_key_item;
+	uint16_t c_rsvd0_ver_m, c_rsvd0_ver_v;
+	uint16_t protocol_m, protocol_v;
+	uint32_t *tunnel_header_v[4];
+	uint32_t *tunnel_header_m[4];
+
+	struct rte_gre_hdr_option gre_option_default_mask = {
+		.checksum = 0xffff,
+		.key = 0xffffffff,
+		.sequence = 0xffffffff,
+	};
+
+	if (!option_v)
+		return;
+	if (!option_m)
+		option_m = &gre_option_default_mask;
+
+	if (!(option_m->sequence || option_m->checksum)) {
+		flow_dv_translate_item_gre(matcher, key, gre_item, pattern_flags);
+		gre_key_item.spec = &option_v->key;
+		gre_key_item.mask = &option_m->key;
+		flow_dv_translate_item_gre_key(matcher, key, &gre_key_item);
+		return;
+	}
+
+	if (!gre_v) {
+		gre_v = &empty_gre;
+		gre_m = &empty_gre;
+	} else {
+		if (!gre_m)
+			gre_m = &rte_flow_item_gre_mask;
+	}
+
+	tunnel_header_v[0] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_v, tunnel_header_0);
+	tunnel_header_m[0] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_m, tunnel_header_0);
+	tunnel_header_v[1] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_v, tunnel_header_1);
+	tunnel_header_m[1] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_m, tunnel_header_1);
+	tunnel_header_v[2] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_v, tunnel_header_2);
+	tunnel_header_m[2] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_m, tunnel_header_2);
+	tunnel_header_v[3] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_v, tunnel_header_3);
+	tunnel_header_m[3] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+						   misc5_m, tunnel_header_3);
+
+	protocol_v = gre_v->protocol;
+	protocol_m = gre_m->protocol;
+	if (!protocol_m) {
+		/* Force next protocol to prevent matchers duplication */
+		uint16_t ether_type = mlx5_translate_tunnel_etypes(pattern_flags);
+		if (ether_type) {
+			protocol_v = rte_be_to_cpu_16(ether_type);
+			protocol_m = 0xFFFF;
+		}
+	}
+	c_rsvd0_ver_v = gre_v->c_rsvd0_ver;
+	c_rsvd0_ver_m = gre_m->c_rsvd0_ver;
+
+
+	if (option_m->sequence) {
+		c_rsvd0_ver_v |= RTE_BE16(0x1000);
+		c_rsvd0_ver_m |= RTE_BE16(0x1000);
+	}
+
+	if (option_m->key) {
+		c_rsvd0_ver_v |= RTE_BE16(0x2000);
+		c_rsvd0_ver_m |= RTE_BE16(0x2000);
+	}
+
+	if (option_m->checksum) {
+		c_rsvd0_ver_v |= RTE_BE16(0x8000);
+		c_rsvd0_ver_m |= RTE_BE16(0x8000);
+	}
+
+	*tunnel_header_v[0] = c_rsvd0_ver_v | protocol_v << 16;
+	*tunnel_header_m[0] = c_rsvd0_ver_m | protocol_m << 16;
+	*tunnel_header_v[1] = option_v->checksum;
+	*tunnel_header_m[1] = option_m->checksum;
+	*tunnel_header_v[2] = option_v->key;
+	*tunnel_header_m[2] = option_m->key;
+	*tunnel_header_v[3] = option_v->sequence;
+	*tunnel_header_m[3] = option_m->sequence;
+}
+
+/**
  * Add NVGRE item to matcher and to the value.
  *
  * @param[in, out] matcher
@@ -12708,6 +12831,7 @@ struct mlx5_list_entry *
 	};
 	const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
 	const struct rte_flow_item *tunnel_item = NULL;
+	const struct rte_flow_item *gre_item = NULL;
 
 	if (!wks)
 		return rte_flow_error_set(error, ENOMEM,
@@ -13480,12 +13604,18 @@ struct mlx5_list_entry *
 			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
 			last_item = MLX5_FLOW_LAYER_GRE;
 			tunnel_item = items;
+			gre_item = items;
 			break;
 		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
 			flow_dv_translate_item_gre_key(match_mask,
 						       match_value, items);
 			last_item = MLX5_FLOW_LAYER_GRE_KEY;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
+			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
+			last_item = MLX5_FLOW_LAYER_GRE;
+			tunnel_item = items;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
 			last_item = MLX5_FLOW_LAYER_GRE;
@@ -13645,6 +13775,9 @@ struct mlx5_list_entry *
 		else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
 			flow_dv_translate_item_nvgre(match_mask, match_value,
 						     tunnel_item, item_flags);
+		else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION)
+			flow_dv_translate_item_gre_option(match_mask, match_value,
+					tunnel_item, gre_item, item_flags);
 		else
 			MLX5_ASSERT(false);
 	}
-- 
1.8.3.1