From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7677EA00BE; Thu, 17 Feb 2022 12:09:57 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6E71C4117A; Thu, 17 Feb 2022 12:09:43 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 2EEA641163 for ; Thu, 17 Feb 2022 12:09:41 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21H9Hmja005516; Thu, 17 Feb 2022 03:09:40 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=1DvBVTVELCdgqd2MQBCxnCarnP2KX0T/w0TNQbPQCwI=; b=HN1rI7uq+Dgs4RhXJzVFDUl+sEz/fcx9ZPJGcKHirTvd6aImGNtiJKh+8x4Q2dvxcMU1 J5TGzxp+LQIHUVl/M2MoWxd+0XqP/oss/Gez5thdCgOd9LcA7H2cqME3VDktBEoshOyJ OcQvjIvOnI5o6wfjVnuESuSMNMYsfr+yxP663NOyMJjfueDo8dhQmDTC4fB6JUENXjY+ qBQWPw6VQr+T5knT1+T5Mg6ogT6qjD5cd+xFd4Aep8lF0K+lWRv9XSV9ydigoHfV1ZPI GD5Uvsur2anOjb8S1gZ9doN06N2fQ4DknSCTQWHwVlleSei4DWLLufKNXjLlDcm4z+z1 1Q== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3e9kktrckk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 17 Feb 2022 03:09:40 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 17 Feb 2022 03:09:38 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 17 Feb 2022 03:09:38 -0800 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id CAA2F3F7051; Thu, 17 Feb 2022 03:09:36 -0800 (PST) From: Tomasz Duszynski To: , Jakub Palider , Tomasz Duszynski CC: , Subject: [PATCH v6 04/11] raw/cnxk_gpio: support queue setup Date: Thu, 17 Feb 2022 12:09:17 +0100 Message-ID: <20220217110924.419024-5-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220217110924.419024-1-tduszynski@marvell.com> References: <20220118132424.2573372-1-tduszynski@marvell.com> <20220217110924.419024-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: ss-dIcXPPd2XM309u-g8zllOaNR1mH9O X-Proofpoint-GUID: ss-dIcXPPd2XM309u-g8zllOaNR1mH9O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-17_04,2022-02-17_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for queue setup. Signed-off-by: Tomasz Duszynski --- drivers/raw/cnxk_gpio/cnxk_gpio.c | 84 ++++++++++++++++++++++++++++++- 1 file changed, 82 insertions(+), 2 deletions(-) diff --git a/drivers/raw/cnxk_gpio/cnxk_gpio.c b/drivers/raw/cnxk_gpio/cnxk_gpio.c index cee75e389a..9baa43187e 100644 --- a/drivers/raw/cnxk_gpio/cnxk_gpio.c +++ b/drivers/raw/cnxk_gpio/cnxk_gpio.c @@ -139,9 +139,80 @@ cnxk_gpio_read_attr_int(char *attr, int *val) } static int -cnxk_gpio_dev_close(struct rte_rawdev *dev) +cnxk_gpio_write_attr(const char *attr, const char *val) { - RTE_SET_USED(dev); + FILE *fp; + int ret; + + if (!val) + return -EINVAL; + + fp = fopen(attr, "w"); + if (!fp) + return -errno; + + ret = fprintf(fp, "%s", val); + if (ret < 0) { + fclose(fp); + return ret; + } + + ret = fclose(fp); + if (ret) + return -errno; + + return 0; +} + +static int +cnxk_gpio_write_attr_int(const char *attr, int val) +{ + char buf[CNXK_GPIO_BUFSZ]; + + snprintf(buf, sizeof(buf), "%d", val); + + return cnxk_gpio_write_attr(attr, buf); +} + +static struct cnxk_gpio * +cnxk_gpio_lookup(struct cnxk_gpiochip *gpiochip, uint16_t queue) +{ + if (queue >= gpiochip->num_gpios) + return NULL; + + return gpiochip->gpios[queue]; +} + +static int +cnxk_gpio_queue_setup(struct rte_rawdev *dev, uint16_t queue_id, + rte_rawdev_obj_t queue_conf, size_t queue_conf_size) +{ + struct cnxk_gpiochip *gpiochip = dev->dev_private; + char buf[CNXK_GPIO_BUFSZ]; + struct cnxk_gpio *gpio; + int ret; + + RTE_SET_USED(queue_conf); + RTE_SET_USED(queue_conf_size); + + gpio = cnxk_gpio_lookup(gpiochip, queue_id); + if (gpio) + return -EEXIST; + + gpio = rte_zmalloc(NULL, sizeof(*gpio), 0); + if (!gpio) + return -ENOMEM; + gpio->num = queue_id + gpiochip->base; + gpio->gpiochip = gpiochip; + + snprintf(buf, sizeof(buf), "%s/export", CNXK_GPIO_CLASS_PATH); + ret = cnxk_gpio_write_attr_int(buf, gpio->num); + if (ret) { + rte_free(gpio); + return ret; + } + + gpiochip->gpios[queue_id] = gpio; return 0; } @@ -172,10 +243,19 @@ cnxk_gpio_queue_count(struct rte_rawdev *dev) return gpiochip->num_gpios; } +static int +cnxk_gpio_dev_close(struct rte_rawdev *dev) +{ + RTE_SET_USED(dev); + + return 0; +} + static const struct rte_rawdev_ops cnxk_gpio_rawdev_ops = { .dev_close = cnxk_gpio_dev_close, .queue_def_conf = cnxk_gpio_queue_def_conf, .queue_count = cnxk_gpio_queue_count, + .queue_setup = cnxk_gpio_queue_setup, }; static int -- 2.25.1