From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0B28EA034C; Tue, 22 Feb 2022 20:37:09 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 17BA0411DB; Tue, 22 Feb 2022 20:36:16 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 2235F4114B for ; Tue, 22 Feb 2022 20:36:10 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21MIavh3019942 for ; Tue, 22 Feb 2022 11:36:10 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=+W7gnLrY56dNbrK/QoTuDdzkuuWbjq5ybeuGTAYaRJM=; b=K0dbNR7k3kJFhV77zGVSuzJ29gfO4/EdZi3Xik6T+/3UhCQd2FunFvjsPW+OwEgnjx66 AGSE4Gd6p/0ja4jhw89Anl8skrJZLPjV08Pi5DRC0a6b5l8oISxjhmdhvIwZoDRxPhNs L01+DbrwfD4PqStbt0WStK4AYFW6U5wwEJn2oFaw0s85VdzEtCk76FyFkvjoMbt3ebYB KwwPNL05/5AOvuTVMTX/oDhmFoDfFC9ju+K1ywaTdRgOd2k/CxmNyks0+9fyW2KjOWwX OAfypeDQlLLwFIYFgGRxR9e+de91ylDdkPGA/5ZKZ2PrezpcRvsfMFRf6bE5nI1Cbko3 TA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3ecwaxar5e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 22 Feb 2022 11:36:10 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 22 Feb 2022 11:36:08 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 22 Feb 2022 11:36:08 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 8B1333F7081; Tue, 22 Feb 2022 11:36:06 -0800 (PST) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Harman Kalra Subject: [PATCH v2 18/21] net/cnxk: enable flow control by default on device configure Date: Wed, 23 Feb 2022 01:05:09 +0530 Message-ID: <20220222193512.19292-18-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220222193512.19292-1-ndabilpuram@marvell.com> References: <20220207072932.22409-1-ndabilpuram@marvell.com> <20220222193512.19292-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: kKheCkoJxkMNtxsE4Hh3p1mCOklg2xPu X-Proofpoint-ORIG-GUID: kKheCkoJxkMNtxsE4Hh3p1mCOklg2xPu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-22_06,2022-02-21_02,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable flow control by default on device configuration instead of basing it on Kernel behaviour. Signed-off-by: Nithin Dabilpuram Signed-off-by: Harman Kalra --- drivers/net/cnxk/cnxk_ethdev.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index ad1e63d..9481af9 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -306,24 +306,22 @@ static int nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev) { struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + enum roc_nix_fc_mode fc_mode = ROC_NIX_FC_FULL; struct cnxk_fc_cfg *fc = &dev->fc_cfg; - struct rte_eth_fc_conf fc_conf = {0}; int rc; - /* Both Rx & Tx flow ctrl get enabled(RTE_ETH_FC_FULL) in HW - * by AF driver, update those info in PMD structure. - */ - rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf); + /* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */ + if (roc_model_is_cn96_ax() && + dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG) + fc_mode = ROC_NIX_FC_TX; + + /* By default enable flow control */ + rc = roc_nix_fc_mode_set(&dev->nix, fc_mode); if (rc) - goto exit; + return rc; - fc->mode = fc_conf.mode; - fc->rx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) || - (fc_conf.mode == RTE_ETH_FC_RX_PAUSE); - fc->tx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) || - (fc_conf.mode == RTE_ETH_FC_TX_PAUSE); - -exit: + fc->mode = (fc_mode == ROC_NIX_FC_FULL) ? RTE_ETH_FC_FULL : + RTE_ETH_FC_TX_PAUSE; return rc; } -- 2.8.4