From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EDA0AA00C2; Wed, 23 Feb 2022 19:49:16 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D9C3341165; Wed, 23 Feb 2022 19:48:57 +0100 (CET) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2077.outbound.protection.outlook.com [40.107.236.77]) by mails.dpdk.org (Postfix) with ESMTP id A163E4115E for ; Wed, 23 Feb 2022 19:48:55 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WaalDSLMithJDEERZw9gy8MypTY0Xw5XdoMew/VPl6qOrEmqiH02v1NECpSxR4jQNbN3ewWzohPUqDuAUEx20p5b6zWYpIY2Shlv2a5trjaH6rwjhVECqKjMZOlL7Gzevua6/Q6Jba3Y9DqfwaWPX9xNxvf1oz0xvA+O05xXunA+oP8dLnBGoWebRXiQ1mdv7JtFGy+DzLhJM9nG/fuvmV2pW/1QKLNaDAXv7LIviNzRWaEUxTgTbccZ6m1+5jZLFFtTNrQKmZC+Cb99PCBJUoXL7c+x02PeAW+OXCDl12jcwyvkDPk+HQwqLvku+h7LEK+1oEQiQxY/LRyqmutYOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=p70WpVmnbax1+bBZOf0etrDM6JmIuLIvew8AdQHRuJk=; b=SyGmxbziiDULfKtGXhNA80cPg1FzjPypwHi3u9EGD/BoNpRoJTn6ZmxvJFaFxqqZqFCDAjrvJqYCk0rj5HIHird7scxgd3hLs8nx1fj12hvUkzCnD7C6ZoQQVSi9Uy7gsHZQDOTa2J5jYuWPJYQ/6ccIggSal8uH84w8QxmwBiFQoBCXUDAvM9Tor6scvIuBNr7D+4WAEr4RM0mC5dyIAc5uunG0DdDrVoVBUKn9YBc9GjxF/UNWeAKd2HQCJVkQ+ykWnCYnl9KfrqkLpfkoSbvbSLpT11U18CrARKtrRQvnu3SFtkB50aGrJ5F7cnkZJRktBzvCcogOeNyrsUvorQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=p70WpVmnbax1+bBZOf0etrDM6JmIuLIvew8AdQHRuJk=; b=dbnDtEReKHu982VgEtc9Ijeju8Ogp4TdqzYxdwysTX784k+Ecu2j+4qQliKCKFlxuO1+wePFRZyVJzGwZlMfPU4JXXNpbsHc/vKZPhNNIutd80ZXhBw005J9E+LdwsLP5OEz70iLXgohEPZ9yJ3SQRNZjTyJ2dWL6YwYgCvXQqZX0B7S3fP/RwaooO8838Ko6fq+EZp3QhDNkjCYxsUdWxC/W/sEBlYip7IIPTotFeSU07RA1L5MYgflR69H5airgyearSwYiYpbW7xUiNYN5W8s6Rp1Vjh8Kw3p+hx+WtTsg9yAN2+bWu4H6ckK6bSKsHO+L+d/Q4hPBl/0YTobcw== Received: from DS7PR03CA0038.namprd03.prod.outlook.com (2603:10b6:5:3b5::13) by BY5PR12MB4872.namprd12.prod.outlook.com (2603:10b6:a03:1c4::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5017.21; Wed, 23 Feb 2022 18:48:53 +0000 Received: from DM6NAM11FT045.eop-nam11.prod.protection.outlook.com (2603:10b6:5:3b5:cafe::7e) by DS7PR03CA0038.outlook.office365.com (2603:10b6:5:3b5::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5017.23 via Frontend Transport; Wed, 23 Feb 2022 18:48:53 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.236) by DM6NAM11FT045.mail.protection.outlook.com (10.13.173.123) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5017.22 via Frontend Transport; Wed, 23 Feb 2022 18:48:53 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 23 Feb 2022 18:48:52 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Wed, 23 Feb 2022 10:48:51 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9 via Frontend Transport; Wed, 23 Feb 2022 10:48:50 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko Subject: [PATCH v2 5/6] net/mlx5: add external RxQ mapping API Date: Wed, 23 Feb 2022 20:48:34 +0200 Message-ID: <20220223184835.3061161-6-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223184835.3061161-1-michaelba@nvidia.com> References: <20220222210416.2669519-1-michaelba@nvidia.com> <20220223184835.3061161-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 778b0b6a-53e3-48b3-6b99-08d9f6fd2392 X-MS-TrafficTypeDiagnostic: BY5PR12MB4872:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: z/9eop/vtjqX9jBi8QUjFWrnIDPRX1iVcQ3e0q2f5nell41xo5EWUV0AFphKydSL2u1HjLUg2XMA4QJcmh9P4stO0GlCPektggXumXYiFCjKibAf+aHy1BkHIBTGt9Ww6IY+TZMbE/U7gtiITov78ZOoWgGJnHF1CYpBItS3Te1ubYibE+eX60wypAOB+/NBYukV+xwJoKCG2O/pSJB+FfyF2q7r+k12hxP0e/xd95HUPd9aVBF45rnYEn0x4/3gRIUOmB/m6spoX92WhGmBGpr3cWaoCr7YrkJKcPjJYTZUZHMkXYxWbZpSw/nATGwHPO9whxD74CPzS1PJCysCBcy8nc1hZg58L0odORdDW7DRnFNSRpykyCpuTSH/e+TnkdOJq2j/NdIvcSUZ9XzkD4jEgsjsqbzdSv7zRieUHI/eHdRSYmv4mHycDWJf/6Y5RNCANniSBO5Y4b/g2dlC5oIkn4lCjQPyFGuLvV3+OcDfwSJQo4meXh/37HkE0MrCsOmWb4nKmF3y3KdLKDLzY5UKAXAct95XAzy96hflvA8JRpnPuPPSD0gVkWgbi4CHu/vorL+x9zbVmujcz8zsoUShgyGGVV6UakzbCpWDLPQ1AhqDbztJLnVqo3S3US5JJpJfCax6QKxdNkpQkFD1y9N6HFhNdDVFH/s8FACWH0pYL8bEOXy1jygkSRtKaFwFvoklPb54Ab7BQF+3hVTWZQ== X-Forefront-Antispam-Report: CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(7696005)(30864003)(2906002)(70586007)(8936002)(5660300002)(508600001)(1076003)(86362001)(40460700003)(2616005)(70206006)(107886003)(6666004)(82310400004)(8676002)(4326008)(6916009)(186003)(54906003)(356005)(81166007)(36860700001)(316002)(6286002)(336012)(426003)(26005)(55016003)(83380400001)(36756003)(47076005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2022 18:48:53.2343 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 778b0b6a-53e3-48b3-6b99-08d9f6fd2392 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4872 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org External queue is a queue that has been created and managed outside the PMD. The queues owner might use PMD to generate flow rules using these external queues. When the queue is created in hardware it is given an ID represented by 32 bits. In contrast, the index of the queues in PMD is represented by 16 bits. To enable the use of PMD to generate flow rules, the queue owner must provide a mapping between the HW index and a 16-bit index corresponding to the RTE Flow API. This patch adds an API enabling to insert/cancel a mapping between HW queue id and RTE Flow queue id. Signed-off-by: Michael Baum --- drivers/net/mlx5/linux/mlx5_os.c | 18 +++++ drivers/net/mlx5/mlx5.c | 2 + drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_defs.h | 3 + drivers/net/mlx5/mlx5_ethdev.c | 16 ++++- drivers/net/mlx5/mlx5_rx.h | 6 ++ drivers/net/mlx5/mlx5_rxq.c | 109 +++++++++++++++++++++++++++++++ drivers/net/mlx5/rte_pmd_mlx5.h | 50 +++++++++++++- drivers/net/mlx5/version.map | 3 + 9 files changed, 204 insertions(+), 4 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index ecf823da56..058c140fe1 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1156,6 +1156,22 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, err = ENOMEM; goto error; } + /* + * When user configures remote PD and CTX and device creates RxQ by + * DevX, external RxQ is both supported and requested. + */ + if (mlx5_imported_pd_and_ctx(sh->cdev) && mlx5_devx_obj_ops_en(sh)) { + priv->ext_rxqs = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, + sizeof(struct mlx5_external_rxq) * + MLX5_MAX_EXT_RX_QUEUES, 0, + SOCKET_ID_ANY); + if (priv->ext_rxqs == NULL) { + DRV_LOG(ERR, "Fail to allocate external RxQ array."); + err = ENOMEM; + goto error; + } + DRV_LOG(DEBUG, "External RxQ is supported."); + } priv->sh = sh; priv->dev_port = spawn->phys_port; priv->pci_dev = spawn->pci_dev; @@ -1613,6 +1629,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, mlx5_list_destroy(priv->hrxqs); if (eth_dev && priv->flex_item_map) mlx5_flex_item_port_cleanup(eth_dev); + if (priv->ext_rxqs) + mlx5_free(priv->ext_rxqs); mlx5_free(priv); if (eth_dev != NULL) eth_dev->data->dev_private = NULL; diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 9f65a8f901..415e0fe2f2 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1855,6 +1855,8 @@ mlx5_dev_close(struct rte_eth_dev *dev) close(priv->nl_socket_rdma); if (priv->vmwa_context) mlx5_vlan_vmwa_exit(priv->vmwa_context); + if (priv->ext_rxqs) + mlx5_free(priv->ext_rxqs); ret = mlx5_hrxq_verify(dev); if (ret) DRV_LOG(WARNING, "port %u some hash Rx queue still remain", diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 0f465d0e9e..fa27f65a36 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1423,6 +1423,7 @@ struct mlx5_priv { /* RX/TX queues. */ unsigned int rxqs_n; /* RX queues array size. */ unsigned int txqs_n; /* TX queues array size. */ + struct mlx5_external_rxq *ext_rxqs; /* External RX queues array. */ struct mlx5_rxq_priv *(*rxq_privs)[]; /* RX queue non-shared data. */ struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h index 2d48fde010..15728fb41f 100644 --- a/drivers/net/mlx5/mlx5_defs.h +++ b/drivers/net/mlx5/mlx5_defs.h @@ -175,6 +175,9 @@ /* Maximum number of indirect actions supported by rte_flow */ #define MLX5_MAX_INDIRECT_ACTIONS 3 +/* Maximum number of external Rx queues supported by rte_flow */ +#define MLX5_MAX_EXT_RX_QUEUES (UINT16_MAX - MLX5_EXTERNAL_RX_QUEUE_ID_MIN + 1) + /* * Linux definition of static_assert is found in /usr/include/assert.h. * Windows does not require a redefinition. diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index 406761ccf8..de0ba2b1ff 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -27,6 +27,7 @@ #include "mlx5_tx.h" #include "mlx5_autoconf.h" #include "mlx5_devx.h" +#include "rte_pmd_mlx5.h" /** * Get the interface index from device name. @@ -81,9 +82,10 @@ mlx5_dev_configure(struct rte_eth_dev *dev) rte_errno = EINVAL; return -rte_errno; } - priv->rss_conf.rss_key = - mlx5_realloc(priv->rss_conf.rss_key, MLX5_MEM_RTE, - MLX5_RSS_HASH_KEY_LEN, 0, SOCKET_ID_ANY); + priv->rss_conf.rss_key = mlx5_realloc(priv->rss_conf.rss_key, + MLX5_MEM_RTE, + MLX5_RSS_HASH_KEY_LEN, 0, + SOCKET_ID_ANY); if (!priv->rss_conf.rss_key) { DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory (%u)", dev->data->port_id, rxqs_n); @@ -127,6 +129,14 @@ mlx5_dev_configure(struct rte_eth_dev *dev) rte_errno = EINVAL; return -rte_errno; } + if (priv->ext_rxqs && rxqs_n >= MLX5_EXTERNAL_RX_QUEUE_ID_MIN) { + DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u), " + "the maximal number of internal Rx queues is %u", + dev->data->port_id, rxqs_n, + MLX5_EXTERNAL_RX_QUEUE_ID_MIN - 1); + rte_errno = EINVAL; + return -rte_errno; + } if (rxqs_n != priv->rxqs_n) { DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u", dev->data->port_id, priv->rxqs_n, rxqs_n); diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index 1fdf4ff161..754c526464 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -175,6 +175,12 @@ struct mlx5_rxq_priv { uint32_t hairpin_status; /* Hairpin binding status. */ }; +/* External RX queue descriptor. */ +struct mlx5_external_rxq { + uint32_t hw_id; /* Queue index in the Hardware. */ + uint32_t refcnt; /* Reference counter. */ +}; + /* mlx5_rxq.c */ extern uint8_t rss_hash_default_key[]; diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 796497ab1a..145da2dbbb 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -30,6 +30,7 @@ #include "mlx5_utils.h" #include "mlx5_autoconf.h" #include "mlx5_devx.h" +#include "rte_pmd_mlx5.h" /* Default RSS hash key also used for ConnectX-3. */ @@ -2983,3 +2984,111 @@ mlx5_rxq_timestamp_set(struct rte_eth_dev *dev) data->rt_timestamp = sh->dev_cap.rt_timestamp; } } + +/** + * Validate given external RxQ rte_plow index, and get pointer to concurrent + * external RxQ object to map/unmap. + * + * @param[in] port_id + * The port identifier of the Ethernet device. + * @param[in] dpdk_idx + * Queue index in rte_flow. + * + * @return + * Pointer to concurrent external RxQ on success, + * NULL otherwise and rte_errno is set. + */ +static struct mlx5_external_rxq * +mlx5_external_rx_queue_get_validate(uint16_t port_id, uint16_t dpdk_idx) +{ + struct rte_eth_dev *dev; + struct mlx5_priv *priv; + + if (dpdk_idx < MLX5_EXTERNAL_RX_QUEUE_ID_MIN) { + DRV_LOG(ERR, "Queue index %u should be in range: [%u, %u].", + dpdk_idx, MLX5_EXTERNAL_RX_QUEUE_ID_MIN, UINT16_MAX); + rte_errno = EINVAL; + return NULL; + } + if (rte_eth_dev_is_valid_port(port_id) < 0) { + DRV_LOG(ERR, "There is no Ethernet device for port %u.", + port_id); + rte_errno = ENODEV; + return NULL; + } + dev = &rte_eth_devices[port_id]; + priv = dev->data->dev_private; + if (!mlx5_imported_pd_and_ctx(priv->sh->cdev)) { + DRV_LOG(ERR, "Port %u " + "external RxQ isn't supported on local PD and CTX.", + port_id); + rte_errno = ENOTSUP; + return NULL; + } + if (!mlx5_devx_obj_ops_en(priv->sh)) { + DRV_LOG(ERR, + "Port %u external RxQ isn't supported by Verbs API.", + port_id); + rte_errno = ENOTSUP; + return NULL; + } + /* + * When user configures remote PD and CTX and device creates RxQ by + * DevX, external RxQs array is allocated. + */ + MLX5_ASSERT(priv->ext_rxqs != NULL); + return &priv->ext_rxqs[dpdk_idx - MLX5_EXTERNAL_RX_QUEUE_ID_MIN]; +} + +int +rte_pmd_mlx5_external_rx_queue_id_map(uint16_t port_id, uint16_t dpdk_idx, + uint32_t hw_idx) +{ + struct mlx5_external_rxq *ext_rxq; + + ext_rxq = mlx5_external_rx_queue_get_validate(port_id, dpdk_idx); + if (ext_rxq == NULL) + return -rte_errno; + if (__atomic_load_n(&ext_rxq->refcnt, __ATOMIC_RELAXED)) { + if (ext_rxq->hw_id != hw_idx) { + DRV_LOG(ERR, "Port %u external RxQ index %u " + "is already mapped to HW index (requesting is " + "%u, existing is %u).", + port_id, dpdk_idx, hw_idx, ext_rxq->hw_id); + rte_errno = EEXIST; + return -rte_errno; + } + DRV_LOG(WARNING, "Port %u external RxQ index %u " + "is already mapped to the requested HW index (%u)", + port_id, dpdk_idx, hw_idx); + + } else { + ext_rxq->hw_id = hw_idx; + __atomic_store_n(&ext_rxq->refcnt, 1, __ATOMIC_RELAXED); + DRV_LOG(DEBUG, "Port %u external RxQ index %u " + "is successfully mapped to the requested HW index (%u)", + port_id, dpdk_idx, hw_idx); + } + return 0; +} + +int +rte_pmd_mlx5_external_rx_queue_id_unmap(uint16_t port_id, uint16_t dpdk_idx) +{ + struct mlx5_external_rxq *ext_rxq; + + ext_rxq = mlx5_external_rx_queue_get_validate(port_id, dpdk_idx); + if (ext_rxq == NULL) + return -rte_errno; + if (__atomic_load_n(&ext_rxq->refcnt, __ATOMIC_RELAXED) == 0) { + DRV_LOG(ERR, "Port %u external RxQ index %u doesn't exist.", + port_id, dpdk_idx); + rte_errno = EINVAL; + return -rte_errno; + } + __atomic_store_n(&ext_rxq->refcnt, 0, __ATOMIC_RELAXED); + DRV_LOG(DEBUG, + "Port %u external RxQ index %u is successfully unmapped.", + port_id, dpdk_idx); + return 0; +} diff --git a/drivers/net/mlx5/rte_pmd_mlx5.h b/drivers/net/mlx5/rte_pmd_mlx5.h index fc37a386db..92dc447648 100644 --- a/drivers/net/mlx5/rte_pmd_mlx5.h +++ b/drivers/net/mlx5/rte_pmd_mlx5.h @@ -61,8 +61,56 @@ int rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n); __rte_experimental int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains); +/** + * External Rx queue rte_flow index minimal value. + */ +#define MLX5_EXTERNAL_RX_QUEUE_ID_MIN (UINT16_MAX - 1000 + 1) + +/** + * Update mapping between rte_flow queue index (16 bits) and HW queue index (32 + * bits) for RxQs which is created outside the PMD. + * + * @param[in] port_id + * The port identifier of the Ethernet device. + * @param[in] dpdk_idx + * Queue index in rte_flow. + * @param[in] hw_idx + * Queue index in hardware. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + * Possible values for rte_errno: + * - EEXIST - a mapping with the same rte_flow index already exists. + * - EINVAL - invalid rte_flow index, out of range. + * - ENODEV - there is no Ethernet device for this port id. + * - ENOTSUP - the port doesn't support external RxQ. + */ +__rte_experimental +int rte_pmd_mlx5_external_rx_queue_id_map(uint16_t port_id, uint16_t dpdk_idx, + uint32_t hw_idx); + +/** + * Remove mapping between rte_flow queue index (16 bits) and HW queue index (32 + * bits) for RxQs which is created outside the PMD. + * + * @param[in] port_id + * The port identifier of the Ethernet device. + * @param[in] dpdk_idx + * Queue index in rte_flow. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + * Possible values for rte_errno: + * - EINVAL - invalid index, out of range or doesn't exist. + * - ENODEV - there is no Ethernet device for this port id. + * - ENOTSUP - the port doesn't support external RxQ. + */ +__rte_experimental +int rte_pmd_mlx5_external_rx_queue_id_unmap(uint16_t port_id, + uint16_t dpdk_idx); + #ifdef __cplusplus } #endif -#endif +#endif /* RTE_PMD_PRIVATE_MLX5_H_ */ diff --git a/drivers/net/mlx5/version.map b/drivers/net/mlx5/version.map index 0af7a12488..79cb79acc6 100644 --- a/drivers/net/mlx5/version.map +++ b/drivers/net/mlx5/version.map @@ -9,4 +9,7 @@ EXPERIMENTAL { rte_pmd_mlx5_get_dyn_flag_names; # added in 20.11 rte_pmd_mlx5_sync_flow; + # added in 22.03 + rte_pmd_mlx5_external_rx_queue_id_map; + rte_pmd_mlx5_external_rx_queue_id_unmap; }; -- 2.25.1