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* [PATCH] common/cnxk: support B0 variant
@ 2022-02-24 10:42 Tomasz Duszynski
  2022-02-24 20:35 ` Jerin Jacob
  2022-02-25 10:34 ` [dpdk-dev] [PATCH v2] common/cnxk: support CNF95xx " Tomasz Duszynski
  0 siblings, 2 replies; 5+ messages in thread
From: Tomasz Duszynski @ 2022-02-24 10:42 UTC (permalink / raw)
  To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
  Cc: thomas, jerinj, Tomasz Duszynski

Add B0 variant to the list of supported models.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_model.c | 1 +
 drivers/common/cnxk/roc_model.h | 6 ++++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
index 49617c02b7..4120029541 100644
--- a/drivers/common/cnxk/roc_model.c
+++ b/drivers/common/cnxk/roc_model.c
@@ -56,6 +56,7 @@ static const struct model_db {
 	{VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
 	{VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"},
 	{VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"},
+	{VENDOR_CAVIUM, PART_95xxN, 1, 0, ROC_MODEL_CNF95xxN_B0, "cnf95xxn_b0"},
 	{VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"},
 	{VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
 	 "cnf95xxmm_a0"}};
diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
index cee06779bc..4567566169 100644
--- a/drivers/common/cnxk/roc_model.h
+++ b/drivers/common/cnxk/roc_model.h
@@ -19,6 +19,7 @@ struct roc_model {
 #define ROC_MODEL_CNF95xxN_A0  BIT_ULL(12)
 #define ROC_MODEL_CNF95xxO_A0  BIT_ULL(13)
 #define ROC_MODEL_CNF95xxN_A1  BIT_ULL(14)
+#define ROC_MODEL_CNF95xxN_B0  BIT_ULL(15)
 #define ROC_MODEL_CN98xx_A0    BIT_ULL(16)
 #define ROC_MODEL_CN106xx_A0   BIT_ULL(20)
 #define ROC_MODEL_CNF105xx_A0  BIT_ULL(21)
@@ -39,11 +40,12 @@ struct roc_model {
 	(ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 |    \
 	 ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 |                       \
 	 ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \
-	 ROC_MODEL_CNF95xxN_A1)
+	 ROC_MODEL_CNF95xxN_A1 | ROC_MODEL_CNF95xxN_B0)
 #define ROC_MODEL_CNF9K                                                        \
 	(ROC_MODEL_CNF95xx_A0 | ROC_MODEL_CNF95xx_B0 |                         \
 	 ROC_MODEL_CNF95xxMM_A0 | ROC_MODEL_CNF95xxO_A0 |                      \
-	 ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1)
+	 ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1 |                       \
+	 ROC_MODEL_CNF95xxN_B0)
 
 #define ROC_MODEL_CN106xx   (ROC_MODEL_CN106xx_A0)
 #define ROC_MODEL_CNF105xx  (ROC_MODEL_CNF105xx_A0)
-- 
2.25.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] common/cnxk: support B0 variant
  2022-02-24 10:42 [PATCH] common/cnxk: support B0 variant Tomasz Duszynski
@ 2022-02-24 20:35 ` Jerin Jacob
  2022-02-25 10:03   ` Ferruh Yigit
  2022-02-25 10:34 ` [dpdk-dev] [PATCH v2] common/cnxk: support CNF95xx " Tomasz Duszynski
  1 sibling, 1 reply; 5+ messages in thread
From: Jerin Jacob @ 2022-02-24 20:35 UTC (permalink / raw)
  To: Tomasz Duszynski
  Cc: dpdk-dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
	Satha Rao, Thomas Monjalon, Jerin Jacob

On Thu, Feb 24, 2022 at 4:13 PM Tomasz Duszynski <tduszynski@marvell.com> wrote:
>
> Add B0 variant to the list of supported models.
>
> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
> Reviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>

Updated the git commit as follows and applied to
dpdk-next-net-mrvl/for-next-net. Thanks

    common/cnxk: support CNF95xx B0 variant

    Add CNF95xx B0 variant to the list of supported models.

    Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
    Reviewed-by: Jerin Jacob <jerinj@marvell.com>


>  drivers/common/cnxk/roc_model.c | 1 +
>  drivers/common/cnxk/roc_model.h | 6 ++++--
>  2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
> index 49617c02b7..4120029541 100644
> --- a/drivers/common/cnxk/roc_model.c
> +++ b/drivers/common/cnxk/roc_model.c
> @@ -56,6 +56,7 @@ static const struct model_db {
>         {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
>         {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"},
>         {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"},
> +       {VENDOR_CAVIUM, PART_95xxN, 1, 0, ROC_MODEL_CNF95xxN_B0, "cnf95xxn_b0"},
>         {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"},
>         {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
>          "cnf95xxmm_a0"}};
> diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
> index cee06779bc..4567566169 100644
> --- a/drivers/common/cnxk/roc_model.h
> +++ b/drivers/common/cnxk/roc_model.h
> @@ -19,6 +19,7 @@ struct roc_model {
>  #define ROC_MODEL_CNF95xxN_A0  BIT_ULL(12)
>  #define ROC_MODEL_CNF95xxO_A0  BIT_ULL(13)
>  #define ROC_MODEL_CNF95xxN_A1  BIT_ULL(14)
> +#define ROC_MODEL_CNF95xxN_B0  BIT_ULL(15)
>  #define ROC_MODEL_CN98xx_A0    BIT_ULL(16)
>  #define ROC_MODEL_CN106xx_A0   BIT_ULL(20)
>  #define ROC_MODEL_CNF105xx_A0  BIT_ULL(21)
> @@ -39,11 +40,12 @@ struct roc_model {
>         (ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 |    \
>          ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 |                       \
>          ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \
> -        ROC_MODEL_CNF95xxN_A1)
> +        ROC_MODEL_CNF95xxN_A1 | ROC_MODEL_CNF95xxN_B0)
>  #define ROC_MODEL_CNF9K                                                        \
>         (ROC_MODEL_CNF95xx_A0 | ROC_MODEL_CNF95xx_B0 |                         \
>          ROC_MODEL_CNF95xxMM_A0 | ROC_MODEL_CNF95xxO_A0 |                      \
> -        ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1)
> +        ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1 |                       \
> +        ROC_MODEL_CNF95xxN_B0)
>
>  #define ROC_MODEL_CN106xx   (ROC_MODEL_CN106xx_A0)
>  #define ROC_MODEL_CNF105xx  (ROC_MODEL_CNF105xx_A0)
> --
> 2.25.1
>

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] common/cnxk: support B0 variant
  2022-02-24 20:35 ` Jerin Jacob
@ 2022-02-25 10:03   ` Ferruh Yigit
  0 siblings, 0 replies; 5+ messages in thread
From: Ferruh Yigit @ 2022-02-25 10:03 UTC (permalink / raw)
  To: Jerin Jacob, Tomasz Duszynski
  Cc: dpdk-dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
	Satha Rao, Thomas Monjalon, Jerin Jacob

On 2/24/2022 8:35 PM, Jerin Jacob wrote:
> On Thu, Feb 24, 2022 at 4:13 PM Tomasz Duszynski <tduszynski@marvell.com> wrote:
>>
>> Add B0 variant to the list of supported models.
>>
>> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
>> Reviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> 
> Updated the git commit as follows and applied to
> dpdk-next-net-mrvl/for-next-net. Thanks
> 
>      common/cnxk: support CNF95xx B0 variant
> 
>      Add CNF95xx B0 variant to the list of supported models.
> 
>      Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
>      Reviewed-by: Jerin Jacob <jerinj@marvell.com>
> 
> 
>>   drivers/common/cnxk/roc_model.c | 1 +
>>   drivers/common/cnxk/roc_model.h | 6 ++++--
>>   2 files changed, 5 insertions(+), 2 deletions(-)

Hi Jerin, Tomasz,

Can you please update release note to document this new
device support? (Although it is still B0, some users may be
interested in with the new device support.)


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [dpdk-dev] [PATCH v2] common/cnxk: support CNF95xx B0 variant
  2022-02-24 10:42 [PATCH] common/cnxk: support B0 variant Tomasz Duszynski
  2022-02-24 20:35 ` Jerin Jacob
@ 2022-02-25 10:34 ` Tomasz Duszynski
  2022-02-25 10:36   ` Jerin Jacob
  1 sibling, 1 reply; 5+ messages in thread
From: Tomasz Duszynski @ 2022-02-25 10:34 UTC (permalink / raw)
  To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
  Cc: ferruh.yigit, Tomasz Duszynski, Jerin Jacob

Add CNF95xx B0 variant to the list of supported models.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
v2:
- Update release notes for new device support (Ferruh)

 doc/guides/rel_notes/release_22_03.rst | 1 +
 drivers/common/cnxk/roc_model.c        | 1 +
 drivers/common/cnxk/roc_model.h        | 6 ++++--
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst
index 54563106d1..43c4db65c3 100644
--- a/doc/guides/rel_notes/release_22_03.rst
+++ b/doc/guides/rel_notes/release_22_03.rst
@@ -135,6 +135,7 @@ New Features
   * Added queue based priority flow control support for CN9K & CN10K.
   * Added support for IP reassembly for inline inbound IPsec packets.
   * Added support for packet marking in traffic manager.
+  * Added support for CNF95xx B0 variant SoC.

 * **Added an API for private user data in asymmetric crypto session.**

diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
index 49617c02b7..4120029541 100644
--- a/drivers/common/cnxk/roc_model.c
+++ b/drivers/common/cnxk/roc_model.c
@@ -56,6 +56,7 @@ static const struct model_db {
 	{VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
 	{VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"},
 	{VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"},
+	{VENDOR_CAVIUM, PART_95xxN, 1, 0, ROC_MODEL_CNF95xxN_B0, "cnf95xxn_b0"},
 	{VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"},
 	{VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
 	 "cnf95xxmm_a0"}};
diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
index cee06779bc..4567566169 100644
--- a/drivers/common/cnxk/roc_model.h
+++ b/drivers/common/cnxk/roc_model.h
@@ -19,6 +19,7 @@ struct roc_model {
 #define ROC_MODEL_CNF95xxN_A0  BIT_ULL(12)
 #define ROC_MODEL_CNF95xxO_A0  BIT_ULL(13)
 #define ROC_MODEL_CNF95xxN_A1  BIT_ULL(14)
+#define ROC_MODEL_CNF95xxN_B0  BIT_ULL(15)
 #define ROC_MODEL_CN98xx_A0    BIT_ULL(16)
 #define ROC_MODEL_CN106xx_A0   BIT_ULL(20)
 #define ROC_MODEL_CNF105xx_A0  BIT_ULL(21)
@@ -39,11 +40,12 @@ struct roc_model {
 	(ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 |    \
 	 ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 |                       \
 	 ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \
-	 ROC_MODEL_CNF95xxN_A1)
+	 ROC_MODEL_CNF95xxN_A1 | ROC_MODEL_CNF95xxN_B0)
 #define ROC_MODEL_CNF9K                                                        \
 	(ROC_MODEL_CNF95xx_A0 | ROC_MODEL_CNF95xx_B0 |                         \
 	 ROC_MODEL_CNF95xxMM_A0 | ROC_MODEL_CNF95xxO_A0 |                      \
-	 ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1)
+	 ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1 |                       \
+	 ROC_MODEL_CNF95xxN_B0)

 #define ROC_MODEL_CN106xx   (ROC_MODEL_CN106xx_A0)
 #define ROC_MODEL_CNF105xx  (ROC_MODEL_CNF105xx_A0)
--
2.35.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [dpdk-dev] [PATCH v2] common/cnxk: support CNF95xx B0 variant
  2022-02-25 10:34 ` [dpdk-dev] [PATCH v2] common/cnxk: support CNF95xx " Tomasz Duszynski
@ 2022-02-25 10:36   ` Jerin Jacob
  0 siblings, 0 replies; 5+ messages in thread
From: Jerin Jacob @ 2022-02-25 10:36 UTC (permalink / raw)
  To: Tomasz Duszynski
  Cc: dpdk-dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
	Satha Rao, Ferruh Yigit, Jerin Jacob

On Fri, Feb 25, 2022 at 4:04 PM Tomasz Duszynski <tduszynski@marvell.com> wrote:
>
> Add CNF95xx B0 variant to the list of supported models.
>
> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
> Reviewed-by: Jerin Jacob <jerinj@marvell.com>
> ---
> v2:
> - Update release notes for new device support (Ferruh)


Applied to dpdk-next-net-mrvl/for-next-net. Thanks


>
>  doc/guides/rel_notes/release_22_03.rst | 1 +
>  drivers/common/cnxk/roc_model.c        | 1 +
>  drivers/common/cnxk/roc_model.h        | 6 ++++--
>  3 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst
> index 54563106d1..43c4db65c3 100644
> --- a/doc/guides/rel_notes/release_22_03.rst
> +++ b/doc/guides/rel_notes/release_22_03.rst
> @@ -135,6 +135,7 @@ New Features
>    * Added queue based priority flow control support for CN9K & CN10K.
>    * Added support for IP reassembly for inline inbound IPsec packets.
>    * Added support for packet marking in traffic manager.
> +  * Added support for CNF95xx B0 variant SoC.
>
>  * **Added an API for private user data in asymmetric crypto session.**
>
> diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
> index 49617c02b7..4120029541 100644
> --- a/drivers/common/cnxk/roc_model.c
> +++ b/drivers/common/cnxk/roc_model.c
> @@ -56,6 +56,7 @@ static const struct model_db {
>         {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
>         {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"},
>         {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"},
> +       {VENDOR_CAVIUM, PART_95xxN, 1, 0, ROC_MODEL_CNF95xxN_B0, "cnf95xxn_b0"},
>         {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"},
>         {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
>          "cnf95xxmm_a0"}};
> diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
> index cee06779bc..4567566169 100644
> --- a/drivers/common/cnxk/roc_model.h
> +++ b/drivers/common/cnxk/roc_model.h
> @@ -19,6 +19,7 @@ struct roc_model {
>  #define ROC_MODEL_CNF95xxN_A0  BIT_ULL(12)
>  #define ROC_MODEL_CNF95xxO_A0  BIT_ULL(13)
>  #define ROC_MODEL_CNF95xxN_A1  BIT_ULL(14)
> +#define ROC_MODEL_CNF95xxN_B0  BIT_ULL(15)
>  #define ROC_MODEL_CN98xx_A0    BIT_ULL(16)
>  #define ROC_MODEL_CN106xx_A0   BIT_ULL(20)
>  #define ROC_MODEL_CNF105xx_A0  BIT_ULL(21)
> @@ -39,11 +40,12 @@ struct roc_model {
>         (ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 |    \
>          ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 |                       \
>          ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \
> -        ROC_MODEL_CNF95xxN_A1)
> +        ROC_MODEL_CNF95xxN_A1 | ROC_MODEL_CNF95xxN_B0)
>  #define ROC_MODEL_CNF9K                                                        \
>         (ROC_MODEL_CNF95xx_A0 | ROC_MODEL_CNF95xx_B0 |                         \
>          ROC_MODEL_CNF95xxMM_A0 | ROC_MODEL_CNF95xxO_A0 |                      \
> -        ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1)
> +        ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1 |                       \
> +        ROC_MODEL_CNF95xxN_B0)
>
>  #define ROC_MODEL_CN106xx   (ROC_MODEL_CN106xx_A0)
>  #define ROC_MODEL_CNF105xx  (ROC_MODEL_CNF105xx_A0)
> --
> 2.35.1
>

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2022-02-25 10:36 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-24 10:42 [PATCH] common/cnxk: support B0 variant Tomasz Duszynski
2022-02-24 20:35 ` Jerin Jacob
2022-02-25 10:03   ` Ferruh Yigit
2022-02-25 10:34 ` [dpdk-dev] [PATCH v2] common/cnxk: support CNF95xx " Tomasz Duszynski
2022-02-25 10:36   ` Jerin Jacob

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