From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B0B5BA034C; Thu, 24 Feb 2022 19:29:22 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 15F624114F; Thu, 24 Feb 2022 19:29:18 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 70F1641153 for ; Thu, 24 Feb 2022 19:29:17 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21OH1cGp019458; Thu, 24 Feb 2022 10:29:16 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=BWTsuCv29cNtjyhD9S9iCr6IFc5st363NT8LteT0zk4=; b=e4yV7qASuno+IEMy3AD0YbY+bYECT0k4RZVV2OX6t3nPkNHvZt7EUMmlzoGfIS3htce0 hn3sHblp8+WGfMPN3/aE4UYcIljXTkXiK1DmxnLmJ7WAAYHyeRWk2jzrqrA1m/bBT3lo Xev5B5Cwh6z06SlRxD424r4hvZ85mr+P0kwMzXM2iW1Tw1b01Y6ElOP9uVyo7XUk9ZPh 8bKt+Uw/Ax8exe6snT6BpB5vUkcwJ65VgVK7P79RsTOcEBZaBBRiS+RF78afQJQLFwQj NrGCsvWhMd2BU8uCPORcn4kbFR8Pmly9dVIUqX0r1zRdHl0LdM2gXp4T9PNmsIcMTTNN qQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3ee5tptx19-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 24 Feb 2022 10:29:16 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 24 Feb 2022 10:29:15 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 24 Feb 2022 10:29:15 -0800 Received: from localhost.localdomain (unknown [10.28.48.55]) by maili.marvell.com (Postfix) with ESMTP id B77925B6939; Thu, 24 Feb 2022 10:29:11 -0800 (PST) From: Akhil Goyal To: CC: , , , , , , , Subject: [PATCH v5 1/2] common/cnxk: configure reassembly specific params Date: Thu, 24 Feb 2022 23:59:00 +0530 Message-ID: <20220224182901.4050206-2-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220224182901.4050206-1-gakhil@marvell.com> References: <20220224172807.4028321-1-gakhil@marvell.com> <20220224182901.4050206-1-gakhil@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: RR59mM7jbTm1B74tUIfg4elfnZshceMi X-Proofpoint-GUID: RR59mM7jbTm1B74tUIfg4elfnZshceMi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-02-24_04,2022-02-24_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri When reassembly is enabled by application, set corresponding flags in SA during creation. Provide roc API to configure reassembly unit with active and zombie limits and step size Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/cnxk_security.c | 10 ++++++++++ drivers/common/cnxk/roc_nix_inl.c | 23 +++++++++++++++++++++++ drivers/common/cnxk/roc_nix_inl.h | 7 +++++++ drivers/common/cnxk/version.map | 1 + 4 files changed, 41 insertions(+) diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c index d6006d3176..ec808c0033 100644 --- a/drivers/common/cnxk/cnxk_security.c +++ b/drivers/common/cnxk/cnxk_security.c @@ -339,6 +339,16 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa, if (rc) return rc; + /* Default options for pkt_out and pkt_fmt are with + * second pass meta and no defrag. + */ + sa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META; + sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_NO_FRAG; + sa->w0.s.pkind = ROC_IE_OT_CPT_PKIND; + + if (ipsec_xfrm->options.ip_reassembly_en) + sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG; + /* ESN */ sa->w2.s.esn_en = !!ipsec_xfrm->options.esn; if (ipsec_xfrm->options.udp_encap) { diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 7bf89a44c1..dc8f004188 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -231,6 +231,29 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi) return (sa_base + ((spi & mask) * sz)); } +int +roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t max_frags) +{ + struct idev_cfg *idev = idev_get_cfg(); + struct roc_cpt *roc_cpt; + struct roc_cpt_rxc_time_cfg cfg; + + PLT_SET_USED(max_frags); + roc_cpt = idev->cpt; + if (!roc_cpt) { + plt_err("Cannot support inline inbound, cryptodev not probed"); + return -ENOTSUP; + } + + cfg.step = (max_wait_time * 1000 / ROC_NIX_INL_REAS_ACTIVE_LIMIT); + cfg.zombie_limit = ROC_NIX_INL_REAS_ZOMBIE_LIMIT; + cfg.zombie_thres = ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD; + cfg.active_limit = ROC_NIX_INL_REAS_ACTIVE_LIMIT; + cfg.active_thres = ROC_NIX_INL_REAS_ACTIVE_THRESHOLD; + + return roc_cpt_rxc_time_cfg(roc_cpt, &cfg); +} + int roc_nix_inl_inb_init(struct roc_nix *roc_nix) { diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 5eb1a81471..45d349acf4 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -43,6 +43,11 @@ /* Alignment of SA Base */ #define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16) +#define ROC_NIX_INL_REAS_ACTIVE_LIMIT 0xFFF +#define ROC_NIX_INL_REAS_ACTIVE_THRESHOLD 10 +#define ROC_NIX_INL_REAS_ZOMBIE_LIMIT 0xFFF +#define ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD 10 + static inline struct roc_onf_ipsec_inb_sa * roc_nix_inl_onf_ipsec_inb_sa(uintptr_t base, uint64_t idx) { @@ -152,6 +157,8 @@ struct roc_nix_rq *__roc_api roc_nix_inl_dev_rq(void); int __roc_api roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix, uint32_t tag_const, uint8_t tt); uint64_t __roc_api roc_nix_inl_dev_rq_limit_get(void); +int __roc_api roc_nix_reassembly_configure(uint32_t max_wait_time, + uint16_t max_frags); /* NIX Inline Outbound API */ int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 21f94e8972..45c8b6c2b4 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -209,6 +209,7 @@ INTERNAL { roc_nix_ptp_tx_ena_dis; roc_nix_queues_ctx_dump; roc_nix_ras_intr_ena_dis; + roc_nix_reassembly_configure; roc_nix_register_cq_irqs; roc_nix_register_queue_irqs; roc_nix_rq_dump; -- 2.25.1