From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A6888A0353; Fri, 25 Feb 2022 02:14:53 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3D6C640688; Fri, 25 Feb 2022 02:14:53 +0100 (CET) Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam07on2075.outbound.protection.outlook.com [40.107.95.75]) by mails.dpdk.org (Postfix) with ESMTP id F1D1540141 for ; Fri, 25 Feb 2022 02:14:51 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MgLg8U10RijBLFUSTxIjfecd2nxtAV00qjg8/ImKCqHSaFzuZ/L/KA18xZllFR5jdTkMUyIg9fcpiJTncNf4y3rwXMv5XP9GwrqH3mihES+rOd/4Yb9a+Fw3RBfAuAZ7JnAXqwK1yBoENSzqTv8M65G3o5NjIGq41Jsr+hy9qnl8qaB7cAzi/0Enl83yntt/UjTAFLnly51UbCr7xw0YnYJSU54ZzTO8nbywNeTnM5X84o0xvDFFtAqtRhNkvh4gJqFVumyYrxAQchUSzPI743KOtYrbF13YnycVDPvozJ1bhzF73o2GBSzinP9ruE4NgeqBSGJRyCREjA+IUTilXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Vf18auA+n9yPCaofGhGhwdFTS7r8L11dGxRqLXq2YyI=; b=QLHJb2/M8BTPOeQQWW8ERiefUjM7idPCNMIzZmmyiz6CJjUOpVVzkHxdFUWpvnQMqGVOD/3fAElK0rceTebN5+FkMexoUbie56fayM8gRnthfQrX/n5P23OEMsgNGAQlhKX87KWyCSayXvrEZ1n9B7sM6QDeBf9ZvSMwpQX78It/8wLWYUG+3X/y7hB370ar/LTHV4eMg4r07PVI2S/lEMabHHNvYyZOHkcwoScqyS+tVAkP8Oo+M2zZEiYlWRZRMYD5wRxUpotEhRQLRZPCsR6AFx5zDw3+YXi/kExqz/vY8pKG3cvf7pbBaUMt0rF7EvW2FLMaQJ5PTbUPhKIiug== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Vf18auA+n9yPCaofGhGhwdFTS7r8L11dGxRqLXq2YyI=; b=UtEFgRMlMIvsD0+iKJ8KRTh+vY5klhSFlseLcSgqoexfuUIkVT//S+qFFwEpV1du/2GaQgrn6/wLKZVJp0Em5tB3+wqo+Ov2sga4dgntOcMXFo5vQ8MgJXB37s0C51zp48xiFdnUQACza6CnDA2e6qF0b6u2nUwOXziIlLIQawpMW5V2HPWwcA9f5D3t4WK6BCOR3Behj4AbU/o9BJoFMfMPdg5bj5qa66toS2mIVC2Ow4eqkTfpEX5MuKfdsfIz67q1dD1Bs+rajnsMgw5AHF3tjusOaEFL5EYFaOvaNCnwHXk7OGX+0h2onxi6/ixfd53Z/ejDYorTyeASyE30/Q== Received: from BN8PR15CA0021.namprd15.prod.outlook.com (2603:10b6:408:c0::34) by DM6PR12MB2681.namprd12.prod.outlook.com (2603:10b6:5:41::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4995.24; Fri, 25 Feb 2022 01:14:47 +0000 Received: from BN8NAM11FT052.eop-nam11.prod.protection.outlook.com (2603:10b6:408:c0:cafe::75) by BN8PR15CA0021.outlook.office365.com (2603:10b6:408:c0::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5017.24 via Frontend Transport; Fri, 25 Feb 2022 01:14:47 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.235) by BN8NAM11FT052.mail.protection.outlook.com (10.13.177.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5017.22 via Frontend Transport; Fri, 25 Feb 2022 01:14:46 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 25 Feb 2022 01:14:34 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Thu, 24 Feb 2022 17:14:31 -0800 From: Sean Zhang To: , , Matan Azrad , Viacheslav Ovsiienko CC: Subject: [v4] net/mlx5: support matching optional fields of GRE Date: Fri, 25 Feb 2022 03:14:17 +0200 Message-ID: <20220225011417.230385-1-xiazhang@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220217062707.51619-1-xiazhang@nvidia.com> References: <20220217062707.51619-1-xiazhang@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bf625111-7069-4482-0eed-08d9f7fc36e7 X-MS-TrafficTypeDiagnostic: DM6PR12MB2681:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ShyAEaYtHt71wZqJImfHbSt6Y3FawKLOlANxOit7NXvKc7ho7VCT97tZEzebKTrNiyHHeNxty9J5zIN4gDbQGjSROSocPeQuKqei/YMyW5z7NZYFVNMzumlJuwBqXCAhQmI4t9u7TdZAiNyNkXl/hG2/pBupjF86Bq2H3lpRy2sOprvHinOkYYaEsm3eGGwMtCIDN1GOY1UakYIQ7WLOt8hm+1zzZIG5qDZmmrvddoZJWNUyNlXRTY0bS1PU7Xz07ZL9YIwpPnXOI3lUZf7NcrznvFmV9sjUlqI3l4qk+MAgiZ5y69IjyxbFtbM9cpcVIpiQMbcHUPOzcYH3c4/ihFgK77vG6Hv8pHdW6v/wJBu9+63yDX66o7CL+5osC1RjAPZKQbdZUedQ8Glg3ihqlgUwxMg3i7Bt85+AtO6g0CsVQmPXn06+fbxv7S3UI64cijLaftjE25RUiYdX8i3fy8HN7QnYjRBz9+7maPEkAXSffIfxzZ7CedCBXdjH4mw1R42IglRPn0ZS/iQL9tL54UDXgZVOU+lFShKPd4tLU12paJBYdY08wSkY0oDenmHxJUoQdM3D7HVgg+MrfcPkHkTa+lzftAhAuN5Rdwhvk3BqL3F3XxZXjLhtBD7ErBEkamb4UxZ3CAAeOZF74qDjtpntKqarNYHuUk6e1ZQrtP9J2nb8QM8Ah6glwfNkhUJhlcjoRfsLPxH3fdRyMH3PMA== X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(5660300002)(36860700001)(7696005)(30864003)(40460700003)(83380400001)(426003)(110136005)(2906002)(6636002)(6666004)(336012)(55016003)(47076005)(8936002)(36756003)(16526019)(2616005)(4326008)(81166007)(26005)(82310400004)(316002)(86362001)(186003)(8676002)(6286002)(356005)(508600001)(70206006)(70586007)(1076003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Feb 2022 01:14:46.9567 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf625111-7069-4482-0eed-08d9f7fc36e7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2681 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds matching on the optional fields (checksum/key/sequence) of GRE header. The matching on checksum and sequence fields requests support from rdma-core with the capability of misc5 and tunnel_header 0-3. For patterns without checksum and sequence specified, keep using misc for matching as before, but for patterns with checksum or sequence, validate capability first and then use misc5 for the matching. Signed-off-by: Sean Zhang Acked-by: Viacheslav Ovsiienko --- v4 - code rebase v3 - some code style change v2 - replace default mask with nic mask --- doc/guides/nics/mlx5.rst | 11 +++ drivers/common/mlx5/mlx5_devx_cmds.c | 3 + drivers/net/mlx5/linux/mlx5_os.c | 2 + drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_flow.c | 101 ++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow.h | 6 ++ drivers/net/mlx5/mlx5_flow_dv.c | 121 +++++++++++++++++++++++++++ 7 files changed, 245 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 7b04e9bac5..e52aa2cb94 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -493,6 +493,17 @@ Limitations - Set ``dv_flow_en`` to 2 in order to enable HW steering. - Async queue-based ``rte_flow_q`` APIs supported only. +- Match on GRE header supports the following fields: + + - c_rsvd0_v: C bit, K bit, S bit + - protocol type + - Checksum + - Key + - Sequence + + Matching on checksum and sequence needs OFED 5.6+. + + Statistics ---------- diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 9f1419ded8..d02ac2a678 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1044,6 +1044,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->flow.tunnel_header_0_1 = MLX5_GET (flow_table_nic_cap, hcattr, ft_field_support_2_nic_receive.tunnel_header_0_1); + attr->flow.tunnel_header_2_3 = MLX5_GET + (flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.tunnel_header_2_3); attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); attr->inner_ipv4_ihl = MLX5_GET (flow_table_nic_cap, hcattr, diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 2e1606a733..ac9be14f54 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1325,6 +1325,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, } if (hca_attr->flow.tunnel_header_0_1) sh->tunnel_header_0_1 = 1; + if (hca_attr->flow.tunnel_header_2_3) + sh->tunnel_header_2_3 = 1; #endif #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO if (hca_attr->flow_hit_aso && priv->mtr_color_reg == REG_C_3) { diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index bd69aa2334..c5301921c5 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1186,6 +1186,7 @@ struct mlx5_dev_ctx_shared { uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */ uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */ uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */ + uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */ uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */ uint32_t dr_drop_action_en:1; /* Use DR drop action. */ uint32_t drop_action_check_flag:1; /* Check Flag for drop action. */ diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 5a4e000c12..b792ddb73a 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -2926,6 +2926,107 @@ mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, return ret; } +/** + * Validate GRE optional item. + * + * @param[in] dev + * Pointer to the Ethernet device structure. + * @param[in] item + * Item specification. + * @param[in] item_flags + * Bit flags to mark detected items. + * @param[in] attr + * Flow rule attributes. + * @param[in] gre_item + * Pointer to gre_item + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev, + const struct rte_flow_item *item, + uint64_t item_flags, + const struct rte_flow_attr *attr, + const struct rte_flow_item *gre_item, + struct rte_flow_error *error) +{ + const struct rte_flow_item_gre *gre_spec = gre_item->spec; + const struct rte_flow_item_gre *gre_mask = gre_item->mask; + const struct rte_flow_item_gre_opt *spec = item->spec; + const struct rte_flow_item_gre_opt *mask = item->mask; + struct mlx5_priv *priv = dev->data->dev_private; + int ret = 0; + struct rte_flow_item_gre_opt nic_mask = { + .checksum_rsvd = { + .checksum = RTE_BE16(UINT16_MAX), + .reserved1 = 0x0, + }, + .key = { + .key = RTE_BE32(UINT32_MAX), + }, + .sequence = { + .sequence = RTE_BE32(UINT32_MAX), + }, + }; + + if (!(item_flags & MLX5_FLOW_LAYER_GRE)) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "No preceding GRE header"); + if (item_flags & MLX5_FLOW_LAYER_INNER) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "GRE option following a wrong item"); + if (!spec || !mask) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "At least one field gre_option(checksum/key/sequence) must be specified"); + if (!gre_mask) + gre_mask = &rte_flow_item_gre_mask; + if (mask->checksum_rsvd.checksum) + if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x8000)) && + !(gre_spec->c_rsvd0_ver & RTE_BE16(0x8000))) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Checksum bit must be on"); + if (mask->key.key) + if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && + !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Key bit must be on"); + if (mask->sequence.sequence) + if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x1000)) && + !(gre_spec->c_rsvd0_ver & RTE_BE16(0x1000))) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Sequence bit must be on"); + if (mask->checksum_rsvd.checksum || mask->sequence.sequence) { + if (priv->sh->steering_format_version == + MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || + ((attr->group || attr->transfer) && + !priv->sh->misc5_cap) || + (!(priv->sh->tunnel_header_0_1 && + priv->sh->tunnel_header_2_3) && + !attr->group && !attr->transfer)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Checksum/Sequence not supported"); + } + ret = mlx5_flow_item_acceptable + (item, (const uint8_t *)mask, + (const uint8_t *)&nic_mask, + sizeof(struct rte_flow_item_gre_opt), + MLX5_ITEM_RANGE_NOT_ACCEPTED, error); + return ret; +} + /** * Validate GRE item. * diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 09f0d7a75d..e510921a3f 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1783,6 +1783,12 @@ int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, uint64_t item_flags, const struct rte_flow_item *gre_item, struct rte_flow_error *error); +int mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev, + const struct rte_flow_item *item, + uint64_t item_flags, + const struct rte_flow_attr *attr, + const struct rte_flow_item *gre_item, + struct rte_flow_error *error); int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, uint64_t item_flags, uint64_t last_item, diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 7a012f7bb9..aca55bbcdb 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7109,6 +7109,13 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, gre_item = items; last_item = MLX5_FLOW_LAYER_GRE; break; + case RTE_FLOW_ITEM_TYPE_GRE_OPTION: + ret = mlx5_flow_validate_item_gre_option(dev, items, item_flags, + attr, gre_item, error); + if (ret < 0) + return ret; + last_item = MLX5_FLOW_LAYER_GRE; + break; case RTE_FLOW_ITEM_TYPE_NVGRE: ret = mlx5_flow_validate_item_nvgre(items, item_flags, next_protocol, @@ -8829,6 +8836,110 @@ flow_dv_translate_item_gre(void *matcher, void *key, protocol_m & protocol_v); } +/** + * Add GRE optional items to matcher and to the value. + * + * @param[in, out] matcher + * Flow matcher. + * @param[in, out] key + * Flow matcher value. + * @param[in] item + * Flow pattern to translate. + * @param[in] gre_item + * Pointer to gre_item. + * @param[in] pattern_flags + * Accumulated pattern flags. + */ +static void +flow_dv_translate_item_gre_option(void *matcher, void *key, + const struct rte_flow_item *item, + const struct rte_flow_item *gre_item, + uint64_t pattern_flags) +{ + const struct rte_flow_item_gre_opt *option_m = item->mask; + const struct rte_flow_item_gre_opt *option_v = item->spec; + const struct rte_flow_item_gre *gre_m = gre_item->mask; + const struct rte_flow_item_gre *gre_v = gre_item->spec; + static const struct rte_flow_item_gre empty_gre = {0}; + struct rte_flow_item gre_key_item; + uint16_t c_rsvd0_ver_m, c_rsvd0_ver_v; + uint16_t protocol_m, protocol_v; + void *misc5_m; + void *misc5_v; + + /* + * If only match key field, keep using misc for matching. + * If need to match checksum or sequence, using misc5 and do + * not need using misc. + */ + if (!(option_m->sequence.sequence || + option_m->checksum_rsvd.checksum)) { + flow_dv_translate_item_gre(matcher, key, gre_item, + pattern_flags); + gre_key_item.spec = &option_v->key.key; + gre_key_item.mask = &option_m->key.key; + flow_dv_translate_item_gre_key(matcher, key, &gre_key_item); + return; + } + if (!gre_v) { + gre_v = &empty_gre; + gre_m = &empty_gre; + } else { + if (!gre_m) + gre_m = &rte_flow_item_gre_mask; + } + protocol_v = gre_v->protocol; + protocol_m = gre_m->protocol; + if (!protocol_m) { + /* Force next protocol to prevent matchers duplication */ + uint16_t ether_type = + mlx5_translate_tunnel_etypes(pattern_flags); + if (ether_type) { + protocol_v = rte_be_to_cpu_16(ether_type); + protocol_m = UINT16_MAX; + } + } + c_rsvd0_ver_v = gre_v->c_rsvd0_ver; + c_rsvd0_ver_m = gre_m->c_rsvd0_ver; + if (option_m->sequence.sequence) { + c_rsvd0_ver_v |= RTE_BE16(0x1000); + c_rsvd0_ver_m |= RTE_BE16(0x1000); + } + if (option_m->key.key) { + c_rsvd0_ver_v |= RTE_BE16(0x2000); + c_rsvd0_ver_m |= RTE_BE16(0x2000); + } + if (option_m->checksum_rsvd.checksum) { + c_rsvd0_ver_v |= RTE_BE16(0x8000); + c_rsvd0_ver_m |= RTE_BE16(0x8000); + } + /* + * Hardware parses GRE optional field into the fixed location, + * do not need to adjust the tunnel dword indices. + */ + misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5); + misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5); + MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_0, + rte_be_to_cpu_32((c_rsvd0_ver_v | protocol_v << 16) & + (c_rsvd0_ver_m | protocol_m << 16))); + MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_0, + rte_be_to_cpu_32(c_rsvd0_ver_m | protocol_m << 16)); + MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_1, + rte_be_to_cpu_32(option_v->checksum_rsvd.checksum & + option_m->checksum_rsvd.checksum)); + MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_1, + rte_be_to_cpu_32(option_m->checksum_rsvd.checksum)); + MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_2, + rte_be_to_cpu_32(option_v->key.key & option_m->key.key)); + MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_2, + rte_be_to_cpu_32(option_m->key.key)); + MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_3, + rte_be_to_cpu_32(option_v->sequence.sequence & + option_m->sequence.sequence)); + MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_3, + rte_be_to_cpu_32(option_m->sequence.sequence)); +} + /** * Add NVGRE item to matcher and to the value. * @@ -12709,6 +12820,7 @@ flow_dv_translate(struct rte_eth_dev *dev, }; const struct rte_flow_item *integrity_items[2] = {NULL, NULL}; const struct rte_flow_item *tunnel_item = NULL; + const struct rte_flow_item *gre_item = NULL; if (!wks) return rte_flow_error_set(error, ENOMEM, @@ -13481,12 +13593,18 @@ flow_dv_translate(struct rte_eth_dev *dev, matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); last_item = MLX5_FLOW_LAYER_GRE; tunnel_item = items; + gre_item = items; break; case RTE_FLOW_ITEM_TYPE_GRE_KEY: flow_dv_translate_item_gre_key(match_mask, match_value, items); last_item = MLX5_FLOW_LAYER_GRE_KEY; break; + case RTE_FLOW_ITEM_TYPE_GRE_OPTION: + matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); + last_item = MLX5_FLOW_LAYER_GRE; + tunnel_item = items; + break; case RTE_FLOW_ITEM_TYPE_NVGRE: matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); last_item = MLX5_FLOW_LAYER_GRE; @@ -13645,6 +13763,9 @@ flow_dv_translate(struct rte_eth_dev *dev, else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE) flow_dv_translate_item_nvgre(match_mask, match_value, tunnel_item, item_flags); + else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION) + flow_dv_translate_item_gre_option(match_mask, match_value, + tunnel_item, gre_item, item_flags); else MLX5_ASSERT(false); } -- 2.25.1