From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 23D5CA0350; Mon, 28 Feb 2022 04:40:47 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9B8B94068C; Mon, 28 Feb 2022 04:40:46 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 86E714068A for ; Mon, 28 Feb 2022 04:40:45 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21S23sqx005328 for ; Sun, 27 Feb 2022 19:40:44 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=T397DEhd43uR9I3AaMlAhn0czXW68o8X5Tyv+1BPHgE=; b=huB/Q8WX/kP8iwEJOvMRPOE7wvS+djMWnF5/zjcoi/zPyQKj+Pcy39YSZJI8eGT1Yayv 00teQBowC+JHuuBA4rl9QTxUyULWy0R2Q/MpDIqqrTqtZB91LHNsE6rY413ArebELdTB RKM9LaPxNAlAPuzmRQPR+NBNXURKMnRtJDWWNP3QBANEsx55hn2UOWQbhs/Q4Rll6tQB 1mnllXWkcuN5ir7cWjuhtSrJxryVuYsiqaJSLo0SQDsIkUpBi9YVzCbJBWOul/PfRNVV v/AgApD9AuaFEl56ZqQWoCZFBG0nNP5z6W3Z7x/aPONVjnpyGy7/NxCL4pIeE06PP/l5 dA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3egn96r8h4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 27 Feb 2022 19:40:44 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 27 Feb 2022 19:40:42 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sun, 27 Feb 2022 19:40:42 -0800 Received: from mahipal-244.marvell.com (unknown [10.29.20.28]) by maili.marvell.com (Postfix) with ESMTP id 56C513F7104; Sun, 27 Feb 2022 19:40:41 -0800 (PST) From: Mahipal Challa To: CC: , Subject: [dpdk-dev] [PATCH v1 1/1] compress/octeontx: add octeontx2 SoC family support Date: Mon, 28 Feb 2022 09:10:35 +0530 Message-ID: <20220228034035.635651-1-mchalla@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: 1TqoMbi2wcYwVPqhItsvW1VcVy1d5QsF X-Proofpoint-ORIG-GUID: 1TqoMbi2wcYwVPqhItsvW1VcVy1d5QsF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-02-28_01,2022-02-26_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The octeontx2 9xxx SoC family support is added. Signed-off-by: Mahipal Challa --- drivers/compress/octeontx/include/zip_regs.h | 12 ++++++++++++ drivers/compress/octeontx/otx_zip.c | 6 +++++- drivers/compress/octeontx/otx_zip.h | 1 + drivers/compress/octeontx/otx_zip_pmd.c | 6 ++++++ 4 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/compress/octeontx/include/zip_regs.h b/drivers/compress/octeontx/include/zip_regs.h index 94a48cde66..a7fcccc055 100644 --- a/drivers/compress/octeontx/include/zip_regs.h +++ b/drivers/compress/octeontx/include/zip_regs.h @@ -63,6 +63,18 @@ typedef union { uint64_t reserved_49_63 : 15; #endif /* Word 0 - End */ } s; + + struct zip_vqx_sbuf_addr_s9x { +#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ + uint64_t reserved_53_63 : 11; + uint64_t ptr : 46; + uint64_t off : 7; +#else /* Word 0 - Little Endian */ + uint64_t off : 7; + uint64_t ptr : 46; + uint64_t reserved_53_63 : 11; +#endif /* Word 0 - End */ + } s9x; } zip_vqx_sbuf_addr_t; /** diff --git a/drivers/compress/octeontx/otx_zip.c b/drivers/compress/octeontx/otx_zip.c index a9046ff351..11471dcbb4 100644 --- a/drivers/compress/octeontx/otx_zip.c +++ b/drivers/compress/octeontx/otx_zip.c @@ -58,7 +58,11 @@ zipvf_q_init(struct zipvf_qp *qp) cmdq->iova = iova; que_sbuf_addr.u = 0ull; - que_sbuf_addr.s.ptr = (cmdq->iova >> 7); + if (vf->pdev->id.device_id == PCI_DEVICE_ID_OCTEONTX2_ZIPVF) + que_sbuf_addr.s9x.ptr = (cmdq->iova >> 7); + else + que_sbuf_addr.s.ptr = (cmdq->iova >> 7); + zip_reg_write64(vf->vbar0, ZIP_VQ_SBUF_ADDR, que_sbuf_addr.u); zip_q_enable(qp); diff --git a/drivers/compress/octeontx/otx_zip.h b/drivers/compress/octeontx/otx_zip.h index 118a95d738..46c80c8dc2 100644 --- a/drivers/compress/octeontx/otx_zip.h +++ b/drivers/compress/octeontx/otx_zip.h @@ -30,6 +30,7 @@ extern int octtx_zip_logtype_driver; #define PCI_VENDOR_ID_CAVIUM 0x177D /**< PCI device id of ZIP VF */ #define PCI_DEVICE_ID_OCTEONTX_ZIPVF 0xA037 +#define PCI_DEVICE_ID_OCTEONTX2_ZIPVF 0xA083 /* maximum number of zip vf devices */ #define ZIP_MAX_VFS 8 diff --git a/drivers/compress/octeontx/otx_zip_pmd.c b/drivers/compress/octeontx/otx_zip_pmd.c index f9b8f7a1ec..dff188e223 100644 --- a/drivers/compress/octeontx/otx_zip_pmd.c +++ b/drivers/compress/octeontx/otx_zip_pmd.c @@ -85,7 +85,9 @@ zip_process_op(struct rte_comp_op *op, op->status = RTE_COMP_OP_STATUS_ERROR; } +#ifdef ZIP_DBG ZIP_PMD_INFO("written %d\n", zresult->s.totalbyteswritten); +#endif /* Update op stats */ switch (op->status) { @@ -630,6 +632,10 @@ static struct rte_pci_id pci_id_octtx_zipvf_table[] = { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_OCTEONTX_ZIPVF), }, + { + RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, + PCI_DEVICE_ID_OCTEONTX2_ZIPVF), + }, { .device_id = 0 }, -- 2.25.1