From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 03937A034C; Mon, 28 Mar 2022 09:03:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EA81E4286B; Mon, 28 Mar 2022 09:03:38 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id AB3D642865 for ; Mon, 28 Mar 2022 09:03:37 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22RMbX72026749 for ; Mon, 28 Mar 2022 00:03:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=XfUajRiQhU1+QSNlaaE1VR6t1IRHfQ1vgrF7ifw9GG0=; b=fWdETQCS4oBZg6qRvbGelHSi+mUiiJkdqa3myULJxUJgEL8gqkXJMoxQwAlSE+y/WfYS 336NxCbLIrJ+GLfKxQ+a+TrqogPsAxYTtryh56Ra3Dra6J0lYbq1GMTfB8IOcseM9zFG tA+9vKxxKl8Gxk5sFjk29cfTSEdEbogRHpru9YQsOVXXkxnauJ9iVb5G9Ilztft5gpxY lQfyyJUJhQMQWc3SPDdGB1PnTMkPCV9z3WRH60RINB9C1jFDbUolFBK0+TKDFfltVmAb D0F2wYvoTJPKby0IQSrxUNOx9YqEnG53UXzPKyovjsuVpBE7vvUE39su4lChHIGO4hYt gg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3f22bn5ga1-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 28 Mar 2022 00:03:36 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 28 Mar 2022 00:03:34 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.32 via Frontend Transport; Mon, 28 Mar 2022 00:03:34 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 52E023F7262; Sun, 27 Mar 2022 22:48:03 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Subject: [PATCH 1/4] common/cnxk: use aggregate level rr prio from mbox Date: Mon, 28 Mar 2022 11:17:54 +0530 Message-ID: <20220328054757.28762-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: fz98mUKTk9PKMgqxPa8625TtlUf92sbB X-Proofpoint-ORIG-GUID: fz98mUKTk9PKMgqxPa8625TtlUf92sbB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-28_02,2022-03-28_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Use aggregate level Round Robin Priority from mbox response instead of fixing it to single macro. This is useful when kernel AF driver changes the constant. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix_priv.h | 5 +++-- drivers/common/cnxk/roc_nix_tm.c | 3 ++- drivers/common/cnxk/roc_nix_tm_utils.c | 8 ++++---- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 9b9ffae..cc69d71 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -181,6 +181,7 @@ struct nix { uint16_t tm_root_lvl; uint16_t tm_flags; uint16_t tm_link_cfg_lvl; + uint8_t tm_aggr_lvl_rr_prio; uint16_t contig_rsvd[NIX_TXSCH_LVL_CNT]; uint16_t discontig_rsvd[NIX_TXSCH_LVL_CNT]; uint64_t tm_markfmt_en; @@ -284,7 +285,6 @@ void nix_unregister_irqs(struct nix *nix); /* Default TL1 priority and Quantum from AF */ #define NIX_TM_TL1_DFLT_RR_QTM ((1 << 24) - 1) -#define NIX_TM_TL1_DFLT_RR_PRIO 1 struct nix_tm_shaper_data { uint64_t burst_exponent; @@ -432,7 +432,8 @@ bool nix_tm_child_res_valid(struct nix_tm_node_list *list, struct nix_tm_node *parent); uint16_t nix_tm_resource_estimate(struct nix *nix, uint16_t *schq_contig, uint16_t *schq, enum roc_nix_tm_tree tree); -uint8_t nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg, +uint8_t nix_tm_tl1_default_prep(struct nix *nix, uint32_t schq, + volatile uint64_t *reg, volatile uint64_t *regval); uint8_t nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node, volatile uint64_t *reg, diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c index 5b70c7b..84815d0 100644 --- a/drivers/common/cnxk/roc_nix_tm.c +++ b/drivers/common/cnxk/roc_nix_tm.c @@ -55,7 +55,7 @@ nix_tm_node_reg_conf(struct nix *nix, struct nix_tm_node *node) req = mbox_alloc_msg_nix_txschq_cfg(mbox); req->lvl = NIX_TXSCH_LVL_TL1; - k = nix_tm_tl1_default_prep(node->parent_hw_id, req->reg, + k = nix_tm_tl1_default_prep(nix, node->parent_hw_id, req->reg, req->regval); req->num_regs = k; rc = mbox_process(mbox); @@ -1281,6 +1281,7 @@ nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree) } while (pend); nix->tm_link_cfg_lvl = rsp->link_cfg_lvl; + nix->tm_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio; return 0; alloc_err: for (i = 0; i < NIX_TXSCH_LVL_CNT; i++) { diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index bcdf990..b9b605f 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -478,7 +478,7 @@ nix_tm_child_res_valid(struct nix_tm_node_list *list, } uint8_t -nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg, +nix_tm_tl1_default_prep(struct nix *nix, uint32_t schq, volatile uint64_t *reg, volatile uint64_t *regval) { uint8_t k = 0; @@ -496,7 +496,7 @@ nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg, k++; reg[k] = NIX_AF_TL1X_TOPOLOGY(schq); - regval[k] = (NIX_TM_TL1_DFLT_RR_PRIO << 1); + regval[k] = (nix->tm_aggr_lvl_rr_prio << 1); k++; reg[k] = NIX_AF_TL1X_CIR(schq); @@ -540,7 +540,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node, * Static Priority is disabled */ if (hw_lvl == NIX_TXSCH_LVL_TL1 && nix->tm_flags & NIX_TM_TL1_NO_SP) { - rr_prio = NIX_TM_TL1_DFLT_RR_PRIO; + rr_prio = nix->tm_aggr_lvl_rr_prio; child = 0; } @@ -662,7 +662,7 @@ nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node, */ if (hw_lvl == NIX_TXSCH_LVL_TL2 && (!nix_tm_have_tl1_access(nix) || nix->tm_flags & NIX_TM_TL1_NO_SP)) - strict_prio = NIX_TM_TL1_DFLT_RR_PRIO; + strict_prio = nix->tm_aggr_lvl_rr_prio; plt_tm_dbg("Schedule config node %s(%u) lvl %u id %u, " "prio 0x%" PRIx64 ", rr_quantum/rr_wt 0x%" PRIx64 " (%p)", -- 2.8.4