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Sun, 10 Apr 2022 02:25:39 -0700 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko Subject: [PATCH 3/3] net/mlx5: optimize Rx is hairpin function Date: Sun, 10 Apr 2022 12:25:28 +0300 Message-ID: <20220410092528.1001685-4-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220410092528.1001685-1-michaelba@nvidia.com> References: <20220410092528.1001685-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1a288500-c3d0-467f-2429-08da1ad41574 X-MS-TrafficTypeDiagnostic: BN8PR12MB4785:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ftcSjC24PbV66d/4KddT4ocDjRw1X/fxho62PFQlXQN7jzeK9ZURf66ocHFYH+oUw1gcnDtNEubARAnqWzghMG56x8ZcE9Na+V25/8esBoXrRJylQRCZVaZ+Y6GWtMyS8oIMqf3hUwbY0v9Da2a4q1iPub2yJr/S8aiALwc45+rUkluhp9qKnLhAe42Lel9MLhhS2ndpOxF6h9mGV1UbrwZaakKXzCru+9OiSO12zMS8ZOEJ31UfpfNakoTFX8EsqU9PdVlM2gea8SnIlDEH5u6AVrKX2MXCj3neMa4lHilLz9I0mqPfISXK+pATk/amq+ZMJ7D/VjMBiOYFZSqwKXngyUzqyBsDfCCv2MnDfrKyUphlq3di4T9DkEPRp9WNU9EYf3HOawmPYFRFuf1etLiHjEwWlbKumcBEwglFaZ5PA1f13k/Yygp6ybXrDOszzRISCRCZEuHK6Vl/z6qeUWZHA3uwoh3lz+lUnucq4lKigr/DrvJbcv6AhCm8uYo8FPv+HUh6rNB5X1D4gy6JISBzmEoT/+3N3cbU6qM7t4DaZjZSayApzT+9cWjHi3O4qlW0rb2JlTr32vV2Ax+ZxZihGDYY4npgSNt994ZG1NyORXHS6tOVntK9gKFNjSk/B2tKIl29k58NrJSQLkROkJAt1j17LEFlfWYX/jv8RH3WTbM0G5biQUFDsX2yM5wNUwzx2iTHnUXODIBb3IoLPw== X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(107886003)(70206006)(426003)(336012)(54906003)(6916009)(26005)(70586007)(2906002)(81166007)(86362001)(508600001)(36860700001)(316002)(8936002)(186003)(2616005)(1076003)(5660300002)(47076005)(40460700003)(356005)(8676002)(4326008)(6286002)(6666004)(36756003)(7696005)(55016003)(83380400001)(82310400005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2022 09:25:42.0574 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a288500-c3d0-467f-2429-08da1ad41574 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB4785 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The mlx5_rxq_is_hairpin() function checks whether RxQ type is Hairpin. It is done by reading a flag in Rx control structure coming from mlx5_rxq_ctrl_get() function. The function verifies that the queue index is valid even though it has been checked within the mlx5_rxq_ctrl_get() function. This patch removes the redundant check. Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_rxq.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index d41834f46f..1782d52f71 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -2332,13 +2332,12 @@ mlx5_ext_rxq_verify(struct rte_eth_dev *dev) bool mlx5_rxq_is_hairpin(struct rte_eth_dev *dev, uint16_t idx) { - struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_rxq_ctrl *rxq_ctrl; if (mlx5_is_external_rxq(dev, idx)) return false; rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); - return (idx < priv->rxqs_n && rxq_ctrl != NULL && rxq_ctrl->is_hairpin); + return (rxq_ctrl != NULL && rxq_ctrl->is_hairpin); } /* @@ -2355,9 +2354,12 @@ mlx5_rxq_is_hairpin(struct rte_eth_dev *dev, uint16_t idx) const struct rte_eth_hairpin_conf * mlx5_rxq_get_hairpin_conf(struct rte_eth_dev *dev, uint16_t idx) { - struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx); + if (mlx5_rxq_is_hairpin(dev, idx)) { + struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx); - return mlx5_rxq_is_hairpin(dev, idx) ? &rxq->hairpin_conf : NULL; + return rxq != NULL ? &rxq->hairpin_conf : NULL; + } + return NULL; } /** @@ -2367,7 +2369,7 @@ mlx5_rxq_get_hairpin_conf(struct rte_eth_dev *dev, uint16_t idx) * @param ind_tbl * Pointer to indirection table to match. * @param queues - * Queues to match to ques in indirection table. + * Queues to match to queues in indirection table. * @param queues_n * Number of queues in the array. * @@ -2376,11 +2378,11 @@ mlx5_rxq_get_hairpin_conf(struct rte_eth_dev *dev, uint16_t idx) */ static int mlx5_ind_table_obj_match_queues(const struct mlx5_ind_table_obj *ind_tbl, - const uint16_t *queues, uint32_t queues_n) + const uint16_t *queues, uint32_t queues_n) { - return (ind_tbl->queues_n == queues_n) && - (!memcmp(ind_tbl->queues, queues, - ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))); + return (ind_tbl->queues_n == queues_n) && + (!memcmp(ind_tbl->queues, queues, + ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))); } /** -- 2.25.1